1 /*
2 * Copyright (c) 2001-2011, Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _IF_IGB_H_
33 #define _IF_IGB_H_
34
35 /* Tunables */
36
37 /*
38 * Max ring count
39 */
40 #define IGB_MAX_RING_I210 4
41 #define IGB_MAX_RING_I211 2
42 #define IGB_MAX_RING_I350 8
43 #define IGB_MAX_RING_I354 8
44 #define IGB_MAX_RING_82580 8
45 #define IGB_MAX_RING_82576 16
46 #define IGB_MAX_RING_82575 4
47 #define IGB_MIN_RING 1
48 #define IGB_MIN_RING_RSS 2
49
50 /*
51 * Max TX/RX interrupt bits
52 */
53 #define IGB_MAX_TXRXINT_I210 4
54 #define IGB_MAX_TXRXINT_I211 4
55 #define IGB_MAX_TXRXINT_I350 8
56 #define IGB_MAX_TXRXINT_I354 8
57 #define IGB_MAX_TXRXINT_82580 8
58 #define IGB_MAX_TXRXINT_82576 16
59 #define IGB_MAX_TXRXINT_82575 4 /* XXX not used */
60 #define IGB_MIN_TXRXINT 2 /* XXX VF? */
61
62 /*
63 * Max IVAR count
64 */
65 #define IGB_MAX_IVAR_I210 4
66 #define IGB_MAX_IVAR_I211 4
67 #define IGB_MAX_IVAR_I350 4
68 #define IGB_MAX_IVAR_I354 4
69 #define IGB_MAX_IVAR_82580 4
70 #define IGB_MAX_IVAR_82576 8
71 #define IGB_MAX_IVAR_VF 1
72
73 /*
74 * Default number of segments received before writing to RX related registers
75 */
76 #define IGB_DEF_RXWREG_NSEGS 32
77
78 /*
79 * Default number of segments sent before writing to TX related registers
80 */
81 #define IGB_DEF_TXWREG_NSEGS 8
82
83 /*
84 * IGB_TXD: Maximum number of Transmit Descriptors
85 *
86 * This value is the number of transmit descriptors allocated by the driver.
87 * Increasing this value allows the driver to queue more transmits. Each
88 * descriptor is 16 bytes.
89 * Since TDLEN should be multiple of 128bytes, the number of transmit
90 * desscriptors should meet the following condition.
91 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
92 */
93 #define IGB_MIN_TXD 256
94 #define IGB_DEFAULT_TXD 1024
95 #define IGB_MAX_TXD 4096
96
97 /*
98 * IGB_RXD: Maximum number of Transmit Descriptors
99 *
100 * This value is the number of receive descriptors allocated by the driver.
101 * Increasing this value allows the driver to buffer more incoming packets.
102 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
103 * descriptor. The maximum MTU size is 16110.
104 * Since TDLEN should be multiple of 128bytes, the number of transmit
105 * desscriptors should meet the following condition.
106 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
107 */
108 #define IGB_MIN_RXD 256
109 #define IGB_DEFAULT_RXD 512
110 #define IGB_MAX_RXD 4096
111
112 /*
113 * This parameter controls when the driver calls the routine to reclaim
114 * transmit descriptors. Cleaning earlier seems a win.
115 */
116 #define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2)
117
118 /*
119 * This parameter controls whether or not autonegotation is enabled.
120 * 0 - Disable autonegotiation
121 * 1 - Enable autonegotiation
122 */
123 #define DO_AUTO_NEG 1
124
125 /*
126 * This parameter control whether or not the driver will wait for
127 * autonegotiation to complete.
128 * 1 - Wait for autonegotiation to complete
129 * 0 - Don't wait for autonegotiation to complete
130 */
131 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
132
133 /* Tunables -- End */
134
135 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
136 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
137 ADVERTISE_1000_FULL)
138
139 #define AUTO_ALL_MODES 0
140
141 /* PHY master/slave setting */
142 #define IGB_MASTER_SLAVE e1000_ms_hw_default
143
144 /*
145 * Micellaneous constants
146 */
147 #define IGB_VENDOR_ID 0x8086
148
149 #define IGB_JUMBO_PBA 0x00000028
150 #define IGB_DEFAULT_PBA 0x00000030
151 #define IGB_SMARTSPEED_DOWNSHIFT 3
152 #define IGB_SMARTSPEED_MAX 15
153 #define IGB_MAX_LOOP 10
154
155 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
156 #define IGB_RX_HTHRESH 8
157 #define IGB_RX_WTHRESH 1
158
159 #define IGB_TX_PTHRESH 8
160 #define IGB_TX_HTHRESH 1
161 #define IGB_TX_WTHRESH 16
162
163 #define MAX_NUM_MULTICAST_ADDRESSES 128
164 #define IGB_FC_PAUSE_TIME 0x0680
165
166 #define IGB_INTR_RATE 6000
167 #define IGB_MSIX_RX_RATE 6000
168 #define IGB_MSIX_TX_RATE 4000
169
170 /*
171 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
172 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
173 * also optimize cache line size effect. H/W supports up to cache line size 128.
174 */
175 #define IGB_DBA_ALIGN 128
176
177 /* PCI Config defines */
178 #define IGB_MSIX_BAR 3
179
180 #define IGB_MAX_SCATTER 64
181 #define IGB_VFTA_SIZE 128
182 #define IGB_TSO_SIZE (IP_MAXPACKET + \
183 sizeof(struct ether_vlan_header))
184 #define IGB_HDR_BUF 128
185 #define IGB_PKTTYPE_MASK 0x0000FFF0
186
187 #define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
188
189 /* One for TX csum offloading desc, the other 2 are reserved */
190 #define IGB_TX_RESERVED 3
191
192 /* Large enough for 64K TSO */
193 #define IGB_TX_SPARE 33
194
195 #define IGB_TX_OACTIVE_MAX 64
196
197 #define IGB_NRSSRK 10
198 #define IGB_RSSRK_SIZE 4
199 #define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] | \
200 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \
201 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \
202 key[(i) * IGB_RSSRK_SIZE + 3] << 24)
203
204 #define IGB_NRETA 32
205 #define IGB_RETA_SIZE 4
206 #define IGB_RETA_SHIFT 0
207 #define IGB_RETA_SHIFT_82575 6
208
209 #define IGB_EITR_INTVL_MASK 0x7ffc
210 #define IGB_EITR_INTVL_SHIFT 2
211
212 struct igb_softc;
213
214 /*
215 * Bus dma information structure
216 */
217 struct igb_dma {
218 bus_addr_t dma_paddr;
219 void *dma_vaddr;
220 bus_dma_tag_t dma_tag;
221 bus_dmamap_t dma_map;
222 };
223
224 /*
225 * Transmit ring: one per queue
226 */
227 struct igb_tx_ring {
228 struct lwkt_serialize tx_serialize;
229 struct igb_softc *sc;
230 struct ifaltq_subque *ifsq;
231 uint32_t me;
232 uint32_t tx_flags;
233 #define IGB_TXFLAG_TSO_IPLEN0 0x1
234 #define IGB_TXFLAG_ENABLED 0x2
235 struct e1000_tx_desc *tx_base;
236 int num_tx_desc;
237 uint32_t next_avail_desc;
238 uint32_t next_to_clean;
239 uint32_t *tx_hdr;
240 int tx_avail;
241 struct igb_tx_buf *tx_buf;
242 bus_dma_tag_t tx_tag;
243 int tx_nsegs;
244 int spare_desc;
245 int oact_lo_desc;
246 int oact_hi_desc;
247 int intr_nsegs;
248 int wreg_nsegs;
249 int tx_intr_bit;
250 uint32_t tx_intr_mask;
251 struct ifsubq_watchdog tx_watchdog;
252
253 /* Soft stats */
254 u_long tx_packets;
255
256 struct igb_dma txdma;
257 bus_dma_tag_t tx_hdr_dtag;
258 bus_dmamap_t tx_hdr_dmap;
259 bus_addr_t tx_hdr_paddr;
260 int tx_intr_cpuid;
261 } __cachealign;
262
263 /*
264 * Receive ring: one per queue
265 */
266 struct igb_rx_ring {
267 struct lwkt_serialize rx_serialize;
268 struct igb_softc *sc;
269 uint32_t me;
270 union e1000_adv_rx_desc *rx_base;
271 boolean_t discard;
272 int num_rx_desc;
273 uint32_t next_to_check;
274 struct igb_rx_buf *rx_buf;
275 bus_dma_tag_t rx_tag;
276 bus_dmamap_t rx_sparemap;
277 int rx_intr_bit;
278 uint32_t rx_intr_mask;
279
280 /*
281 * First/last mbuf pointers, for
282 * collecting multisegment RX packets.
283 */
284 struct mbuf *fmp;
285 struct mbuf *lmp;
286 int wreg_nsegs;
287
288 /* Soft stats */
289 u_long rx_packets;
290
291 struct igb_dma rxdma;
292 } __cachealign;
293
294 struct igb_msix_data {
295 struct lwkt_serialize *msix_serialize;
296 struct lwkt_serialize msix_serialize0;
297 struct igb_softc *msix_sc;
298 uint32_t msix_mask;
299 struct igb_rx_ring *msix_rx;
300 struct igb_tx_ring *msix_tx;
301
302 driver_intr_t *msix_func;
303 void *msix_arg;
304
305 int msix_cpuid;
306 char msix_desc[32];
307 int msix_rid;
308 struct resource *msix_res;
309 void *msix_handle;
310 u_int msix_vector;
311 int msix_rate;
312 char msix_rate_desc[32];
313 } __cachealign;
314
315 struct igb_softc {
316 struct arpcom arpcom;
317 struct e1000_hw hw;
318
319 struct e1000_osdep osdep;
320 device_t dev;
321 uint32_t flags;
322 #define IGB_FLAG_SHARED_INTR 0x1
323 #define IGB_FLAG_HAS_MGMT 0x2
324
325 bus_dma_tag_t parent_tag;
326
327 int mem_rid;
328 struct resource *mem_res;
329
330 struct ifmedia media;
331 struct callout timer;
332 int timer_cpuid;
333
334 int intr_type;
335 int intr_rid;
336 struct resource *intr_res;
337 void *intr_tag;
338
339 int if_flags;
340 int max_frame_size;
341 int pause_frames;
342 uint16_t vf_ifp; /* a VF interface */
343
344 /* Management and WOL features */
345 int wol;
346
347 /* Info about the interface */
348 uint8_t link_active;
349 uint16_t link_speed;
350 uint16_t link_duplex;
351 uint32_t smartspeed;
352 uint32_t dma_coalesce;
353
354 /* Multicast array pointer */
355 uint8_t *mta;
356
357 int rx_npoll_off;
358 int tx_npoll_off;
359 int serialize_cnt;
360 struct lwkt_serialize **serializes;
361 struct lwkt_serialize main_serialize;
362
363 int intr_rate;
364 uint32_t intr_mask;
365 int sts_intr_bit;
366 uint32_t sts_intr_mask;
367
368 /*
369 * Transmit rings
370 */
371 int tx_ring_cnt;
372 int tx_ring_msix;
373 int tx_ring_inuse;
374 struct igb_tx_ring *tx_rings;
375
376 /*
377 * Receive rings
378 */
379 int rss_debug;
380 int rx_ring_cnt;
381 int rx_ring_msix;
382 int rx_ring_inuse;
383 struct igb_rx_ring *rx_rings;
384
385 /* Misc stats maintained by the driver */
386 u_long dropped_pkts;
387 u_long mbuf_defrag_failed;
388 u_long no_tx_dma_setup;
389 u_long watchdog_events;
390 u_long rx_overruns;
391 u_long device_control;
392 u_long rx_control;
393 u_long int_mask;
394 u_long eint_mask;
395 u_long packet_buf_alloc_rx;
396 u_long packet_buf_alloc_tx;
397
398 /* sysctl tree glue */
399 struct sysctl_ctx_list sysctl_ctx;
400 struct sysctl_oid *sysctl_tree;
401
402 void *stats;
403
404 int msix_mem_rid;
405 struct resource *msix_mem_res;
406 int msix_cnt;
407 struct igb_msix_data *msix_data;
408 };
409
410 #define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1)
411 #define IGB_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1)
412
413 struct igb_tx_buf {
414 struct mbuf *m_head;
415 bus_dmamap_t map; /* bus_dma map for packet */
416 };
417
418 struct igb_rx_buf {
419 struct mbuf *m_head;
420 bus_dmamap_t map; /* bus_dma map for packet */
421 bus_addr_t paddr;
422 };
423
424 #define UPDATE_VF_REG(reg, last, cur) \
425 { \
426 uint32_t new = E1000_READ_REG(hw, reg); \
427 if (new < last) \
428 cur += 0x100000000LL; \
429 last = new; \
430 cur &= 0xFFFFFFFF00000000LL; \
431 cur |= new; \
432 }
433
434 #define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc)
435 #define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc)
436
437 #define IGB_I210_LINK_DELAY 1000 /* unit: ms */
438
439 #endif /* _IF_IGB_H_ */
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