Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/mii_layer/e1000phyreg.h
Version:
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1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additonal Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 /* 33 * Marvell E1000 PHY registers 34 */ 35 36 #define E1000_MAX_REG_ADDRESS 0x1F 37 38 #define E1000_CR 0x00 /* control register */ 39 #define E1000_CR_SPEED_SELECT_MSB 0x0040 40 #define E1000_CR_COLL_TEST_ENABLE 0x0080 41 #define E1000_CR_FULL_DUPLEX 0x0100 42 #define E1000_CR_RESTART_AUTO_NEG 0x0200 43 #define E1000_CR_ISOLATE 0x0400 44 #define E1000_CR_POWER_DOWN 0x0800 45 #define E1000_CR_AUTO_NEG_ENABLE 0x1000 46 #define E1000_CR_SPEED_SELECT_LSB 0x2000 47 #define E1000_CR_LOOPBACK 0x4000 48 #define E1000_CR_RESET 0x8000 49 50 #define E1000_CR_SPEED_1000 0x0040 51 #define E1000_CR_SPEED_100 0x2000 52 #define E1000_CR_SPEED_10 0x0000 53 54 #define E1000_SR 0x01 /* status register */ 55 #define E1000_SR_EXTENDED 0x0001 56 #define E1000_SR_JABBER_DETECT 0x0002 57 #define E1000_SR_LINK_STATUS 0x0004 58 #define E1000_SR_AUTO_NEG 0x0008 59 #define E1000_SR_REMOTE_FAULT 0x0010 60 #define E1000_SR_AUTO_NEG_COMPLETE 0x0020 61 #define E1000_SR_PREAMBLE_SUPPRESS 0x0040 62 #define E1000_SR_EXTENDED_STATUS 0x0100 63 #define E1000_SR_100T2 0x0200 64 #define E1000_SR_100T2_FD 0x0400 65 #define E1000_SR_10T 0x0800 66 #define E1000_SR_10T_FD 0x1000 67 #define E1000_SR_100TX 0x2000 68 #define E1000_SR_100TX_FD 0x4000 69 #define E1000_SR_100T4 0x8000 70 71 #define E1000_ID1 0x02 /* ID register 1 */ 72 #define E1000_ID2 0x03 /* ID register 2 */ 73 #define E1000_ID_88E1000 0x01410C50 74 #define E1000_ID_88E1000S 0x01410C40 75 #define E1000_ID_88E1011 0x01410C20 76 #define E1000_ID_MASK 0xFFFFFFF0 77 78 #define E1000_AR 0x04 /* autonegotiation advertise reg */ 79 #define E1000_AR_SELECTOR_FIELD 0x0001 80 #define E1000_AR_10T 0x0020 81 #define E1000_AR_10T_FD 0x0040 82 #define E1000_AR_100TX 0x0080 83 #define E1000_AR_100TX_FD 0x0100 84 #define E1000_AR_100T4 0x0200 85 #define E1000_AR_PAUSE 0x0400 86 #define E1000_AR_ASM_DIR 0x0800 87 #define E1000_AR_REMOTE_FAULT 0x2000 88 #define E1000_AR_NEXT_PAGE 0x8000 89 #define E1000_AR_SPEED_MASK 0x01E0 90 91 /* Autonegotiation register bits for fiber cards (Alaska Only!) */ 92 #define E1000_FA_1000X_FD 0x0020 93 #define E1000_FA_1000X 0x0040 94 #define E1000_FA_SYM_PAUSE 0x0080 95 #define E1000_FA_ASYM_PAUSE 0x0100 96 #define E1000_FA_FAULT1 0x1000 97 #define E1000_FA_FAULT2 0x2000 98 #define E1000_FA_NEXT_PAGE 0x8000 99 100 #define E1000_LPAR 0x05 /* autoneg link partner abilities reg */ 101 #define E1000_LPAR_SELECTOR_FIELD 0x0001 102 #define E1000_LPAR_10T 0x0020 103 #define E1000_LPAR_10T_FD 0x0040 104 #define E1000_LPAR_100TX 0x0080 105 #define E1000_LPAR_100TX_FD 0x0100 106 #define E1000_LPAR_100T4 0x0200 107 #define E1000_LPAR_PAUSE 0x0400 108 #define E1000_LPAR_ASM_DIR 0x0800 109 #define E1000_LPAR_REMOTE_FAULT 0x2000 110 #define E1000_LPAR_ACKNOWLEDGE 0x4000 111 #define E1000_LPAR_NEXT_PAGE 0x8000 112 113 /* autoneg link partner ability register bits for fiber cards (Alaska Only!) */ 114 #define E1000_FPAR_1000X_FD 0x0020 115 #define E1000_FPAR_1000X 0x0040 116 #define E1000_FPAR_SYM_PAUSE 0x0080 117 #define E1000_FPAR_ASYM_PAUSE 0x0100 118 #define E1000_FPAR_FAULT1 0x1000 119 #define E1000_FPAR_FAULT2 0x2000 120 #define E1000_FPAR_ACK 0x4000 121 #define E1000_FPAR_NEXT_PAGE 0x8000 122 123 #define E1000_ER 0x06 /* autoneg expansion reg */ 124 #define E1000_ER_LP_NWAY 0x0001 125 #define E1000_ER_PAGE_RXD 0x0002 126 #define E1000_ER_NEXT_PAGE 0x0004 127 #define E1000_ER_LP_NEXT_PAGE 0x0008 128 #define E1000_ER_PAR_DETECT_FAULT 0x0100 129 130 #define E1000_NPTX 0x07 /* autoneg next page TX */ 131 #define E1000_NPTX_MSG_CODE_FIELD 0x0001 132 #define E1000_NPTX_TOGGLE 0x0800 133 #define E1000_NPTX_ACKNOWLDGE2 0x1000 134 #define E1000_NPTX_MSG_PAGE 0x2000 135 #define E1000_NPTX_NEXT_PAGE 0x8000 136 137 #define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */ 138 #define E1000_RNPR_MSG_CODE_FIELD 0x0001 139 #define E1000_RNPR_TOGGLE 0x0800 140 #define E1000_RNPR_ACKNOWLDGE2 0x1000 141 #define E1000_RNPR_MSG_PAGE 0x2000 142 #define E1000_RNPR_ACKNOWLDGE 0x4000 143 #define E1000_RNPR_NEXT_PAGE 0x8000 144 145 #define E1000_1GCR 0x09 /* 1000T (1G) control reg */ 146 #define E1000_1GCR_ASYM_PAUSE 0x0080 147 #define E1000_1GCR_1000T 0x0100 148 #define E1000_1GCR_1000T_FD 0x0200 149 #define E1000_1GCR_REPEATER_DTE 0x0400 150 #define E1000_1GCR_MS_VALUE 0x0800 151 #define E1000_1GCR_MS_ENABLE 0x1000 152 #define E1000_1GCR_TEST_MODE_NORMAL 0x0000 153 #define E1000_1GCR_TEST_MODE_1 0x2000 154 #define E1000_1GCR_TEST_MODE_2 0x4000 155 #define E1000_1GCR_TEST_MODE_3 0x6000 156 #define E1000_1GCR_TEST_MODE_4 0x8000 157 #define E1000_1GCR_SPEED_MASK 0x0300 158 159 #define E1000_1GSR 0x0A /* 1000T (1G) status reg */ 160 #define E1000_1GSR_IDLE_ERROR_CNT 0x0000 161 #define E1000_1GSR_ASYM_PAUSE_DIR 0x0100 162 #define E1000_1GSR_LP 0x0400 163 #define E1000_1GSR_LP_FD 0x0800 164 #define E1000_1GSR_REMOTE_RX_STATUS 0x1000 165 #define E1000_1GSR_LOCAL_RX_STATUS 0x2000 166 #define E1000_1GSR_MS_CONFIG_RES 0x4000 167 #define E1000_1GSR_MS_CONFIG_FAULT 0x8000 168 169 #define E1000_ESR 0x0F /* IEEE extended status reg */ 170 #define E1000_ESR_1000T 0x1000 171 #define E1000_ESR_1000T_FD 0x2000 172 #define E1000_ESR_1000X 0x4000 173 #define E1000_ESR_1000X_FD 0x8000 174 175 #define E1000_TX_POLARITY_MASK 0x0100 176 #define E1000_TX_NORMAL_POLARITY 0 177 178 #define E1000_AUTO_POLARITY_DISABLE 0x0010 179 180 #define E1000_SCR 0x10 /* special control register */ 181 #define E1000_SCR_JABBER_DISABLE 0x0001 182 #define E1000_SCR_POLARITY_REVERSAL 0x0002 183 #define E1000_SCR_SQE_TEST 0x0004 184 #define E1000_SCR_INT_FIFO_DISABLE 0x0008 185 #define E1000_SCR_CLK125_DISABLE 0x0010 186 #define E1000_SCR_MDI_MANUAL_MODE 0x0000 187 #define E1000_SCR_MDIX_MANUAL_MODE 0x0020 188 #define E1000_SCR_AUTO_X_1000T 0x0040 189 #define E1000_SCR_AUTO_X_MODE 0x0060 190 #define E1000_SCR_10BT_EXT_ENABLE 0x0080 191 #define E1000_SCR_MII_5BIT_ENABLE 0x0100 192 #define E1000_SCR_SCRAMBLER_DISABLE 0x0200 193 #define E1000_SCR_FORCE_LINK_GOOD 0x0400 194 #define E1000_SCR_ASSERT_CRS_ON_TX 0x0800 195 #define E1000_SCR_RX_FIFO_DEPTH_6 0x0000 196 #define E1000_SCR_RX_FIFO_DEPTH_8 0x1000 197 #define E1000_SCR_RX_FIFO_DEPTH_10 0x2000 198 #define E1000_SCR_RX_FIFO_DEPTH_12 0x3000 199 #define E1000_SCR_TX_FIFO_DEPTH_6 0x0000 200 #define E1000_SCR_TX_FIFO_DEPTH_8 0x4000 201 #define E1000_SCR_TX_FIFO_DEPTH_10 0x8000 202 #define E1000_SCR_TX_FIFO_DEPTH_12 0xC000 203 204 /* 88E3016 only */ 205 #define E1000_SCR_AUTO_MDIX 0x0030 206 #define E1000_SCR_SIGDET_POLARITY 0x0040 207 #define E1000_SCR_EXT_DISTANCE 0x0080 208 #define E1000_SCR_FEFI_DISABLE 0x0100 209 #define E1000_SCR_NLP_GEN_DISABLE 0x0800 210 #define E1000_SCR_LPNP 0x1000 211 #define E1000_SCR_NLP_CHK_DISABLE 0x2000 212 #define E1000_SCR_EN_DETECT 0x4000 213 214 #define E1000_SCR_EN_DETECT_MASK 0x0300 215 216 /* 88E1112 page 1 fiber specific control */ 217 #define E1000_SCR_FIB_TX_DIS 0x0008 218 #define E1000_SCR_FIB_SIGDET_POLARITY 0x0200 219 #define E1000_SCR_FIB_FORCE_LINK 0x0400 220 221 /* 88E1112 page 2 */ 222 #define E1000_SCR_MODE_MASK 0x0380 223 #define E1000_SCR_MODE_AUTO 0x0180 224 #define E1000_SCR_MODE_COPPER 0x0280 225 #define E1000_SCR_MODE_1000BX 0x0380 226 227 /* 88E1116 page 0 */ 228 #define E1000_SCR_POWER_DOWN 0x0004 229 /* 88E1116, 88E1149 page 2 */ 230 #define E1000_SCR_RGMII_POWER_UP 0x0008 231 232 /* 88E1116, 88E1149 page 3 */ 233 #define E1000_SCR_LED_STAT0_MASK 0x000F 234 #define E1000_SCR_LED_STAT1_MASK 0x00F0 235 #define E1000_SCR_LED_INIT_MASK 0x0F00 236 #define E1000_SCR_LED_LOS_MASK 0xF000 237 #define E1000_SCR_LED_STAT0(x) ((x) & E1000_SCR_LED_STAT0_MASK) 238 #define E1000_SCR_LED_STAT1(x) ((x) & E1000_SCR_LED_STAT1_MASK) 239 #define E1000_SCR_LED_INIT(x) ((x) & E1000_SCR_LED_INIT_MASK) 240 #define E1000_SCR_LED_LOS(x) ((x) & E1000_SCR_LED_LOS_MASK) 241 242 #define E1000_SSR 0x11 /* special status register */ 243 #define E1000_SSR_JABBER 0x0001 244 #define E1000_SSR_REV_POLARITY 0x0002 245 #define E1000_SSR_MDIX 0x0020 246 #define E1000_SSR_LINK 0x0400 247 #define E1000_SSR_SPD_DPLX_RESOLVED 0x0800 248 #define E1000_SSR_PAGE_RCVD 0x1000 249 #define E1000_SSR_DUPLEX 0x2000 250 #define E1000_SSR_SPEED 0xC000 251 #define E1000_SSR_10MBS 0x0000 252 #define E1000_SSR_100MBS 0x4000 253 #define E1000_SSR_1000MBS 0x8000 254 255 #define E1000_IER 0x12 /* interrupt enable reg */ 256 #define E1000_IER_JABBER 0x0001 257 #define E1000_IER_POLARITY_CHANGE 0x0002 258 #define E1000_IER_MDIX_CHANGE 0x0040 259 #define E1000_IER_FIFO_OVER_UNDERUN 0x0080 260 #define E1000_IER_FALSE_CARRIER 0x0100 261 #define E1000_IER_SYMBOL_ERROR 0x0200 262 #define E1000_IER_LINK_STAT_CHANGE 0x0400 263 #define E1000_IER_AUTO_NEG_COMPLETE 0x0800 264 #define E1000_IER_PAGE_RECEIVED 0x1000 265 #define E1000_IER_DUPLEX_CHANGED 0x2000 266 #define E1000_IER_SPEED_CHANGED 0x4000 267 #define E1000_IER_AUTO_NEG_ERR 0x8000 268 269 /* 88E1116, 88E1149 page 3, LED timer control. */ 270 #define E1000_PULSE_MASK 0x7000 271 #define E1000_PULSE_NO_STR 0 /* no pulse stretching */ 272 #define E1000_PULSE_21MS 1 /* 21 ms to 42 ms */ 273 #define E1000_PULSE_42MS 2 /* 42 ms to 84 ms */ 274 #define E1000_PULSE_84MS 3 /* 84 ms to 170 ms */ 275 #define E1000_PULSE_170MS 4 /* 170 ms to 340 ms */ 276 #define E1000_PULSE_340MS 5 /* 340 ms to 670 ms */ 277 #define E1000_PULSE_670MS 6 /* 670 ms to 1300 ms */ 278 #define E1000_PULSE_1300MS 7 /* 1300 ms to 2700 ms */ 279 #define E1000_PULSE_DUR(x) ((x) & E1000_PULSE_MASK) 280 281 #define E1000_BLINK_MASK 0x0700 282 #define E1000_BLINK_42MS 0 /* 42 ms */ 283 #define E1000_BLINK_84MS 1 /* 84 ms */ 284 #define E1000_BLINK_170MS 2 /* 170 ms */ 285 #define E1000_BLINK_340MS 3 /* 340 ms */ 286 #define E1000_BLINK_670MS 4 /* 670 ms */ 287 #define E1000_BLINK_RATE(x) ((x) & E1000_BLINK_MASK) 288 289 #define E1000_ISR 0x13 /* interrupt status reg */ 290 #define E1000_ISR_JABBER 0x0001 291 #define E1000_ISR_POLARITY_CHANGE 0x0002 292 #define E1000_ISR_MDIX_CHANGE 0x0040 293 #define E1000_ISR_FIFO_OVER_UNDERUN 0x0080 294 #define E1000_ISR_FALSE_CARRIER 0x0100 295 #define E1000_ISR_SYMBOL_ERROR 0x0200 296 #define E1000_ISR_LINK_STAT_CHANGE 0x0400 297 #define E1000_ISR_AUTO_NEG_COMPLETE 0x0800 298 #define E1000_ISR_PAGE_RECEIVED 0x1000 299 #define E1000_ISR_DUPLEX_CHANGED 0x2000 300 #define E1000_ISR_SPEED_CHANGED 0x4000 301 #define E1000_ISR_AUTO_NEG_ERR 0x8000 302 303 #define E1000_ESCR 0x14 /* extended special control reg */ 304 #define E1000_ESCR_FIBER_LOOPBACK 0x4000 305 #define E1000_ESCR_DOWN_NO_IDLE 0x8000 306 #define E1000_ESCR_TX_CLK_2_5 0x0060 307 #define E1000_ESCR_TX_CLK_25 0x0070 308 #define E1000_ESCR_TX_CLK_0 0x0000 309 310 #define E1000_RECR 0x15 /* RX error counter reg */ 311 312 #define E1000_EADR 0x16 /* extended address reg */ 313 314 #define E1000_LCR 0x18 /* LED control reg */ 315 #define E1000_LCR_LED_TX 0x0001 316 #define E1000_LCR_LED_RX 0x0002 317 #define E1000_LCR_LED_DUPLEX 0x0004 318 #define E1000_LCR_LINK 0x0008 319 #define E1000_LCR_BLINK_42MS 0x0000 320 #define E1000_LCR_BLINK_84MS 0x0100 321 #define E1000_LCR_BLINK_170MS 0x0200 322 #define E1000_LCR_BLINK_340MS 0x0300 323 #define E1000_LCR_BLINK_670MS 0x0400 324 #define E1000_LCR_PULSE_OFF 0x0000 325 #define E1000_LCR_PULSE_21_42MS 0x1000 326 #define E1000_LCR_PULSE_42_84MS 0x2000 327 #define E1000_LCR_PULSE_84_170MS 0x3000 328 #define E1000_LCR_PULSE_170_340MS 0x4000 329 #define E1000_LCR_PULSE_340_670MS 0x5000 330 #define E1000_LCR_PULSE_670_13S 0x6000 331 #define E1000_LCR_PULSE_13_26S 0x7000 332 333 /* The following register is found only on the 88E1011 Alaska PHY */ 334 #define E1000_ESSR 0x1B /* Extended PHY specific sts */ 335 #define E1000_ESSR_FIBER_LINK 0x2000 336 #define E1000_ESSR_GMII_COPPER 0x000f 337 #define E1000_ESSR_GMII_FIBER 0x0007 338 #define E1000_ESSR_TBI_COPPER 0x000d 339 #define E1000_ESSR_TBI_FIBER 0x0005
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