Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/mn/if_mn.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * ---------------------------------------------------------------------------- 3 * "THE BEER-WARE LICENSE" (Revision 42): 4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you 5 * can do whatever you want with this stuff. If we meet some day, and you think 6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 7 * ---------------------------------------------------------------------------- 8 * 9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $ 10 * 11 * Driver for Siemens reference design card "Easy321-R1". 12 * 13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 14 * controller. 15 * 16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 17 * check it coming in. 18 * 19 * The FALC54 and MUNICH32X have far too many registers and weird modes for 20 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 21 * you will (badly!) need the documentation anyway if you want to mess with 22 * this gadget. 23 * 24 * $FreeBSD: src/sys/pci/if_mn.c,v 1.11.2.3 2001/01/23 12:47:09 phk Exp $ 25 */ 26 27 /* 28 * Stuff to describe the MUNIC32X and FALC54 chips. 29 */ 30 31 #define M32_CHAN 32 /* We have 32 channels */ 32 #define M32_TS 32 /* We have 32 timeslots */ 33 34 #define NG_MN_NODE_TYPE "mn" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/sysctl.h> 40 #include <sys/bus.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/rman.h> 44 45 #include <bus/pci/pcireg.h> 46 #include <bus/pci/pcivar.h> 47 #include "pci_if.h" 48 49 #include <machine/clock.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 54 #include <netgraph/ng_message.h> 55 #include <netgraph/netgraph.h> 56 57 58 static int mn_maxlatency = 1000; 59 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 60 &mn_maxlatency, 0, 61 "The number of milliseconds a packet is allowed to spend in the output queue. " 62 "If the output queue is longer than this number of milliseconds when the packet " 63 "arrives for output, the packet will be dropped." 64 ); 65 66 #ifndef NMN 67 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 68 #define NMN 4 69 #endif 70 71 /* From: PEB 20321 data sheet, p187, table 22 */ 72 struct m32xreg { 73 u_int32_t conf, cmd, stat, imask; 74 u_int32_t fill10, piqba, piql, fill1c; 75 u_int32_t mode1, mode2, ccba, txpoll; 76 u_int32_t tiqba, tiql, riqba, riql; 77 u_int32_t lconf, lccba, fill48, ltran; 78 u_int32_t ltiqba, ltiql, lriqba, lriql; 79 u_int32_t lreg0, lreg1, lreg2, lreg3; 80 u_int32_t lreg4, lreg5, lre6, lstat; 81 u_int32_t gpdir, gpdata, gpod, fill8c; 82 u_int32_t ssccon, sscbr, ssctb, sscrb; 83 u_int32_t ssccse, sscim, fillab, fillac; 84 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 85 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 86 u_int32_t iomtmo, iomrmo, filld8, filldc; 87 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 88 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 89 }; 90 91 /* From: PEB 2254 data sheet, p80, table 10 */ 92 struct f54wreg { 93 u_int16_t xfifo; 94 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 95 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 96 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 97 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 98 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 99 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 100 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 101 u_int8_t lim2, fill39[7]; 102 u_int8_t fill40[8]; 103 u_int8_t fill48[8]; 104 u_int8_t fill50[8]; 105 u_int8_t fill58[8]; 106 u_int8_t dec, fill61, test2, fill63[5]; 107 u_int8_t fill68[8]; 108 u_int8_t xs[16]; 109 }; 110 111 /* From: PEB 2254 data sheet, p117, table 10 */ 112 struct f54rreg { 113 u_int16_t rfifo; 114 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 115 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 116 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 117 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 118 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 119 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 120 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 121 u_int8_t lim2, fill39[7]; 122 u_int8_t fill40[8]; 123 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 124 u_int16_t fec, cvc, cec1, ebc; 125 u_int16_t cec2, cec3; 126 u_int8_t rsa4, rsa5, rsa6, rsa7; 127 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 128 u_int16_t rbc; 129 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 130 u_int8_t rs[16]; 131 }; 132 133 /* Transmit & receive descriptors */ 134 struct trxd { 135 u_int32_t flags; 136 vm_offset_t next; 137 vm_offset_t data; 138 u_int32_t status; /* only used for receive */ 139 struct mbuf *m; /* software use only */ 140 struct trxd *vnext; /* software use only */ 141 }; 142 143 /* Channel specification */ 144 struct cspec { 145 u_int32_t flags; 146 vm_offset_t rdesc; 147 vm_offset_t tdesc; 148 u_int32_t itbs; 149 }; 150 151 struct m32_mem { 152 vm_offset_t csa; 153 u_int32_t ccb; 154 u_int32_t reserve1[2]; 155 u_int32_t ts[M32_TS]; 156 struct cspec cs[M32_CHAN]; 157 vm_offset_t crxd[M32_CHAN]; 158 vm_offset_t ctxd[M32_CHAN]; 159 }; 160 161 struct softc; 162 struct sockaddr; 163 struct rtentry; 164 165 static int mn_probe (device_t self); 166 static int mn_attach (device_t self); 167 static void mn_create_channel(struct softc *sc, int chan); 168 static int mn_reset(struct softc *sc); 169 static struct trxd * mn_alloc_desc(void); 170 static void mn_free_desc(struct trxd *dp); 171 static void mn_intr(void *xsc); 172 static u_int32_t mn_parse_ts(const char *s, int *nbit); 173 #ifdef notyet 174 static void m32_dump(struct softc *sc); 175 static void f54_dump(struct softc *sc); 176 static void mn_fmt_ts(char *p, u_int32_t ts); 177 #endif /* notyet */ 178 static void f54_init(struct softc *sc); 179 180 static ng_constructor_t ngmn_constructor; 181 static ng_rcvmsg_t ngmn_rcvmsg; 182 static ng_shutdown_t ngmn_shutdown; 183 static ng_newhook_t ngmn_newhook; 184 static ng_connect_t ngmn_connect; 185 static ng_rcvdata_t ngmn_rcvdata; 186 static ng_disconnect_t ngmn_disconnect; 187 188 static struct ng_type mntypestruct = { 189 NG_VERSION, 190 NG_MN_NODE_TYPE, 191 NULL, 192 ngmn_constructor, 193 ngmn_rcvmsg, 194 ngmn_shutdown, 195 ngmn_newhook, 196 NULL, 197 ngmn_connect, 198 ngmn_rcvdata, 199 ngmn_rcvdata, 200 ngmn_disconnect, 201 NULL 202 }; 203 204 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 205 206 #define NIQB 64 207 208 struct schan { 209 enum {DOWN, UP} state; 210 struct softc *sc; 211 int chan; 212 u_int32_t ts; 213 char name[8]; 214 struct trxd *r1, *rl; 215 struct trxd *x1, *xl; 216 hook_p hook; 217 218 time_t last_recv; 219 time_t last_rxerr; 220 time_t last_xmit; 221 222 u_long rx_error; 223 224 u_long short_error; 225 u_long crc_error; 226 u_long dribble_error; 227 u_long long_error; 228 u_long abort_error; 229 u_long overflow_error; 230 231 int last_error; 232 int prev_error; 233 234 u_long tx_pending; 235 u_long tx_limit; 236 }; 237 238 enum framing {WHOKNOWS, E1, E1U, T1, T1U}; 239 240 struct softc { 241 int unit; 242 device_t dev; 243 struct resource *irq; 244 void *intrhand; 245 enum framing framing; 246 int nhooks; 247 void *m0v, *m1v; 248 vm_offset_t m0p, m1p; 249 struct m32xreg *m32x; 250 struct f54wreg *f54w; 251 struct f54rreg *f54r; 252 struct m32_mem m32_mem; 253 u_int32_t tiqb[NIQB]; 254 u_int32_t riqb[NIQB]; 255 u_int32_t piqb[NIQB]; 256 u_int32_t ltiqb[NIQB]; 257 u_int32_t lriqb[NIQB]; 258 char name[8]; 259 u_int32_t falc_irq, falc_state, framer_state; 260 struct schan *ch[M32_CHAN]; 261 char nodename[NG_NODESIZ]; 262 node_p node; 263 264 u_long cnt_fec; 265 u_long cnt_cvc; 266 u_long cnt_cec1; 267 u_long cnt_ebc; 268 u_long cnt_cec2; 269 u_long cnt_cec3; 270 u_long cnt_rbc; 271 }; 272 273 static int 274 ngmn_constructor(node_p *nodep) 275 { 276 277 return (EINVAL); 278 } 279 280 static int 281 ngmn_shutdown(node_p nodep) 282 { 283 284 return (EINVAL); 285 } 286 287 static void 288 ngmn_config(node_p node, char *set, char *ret) 289 { 290 struct softc *sc; 291 enum framing wframing; 292 293 sc = node->private; 294 295 if (set != NULL) { 296 if (!strncmp(set, "line ", 5)) { 297 wframing = sc->framing; 298 if (!strcmp(set, "line e1")) { 299 wframing = E1; 300 } else if (!strcmp(set, "line e1u")) { 301 wframing = E1U; 302 } else { 303 strcat(ret, "ENOGROK\n"); 304 return; 305 } 306 if (wframing == sc->framing) 307 return; 308 if (sc->nhooks > 0) { 309 ksprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks); 310 return; 311 } 312 sc->framing = wframing; 313 #if 1 314 f54_init(sc); 315 #else 316 mn_reset(sc); 317 #endif 318 } else { 319 kprintf("%s CONFIG SET [%s]\n", sc->nodename, set); 320 strcat(ret, "ENOGROK\n"); 321 return; 322 } 323 } 324 325 } 326 327 static int 328 ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 329 { 330 struct softc *sc; 331 struct schan *sch; 332 char *s, *r; 333 int pos, i; 334 335 sc = node->private; 336 337 if (msg->header.typecookie != NGM_GENERIC_COOKIE) { 338 if (resp != NULL) 339 *resp = NULL; 340 kfree(msg, M_NETGRAPH); 341 return (EINVAL); 342 } 343 344 if (msg->header.cmd != NGM_TEXT_CONFIG && 345 msg->header.cmd != NGM_TEXT_STATUS) { 346 if (resp != NULL) 347 *resp = NULL; 348 kfree(msg, M_NETGRAPH); 349 return (EINVAL); 350 } 351 352 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 353 M_INTWAIT); 354 if (*resp == NULL) { 355 kfree(msg, M_NETGRAPH); 356 return (ENOMEM); 357 } 358 359 if (msg->header.arglen) 360 s = (char *)msg->data; 361 else 362 s = NULL; 363 r = (char *)(*resp)->data; 364 *r = '\0'; 365 366 if (msg->header.cmd == NGM_TEXT_CONFIG) { 367 ngmn_config(node, s, r); 368 (*resp)->header.arglen = strlen(r) + 1; 369 kfree(msg, M_NETGRAPH); 370 return (0); 371 } 372 373 pos = 0; 374 pos += ksprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\2" 375 "\40LOS\37AIS\36LFA\35RRA" 376 "\34AUXP\33NMF\32LMFA\31frs0.0" 377 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 378 "\24TS16LFA\23frs1.2\22XLS\21XLO" 379 "\20RS1\17rsw.6\16RRA\15RY0" 380 "\14RY1\13RY2\12RY3\11RY4" 381 "\10SI1\7SI2\6rsp.5\5rsp.4" 382 "\4rsp.3\3RSIF\2RS13\1RS15"); 383 pos += ksprintf(pos + r," Framing errors: %lu", sc->cnt_fec); 384 pos += ksprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc); 385 386 pos += ksprintf(pos + r," Falc State %b;\n", sc->falc_state, "\2" 387 "\40LOS\37AIS\36LFA\35RRA" 388 "\34AUXP\33NMF\32LMFA\31frs0.0" 389 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 390 "\24TS16LFA\23frs1.2\22XLS\21XLO" 391 "\20RS1\17rsw.6\16RRA\15RY0" 392 "\14RY1\13RY2\12RY3\11RY4" 393 "\10SI1\7SI2\6rsp.5\5rsp.4" 394 "\4rsp.3\3RSIF\2RS13\1RS15"); 395 pos += ksprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\2" 396 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 397 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 398 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 399 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 400 for (i = 0; i < M32_CHAN; i++) { 401 if (!sc->ch[i]) 402 continue; 403 sch = sc->ch[i]; 404 405 pos += ksprintf(r + pos, " Chan %d <%s> ", 406 i, sch->hook->name); 407 408 pos += ksprintf(r + pos, " Last Rx: "); 409 if (sch->last_recv) 410 pos += ksprintf(r + pos, "%lu s", time_uptime - sch->last_recv); 411 else 412 pos += ksprintf(r + pos, "never"); 413 414 pos += ksprintf(r + pos, ", last RxErr: "); 415 if (sch->last_rxerr) 416 pos += ksprintf(r + pos, "%lu s", time_uptime - sch->last_rxerr); 417 else 418 pos += ksprintf(r + pos, "never"); 419 420 pos += ksprintf(r + pos, ", last Tx: "); 421 if (sch->last_xmit) 422 pos += ksprintf(r + pos, "%lu s\n", time_uptime - sch->last_xmit); 423 else 424 pos += ksprintf(r + pos, "never\n"); 425 426 pos += ksprintf(r + pos, " RX error(s) %lu", sch->rx_error); 427 pos += ksprintf(r + pos, " Short: %lu", sch->short_error); 428 pos += ksprintf(r + pos, " CRC: %lu", sch->crc_error); 429 pos += ksprintf(r + pos, " Mod8: %lu", sch->dribble_error); 430 pos += ksprintf(r + pos, " Long: %lu", sch->long_error); 431 pos += ksprintf(r + pos, " Abort: %lu", sch->abort_error); 432 pos += ksprintf(r + pos, " Overflow: %lu\n", sch->overflow_error); 433 434 pos += ksprintf(r + pos, " Last error: %b Prev error: %b\n", 435 sch->last_error, "\2\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 436 sch->prev_error, "\2\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 437 pos += ksprintf(r + pos, " Xmit bytes pending %ld\n", 438 sch->tx_pending); 439 } 440 (*resp)->header.arglen = pos + 1; 441 kfree(msg, M_NETGRAPH); 442 return (0); 443 } 444 445 static int 446 ngmn_newhook(node_p node, hook_p hook, const char *name) 447 { 448 u_int32_t ts, chan; 449 struct softc *sc; 450 int nbit; 451 452 sc = node->private; 453 454 if (name[0] != 't' || name[1] != 's') 455 return (EINVAL); 456 457 ts = mn_parse_ts(name + 2, &nbit); 458 kprintf("%d bits %x\n", nbit, ts); 459 if (sc->framing == E1 && (ts & 1)) 460 return (EINVAL); 461 if (sc->framing == E1U && nbit != 32) 462 return (EINVAL); 463 if (ts == 0) 464 return (EINVAL); 465 if (sc->framing == E1) 466 chan = ffs(ts) - 1; 467 else 468 chan = 1; 469 if (!sc->ch[chan]) 470 mn_create_channel(sc, chan); 471 else if (sc->ch[chan]->state == UP) 472 return (EBUSY); 473 sc->ch[chan]->ts = ts; 474 sc->ch[chan]->hook = hook; 475 sc->ch[chan]->tx_limit = nbit * 8; 476 hook->private = sc->ch[chan]; 477 sc->nhooks++; 478 return(0); 479 } 480 481 482 static struct trxd *mn_desc_free; 483 484 static struct trxd * 485 mn_alloc_desc(void) 486 { 487 struct trxd *dp; 488 489 dp = mn_desc_free; 490 if (dp) 491 mn_desc_free = dp->vnext; 492 else 493 dp = (struct trxd *)kmalloc(sizeof *dp, M_MN, M_INTWAIT); 494 return (dp); 495 } 496 497 static void 498 mn_free_desc(struct trxd *dp) 499 { 500 dp->vnext = mn_desc_free; 501 mn_desc_free = dp; 502 } 503 504 static u_int32_t 505 mn_parse_ts(const char *s, int *nbit) 506 { 507 unsigned r; 508 int i, j; 509 char *p; 510 511 r = 0; 512 j = -1; 513 *nbit = 0; 514 while(*s) { 515 i = strtol(s, &p, 0); 516 if (i < 0 || i > 31) 517 return (0); 518 while (j != -1 && j < i) { 519 r |= 1 << j++; 520 (*nbit)++; 521 } 522 j = -1; 523 r |= 1 << i; 524 (*nbit)++; 525 if (*p == ',') { 526 s = p + 1; 527 continue; 528 } else if (*p == '-') { 529 j = i + 1; 530 s = p + 1; 531 continue; 532 } else if (!*p) { 533 break; 534 } else { 535 return (0); 536 } 537 } 538 return (r); 539 } 540 541 #ifdef notyet 542 static void 543 mn_fmt_ts(char *p, u_int32_t ts) 544 { 545 char *s; 546 int j; 547 548 s = ""; 549 ts &= 0xffffffff; 550 for (j = 0; j < 32; j++) { 551 if (!(ts & (1 << j))) 552 continue; 553 ksprintf(p, "%s%d", s, j); 554 p += strlen(p); 555 s = ","; 556 if (!(ts & (1 << (j+1)))) 557 continue; 558 for (; j < 32; j++) 559 if (!(ts & (1 << (j+1)))) 560 break; 561 ksprintf(p, "-%d", j); 562 p += strlen(p); 563 s = ","; 564 } 565 } 566 #endif /* notyet */ 567 568 /* 569 * OUTPUT 570 */ 571 572 static int 573 ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 574 { 575 struct mbuf *m2; 576 struct trxd *dp, *dp2; 577 struct schan *sch; 578 struct softc *sc; 579 int chan, pitch, len; 580 581 sch = hook->private; 582 sc = sch->sc; 583 chan = sch->chan; 584 585 if (sch->state != UP) { 586 NG_FREE_DATA(m, meta); 587 return (0); 588 } 589 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 590 NG_FREE_DATA(m, meta); 591 return (0); 592 } 593 NG_FREE_META(meta); 594 pitch = 0; 595 m2 = m; 596 dp2 = sc->ch[chan]->xl; 597 len = m->m_pkthdr.len; 598 while (len) { 599 dp = mn_alloc_desc(); 600 if (!dp) { 601 pitch++; 602 m_freem(m); 603 sc->ch[chan]->xl = dp2; 604 dp = dp2->vnext; 605 while (dp) { 606 dp2 = dp->vnext; 607 mn_free_desc(dp); 608 dp = dp2; 609 } 610 sc->ch[chan]->xl->vnext = NULL; 611 break; 612 } 613 dp->data = vtophys(m2->m_data); 614 dp->flags = m2->m_len << 16; 615 dp->flags += 1; 616 len -= m2->m_len; 617 dp->next = vtophys(dp); 618 dp->vnext = NULL; 619 sc->ch[chan]->xl->next = vtophys(dp); 620 sc->ch[chan]->xl->vnext = dp; 621 sc->ch[chan]->xl = dp; 622 if (!len) { 623 dp->m = m; 624 dp->flags |= 0xc0000000; 625 dp2->flags &= ~0x40000000; 626 } else { 627 dp->m = NULL; 628 m2 = m2->m_next; 629 } 630 } 631 if (pitch) 632 kprintf("%s%d: Short on mem, pitched %d packets\n", 633 sc->name, chan, pitch); 634 else { 635 #if 0 636 kprintf("%d = %d + %d (%p)\n", 637 sch->tx_pending + m->m_pkthdr.len, 638 sch->tx_pending , m->m_pkthdr.len, m); 639 #endif 640 sch->tx_pending += m->m_pkthdr.len; 641 sc->m32x->txpoll &= ~(1 << chan); 642 } 643 return (0); 644 } 645 646 /* 647 * OPEN 648 */ 649 static int 650 ngmn_connect(hook_p hook) 651 { 652 int i, nts, chan; 653 struct trxd *dp, *dp2; 654 struct mbuf *m; 655 struct softc *sc; 656 struct schan *sch; 657 u_int32_t u; 658 659 sch = hook->private; 660 chan = sch->chan; 661 sc = sch->sc; 662 663 if (sch->state == UP) 664 return (0); 665 sch->state = UP; 666 667 /* Count and configure the timeslots for this channel */ 668 for (nts = i = 0; i < 32; i++) 669 if (sch->ts & (1 << i)) { 670 sc->m32_mem.ts[i] = 0x00ff00ff | 671 (chan << 24) | (chan << 8); 672 nts++; 673 } 674 675 /* Init the receiver & xmitter to HDLC */ 676 sc->m32_mem.cs[chan].flags = 0x80e90006; 677 /* Allocate two buffers per timeslot */ 678 if (nts == 32) 679 sc->m32_mem.cs[chan].itbs = 63; 680 else 681 sc->m32_mem.cs[chan].itbs = nts * 2; 682 683 /* Setup a transmit chain with one descriptor */ 684 /* XXX: we actually send a 1 byte packet */ 685 dp = mn_alloc_desc(); 686 MGETHDR(m, MB_WAIT, MT_DATA); 687 if (m == NULL) 688 return (ENOBUFS); 689 m->m_pkthdr.len = 0; 690 dp->m = m; 691 dp->flags = 0xc0000000 + (1 << 16); 692 dp->next = vtophys(dp); 693 dp->vnext = NULL; 694 dp->data = vtophys(sc->name); 695 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 696 sc->ch[chan]->x1 = dp; 697 sc->ch[chan]->xl = dp; 698 699 /* Setup a receive chain with 5 + NTS descriptors */ 700 701 dp = mn_alloc_desc(); 702 m = NULL; 703 MGETHDR(m, MB_WAIT, MT_DATA); 704 if (m == NULL) { 705 mn_free_desc(dp); 706 return (ENOBUFS); 707 } 708 MCLGET(m, MB_WAIT); 709 if ((m->m_flags & M_EXT) == 0) { 710 mn_free_desc(dp); 711 m_freem(m); 712 return (ENOBUFS); 713 } 714 dp->m = m; 715 dp->data = vtophys(m->m_data); 716 dp->flags = 0x40000000; 717 dp->flags += 1600 << 16; 718 dp->next = vtophys(dp); 719 dp->vnext = NULL; 720 sc->ch[chan]->rl = dp; 721 722 for (i = 0; i < (nts + 10); i++) { 723 dp2 = dp; 724 dp = mn_alloc_desc(); 725 m = NULL; 726 MGETHDR(m, MB_WAIT, MT_DATA); 727 if (m == NULL) { 728 mn_free_desc(dp); 729 m_freem(m); 730 return (ENOBUFS); 731 } 732 MCLGET(m, MB_WAIT); 733 if ((m->m_flags & M_EXT) == 0) { 734 mn_free_desc(dp); 735 m_freem(m); 736 return (ENOBUFS); 737 } 738 dp->m = m; 739 dp->data = vtophys(m->m_data); 740 dp->flags = 0x00000000; 741 dp->flags += 1600 << 16; 742 dp->next = vtophys(dp2); 743 dp->vnext = dp2; 744 } 745 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 746 sc->ch[chan]->r1 = dp; 747 748 /* Initialize this channel */ 749 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 750 sc->m32x->cmd = 0x1; 751 DELAY(1000); 752 u = sc->m32x->stat; 753 if (!(u & 1)) 754 kprintf("%s: init chan %d stat %08x\n", sc->name, chan, u); 755 sc->m32x->stat = 1; 756 757 return (0); 758 } 759 760 /* 761 * CLOSE 762 */ 763 static int 764 ngmn_disconnect(hook_p hook) 765 { 766 int chan, i; 767 struct softc *sc; 768 struct schan *sch; 769 struct trxd *dp, *dp2; 770 u_int32_t u; 771 772 sch = hook->private; 773 chan = sch->chan; 774 sc = sch->sc; 775 776 if (sch->state == DOWN) 777 return (0); 778 sch->state = DOWN; 779 780 /* Set receiver & transmitter off */ 781 sc->m32_mem.cs[chan].flags = 0x80920006; 782 sc->m32_mem.cs[chan].itbs = 0; 783 784 /* free the timeslots */ 785 for (i = 0; i < 32; i++) 786 if (sc->ch[chan]->ts & (1 << i)) 787 sc->m32_mem.ts[i] = 0x20002000; 788 789 /* Initialize this channel */ 790 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 791 sc->m32x->cmd = 0x1; 792 DELAY(30); 793 u = sc->m32x->stat; 794 if (!(u & 1)) 795 kprintf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 796 sc->m32x->stat = 1; 797 798 /* Free all receive descriptors and mbufs */ 799 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 800 if (dp->m) 801 m_freem(dp->m); 802 sc->ch[chan]->r1 = dp2 = dp->vnext; 803 mn_free_desc(dp); 804 } 805 806 /* Free all transmit descriptors and mbufs */ 807 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 808 if (dp->m) { 809 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 810 m_freem(dp->m); 811 } 812 sc->ch[chan]->x1 = dp2 = dp->vnext; 813 mn_free_desc(dp); 814 } 815 sc->nhooks--; 816 return(0); 817 } 818 819 /* 820 * Create a new channel. 821 */ 822 static void 823 mn_create_channel(struct softc *sc, int chan) 824 { 825 struct schan *sch; 826 827 sch = sc->ch[chan] = (struct schan *)kmalloc(sizeof *sc->ch[chan], 828 M_MN, M_WAITOK | M_ZERO); 829 sch->sc = sc; 830 sch->state = DOWN; 831 sch->chan = chan; 832 ksprintf(sch->name, "%s%d", sc->name, chan); 833 return; 834 } 835 836 #ifdef notyet 837 /* 838 * Dump Munich32x state 839 */ 840 static void 841 m32_dump(struct softc *sc) 842 { 843 u_int32_t *tp4; 844 int i, j; 845 846 kprintf("mn%d: MUNICH32X dump\n", sc->unit); 847 tp4 = (u_int32_t *)sc->m0v; 848 for(j = 0; j < 64; j += 8) { 849 kprintf("%02x", j * sizeof *tp4); 850 for(i = 0; i < 8; i++) 851 kprintf(" %08x", tp4[i+j]); 852 kprintf("\n"); 853 } 854 for(j = 0; j < M32_CHAN; j++) { 855 if (!sc->ch[j]) 856 continue; 857 kprintf("CH%d: state %d ts %08x", 858 j, sc->ch[j]->state, sc->ch[j]->ts); 859 kprintf(" %08x %08x %08x %08x %08x %08x\n", 860 sc->m32_mem.cs[j].flags, 861 sc->m32_mem.cs[j].rdesc, 862 sc->m32_mem.cs[j].tdesc, 863 sc->m32_mem.cs[j].itbs, 864 sc->m32_mem.crxd[j], 865 sc->m32_mem.ctxd[j] ); 866 } 867 } 868 869 /* 870 * Dump Falch54 state 871 */ 872 static void 873 f54_dump(struct softc *sc) 874 { 875 u_int8_t *tp1; 876 int i, j; 877 878 kprintf("%s: FALC54 dump\n", sc->name); 879 tp1 = (u_int8_t *)sc->m1v; 880 for(j = 0; j < 128; j += 16) { 881 kprintf("%s: %02x |", sc->name, j * sizeof *tp1); 882 for(i = 0; i < 16; i++) 883 kprintf(" %02x", tp1[i+j]); 884 kprintf("\n"); 885 } 886 } 887 #endif /* notyet */ 888 889 /* 890 * Init Munich32x 891 */ 892 static void 893 m32_init(struct softc *sc) 894 { 895 896 sc->m32x->conf = 0x00000000; 897 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 898 #if 1 899 sc->m32x->mode2 = 0x00000081; 900 sc->m32x->txpoll = 0xffffffff; 901 #elif 1 902 sc->m32x->mode2 = 0x00000081; 903 sc->m32x->txpoll = 0xffffffff; 904 #else 905 sc->m32x->mode2 = 0x00000101; 906 #endif 907 sc->m32x->lconf = 0x6060009B; 908 sc->m32x->imask = 0x00000000; 909 } 910 911 /* 912 * Init the Falc54 913 */ 914 static void 915 f54_init(struct softc *sc) 916 { 917 sc->f54w->ipc = 0x07; 918 919 sc->f54w->xpm0 = 0xbd; 920 sc->f54w->xpm1 = 0x03; 921 sc->f54w->xpm2 = 0x00; 922 923 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 924 sc->f54w->imr1 = 0x08; /* XMB */ 925 sc->f54w->imr2 = 0x00; 926 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 927 sc->f54w->imr4 = 0x00; 928 929 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 930 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 931 if (sc->framing == E1) 932 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 933 else if (sc->framing == E1U) 934 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */ 935 936 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 937 sc->f54w->pcd = 0x0a; 938 sc->f54w->pcr = 0x15; 939 sc->f54w->xsw = 0x9f; /* fmr4 */ 940 if (sc->framing == E1) 941 sc->f54w->xsp = 0x1c; /* fmr5 */ 942 else if (sc->framing == E1U) 943 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */ 944 sc->f54w->xc0 = 0x07; 945 sc->f54w->xc1 = 0x3d; 946 sc->f54w->rc0 = 0x05; 947 sc->f54w->rc1 = 0x00; 948 sc->f54w->cmdr = 0x51; 949 } 950 951 static int 952 mn_reset(struct softc *sc) 953 { 954 u_int32_t u; 955 int i; 956 957 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 958 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 959 960 bzero(sc->tiqb, sizeof sc->tiqb); 961 sc->m32x->tiqba = vtophys(&sc->tiqb); 962 sc->m32x->tiql = NIQB / 16 - 1; 963 964 bzero(sc->riqb, sizeof sc->riqb); 965 sc->m32x->riqba = vtophys(&sc->riqb); 966 sc->m32x->riql = NIQB / 16 - 1; 967 968 bzero(sc->ltiqb, sizeof sc->ltiqb); 969 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 970 sc->m32x->ltiql = NIQB / 16 - 1; 971 972 bzero(sc->lriqb, sizeof sc->lriqb); 973 sc->m32x->lriqba = vtophys(&sc->lriqb); 974 sc->m32x->lriql = NIQB / 16 - 1; 975 976 bzero(sc->piqb, sizeof sc->piqb); 977 sc->m32x->piqba = vtophys(&sc->piqb); 978 sc->m32x->piql = NIQB / 16 - 1; 979 980 m32_init(sc); 981 f54_init(sc); 982 983 u = sc->m32x->stat; 984 sc->m32x->stat = u; 985 sc->m32_mem.ccb = 0x4; 986 sc->m32x->cmd = 0x1; 987 DELAY(1000); 988 u = sc->m32x->stat; 989 sc->m32x->stat = u; 990 991 /* set all timeslots to known state */ 992 for (i = 0; i < 32; i++) 993 sc->m32_mem.ts[i] = 0x20002000; 994 995 if (!(u & 1)) { 996 kprintf( 997 "mn%d: WARNING: Controller failed the PCI bus-master test.\n" 998 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 999 sc->unit, sc->unit); 1000 return (0); 1001 } 1002 return (1); 1003 } 1004 1005 /* 1006 * FALC54 interrupt handling 1007 */ 1008 static void 1009 f54_intr(struct softc *sc) 1010 { 1011 unsigned u, s; 1012 #if 0 1013 unsigned g; 1014 g = sc->f54r->gis; 1015 #endif 1016 u = sc->f54r->isr0 << 24; 1017 u |= sc->f54r->isr1 << 16; 1018 u |= sc->f54r->isr2 << 8; 1019 u |= sc->f54r->isr3; 1020 sc->falc_irq = u; 1021 /* don't chat about the 1 sec heart beat */ 1022 if (u & ~0x40) { 1023 #if 0 1024 kprintf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\2" 1025 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 1026 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 1027 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 1028 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 1029 #endif 1030 s = sc->f54r->frs0 << 24; 1031 s |= sc->f54r->frs1 << 16; 1032 s |= sc->f54r->rsw << 8; 1033 s |= sc->f54r->rsp; 1034 sc->falc_state = s; 1035 1036 s &= ~0x01844038; /* undefined or static bits */ 1037 s &= ~0x00009fc7; /* bits we don't care about */ 1038 s &= ~0x00780000; /* XXX: TS16 related */ 1039 s &= ~0x06000000; /* XXX: Multiframe related */ 1040 #if 0 1041 kprintf("%s*: FALC54 Status %b\n", sc->name, s, "\2" 1042 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 1043 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 1044 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 1045 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 1046 #endif 1047 if (s != sc->framer_state) { 1048 #if 0 1049 for (i = 0; i < M32_CHAN; i++) { 1050 if (!sc->ch[i]) 1051 continue; 1052 sp = &sc->ch[i]->ifsppp; 1053 if (!(sp->pp_if.if_flags & IFF_UP)) 1054 continue; 1055 if (s) 1056 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 1057 else 1058 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 1059 } 1060 #endif 1061 sc->framer_state = s; 1062 } 1063 } 1064 /* Once per second check error counters */ 1065 /* XXX: not clear if this is actually ok */ 1066 if (!(u & 0x40)) 1067 return; 1068 sc->cnt_fec += sc->f54r->fec; 1069 sc->cnt_cvc += sc->f54r->cvc; 1070 sc->cnt_cec1 += sc->f54r->cec1; 1071 sc->cnt_ebc += sc->f54r->ebc; 1072 sc->cnt_cec2 += sc->f54r->cec2; 1073 sc->cnt_cec3 += sc->f54r->cec3; 1074 sc->cnt_rbc += sc->f54r->rbc; 1075 } 1076 1077 /* 1078 * Transmit interrupt for one channel 1079 */ 1080 static void 1081 mn_tx_intr(struct softc *sc, u_int32_t vector) 1082 { 1083 u_int32_t chan; 1084 struct trxd *dp; 1085 struct mbuf *m; 1086 1087 chan = vector & 0x1f; 1088 if (!sc->ch[chan]) 1089 return; 1090 if (sc->ch[chan]->state != UP) { 1091 kprintf("%s: tx_intr when not UP\n", sc->name); 1092 return; 1093 } 1094 for (;;) { 1095 dp = sc->ch[chan]->x1; 1096 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1097 return; 1098 m = dp->m; 1099 if (m) { 1100 #if 0 1101 kprintf("%d = %d - %d (%p)\n", 1102 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1103 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1104 #endif 1105 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1106 m_freem(m); 1107 } 1108 sc->ch[chan]->last_xmit = time_uptime; 1109 sc->ch[chan]->x1 = dp->vnext; 1110 mn_free_desc(dp); 1111 } 1112 } 1113 1114 /* 1115 * Receive interrupt for one channel 1116 */ 1117 static void 1118 mn_rx_intr(struct softc *sc, u_int32_t vector) 1119 { 1120 u_int32_t chan, err; 1121 struct trxd *dp; 1122 struct mbuf *m; 1123 struct schan *sch; 1124 1125 chan = vector & 0x1f; 1126 if (!sc->ch[chan]) 1127 return; 1128 sch = sc->ch[chan]; 1129 if (sch->state != UP) { 1130 kprintf("%s: rx_intr when not UP\n", sc->name); 1131 return; 1132 } 1133 vector &= ~0x1f; 1134 if (vector == 0x30000b00) 1135 sch->rx_error++; 1136 for (;;) { 1137 dp = sch->r1; 1138 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1139 return; 1140 m = dp->m; 1141 dp->m = NULL; 1142 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1143 err = (dp->status >> 8) & 0xff; 1144 if (!err) { 1145 ng_queue_data(sch->hook, m, NULL); 1146 sch->last_recv = time_uptime; 1147 m = NULL; 1148 /* we could be down by now... */ 1149 if (sch->state != UP) 1150 return; 1151 } else if (err & 0x40) { 1152 sch->short_error++; 1153 } else if (err & 0x10) { 1154 sch->crc_error++; 1155 } else if (err & 0x08) { 1156 sch->dribble_error++; 1157 } else if (err & 0x04) { 1158 sch->long_error++; 1159 } else if (err & 0x02) { 1160 sch->abort_error++; 1161 } else if (err & 0x01) { 1162 sch->overflow_error++; 1163 } 1164 if (err) { 1165 sch->last_rxerr = time_uptime; 1166 sch->prev_error = sch->last_error; 1167 sch->last_error = err; 1168 } 1169 1170 sc->ch[chan]->r1 = dp->vnext; 1171 1172 /* Replenish desc + mbuf supplies */ 1173 if (!m) { 1174 MGETHDR(m, MB_DONTWAIT, MT_DATA); 1175 if (m == NULL) { 1176 mn_free_desc(dp); 1177 return; /* ENOBUFS */ 1178 } 1179 MCLGET(m, MB_DONTWAIT); 1180 if((m->m_flags & M_EXT) == 0) { 1181 mn_free_desc(dp); 1182 m_freem(m); 1183 return; /* ENOBUFS */ 1184 } 1185 } 1186 dp->m = m; 1187 dp->data = vtophys(m->m_data); 1188 dp->flags = 0x40000000; 1189 dp->flags += 1600 << 16; 1190 dp->next = vtophys(dp); 1191 dp->vnext = NULL; 1192 sc->ch[chan]->rl->next = vtophys(dp); 1193 sc->ch[chan]->rl->vnext = dp; 1194 sc->ch[chan]->rl->flags &= ~0x40000000; 1195 sc->ch[chan]->rl = dp; 1196 } 1197 } 1198 1199 1200 /* 1201 * Interupt handler 1202 */ 1203 1204 static void 1205 mn_intr(void *xsc) 1206 { 1207 struct softc *sc; 1208 u_int32_t stat, lstat, u; 1209 int i, j; 1210 1211 sc = xsc; 1212 stat = sc->m32x->stat; 1213 lstat = sc->m32x->lstat; 1214 #if 0 1215 if (!stat && !(lstat & 2)) 1216 return; 1217 #endif 1218 1219 if (stat & ~0xc200) { 1220 kprintf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1221 } 1222 1223 if ((stat & 0x200) || (lstat & 2)) 1224 f54_intr(sc); 1225 1226 for (j = i = 0; i < 64; i ++) { 1227 u = sc->riqb[i]; 1228 if (u) { 1229 sc->riqb[i] = 0; 1230 mn_rx_intr(sc, u); 1231 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1232 continue; 1233 u &= ~0x30000400; /* bits we don't care about */ 1234 if ((u & ~0x1f) == 0x00000900) 1235 continue; 1236 if (!(u & ~0x1f)) 1237 continue; 1238 if (!j) 1239 kprintf("%s*: RIQB:", sc->name); 1240 kprintf(" [%d]=%08x", i, u); 1241 j++; 1242 } 1243 } 1244 if (j) 1245 kprintf("\n"); 1246 1247 for (j = i = 0; i < 64; i ++) { 1248 u = sc->tiqb[i]; 1249 if (u) { 1250 sc->tiqb[i] = 0; 1251 mn_tx_intr(sc, u); 1252 if ((u & ~0x1f) == 0x20000800) 1253 continue; 1254 u &= ~0x20000000; /* bits we don't care about */ 1255 if (!u) 1256 continue; 1257 if (!j) 1258 kprintf("%s*: TIQB:", sc->name); 1259 kprintf(" [%d]=%08x", i, u); 1260 j++; 1261 } 1262 } 1263 if (j) 1264 kprintf("\n"); 1265 sc->m32x->stat = stat; 1266 } 1267 1268 /* 1269 * PCI initialization stuff 1270 */ 1271 1272 static int 1273 mn_probe (device_t self) 1274 { 1275 u_int id = pci_get_devid(self); 1276 1277 if (sizeof (struct m32xreg) != 256) { 1278 kprintf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg)); 1279 return (ENXIO); 1280 } 1281 if (sizeof (struct f54rreg) != 128) { 1282 kprintf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg)); 1283 return (ENXIO); 1284 } 1285 if (sizeof (struct f54wreg) != 128) { 1286 kprintf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg)); 1287 return (ENXIO); 1288 } 1289 1290 if (id != 0x2101110a) 1291 return (ENXIO); 1292 1293 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1294 return (0); 1295 } 1296 1297 static int 1298 mn_attach (device_t self) 1299 { 1300 struct softc *sc; 1301 u_int32_t u; 1302 u_int32_t ver; 1303 static int once; 1304 int rid, error; 1305 struct resource *res; 1306 1307 if (!once) { 1308 if (ng_newtype(&mntypestruct)) 1309 kprintf("ng_newtype failed\n"); 1310 once++; 1311 } 1312 1313 sc = (struct softc *)kmalloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1314 device_set_softc(self, sc); 1315 1316 sc->dev = self; 1317 sc->unit = device_get_unit(self); 1318 sc->framing = E1; 1319 ksprintf(sc->name, "mn%d", sc->unit); 1320 1321 rid = PCIR_MAPS; 1322 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 1323 if (res == NULL) { 1324 device_printf(self, "Could not map memory\n"); 1325 return ENXIO; 1326 } 1327 sc->m0v = rman_get_virtual(res); 1328 sc->m0p = rman_get_start(res); 1329 1330 rid = PCIR_MAPS + 4; 1331 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 1332 if (res == NULL) { 1333 device_printf(self, "Could not map memory\n"); 1334 return ENXIO; 1335 } 1336 sc->m1v = rman_get_virtual(res); 1337 sc->m1p = rman_get_start(res); 1338 1339 /* Allocate interrupt */ 1340 rid = 0; 1341 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 1342 RF_SHAREABLE | RF_ACTIVE); 1343 1344 if (sc->irq == NULL) { 1345 kprintf("couldn't map interrupt\n"); 1346 return(ENXIO); 1347 } 1348 1349 error = bus_setup_intr(self, sc->irq, INTR_MPSAFE, mn_intr, sc, 1350 &sc->intrhand, NULL); 1351 1352 if (error) { 1353 kprintf("couldn't set up irq\n"); 1354 return(ENXIO); 1355 } 1356 1357 u = pci_read_config(self, PCIR_COMMAND, 1); 1358 kprintf("%x\n", u); 1359 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1); 1360 #if 0 1361 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1362 #endif 1363 u = pci_read_config(self, PCIR_COMMAND, 1); 1364 kprintf("%x\n", u); 1365 1366 ver = pci_get_revid(self); 1367 1368 sc->m32x = (struct m32xreg *) sc->m0v; 1369 sc->f54w = (struct f54wreg *) sc->m1v; 1370 sc->f54r = (struct f54rreg *) sc->m1v; 1371 1372 /* We must reset before poking at FALC54 registers */ 1373 u = mn_reset(sc); 1374 if (!u) 1375 return (0); 1376 1377 kprintf("mn%d: Munich32X", sc->unit); 1378 switch (ver) { 1379 case 0x13: 1380 kprintf(" Rev 2.2"); 1381 break; 1382 default: 1383 kprintf(" Rev 0x%x\n", ver); 1384 } 1385 kprintf(", Falc54"); 1386 switch (sc->f54r->vstr) { 1387 case 0: 1388 kprintf(" Rev < 1.3\n"); 1389 break; 1390 case 1: 1391 kprintf(" Rev 1.3\n"); 1392 break; 1393 case 2: 1394 kprintf(" Rev 1.4\n"); 1395 break; 1396 case 0x10: 1397 kprintf("-LH Rev 1.1\n"); 1398 break; 1399 case 0x13: 1400 kprintf("-LH Rev 1.3\n"); 1401 break; 1402 default: 1403 kprintf(" Rev 0x%x\n", sc->f54r->vstr); 1404 } 1405 1406 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1407 kprintf("ng_make_node_common failed\n"); 1408 return (0); 1409 } 1410 sc->node->private = sc; 1411 ksprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1412 if (ng_name_node(sc->node, sc->nodename)) { 1413 ng_rmnode(sc->node); 1414 ng_unref(sc->node); 1415 return (0); 1416 } 1417 1418 return (0); 1419 } 1420 1421 1422 static device_method_t mn_methods[] = { 1423 /* Device interface */ 1424 DEVMETHOD(device_probe, mn_probe), 1425 DEVMETHOD(device_attach, mn_attach), 1426 DEVMETHOD(device_suspend, bus_generic_suspend), 1427 DEVMETHOD(device_resume, bus_generic_resume), 1428 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1429 1430 DEVMETHOD_END 1431 }; 1432 1433 static driver_t mn_driver = { 1434 "mn", 1435 mn_methods, 1436 0 1437 }; 1438 1439 static devclass_t mn_devclass; 1440 1441 DECLARE_DUMMY_MODULE(if_mn); 1442 DRIVER_MODULE(if_mn, pci, mn_driver, mn_devclass, NULL, NULL); 1443
Cache object: f09345d1ca0feb0692aef4dc8989b15a
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]