1 /*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34 */
35
36 /*
37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
38 * for FreeBSD. Datasheets are available from:
39 *
40 * http://www.national.com/ds/DP/DP83820.pdf
41 * http://www.national.com/ds/DP/DP83821.pdf
42 *
43 * These chips are used on several low cost gigabit ethernet NICs
44 * sold by D-Link, Addtron, SMC and Asante. Both parts are
45 * virtually the same, except the 83820 is a 64-bit/32-bit part,
46 * while the 83821 is 32-bit only.
47 *
48 * Many cards also use National gigE transceivers, such as the
49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
50 * contains a full register description that applies to all of these
51 * components:
52 *
53 * http://www.national.com/ds/DP/DP83861.pdf
54 *
55 * Written by Bill Paul <wpaul@bsdi.com>
56 * BSDi Open Source Solutions
57 */
58
59 /*
60 * The NatSemi DP83820 and 83821 controllers are enhanced versions
61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
66 * matching buffers, one perfect address filter buffer and interrupt
67 * moderation. The 83820 supports both 64-bit and 32-bit addressing
68 * and data transfers: the 64-bit support can be toggled on or off
69 * via software. This affects the size of certain fields in the DMA
70 * descriptors.
71 *
72 * There are two bugs/misfeatures in the 83820/83821 that I have
73 * discovered so far:
74 *
75 * - Receive buffers must be aligned on 64-bit boundaries, which means
76 * you must resort to copying data in order to fix up the payload
77 * alignment.
78 *
79 * - In order to transmit jumbo frames larger than 8170 bytes, you have
80 * to turn off transmit checksum offloading, because the chip can't
81 * compute the checksum on an outgoing frame unless it fits entirely
82 * within the TX FIFO, which is only 8192 bytes in size. If you have
83 * TX checksum offload enabled and you transmit attempt to transmit a
84 * frame larger than 8170 bytes, the transmitter will wedge.
85 *
86 * To work around the latter problem, TX checksum offload is disabled
87 * if the user selects an MTU larger than 8152 (8170 - 18).
88 */
89
90 #include "opt_ifpoll.h"
91
92 #include <sys/param.h>
93 #include <sys/systm.h>
94 #include <sys/sockio.h>
95 #include <sys/mbuf.h>
96 #include <sys/malloc.h>
97 #include <sys/kernel.h>
98 #include <sys/interrupt.h>
99 #include <sys/socket.h>
100 #include <sys/serialize.h>
101 #include <sys/bus.h>
102 #include <sys/rman.h>
103 #include <sys/thread2.h>
104
105 #include <net/if.h>
106 #include <net/ifq_var.h>
107 #include <net/if_arp.h>
108 #include <net/ethernet.h>
109 #include <net/if_dl.h>
110 #include <net/if_media.h>
111 #include <net/if_poll.h>
112 #include <net/if_types.h>
113 #include <net/vlan/if_vlan_var.h>
114 #include <net/vlan/if_vlan_ether.h>
115
116 #include <net/bpf.h>
117
118 #include <vm/vm.h> /* for vtophys */
119 #include <vm/pmap.h> /* for vtophys */
120
121 #include <dev/netif/mii_layer/mii.h>
122 #include <dev/netif/mii_layer/miivar.h>
123
124 #include "pcidevs.h"
125 #include <bus/pci/pcireg.h>
126 #include <bus/pci/pcivar.h>
127
128 #define NGE_USEIOSPACE
129
130 #include "if_ngereg.h"
131
132
133 /* "controller miibus0" required. See GENERIC if you get errors here. */
134 #include "miibus_if.h"
135
136 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
137
138 /*
139 * Various supported device vendors/types and their names.
140 */
141 static struct nge_type nge_devs[] = {
142 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820,
143 "National Semiconductor Gigabit Ethernet" },
144 { 0, 0, NULL }
145 };
146
147 static int nge_probe(device_t);
148 static int nge_attach(device_t);
149 static int nge_detach(device_t);
150
151 static int nge_alloc_jumbo_mem(struct nge_softc *);
152 static struct nge_jslot
153 *nge_jalloc(struct nge_softc *);
154 static void nge_jfree(void *);
155 static void nge_jref(void *);
156
157 static int nge_newbuf(struct nge_softc *, struct nge_desc *,
158 struct mbuf *);
159 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
160 static void nge_rxeof(struct nge_softc *);
161 static void nge_txeof(struct nge_softc *);
162 static void nge_intr(void *);
163 static void nge_tick(void *);
164 static void nge_start(struct ifnet *, struct ifaltq_subque *);
165 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
166 static void nge_init(void *);
167 static void nge_stop(struct nge_softc *);
168 static void nge_watchdog(struct ifnet *);
169 static void nge_shutdown(device_t);
170 static int nge_ifmedia_upd(struct ifnet *);
171 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
172
173 static void nge_delay(struct nge_softc *);
174 static void nge_eeprom_idle(struct nge_softc *);
175 static void nge_eeprom_putbyte(struct nge_softc *, int);
176 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
177 static void nge_read_eeprom(struct nge_softc *, void *, int, int);
178
179 static void nge_mii_sync(struct nge_softc *);
180 static void nge_mii_send(struct nge_softc *, uint32_t, int);
181 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
182 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
183
184 static int nge_miibus_readreg(device_t, int, int);
185 static int nge_miibus_writereg(device_t, int, int, int);
186 static void nge_miibus_statchg(device_t);
187
188 static void nge_setmulti(struct nge_softc *);
189 static void nge_reset(struct nge_softc *);
190 static int nge_list_rx_init(struct nge_softc *);
191 static int nge_list_tx_init(struct nge_softc *);
192 #ifdef IFPOLL_ENABLE
193 static void nge_npoll(struct ifnet *, struct ifpoll_info *);
194 static void nge_npoll_compat(struct ifnet *, void *, int);
195 #endif
196
197 #ifdef NGE_USEIOSPACE
198 #define NGE_RES SYS_RES_IOPORT
199 #define NGE_RID NGE_PCI_LOIO
200 #else
201 #define NGE_RES SYS_RES_MEMORY
202 #define NGE_RID NGE_PCI_LOMEM
203 #endif
204
205 static device_method_t nge_methods[] = {
206 /* Device interface */
207 DEVMETHOD(device_probe, nge_probe),
208 DEVMETHOD(device_attach, nge_attach),
209 DEVMETHOD(device_detach, nge_detach),
210 DEVMETHOD(device_shutdown, nge_shutdown),
211
212 /* bus interface */
213 DEVMETHOD(bus_print_child, bus_generic_print_child),
214 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
215
216 /* MII interface */
217 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
218 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
219 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
220
221 DEVMETHOD_END
222 };
223
224 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
225 static devclass_t nge_devclass;
226
227 DECLARE_DUMMY_MODULE(if_nge);
228 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
229 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, NULL, NULL);
230 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, NULL, NULL);
231
232 #define NGE_SETBIT(sc, reg, x) \
233 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
234
235 #define NGE_CLRBIT(sc, reg, x) \
236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
237
238 #define SIO_SET(x) \
239 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
240
241 #define SIO_CLR(x) \
242 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
243
244 static void
245 nge_delay(struct nge_softc *sc)
246 {
247 int idx;
248
249 for (idx = (300 / 33) + 1; idx > 0; idx--)
250 CSR_READ_4(sc, NGE_CSR);
251 }
252
253 static void
254 nge_eeprom_idle(struct nge_softc *sc)
255 {
256 int i;
257
258 SIO_SET(NGE_MEAR_EE_CSEL);
259 nge_delay(sc);
260 SIO_SET(NGE_MEAR_EE_CLK);
261 nge_delay(sc);
262
263 for (i = 0; i < 25; i++) {
264 SIO_CLR(NGE_MEAR_EE_CLK);
265 nge_delay(sc);
266 SIO_SET(NGE_MEAR_EE_CLK);
267 nge_delay(sc);
268 }
269
270 SIO_CLR(NGE_MEAR_EE_CLK);
271 nge_delay(sc);
272 SIO_CLR(NGE_MEAR_EE_CSEL);
273 nge_delay(sc);
274 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
275 }
276
277 /*
278 * Send a read command and address to the EEPROM, check for ACK.
279 */
280 static void
281 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
282 {
283 int d, i;
284
285 d = addr | NGE_EECMD_READ;
286
287 /*
288 * Feed in each bit and stobe the clock.
289 */
290 for (i = 0x400; i; i >>= 1) {
291 if (d & i)
292 SIO_SET(NGE_MEAR_EE_DIN);
293 else
294 SIO_CLR(NGE_MEAR_EE_DIN);
295 nge_delay(sc);
296 SIO_SET(NGE_MEAR_EE_CLK);
297 nge_delay(sc);
298 SIO_CLR(NGE_MEAR_EE_CLK);
299 nge_delay(sc);
300 }
301 }
302
303 /*
304 * Read a word of data stored in the EEPROM at address 'addr.'
305 */
306 static void
307 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
308 {
309 int i;
310 uint16_t word = 0;
311
312 /* Force EEPROM to idle state. */
313 nge_eeprom_idle(sc);
314
315 /* Enter EEPROM access mode. */
316 nge_delay(sc);
317 SIO_CLR(NGE_MEAR_EE_CLK);
318 nge_delay(sc);
319 SIO_SET(NGE_MEAR_EE_CSEL);
320 nge_delay(sc);
321
322 /*
323 * Send address of word we want to read.
324 */
325 nge_eeprom_putbyte(sc, addr);
326
327 /*
328 * Start reading bits from EEPROM.
329 */
330 for (i = 0x8000; i; i >>= 1) {
331 SIO_SET(NGE_MEAR_EE_CLK);
332 nge_delay(sc);
333 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
334 word |= i;
335 nge_delay(sc);
336 SIO_CLR(NGE_MEAR_EE_CLK);
337 nge_delay(sc);
338 }
339
340 /* Turn off EEPROM access mode. */
341 nge_eeprom_idle(sc);
342
343 *dest = word;
344 }
345
346 /*
347 * Read a sequence of words from the EEPROM.
348 */
349 static void
350 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
351 {
352 int i;
353 uint16_t word = 0, *ptr;
354
355 for (i = 0; i < cnt; i++) {
356 nge_eeprom_getword(sc, off + i, &word);
357 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
358 *ptr = word;
359 }
360 }
361
362 /*
363 * Sync the PHYs by setting data bit and strobing the clock 32 times.
364 */
365 static void
366 nge_mii_sync(struct nge_softc *sc)
367 {
368 int i;
369
370 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
371
372 for (i = 0; i < 32; i++) {
373 SIO_SET(NGE_MEAR_MII_CLK);
374 DELAY(1);
375 SIO_CLR(NGE_MEAR_MII_CLK);
376 DELAY(1);
377 }
378 }
379
380 /*
381 * Clock a series of bits through the MII.
382 */
383 static void
384 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
385 {
386 int i;
387
388 SIO_CLR(NGE_MEAR_MII_CLK);
389
390 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
391 if (bits & i)
392 SIO_SET(NGE_MEAR_MII_DATA);
393 else
394 SIO_CLR(NGE_MEAR_MII_DATA);
395 DELAY(1);
396 SIO_CLR(NGE_MEAR_MII_CLK);
397 DELAY(1);
398 SIO_SET(NGE_MEAR_MII_CLK);
399 }
400 }
401
402 /*
403 * Read an PHY register through the MII.
404 */
405 static int
406 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
407 {
408 int ack, i;
409
410 /*
411 * Set up frame for RX.
412 */
413 frame->mii_stdelim = NGE_MII_STARTDELIM;
414 frame->mii_opcode = NGE_MII_READOP;
415 frame->mii_turnaround = 0;
416 frame->mii_data = 0;
417
418 CSR_WRITE_4(sc, NGE_MEAR, 0);
419
420 /*
421 * Turn on data xmit.
422 */
423 SIO_SET(NGE_MEAR_MII_DIR);
424
425 nge_mii_sync(sc);
426
427 /*
428 * Send command/address info.
429 */
430 nge_mii_send(sc, frame->mii_stdelim, 2);
431 nge_mii_send(sc, frame->mii_opcode, 2);
432 nge_mii_send(sc, frame->mii_phyaddr, 5);
433 nge_mii_send(sc, frame->mii_regaddr, 5);
434
435 /* Idle bit */
436 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
437 DELAY(1);
438 SIO_SET(NGE_MEAR_MII_CLK);
439 DELAY(1);
440
441 /* Turn off xmit. */
442 SIO_CLR(NGE_MEAR_MII_DIR);
443 /* Check for ack */
444 SIO_CLR(NGE_MEAR_MII_CLK);
445 DELAY(1);
446 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
447 SIO_SET(NGE_MEAR_MII_CLK);
448 DELAY(1);
449
450 /*
451 * Now try reading data bits. If the ack failed, we still
452 * need to clock through 16 cycles to keep the PHY(s) in sync.
453 */
454 if (ack) {
455 for(i = 0; i < 16; i++) {
456 SIO_CLR(NGE_MEAR_MII_CLK);
457 DELAY(1);
458 SIO_SET(NGE_MEAR_MII_CLK);
459 DELAY(1);
460 }
461 goto fail;
462 }
463
464 for (i = 0x8000; i; i >>= 1) {
465 SIO_CLR(NGE_MEAR_MII_CLK);
466 DELAY(1);
467 if (!ack) {
468 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
469 frame->mii_data |= i;
470 DELAY(1);
471 }
472 SIO_SET(NGE_MEAR_MII_CLK);
473 DELAY(1);
474 }
475
476 fail:
477 SIO_CLR(NGE_MEAR_MII_CLK);
478 DELAY(1);
479 SIO_SET(NGE_MEAR_MII_CLK);
480 DELAY(1);
481
482 if (ack)
483 return(1);
484 return(0);
485 }
486
487 /*
488 * Write to a PHY register through the MII.
489 */
490 static int
491 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
492 {
493 /*
494 * Set up frame for TX.
495 */
496
497 frame->mii_stdelim = NGE_MII_STARTDELIM;
498 frame->mii_opcode = NGE_MII_WRITEOP;
499 frame->mii_turnaround = NGE_MII_TURNAROUND;
500
501 /*
502 * Turn on data output.
503 */
504 SIO_SET(NGE_MEAR_MII_DIR);
505
506 nge_mii_sync(sc);
507
508 nge_mii_send(sc, frame->mii_stdelim, 2);
509 nge_mii_send(sc, frame->mii_opcode, 2);
510 nge_mii_send(sc, frame->mii_phyaddr, 5);
511 nge_mii_send(sc, frame->mii_regaddr, 5);
512 nge_mii_send(sc, frame->mii_turnaround, 2);
513 nge_mii_send(sc, frame->mii_data, 16);
514
515 /* Idle bit. */
516 SIO_SET(NGE_MEAR_MII_CLK);
517 DELAY(1);
518 SIO_CLR(NGE_MEAR_MII_CLK);
519 DELAY(1);
520
521 /*
522 * Turn off xmit.
523 */
524 SIO_CLR(NGE_MEAR_MII_DIR);
525
526 return(0);
527 }
528
529 static int
530 nge_miibus_readreg(device_t dev, int phy, int reg)
531 {
532 struct nge_softc *sc = device_get_softc(dev);
533 struct nge_mii_frame frame;
534
535 bzero((char *)&frame, sizeof(frame));
536
537 frame.mii_phyaddr = phy;
538 frame.mii_regaddr = reg;
539 nge_mii_readreg(sc, &frame);
540
541 return(frame.mii_data);
542 }
543
544 static int
545 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
546 {
547 struct nge_softc *sc = device_get_softc(dev);
548 struct nge_mii_frame frame;
549
550 bzero((char *)&frame, sizeof(frame));
551
552 frame.mii_phyaddr = phy;
553 frame.mii_regaddr = reg;
554 frame.mii_data = data;
555 nge_mii_writereg(sc, &frame);
556
557 return(0);
558 }
559
560 static void
561 nge_miibus_statchg(device_t dev)
562 {
563 struct nge_softc *sc = device_get_softc(dev);
564 struct mii_data *mii;
565 int status;
566
567 if (sc->nge_tbi) {
568 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
569 == IFM_AUTO) {
570 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
571 if (status == 0 || status & NGE_TBIANAR_FDX) {
572 NGE_SETBIT(sc, NGE_TX_CFG,
573 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
574 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
575 } else {
576 NGE_CLRBIT(sc, NGE_TX_CFG,
577 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
578 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
579 }
580 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
581 != IFM_FDX) {
582 NGE_CLRBIT(sc, NGE_TX_CFG,
583 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
584 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
585 } else {
586 NGE_SETBIT(sc, NGE_TX_CFG,
587 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
588 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
589 }
590 } else {
591 mii = device_get_softc(sc->nge_miibus);
592
593 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
594 NGE_SETBIT(sc, NGE_TX_CFG,
595 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
596 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
597 } else {
598 NGE_CLRBIT(sc, NGE_TX_CFG,
599 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
600 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
601 }
602
603 /* If we have a 1000Mbps link, set the mode_1000 bit. */
604 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
605 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
606 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
607 } else {
608 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
609 }
610 }
611 }
612
613 static void
614 nge_setmulti(struct nge_softc *sc)
615 {
616 struct ifnet *ifp = &sc->arpcom.ac_if;
617 struct ifmultiaddr *ifma;
618 uint32_t filtsave, h = 0, i;
619 int bit, index;
620
621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
622 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
623 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
624 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
625 return;
626 }
627
628 /*
629 * We have to explicitly enable the multicast hash table
630 * on the NatSemi chip if we want to use it, which we do.
631 * We also have to tell it that we don't want to use the
632 * hash table for matching unicast addresses.
633 */
634 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
635 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
636 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
637
638 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
639
640 /* first, zot all the existing hash bits */
641 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
642 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
643 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
644 }
645
646 /*
647 * From the 11 bits returned by the crc routine, the top 7
648 * bits represent the 16-bit word in the mcast hash table
649 * that needs to be updated, and the lower 4 bits represent
650 * which bit within that byte needs to be set.
651 */
652 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
653 if (ifma->ifma_addr->sa_family != AF_LINK)
654 continue;
655 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
656 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
657 index = (h >> 4) & 0x7F;
658 bit = h & 0xF;
659 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
660 NGE_FILTADDR_MCAST_LO + (index * 2));
661 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
662 }
663
664 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
665 }
666
667 static void
668 nge_reset(struct nge_softc *sc)
669 {
670 int i;
671
672 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
673
674 for (i = 0; i < NGE_TIMEOUT; i++) {
675 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
676 break;
677 }
678
679 if (i == NGE_TIMEOUT)
680 kprintf("nge%d: reset never completed\n", sc->nge_unit);
681
682 /* Wait a little while for the chip to get its brains in order. */
683 DELAY(1000);
684
685 /*
686 * If this is a NetSemi chip, make sure to clear
687 * PME mode.
688 */
689 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
690 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
691 }
692
693 /*
694 * Probe for an NatSemi chip. Check the PCI vendor and device
695 * IDs against our list and return a device name if we find a match.
696 */
697 static int
698 nge_probe(device_t dev)
699 {
700 struct nge_type *t;
701 uint16_t vendor, product;
702
703 vendor = pci_get_vendor(dev);
704 product = pci_get_device(dev);
705
706 for (t = nge_devs; t->nge_name != NULL; t++) {
707 if (vendor == t->nge_vid && product == t->nge_did) {
708 device_set_desc(dev, t->nge_name);
709 return(0);
710 }
711 }
712
713 return(ENXIO);
714 }
715
716 /*
717 * Attach the interface. Allocate softc structures, do ifmedia
718 * setup and ethernet/BPF attach.
719 */
720 static int
721 nge_attach(device_t dev)
722 {
723 struct nge_softc *sc;
724 struct ifnet *ifp;
725 uint8_t eaddr[ETHER_ADDR_LEN];
726 uint32_t command;
727 int error = 0, rid, unit;
728 const char *sep = "";
729
730 sc = device_get_softc(dev);
731 unit = device_get_unit(dev);
732 callout_init(&sc->nge_stat_timer);
733 lwkt_serialize_init(&sc->nge_jslot_serializer);
734
735 /*
736 * Handle power management nonsense.
737 */
738 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
739 if (command == 0x01) {
740 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
741 if (command & NGE_PSTATE_MASK) {
742 uint32_t iobase, membase, irq;
743
744 /* Save important PCI config data. */
745 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
746 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
747 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
748
749 /* Reset the power state. */
750 kprintf("nge%d: chip is in D%d power mode "
751 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
752 command &= 0xFFFFFFFC;
753 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
754
755 /* Restore PCI config data. */
756 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
757 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
758 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
759 }
760 }
761
762 /*
763 * Map control/status registers.
764 */
765 command = pci_read_config(dev, PCIR_COMMAND, 4);
766 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
767 pci_write_config(dev, PCIR_COMMAND, command, 4);
768 command = pci_read_config(dev, PCIR_COMMAND, 4);
769
770 #ifdef NGE_USEIOSPACE
771 if (!(command & PCIM_CMD_PORTEN)) {
772 kprintf("nge%d: failed to enable I/O ports!\n", unit);
773 error = ENXIO;
774 return(error);
775 }
776 #else
777 if (!(command & PCIM_CMD_MEMEN)) {
778 kprintf("nge%d: failed to enable memory mapping!\n", unit);
779 error = ENXIO;
780 return(error);
781 }
782 #endif
783
784 rid = NGE_RID;
785 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
786
787 if (sc->nge_res == NULL) {
788 kprintf("nge%d: couldn't map ports/memory\n", unit);
789 error = ENXIO;
790 return(error);
791 }
792
793 sc->nge_btag = rman_get_bustag(sc->nge_res);
794 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
795
796 /* Allocate interrupt */
797 rid = 0;
798 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
799 RF_SHAREABLE | RF_ACTIVE);
800
801 if (sc->nge_irq == NULL) {
802 kprintf("nge%d: couldn't map interrupt\n", unit);
803 error = ENXIO;
804 goto fail;
805 }
806
807 /* Reset the adapter. */
808 nge_reset(sc);
809
810 /*
811 * Get station address from the EEPROM.
812 */
813 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
814 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
815 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
816
817 sc->nge_unit = unit;
818
819 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
820 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
821
822 if (sc->nge_ldata == NULL) {
823 kprintf("nge%d: no memory for list buffers!\n", unit);
824 error = ENXIO;
825 goto fail;
826 }
827
828 /* Try to allocate memory for jumbo buffers. */
829 if (nge_alloc_jumbo_mem(sc)) {
830 kprintf("nge%d: jumbo buffer allocation failed\n",
831 sc->nge_unit);
832 error = ENXIO;
833 goto fail;
834 }
835
836 ifp = &sc->arpcom.ac_if;
837 ifp->if_softc = sc;
838 if_initname(ifp, "nge", unit);
839 ifp->if_mtu = ETHERMTU;
840 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
841 ifp->if_ioctl = nge_ioctl;
842 ifp->if_start = nge_start;
843 #ifdef IFPOLL_ENABLE
844 ifp->if_npoll = nge_npoll;
845 #endif
846 ifp->if_watchdog = nge_watchdog;
847 ifp->if_init = nge_init;
848 ifp->if_baudrate = 1000000000;
849 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
850 ifq_set_ready(&ifp->if_snd);
851 ifp->if_hwassist = NGE_CSUM_FEATURES;
852 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
853 ifp->if_capenable = ifp->if_capabilities;
854
855 /*
856 * Do MII setup.
857 */
858 if (mii_phy_probe(dev, &sc->nge_miibus,
859 nge_ifmedia_upd, nge_ifmedia_sts)) {
860 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
861 sc->nge_tbi = 1;
862 device_printf(dev, "Using TBI\n");
863
864 sc->nge_miibus = dev;
865
866 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
867 nge_ifmedia_sts);
868 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
869 #define PRINT(s) kprintf("%s%s", sep, s); sep = ", "
870 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
871 device_printf(dev, " ");
872 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
873 PRINT("1000baseSX");
874 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
875 PRINT("1000baseSX-FDX");
876 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
877 PRINT("auto");
878
879 kprintf("\n");
880 #undef ADD
881 #undef PRINT
882 ifmedia_set(&sc->nge_ifmedia,
883 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
884
885 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
886 | NGE_GPIO_GP4_OUT
887 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
888 | NGE_GPIO_GP3_OUTENB
889 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
890
891 } else {
892 kprintf("nge%d: MII without any PHY!\n", sc->nge_unit);
893 error = ENXIO;
894 goto fail;
895 }
896 }
897
898 /*
899 * Call MI attach routine.
900 */
901 ether_ifattach(ifp, eaddr, NULL);
902
903 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->nge_irq));
904
905 #ifdef IFPOLL_ENABLE
906 ifpoll_compat_setup(&sc->nge_npoll, NULL, NULL, device_get_unit(dev),
907 ifp->if_serializer);
908 #endif
909
910 error = bus_setup_intr(dev, sc->nge_irq, INTR_MPSAFE,
911 nge_intr, sc, &sc->nge_intrhand,
912 ifp->if_serializer);
913 if (error) {
914 ether_ifdetach(ifp);
915 device_printf(dev, "couldn't set up irq\n");
916 goto fail;
917 }
918
919 return(0);
920 fail:
921 nge_detach(dev);
922 return(error);
923 }
924
925 static int
926 nge_detach(device_t dev)
927 {
928 struct nge_softc *sc = device_get_softc(dev);
929 struct ifnet *ifp = &sc->arpcom.ac_if;
930
931 if (device_is_attached(dev)) {
932 lwkt_serialize_enter(ifp->if_serializer);
933 nge_reset(sc);
934 nge_stop(sc);
935 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
936 lwkt_serialize_exit(ifp->if_serializer);
937
938 ether_ifdetach(ifp);
939 }
940
941 if (sc->nge_miibus)
942 device_delete_child(dev, sc->nge_miibus);
943 bus_generic_detach(dev);
944
945 if (sc->nge_irq)
946 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
947 if (sc->nge_res)
948 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
949 if (sc->nge_ldata) {
950 contigfree(sc->nge_ldata, sizeof(struct nge_list_data),
951 M_DEVBUF);
952 }
953 if (sc->nge_cdata.nge_jumbo_buf)
954 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
955
956 return(0);
957 }
958
959 /*
960 * Initialize the transmit descriptors.
961 */
962 static int
963 nge_list_tx_init(struct nge_softc *sc)
964 {
965 struct nge_list_data *ld;
966 struct nge_ring_data *cd;
967 int i;
968
969 cd = &sc->nge_cdata;
970 ld = sc->nge_ldata;
971
972 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
973 if (i == (NGE_TX_LIST_CNT - 1)) {
974 ld->nge_tx_list[i].nge_nextdesc =
975 &ld->nge_tx_list[0];
976 ld->nge_tx_list[i].nge_next =
977 vtophys(&ld->nge_tx_list[0]);
978 } else {
979 ld->nge_tx_list[i].nge_nextdesc =
980 &ld->nge_tx_list[i + 1];
981 ld->nge_tx_list[i].nge_next =
982 vtophys(&ld->nge_tx_list[i + 1]);
983 }
984 ld->nge_tx_list[i].nge_mbuf = NULL;
985 ld->nge_tx_list[i].nge_ptr = 0;
986 ld->nge_tx_list[i].nge_ctl = 0;
987 }
988
989 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
990
991 return(0);
992 }
993
994
995 /*
996 * Initialize the RX descriptors and allocate mbufs for them. Note that
997 * we arrange the descriptors in a closed ring, so that the last descriptor
998 * points back to the first.
999 */
1000 static int
1001 nge_list_rx_init(struct nge_softc *sc)
1002 {
1003 struct nge_list_data *ld;
1004 struct nge_ring_data *cd;
1005 int i;
1006
1007 ld = sc->nge_ldata;
1008 cd = &sc->nge_cdata;
1009
1010 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1011 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1012 return(ENOBUFS);
1013 if (i == (NGE_RX_LIST_CNT - 1)) {
1014 ld->nge_rx_list[i].nge_nextdesc =
1015 &ld->nge_rx_list[0];
1016 ld->nge_rx_list[i].nge_next =
1017 vtophys(&ld->nge_rx_list[0]);
1018 } else {
1019 ld->nge_rx_list[i].nge_nextdesc =
1020 &ld->nge_rx_list[i + 1];
1021 ld->nge_rx_list[i].nge_next =
1022 vtophys(&ld->nge_rx_list[i + 1]);
1023 }
1024 }
1025
1026 cd->nge_rx_prod = 0;
1027
1028 return(0);
1029 }
1030
1031 /*
1032 * Initialize an RX descriptor and attach an MBUF cluster.
1033 */
1034 static int
1035 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
1036 {
1037 struct mbuf *m_new = NULL;
1038 struct nge_jslot *buf;
1039
1040 if (m == NULL) {
1041 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1042 if (m_new == NULL) {
1043 kprintf("nge%d: no memory for rx list "
1044 "-- packet dropped!\n", sc->nge_unit);
1045 return(ENOBUFS);
1046 }
1047
1048 /* Allocate the jumbo buffer */
1049 buf = nge_jalloc(sc);
1050 if (buf == NULL) {
1051 #ifdef NGE_VERBOSE
1052 kprintf("nge%d: jumbo allocation failed "
1053 "-- packet dropped!\n", sc->nge_unit);
1054 #endif
1055 m_freem(m_new);
1056 return(ENOBUFS);
1057 }
1058 /* Attach the buffer to the mbuf */
1059 m_new->m_ext.ext_arg = buf;
1060 m_new->m_ext.ext_buf = buf->nge_buf;
1061 m_new->m_ext.ext_free = nge_jfree;
1062 m_new->m_ext.ext_ref = nge_jref;
1063 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1064
1065 m_new->m_data = m_new->m_ext.ext_buf;
1066 m_new->m_flags |= M_EXT;
1067 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1068 } else {
1069 m_new = m;
1070 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
1071 m_new->m_data = m_new->m_ext.ext_buf;
1072 }
1073
1074 m_adj(m_new, sizeof(uint64_t));
1075
1076 c->nge_mbuf = m_new;
1077 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1078 c->nge_ctl = m_new->m_len;
1079 c->nge_extsts = 0;
1080
1081 return(0);
1082 }
1083
1084 static int
1085 nge_alloc_jumbo_mem(struct nge_softc *sc)
1086 {
1087 caddr_t ptr;
1088 int i;
1089 struct nge_jslot *entry;
1090
1091 /* Grab a big chunk o' storage. */
1092 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1093 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1094
1095 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1096 kprintf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1097 return(ENOBUFS);
1098 }
1099
1100 SLIST_INIT(&sc->nge_jfree_listhead);
1101
1102 /*
1103 * Now divide it up into 9K pieces and save the addresses
1104 * in an array.
1105 */
1106 ptr = sc->nge_cdata.nge_jumbo_buf;
1107 for (i = 0; i < NGE_JSLOTS; i++) {
1108 entry = &sc->nge_cdata.nge_jslots[i];
1109 entry->nge_sc = sc;
1110 entry->nge_buf = ptr;
1111 entry->nge_inuse = 0;
1112 entry->nge_slot = i;
1113 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1114 ptr += NGE_JLEN;
1115 }
1116
1117 return(0);
1118 }
1119
1120
1121 /*
1122 * Allocate a jumbo buffer.
1123 */
1124 static struct nge_jslot *
1125 nge_jalloc(struct nge_softc *sc)
1126 {
1127 struct nge_jslot *entry;
1128
1129 lwkt_serialize_enter(&sc->nge_jslot_serializer);
1130 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1131 if (entry) {
1132 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1133 entry->nge_inuse = 1;
1134 } else {
1135 #ifdef NGE_VERBOSE
1136 kprintf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1137 #endif
1138 }
1139 lwkt_serialize_exit(&sc->nge_jslot_serializer);
1140 return(entry);
1141 }
1142
1143 /*
1144 * Adjust usage count on a jumbo buffer. In general this doesn't
1145 * get used much because our jumbo buffers don't get passed around
1146 * a lot, but it's implemented for correctness.
1147 */
1148 static void
1149 nge_jref(void *arg)
1150 {
1151 struct nge_jslot *entry = (struct nge_jslot *)arg;
1152 struct nge_softc *sc = entry->nge_sc;
1153
1154 if (sc == NULL)
1155 panic("nge_jref: can't find softc pointer!");
1156
1157 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1158 panic("nge_jref: asked to reference buffer "
1159 "that we don't manage!");
1160 else if (entry->nge_inuse == 0)
1161 panic("nge_jref: buffer already free!");
1162 else
1163 atomic_add_int(&entry->nge_inuse, 1);
1164 }
1165
1166 /*
1167 * Release a jumbo buffer.
1168 */
1169 static void
1170 nge_jfree(void *arg)
1171 {
1172 struct nge_jslot *entry = (struct nge_jslot *)arg;
1173 struct nge_softc *sc = entry->nge_sc;
1174
1175 if (sc == NULL)
1176 panic("nge_jref: can't find softc pointer!");
1177
1178 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) {
1179 panic("nge_jref: asked to reference buffer "
1180 "that we don't manage!");
1181 } else if (entry->nge_inuse == 0) {
1182 panic("nge_jref: buffer already free!");
1183 } else {
1184 lwkt_serialize_enter(&sc->nge_jslot_serializer);
1185 atomic_subtract_int(&entry->nge_inuse, 1);
1186 if (entry->nge_inuse == 0) {
1187 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1188 entry, jslot_link);
1189 }
1190 lwkt_serialize_exit(&sc->nge_jslot_serializer);
1191 }
1192 }
1193 /*
1194 * A frame has been uploaded: pass the resulting mbuf chain up to
1195 * the higher level protocols.
1196 */
1197 static void
1198 nge_rxeof(struct nge_softc *sc)
1199 {
1200 struct mbuf *m;
1201 struct ifnet *ifp = &sc->arpcom.ac_if;
1202 struct nge_desc *cur_rx;
1203 int i, total_len = 0;
1204 uint32_t rxstat;
1205
1206 i = sc->nge_cdata.nge_rx_prod;
1207
1208 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1209 struct mbuf *m0 = NULL;
1210 uint32_t extsts;
1211
1212 #ifdef IFPOLL_ENABLE
1213 if (ifp->if_flags & IFF_NPOLLING) {
1214 if (sc->rxcycles <= 0)
1215 break;
1216 sc->rxcycles--;
1217 }
1218 #endif /* IFPOLL_ENABLE */
1219
1220 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1221 rxstat = cur_rx->nge_rxstat;
1222 extsts = cur_rx->nge_extsts;
1223 m = cur_rx->nge_mbuf;
1224 cur_rx->nge_mbuf = NULL;
1225 total_len = NGE_RXBYTES(cur_rx);
1226 NGE_INC(i, NGE_RX_LIST_CNT);
1227 /*
1228 * If an error occurs, update stats, clear the
1229 * status word and leave the mbuf cluster in place:
1230 * it should simply get re-used next time this descriptor
1231 * comes up in the ring.
1232 */
1233 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
1234 IFNET_STAT_INC(ifp, ierrors, 1);
1235 nge_newbuf(sc, cur_rx, m);
1236 continue;
1237 }
1238
1239 /*
1240 * Ok. NatSemi really screwed up here. This is the
1241 * only gigE chip I know of with alignment constraints
1242 * on receive buffers. RX buffers must be 64-bit aligned.
1243 */
1244 #ifdef __i386__
1245 /*
1246 * By popular demand, ignore the alignment problems
1247 * on the Intel x86 platform. The performance hit
1248 * incurred due to unaligned accesses is much smaller
1249 * than the hit produced by forcing buffer copies all
1250 * the time, especially with jumbo frames. We still
1251 * need to fix up the alignment everywhere else though.
1252 */
1253 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1254 #endif
1255 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1256 total_len + ETHER_ALIGN, 0, ifp, NULL);
1257 nge_newbuf(sc, cur_rx, m);
1258 if (m0 == NULL) {
1259 kprintf("nge%d: no receive buffers "
1260 "available -- packet dropped!\n",
1261 sc->nge_unit);
1262 IFNET_STAT_INC(ifp, ierrors, 1);
1263 continue;
1264 }
1265 m_adj(m0, ETHER_ALIGN);
1266 m = m0;
1267 #ifdef __i386__
1268 } else {
1269 m->m_pkthdr.rcvif = ifp;
1270 m->m_pkthdr.len = m->m_len = total_len;
1271 }
1272 #endif
1273
1274 IFNET_STAT_INC(ifp, ipackets, 1);
1275
1276 /* Do IP checksum checking. */
1277 if (extsts & NGE_RXEXTSTS_IPPKT)
1278 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1279 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1280 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1281 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1282 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
1283 (extsts & NGE_RXEXTSTS_UDPPKT &&
1284 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
1285 m->m_pkthdr.csum_flags |=
1286 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1287 CSUM_FRAG_NOT_CHECKED;
1288 m->m_pkthdr.csum_data = 0xffff;
1289 }
1290
1291 /*
1292 * If we received a packet with a vlan tag, pass it
1293 * to vlan_input() instead of ether_input().
1294 */
1295 if (extsts & NGE_RXEXTSTS_VLANPKT) {
1296 m->m_flags |= M_VLANTAG;
1297 m->m_pkthdr.ether_vlantag =
1298 (extsts & NGE_RXEXTSTS_VTCI);
1299 }
1300 ifp->if_input(ifp, m);
1301 }
1302
1303 sc->nge_cdata.nge_rx_prod = i;
1304 }
1305
1306 /*
1307 * A frame was downloaded to the chip. It's safe for us to clean up
1308 * the list buffers.
1309 */
1310 static void
1311 nge_txeof(struct nge_softc *sc)
1312 {
1313 struct ifnet *ifp = &sc->arpcom.ac_if;
1314 struct nge_desc *cur_tx = NULL;
1315 uint32_t idx;
1316
1317 /* Clear the timeout timer. */
1318 ifp->if_timer = 0;
1319
1320 /*
1321 * Go through our tx list and free mbufs for those
1322 * frames that have been transmitted.
1323 */
1324 idx = sc->nge_cdata.nge_tx_cons;
1325 while (idx != sc->nge_cdata.nge_tx_prod) {
1326 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1327
1328 if (NGE_OWNDESC(cur_tx))
1329 break;
1330
1331 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1332 sc->nge_cdata.nge_tx_cnt--;
1333 NGE_INC(idx, NGE_TX_LIST_CNT);
1334 continue;
1335 }
1336
1337 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1338 IFNET_STAT_INC(ifp, oerrors, 1);
1339 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1340 IFNET_STAT_INC(ifp, collisions, 1);
1341 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1342 IFNET_STAT_INC(ifp, collisions, 1);
1343 }
1344
1345 IFNET_STAT_INC(ifp, collisions,
1346 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16);
1347
1348 IFNET_STAT_INC(ifp, opackets, 1);
1349 if (cur_tx->nge_mbuf != NULL) {
1350 m_freem(cur_tx->nge_mbuf);
1351 cur_tx->nge_mbuf = NULL;
1352 }
1353
1354 sc->nge_cdata.nge_tx_cnt--;
1355 NGE_INC(idx, NGE_TX_LIST_CNT);
1356 ifp->if_timer = 0;
1357 }
1358
1359 sc->nge_cdata.nge_tx_cons = idx;
1360
1361 if (cur_tx != NULL)
1362 ifq_clr_oactive(&ifp->if_snd);
1363 }
1364
1365 static void
1366 nge_tick(void *xsc)
1367 {
1368 struct nge_softc *sc = xsc;
1369 struct ifnet *ifp = &sc->arpcom.ac_if;
1370 struct mii_data *mii;
1371
1372 lwkt_serialize_enter(ifp->if_serializer);
1373
1374 if (sc->nge_tbi) {
1375 if (sc->nge_link == 0) {
1376 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1377 & NGE_TBIBMSR_ANEG_DONE) {
1378 kprintf("nge%d: gigabit link up\n",
1379 sc->nge_unit);
1380 nge_miibus_statchg(sc->nge_miibus);
1381 sc->nge_link++;
1382 if (!ifq_is_empty(&ifp->if_snd))
1383 if_devstart(ifp);
1384 }
1385 }
1386 } else {
1387 mii = device_get_softc(sc->nge_miibus);
1388 mii_tick(mii);
1389
1390 if (sc->nge_link == 0) {
1391 if (mii->mii_media_status & IFM_ACTIVE &&
1392 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1393 sc->nge_link++;
1394 if (IFM_SUBTYPE(mii->mii_media_active)
1395 == IFM_1000_T)
1396 kprintf("nge%d: gigabit link up\n",
1397 sc->nge_unit);
1398 if (!ifq_is_empty(&ifp->if_snd))
1399 if_devstart(ifp);
1400 }
1401 }
1402 }
1403 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1404
1405 lwkt_serialize_exit(ifp->if_serializer);
1406 }
1407
1408 #ifdef IFPOLL_ENABLE
1409
1410 static void
1411 nge_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1412 {
1413 struct nge_softc *sc = ifp->if_softc;
1414
1415 ASSERT_SERIALIZED(ifp->if_serializer);
1416
1417 /*
1418 * On the nge, reading the status register also clears it.
1419 * So before returning to intr mode we must make sure that all
1420 * possible pending sources of interrupts have been served.
1421 * In practice this means run to completion the *eof routines,
1422 * and then call the interrupt routine
1423 */
1424 sc->rxcycles = count;
1425 nge_rxeof(sc);
1426 nge_txeof(sc);
1427 if (!ifq_is_empty(&ifp->if_snd))
1428 if_devstart(ifp);
1429
1430 if (sc->nge_npoll.ifpc_stcount-- == 0) {
1431 uint32_t status;
1432
1433 sc->nge_npoll.ifpc_stcount = sc->nge_npoll.ifpc_stfrac;
1434
1435 /* Reading the ISR register clears all interrupts. */
1436 status = CSR_READ_4(sc, NGE_ISR);
1437
1438 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1439 nge_rxeof(sc);
1440
1441 if (status & (NGE_ISR_RX_IDLE))
1442 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1443
1444 if (status & NGE_ISR_SYSERR) {
1445 nge_reset(sc);
1446 nge_init(sc);
1447 }
1448 }
1449 }
1450
1451 static void
1452 nge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1453 {
1454 struct nge_softc *sc = ifp->if_softc;
1455
1456 ASSERT_SERIALIZED(ifp->if_serializer);
1457
1458 if (info != NULL) {
1459 int cpuid = sc->nge_npoll.ifpc_cpuid;
1460
1461 info->ifpi_rx[cpuid].poll_func = nge_npoll_compat;
1462 info->ifpi_rx[cpuid].arg = NULL;
1463 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1464
1465 if (ifp->if_flags & IFF_RUNNING) {
1466 /* disable interrupts */
1467 CSR_WRITE_4(sc, NGE_IER, 0);
1468 sc->nge_npoll.ifpc_stcount = 0;
1469 }
1470 ifq_set_cpuid(&ifp->if_snd, cpuid);
1471 } else {
1472 if (ifp->if_flags & IFF_RUNNING) {
1473 /* enable interrupts */
1474 CSR_WRITE_4(sc, NGE_IER, 1);
1475 }
1476 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->nge_irq));
1477 }
1478 }
1479
1480 #endif /* IFPOLL_ENABLE */
1481
1482 static void
1483 nge_intr(void *arg)
1484 {
1485 struct nge_softc *sc = arg;
1486 struct ifnet *ifp = &sc->arpcom.ac_if;
1487 uint32_t status;
1488
1489 /* Supress unwanted interrupts */
1490 if (!(ifp->if_flags & IFF_UP)) {
1491 nge_stop(sc);
1492 return;
1493 }
1494
1495 /* Disable interrupts. */
1496 CSR_WRITE_4(sc, NGE_IER, 0);
1497
1498 /* Data LED on for TBI mode */
1499 if(sc->nge_tbi)
1500 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1501 | NGE_GPIO_GP3_OUT);
1502
1503 for (;;) {
1504 /* Reading the ISR register clears all interrupts. */
1505 status = CSR_READ_4(sc, NGE_ISR);
1506
1507 if ((status & NGE_INTRS) == 0)
1508 break;
1509
1510 if ((status & NGE_ISR_TX_DESC_OK) ||
1511 (status & NGE_ISR_TX_ERR) ||
1512 (status & NGE_ISR_TX_OK) ||
1513 (status & NGE_ISR_TX_IDLE))
1514 nge_txeof(sc);
1515
1516 if ((status & NGE_ISR_RX_DESC_OK) ||
1517 (status & NGE_ISR_RX_ERR) ||
1518 (status & NGE_ISR_RX_OFLOW) ||
1519 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1520 (status & NGE_ISR_RX_IDLE) ||
1521 (status & NGE_ISR_RX_OK))
1522 nge_rxeof(sc);
1523
1524 if ((status & NGE_ISR_RX_IDLE))
1525 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1526
1527 if (status & NGE_ISR_SYSERR) {
1528 nge_reset(sc);
1529 ifp->if_flags &= ~IFF_RUNNING;
1530 nge_init(sc);
1531 }
1532
1533 #ifdef notyet
1534 /* mii_tick should only be called once per second */
1535 if (status & NGE_ISR_PHY_INTR) {
1536 sc->nge_link = 0;
1537 nge_tick_serialized(sc);
1538 }
1539 #endif
1540 }
1541
1542 /* Re-enable interrupts. */
1543 CSR_WRITE_4(sc, NGE_IER, 1);
1544
1545 if (!ifq_is_empty(&ifp->if_snd))
1546 if_devstart(ifp);
1547
1548 /* Data LED off for TBI mode */
1549
1550 if(sc->nge_tbi)
1551 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1552 & ~NGE_GPIO_GP3_OUT);
1553 }
1554
1555 /*
1556 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1557 * pointers to the fragment pointers.
1558 */
1559 static int
1560 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1561 {
1562 struct nge_desc *f = NULL;
1563 struct mbuf *m;
1564 int frag, cur, cnt = 0;
1565
1566 /*
1567 * Start packing the mbufs in this chain into
1568 * the fragment pointers. Stop when we run out
1569 * of fragments or hit the end of the mbuf chain.
1570 */
1571 cur = frag = *txidx;
1572
1573 for (m = m_head; m != NULL; m = m->m_next) {
1574 if (m->m_len != 0) {
1575 if ((NGE_TX_LIST_CNT -
1576 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1577 break;
1578 f = &sc->nge_ldata->nge_tx_list[frag];
1579 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1580 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1581 if (cnt != 0)
1582 f->nge_ctl |= NGE_CMDSTS_OWN;
1583 cur = frag;
1584 NGE_INC(frag, NGE_TX_LIST_CNT);
1585 cnt++;
1586 }
1587 }
1588 /* Caller should make sure that 'm_head' is not excessive fragmented */
1589 KASSERT(m == NULL, ("too many fragments"));
1590
1591 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1592 if (m_head->m_pkthdr.csum_flags) {
1593 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1594 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1595 NGE_TXEXTSTS_IPCSUM;
1596 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1597 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1598 NGE_TXEXTSTS_TCPCSUM;
1599 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1600 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1601 NGE_TXEXTSTS_UDPCSUM;
1602 }
1603
1604 if (m_head->m_flags & M_VLANTAG) {
1605 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1606 (NGE_TXEXTSTS_VLANPKT|m_head->m_pkthdr.ether_vlantag);
1607 }
1608
1609 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1610 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1611 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1612 sc->nge_cdata.nge_tx_cnt += cnt;
1613 *txidx = frag;
1614
1615 return(0);
1616 }
1617
1618 /*
1619 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1620 * to the mbuf data regions directly in the transmit lists. We also save a
1621 * copy of the pointers since the transmit list fragment pointers are
1622 * physical addresses.
1623 */
1624
1625 static void
1626 nge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1627 {
1628 struct nge_softc *sc = ifp->if_softc;
1629 struct mbuf *m_head = NULL, *m_defragged;
1630 uint32_t idx;
1631 int need_trans;
1632
1633 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1634
1635 if (!sc->nge_link) {
1636 ifq_purge(&ifp->if_snd);
1637 return;
1638 }
1639
1640 idx = sc->nge_cdata.nge_tx_prod;
1641
1642 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1643 return;
1644
1645 need_trans = 0;
1646 while (sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1647 struct mbuf *m;
1648 int cnt;
1649
1650 m_defragged = NULL;
1651 m_head = ifq_dequeue(&ifp->if_snd);
1652 if (m_head == NULL)
1653 break;
1654
1655 again:
1656 cnt = 0;
1657 for (m = m_head; m != NULL; m = m->m_next)
1658 ++cnt;
1659 if ((NGE_TX_LIST_CNT -
1660 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) {
1661 if (m_defragged != NULL) {
1662 /*
1663 * Even after defragmentation, there
1664 * are still too many fragments, so
1665 * drop this packet.
1666 */
1667 m_freem(m_head);
1668 ifq_set_oactive(&ifp->if_snd);
1669 break;
1670 }
1671
1672 m_defragged = m_defrag(m_head, MB_DONTWAIT);
1673 if (m_defragged == NULL) {
1674 m_freem(m_head);
1675 continue;
1676 }
1677 m_head = m_defragged;
1678
1679 /* Recount # of fragments */
1680 goto again;
1681 }
1682
1683 nge_encap(sc, m_head, &idx);
1684 need_trans = 1;
1685
1686 ETHER_BPF_MTAP(ifp, m_head);
1687 }
1688
1689 if (!need_trans)
1690 return;
1691
1692 /* Transmit */
1693 sc->nge_cdata.nge_tx_prod = idx;
1694 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1695
1696 /*
1697 * Set a timeout in case the chip goes out to lunch.
1698 */
1699 ifp->if_timer = 5;
1700 }
1701
1702 static void
1703 nge_init(void *xsc)
1704 {
1705 struct nge_softc *sc = xsc;
1706 struct ifnet *ifp = &sc->arpcom.ac_if;
1707 struct mii_data *mii;
1708
1709 if (ifp->if_flags & IFF_RUNNING) {
1710 return;
1711 }
1712
1713 /*
1714 * Cancel pending I/O and free all RX/TX buffers.
1715 */
1716 nge_stop(sc);
1717 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1718
1719 if (sc->nge_tbi)
1720 mii = NULL;
1721 else
1722 mii = device_get_softc(sc->nge_miibus);
1723
1724 /* Set MAC address */
1725 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1726 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1727 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1728 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1729 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1730 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1731 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1732 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1733 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1734
1735 /* Init circular RX list. */
1736 if (nge_list_rx_init(sc) == ENOBUFS) {
1737 kprintf("nge%d: initialization failed: no "
1738 "memory for rx buffers\n", sc->nge_unit);
1739 nge_stop(sc);
1740 return;
1741 }
1742
1743 /*
1744 * Init tx descriptors.
1745 */
1746 nge_list_tx_init(sc);
1747
1748 /*
1749 * For the NatSemi chip, we have to explicitly enable the
1750 * reception of ARP frames, as well as turn on the 'perfect
1751 * match' filter where we store the station address, otherwise
1752 * we won't receive unicasts meant for this host.
1753 */
1754 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1755 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1756
1757 /* If we want promiscuous mode, set the allframes bit. */
1758 if (ifp->if_flags & IFF_PROMISC)
1759 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1760 else
1761 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1762
1763 /*
1764 * Set the capture broadcast bit to capture broadcast frames.
1765 */
1766 if (ifp->if_flags & IFF_BROADCAST)
1767 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1768 else
1769 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1770
1771 /*
1772 * Load the multicast filter.
1773 */
1774 nge_setmulti(sc);
1775
1776 /* Turn the receive filter on */
1777 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1778
1779 /*
1780 * Load the address of the RX and TX lists.
1781 */
1782 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1783 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1784 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1785 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1786
1787 /* Set RX configuration */
1788 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1789 /*
1790 * Enable hardware checksum validation for all IPv4
1791 * packets, do not reject packets with bad checksums.
1792 */
1793 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1794
1795 /*
1796 * Tell the chip to detect and strip VLAN tag info from
1797 * received frames. The tag will be provided in the extsts
1798 * field in the RX descriptors.
1799 */
1800 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1801 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1802
1803 /* Set TX configuration */
1804 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1805
1806 /*
1807 * Enable TX IPv4 checksumming on a per-packet basis.
1808 */
1809 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1810
1811 /*
1812 * Tell the chip to insert VLAN tags on a per-packet basis as
1813 * dictated by the code in the frame encapsulation routine.
1814 */
1815 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1816
1817 /* Set full/half duplex mode. */
1818 if (sc->nge_tbi) {
1819 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1820 == IFM_FDX) {
1821 NGE_SETBIT(sc, NGE_TX_CFG,
1822 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1823 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1824 } else {
1825 NGE_CLRBIT(sc, NGE_TX_CFG,
1826 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1827 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1828 }
1829 } else {
1830 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1831 NGE_SETBIT(sc, NGE_TX_CFG,
1832 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1833 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1834 } else {
1835 NGE_CLRBIT(sc, NGE_TX_CFG,
1836 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1837 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1838 }
1839 }
1840
1841 /*
1842 * Enable the delivery of PHY interrupts based on
1843 * link/speed/duplex status changes. Also enable the
1844 * extsts field in the DMA descriptors (needed for
1845 * TCP/IP checksum offload on transmit).
1846 */
1847 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1848 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
1849
1850 /*
1851 * Configure interrupt holdoff (moderation). We can
1852 * have the chip delay interrupt delivery for a certain
1853 * period. Units are in 100us, and the max setting
1854 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1855 */
1856 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1857
1858 /*
1859 * Enable interrupts.
1860 */
1861 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1862 #ifdef IFPOLL_ENABLE
1863 /*
1864 * ... only enable interrupts if we are not polling, make sure
1865 * they are off otherwise.
1866 */
1867 if (ifp->if_flags & IFF_NPOLLING) {
1868 CSR_WRITE_4(sc, NGE_IER, 0);
1869 sc->nge_npoll.ifpc_stcount = 0;
1870 } else
1871 #endif /* IFPOLL_ENABLE */
1872 CSR_WRITE_4(sc, NGE_IER, 1);
1873
1874 /* Enable receiver and transmitter. */
1875 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
1876 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1877
1878 nge_ifmedia_upd(ifp);
1879
1880 ifp->if_flags |= IFF_RUNNING;
1881 ifq_clr_oactive(&ifp->if_snd);
1882 }
1883
1884 /*
1885 * Set media options.
1886 */
1887 static int
1888 nge_ifmedia_upd(struct ifnet *ifp)
1889 {
1890 struct nge_softc *sc = ifp->if_softc;
1891 struct mii_data *mii;
1892
1893 if (sc->nge_tbi) {
1894 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1895 == IFM_AUTO) {
1896 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1897 CSR_READ_4(sc, NGE_TBI_ANAR)
1898 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1899 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1900 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1901 | NGE_TBIBMCR_RESTART_ANEG);
1902 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1903 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1904 & IFM_GMASK) == IFM_FDX) {
1905 NGE_SETBIT(sc, NGE_TX_CFG,
1906 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1907 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1908
1909 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1910 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1911 } else {
1912 NGE_CLRBIT(sc, NGE_TX_CFG,
1913 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1914 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1915
1916 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1917 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1918 }
1919
1920 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1921 & ~NGE_GPIO_GP3_OUT);
1922 } else {
1923 mii = device_get_softc(sc->nge_miibus);
1924 sc->nge_link = 0;
1925 if (mii->mii_instance) {
1926 struct mii_softc *miisc;
1927 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1928 miisc = LIST_NEXT(miisc, mii_list))
1929 mii_phy_reset(miisc);
1930 }
1931 mii_mediachg(mii);
1932 }
1933
1934 return(0);
1935 }
1936
1937 /*
1938 * Report current media status.
1939 */
1940 static void
1941 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1942 {
1943 struct nge_softc *sc = ifp->if_softc;
1944 struct mii_data *mii;
1945
1946 if (sc->nge_tbi) {
1947 ifmr->ifm_status = IFM_AVALID;
1948 ifmr->ifm_active = IFM_ETHER;
1949
1950 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
1951 ifmr->ifm_status |= IFM_ACTIVE;
1952 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1953 ifmr->ifm_active |= IFM_LOOP;
1954 if (!(CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)) {
1955 ifmr->ifm_active |= IFM_NONE;
1956 ifmr->ifm_status = 0;
1957 return;
1958 }
1959 ifmr->ifm_active |= IFM_1000_SX;
1960 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1961 == IFM_AUTO) {
1962 ifmr->ifm_active |= IFM_AUTO;
1963 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1964 & NGE_TBIANAR_FDX) {
1965 ifmr->ifm_active |= IFM_FDX;
1966 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1967 & NGE_TBIANAR_HDX) {
1968 ifmr->ifm_active |= IFM_HDX;
1969 }
1970 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1971 == IFM_FDX)
1972 ifmr->ifm_active |= IFM_FDX;
1973 else
1974 ifmr->ifm_active |= IFM_HDX;
1975
1976 } else {
1977 mii = device_get_softc(sc->nge_miibus);
1978 mii_pollstat(mii);
1979 ifmr->ifm_active = mii->mii_media_active;
1980 ifmr->ifm_status = mii->mii_media_status;
1981 }
1982 }
1983
1984 static int
1985 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1986 {
1987 struct nge_softc *sc = ifp->if_softc;
1988 struct ifreq *ifr = (struct ifreq *) data;
1989 struct mii_data *mii;
1990 int error = 0;
1991
1992 switch(command) {
1993 case SIOCSIFMTU:
1994 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
1995 error = EINVAL;
1996 } else {
1997 ifp->if_mtu = ifr->ifr_mtu;
1998 /*
1999 * Workaround: if the MTU is larger than
2000 * 8152 (TX FIFO size minus 64 minus 18), turn off
2001 * TX checksum offloading.
2002 */
2003 if (ifr->ifr_mtu >= 8152)
2004 ifp->if_hwassist = 0;
2005 else
2006 ifp->if_hwassist = NGE_CSUM_FEATURES;
2007 }
2008 break;
2009 case SIOCSIFFLAGS:
2010 if (ifp->if_flags & IFF_UP) {
2011 if (ifp->if_flags & IFF_RUNNING &&
2012 ifp->if_flags & IFF_PROMISC &&
2013 !(sc->nge_if_flags & IFF_PROMISC)) {
2014 NGE_SETBIT(sc, NGE_RXFILT_CTL,
2015 NGE_RXFILTCTL_ALLPHYS|
2016 NGE_RXFILTCTL_ALLMULTI);
2017 } else if (ifp->if_flags & IFF_RUNNING &&
2018 !(ifp->if_flags & IFF_PROMISC) &&
2019 sc->nge_if_flags & IFF_PROMISC) {
2020 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2021 NGE_RXFILTCTL_ALLPHYS);
2022 if (!(ifp->if_flags & IFF_ALLMULTI))
2023 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2024 NGE_RXFILTCTL_ALLMULTI);
2025 } else {
2026 ifp->if_flags &= ~IFF_RUNNING;
2027 nge_init(sc);
2028 }
2029 } else {
2030 if (ifp->if_flags & IFF_RUNNING)
2031 nge_stop(sc);
2032 }
2033 sc->nge_if_flags = ifp->if_flags;
2034 error = 0;
2035 break;
2036 case SIOCADDMULTI:
2037 case SIOCDELMULTI:
2038 nge_setmulti(sc);
2039 error = 0;
2040 break;
2041 case SIOCGIFMEDIA:
2042 case SIOCSIFMEDIA:
2043 if (sc->nge_tbi) {
2044 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2045 command);
2046 } else {
2047 mii = device_get_softc(sc->nge_miibus);
2048 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2049 command);
2050 }
2051 break;
2052 default:
2053 error = ether_ioctl(ifp, command, data);
2054 break;
2055 }
2056 return(error);
2057 }
2058
2059 static void
2060 nge_watchdog(struct ifnet *ifp)
2061 {
2062 struct nge_softc *sc = ifp->if_softc;
2063
2064 IFNET_STAT_INC(ifp, oerrors, 1);
2065 kprintf("nge%d: watchdog timeout\n", sc->nge_unit);
2066
2067 nge_stop(sc);
2068 nge_reset(sc);
2069 ifp->if_flags &= ~IFF_RUNNING;
2070 nge_init(sc);
2071
2072 if (!ifq_is_empty(&ifp->if_snd))
2073 if_devstart(ifp);
2074 }
2075
2076 /*
2077 * Stop the adapter and free any mbufs allocated to the
2078 * RX and TX lists.
2079 */
2080 static void
2081 nge_stop(struct nge_softc *sc)
2082 {
2083 struct ifnet *ifp = &sc->arpcom.ac_if;
2084 struct ifmedia_entry *ifm;
2085 struct mii_data *mii;
2086 int i, itmp, mtmp, dtmp;
2087
2088 ifp->if_timer = 0;
2089 if (sc->nge_tbi)
2090 mii = NULL;
2091 else
2092 mii = device_get_softc(sc->nge_miibus);
2093
2094 callout_stop(&sc->nge_stat_timer);
2095 CSR_WRITE_4(sc, NGE_IER, 0);
2096 CSR_WRITE_4(sc, NGE_IMR, 0);
2097 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2098 DELAY(1000);
2099 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2100 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2101
2102 /*
2103 * Isolate/power down the PHY, but leave the media selection
2104 * unchanged so that things will be put back to normal when
2105 * we bring the interface back up.
2106 */
2107 itmp = ifp->if_flags;
2108 ifp->if_flags |= IFF_UP;
2109
2110 if (sc->nge_tbi)
2111 ifm = sc->nge_ifmedia.ifm_cur;
2112 else
2113 ifm = mii->mii_media.ifm_cur;
2114
2115 mtmp = ifm->ifm_media;
2116 dtmp = ifm->ifm_data;
2117 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2118 ifm->ifm_data = MII_MEDIA_NONE;
2119
2120 if (!sc->nge_tbi)
2121 mii_mediachg(mii);
2122 ifm->ifm_media = mtmp;
2123 ifm->ifm_data = dtmp;
2124 ifp->if_flags = itmp;
2125
2126 sc->nge_link = 0;
2127
2128 /*
2129 * Free data in the RX lists.
2130 */
2131 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2132 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2133 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2134 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2135 }
2136 }
2137 bzero(&sc->nge_ldata->nge_rx_list,
2138 sizeof(sc->nge_ldata->nge_rx_list));
2139
2140 /*
2141 * Free the TX list buffers.
2142 */
2143 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2144 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2145 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2146 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2147 }
2148 }
2149
2150 bzero(&sc->nge_ldata->nge_tx_list,
2151 sizeof(sc->nge_ldata->nge_tx_list));
2152
2153 ifp->if_flags &= ~IFF_RUNNING;
2154 ifq_clr_oactive(&ifp->if_snd);
2155 }
2156
2157 /*
2158 * Stop all chip I/O so that the kernel's probe routines don't
2159 * get confused by errant DMAs when rebooting.
2160 */
2161 static void
2162 nge_shutdown(device_t dev)
2163 {
2164 struct nge_softc *sc = device_get_softc(dev);
2165 struct ifnet *ifp = &sc->arpcom.ac_if;
2166
2167 lwkt_serialize_enter(ifp->if_serializer);
2168 nge_reset(sc);
2169 nge_stop(sc);
2170 lwkt_serialize_exit(ifp->if_serializer);
2171 }
2172
Cache object: f64b46974ca5377c0daee80fc2ffc25c
|