Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/netif/oce/oce_if.h
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1 /*- 2 * Copyright (C) 2013 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Emulex Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39 40 /* $FreeBSD: src/sys/dev/oce/oce_if.h,v 1.6 2013/07/07 00:30:13 svnexp Exp $ */ 41 42 #include <sys/param.h> 43 #include <sys/endian.h> 44 #include <sys/module.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/mbuf.h> 48 #include <sys/rman.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/queue.h> 52 #include <sys/taskqueue.h> 53 #include <sys/lock.h> 54 #include <sys/sysctl.h> 55 #include <sys/random.h> 56 #include <sys/firmware.h> 57 #include <sys/systm.h> 58 #include <sys/proc.h> 59 60 #include <bus/pci/pcireg.h> 61 #include <bus/pci/pcivar.h> 62 63 #include <net/bpf.h> 64 #include <net/ethernet.h> 65 #include <net/if.h> 66 #include <net/if_types.h> 67 #include <net/if_media.h> 68 #include <net/ifq_var.h> 69 #include <net/vlan/if_vlan_ether.h> 70 #include <net/vlan/if_vlan_var.h> 71 #include <net/if_dl.h> 72 73 #include <netinet/in.h> 74 #include <netinet/in_systm.h> 75 #include <netinet/in_var.h> 76 #include <netinet/if_ether.h> 77 #include <netinet/ip.h> 78 #include <netinet/ip6.h> 79 #include <netinet6/in6_var.h> 80 #include <netinet6/ip6_mroute.h> 81 82 #include <netinet/udp.h> 83 #include <netinet/tcp.h> 84 #include <netinet/sctp.h> 85 #if 0 /* XXX swildner: LRO */ 86 #include <netinet/tcp_lro.h> 87 #endif 88 89 #include "oce_hw.h" 90 91 #define COMPONENT_REVISION "4.6.95.0" 92 93 /* OCE devices supported by this driver */ 94 #define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 95 #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 96 #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 97 #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 98 #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 99 #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ 100 #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */ 101 102 #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 103 (sc->flags & OCE_FLAGS_BE2))? 1:0) 104 #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3) 105 #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2) 106 #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 107 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) 108 #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0) 109 110 #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \ 111 (sc->function_mode & FNM_UMC_MODE) || \ 112 (sc->function_mode & FNM_VNIC_MODE)) 113 #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40 114 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC) 115 116 117 /* proportion Service Level Interface queues */ 118 #define OCE_MAX_UNITS 2 119 #define OCE_MAX_PPORT OCE_MAX_UNITS 120 #define OCE_MAX_VPORT OCE_MAX_UNITS 121 122 #define OCE_NCPUS ncpus 123 124 /* This should be powers of 2. Like 2,4,8 & 16 */ 125 #define OCE_MAX_RSS 8 126 #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ 127 #if 0 /* XXX swildner: RSS */ 128 #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc)) 129 #else 130 #define is_rss_enabled(sc) 0 131 #endif 132 133 #define OCE_MIN_RQ 1 134 #define OCE_MIN_WQ 1 135 136 #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 137 #define OCE_MAX_WQ 8 138 139 #define OCE_MAX_EQ 32 140 #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */ 141 #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */ 142 143 #define OCE_DEFAULT_WQ_EQD 16 144 #define OCE_MAX_PACKET_Q 16 145 #define OCE_RQ_BUF_SIZE 2048 146 #define OCE_LSO_MAX_SIZE (64 * 1024) 147 #define LONG_TIMEOUT 30 148 #define OCE_MAX_JUMBO_FRAME_SIZE 9018 149 #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \ 150 ETHER_VLAN_ENCAP_LEN - \ 151 ETHER_HDR_LEN) 152 153 #define OCE_MAX_TX_ELEMENTS 29 154 #define OCE_MAX_TX_DESC 1024 155 #define OCE_MAX_TX_SIZE 65535 156 #define OCE_MAX_RX_SIZE 4096 157 #define OCE_MAX_RQ_POSTS 255 158 #define OCE_DEFAULT_PROMISCUOUS 0 159 160 161 #define RSS_ENABLE_IPV4 0x1 162 #define RSS_ENABLE_TCP_IPV4 0x2 163 #define RSS_ENABLE_IPV6 0x4 164 #define RSS_ENABLE_TCP_IPV6 0x8 165 166 #define INDIRECTION_TABLE_ENTRIES 128 167 168 /* flow control definitions */ 169 #define OCE_FC_NONE 0x00000000 170 #define OCE_FC_TX 0x00000001 171 #define OCE_FC_RX 0x00000002 172 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 173 174 175 /* Interface capabilities to give device when creating interface */ 176 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 177 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 178 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 179 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 180 MBX_RX_IFACE_FLAGS_RSS | \ 181 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 182 183 /* Interface capabilities to enable by default (others set dynamically) */ 184 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 185 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 186 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 187 188 #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 189 #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 190 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \ 191 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU) 192 #define OCE_IF_HWASSIST_NONE 0 193 #define OCE_IF_CAPABILITIES_NONE 0 194 195 196 #define ETH_ADDR_LEN 6 197 #define MAX_VLANFILTER_SIZE 64 198 #define MAX_VLANS 4096 199 200 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 201 #define BSWAP_8(x) ((x) & 0xff) 202 #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8)) 203 #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \ 204 BSWAP_16((x) >> 16)) 205 #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 206 BSWAP_32((x) >> 32)) 207 208 #define for_all_wq_queues(sc, wq, i) \ 209 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 210 #define for_all_rq_queues(sc, rq, i) \ 211 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) 212 #define for_all_rss_queues(sc, rq, i) \ 213 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \ 214 i++, rq = sc->rq[i + 1]) 215 #define for_all_evnt_queues(sc, eq, i) \ 216 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 217 #define for_all_cq_queues(sc, cq, i) \ 218 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 219 220 221 /* Flash specific */ 222 #define IOCTL_COOKIE "SERVERENGINES CORP" 223 #define MAX_FLASH_COMP 32 224 225 #define IMG_ISCSI 160 226 #define IMG_REDBOOT 224 227 #define IMG_BIOS 34 228 #define IMG_PXEBIOS 32 229 #define IMG_FCOEBIOS 33 230 #define IMG_ISCSI_BAK 176 231 #define IMG_FCOE 162 232 #define IMG_FCOE_BAK 178 233 #define IMG_NCSI 16 234 #define IMG_PHY 192 235 #define FLASHROM_OPER_FLASH 1 236 #define FLASHROM_OPER_SAVE 2 237 #define FLASHROM_OPER_REPORT 4 238 #define FLASHROM_OPER_FLASH_PHY 9 239 #define FLASHROM_OPER_SAVE_PHY 10 240 #define TN_8022 13 241 242 enum { 243 PHY_TYPE_CX4_10GB = 0, 244 PHY_TYPE_XFP_10GB, 245 PHY_TYPE_SFP_1GB, 246 PHY_TYPE_SFP_PLUS_10GB, 247 PHY_TYPE_KR_10GB, 248 PHY_TYPE_KX4_10GB, 249 PHY_TYPE_BASET_10GB, 250 PHY_TYPE_BASET_1GB, 251 PHY_TYPE_BASEX_1GB, 252 PHY_TYPE_SGMII, 253 PHY_TYPE_DISABLED = 255 254 }; 255 256 /** 257 * @brief Define and hold all necessary info for a single interrupt 258 */ 259 #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */ 260 #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */ 261 262 typedef struct oce_intr_info { 263 void *tag; /* cookie returned by bus_setup_intr */ 264 struct resource *intr_res; /* PCI resource container */ 265 int irq_rr; /* resource id for the interrupt */ 266 int irq_type; /* interrupt type */ 267 struct oce_softc *sc; /* pointer to the parent soft c */ 268 struct oce_eq *eq; /* pointer to the connected EQ */ 269 struct taskqueue *tq; /* Associated task queue */ 270 struct task task; /* task queue task */ 271 char task_name[32]; /* task name */ 272 int vector; /* interrupt vector number */ 273 } OCE_INTR_INFO, *POCE_INTR_INFO; 274 275 276 /* Ring related */ 277 #define GET_Q_NEXT(_START, _STEP, _END) \ 278 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ 279 : (((_START) + (_STEP)) - (_END))) 280 281 #define DBUF_PA(obj) ((obj)->addr) 282 #define DBUF_VA(obj) ((obj)->ptr) 283 #define DBUF_TAG(obj) ((obj)->tag) 284 #define DBUF_MAP(obj) ((obj)->map) 285 #define DBUF_SYNC(obj, flags) \ 286 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags)) 287 288 #define RING_NUM_PENDING(ring) ring->num_used 289 #define RING_FULL(ring) (ring->num_used == ring->num_items) 290 #define RING_EMPTY(ring) (ring->num_used == 0) 291 #define RING_NUM_FREE(ring) \ 292 (uint32_t)(ring->num_items - ring->num_used) 293 #define RING_GET(ring, n) \ 294 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items) 295 #define RING_PUT(ring, n) \ 296 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items) 297 298 #define RING_GET_CONSUMER_ITEM_VA(ring, type) \ 299 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx) 300 #define RING_GET_CONSUMER_ITEM_PA(ring, type) \ 301 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx) 302 #define RING_GET_PRODUCER_ITEM_VA(ring, type) \ 303 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx) 304 #define RING_GET_PRODUCER_ITEM_PA(ring, type) \ 305 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx) 306 307 #define OCE_DMAPTR(o, c) ((c *)(o)->ptr) 308 309 struct oce_packet_desc { 310 struct mbuf *mbuf; 311 bus_dmamap_t map; 312 int nsegs; 313 uint32_t wqe_idx; 314 }; 315 316 typedef struct oce_dma_mem { 317 bus_dma_tag_t tag; 318 bus_dmamap_t map; 319 void *ptr; 320 bus_addr_t paddr; 321 } OCE_DMA_MEM, *POCE_DMA_MEM; 322 323 typedef struct oce_ring_buffer_s { 324 uint16_t cidx; /* Get ptr */ 325 uint16_t pidx; /* Put Ptr */ 326 size_t item_size; 327 size_t num_items; 328 uint32_t num_used; 329 OCE_DMA_MEM dma; 330 } oce_ring_buffer_t; 331 332 /* Stats */ 333 #define OCE_UNICAST_PACKET 0 334 #define OCE_MULTICAST_PACKET 1 335 #define OCE_BROADCAST_PACKET 2 336 #define OCE_RSVD_PACKET 3 337 338 struct oce_rx_stats { 339 /* Total Receive Stats*/ 340 uint64_t t_rx_pkts; 341 uint64_t t_rx_bytes; 342 uint32_t t_rx_frags; 343 uint32_t t_rx_mcast_pkts; 344 uint32_t t_rx_ucast_pkts; 345 uint32_t t_rxcp_errs; 346 }; 347 struct oce_tx_stats { 348 /*Total Transmit Stats */ 349 uint64_t t_tx_pkts; 350 uint64_t t_tx_bytes; 351 uint32_t t_tx_reqs; 352 uint32_t t_tx_stops; 353 uint32_t t_tx_wrbs; 354 uint32_t t_tx_compl; 355 uint32_t t_ipv6_ext_hdr_tx_drop; 356 }; 357 358 struct oce_be_stats { 359 uint8_t be_on_die_temperature; 360 uint32_t be_tx_events; 361 uint32_t eth_red_drops; 362 uint32_t rx_drops_no_pbuf; 363 uint32_t rx_drops_no_txpb; 364 uint32_t rx_drops_no_erx_descr; 365 uint32_t rx_drops_no_tpre_descr; 366 uint32_t rx_drops_too_many_frags; 367 uint32_t rx_drops_invalid_ring; 368 uint32_t forwarded_packets; 369 uint32_t rx_drops_mtu; 370 uint32_t rx_crc_errors; 371 uint32_t rx_alignment_symbol_errors; 372 uint32_t rx_pause_frames; 373 uint32_t rx_priority_pause_frames; 374 uint32_t rx_control_frames; 375 uint32_t rx_in_range_errors; 376 uint32_t rx_out_range_errors; 377 uint32_t rx_frame_too_long; 378 uint32_t rx_address_match_errors; 379 uint32_t rx_dropped_too_small; 380 uint32_t rx_dropped_too_short; 381 uint32_t rx_dropped_header_too_small; 382 uint32_t rx_dropped_tcp_length; 383 uint32_t rx_dropped_runt; 384 uint32_t rx_ip_checksum_errs; 385 uint32_t rx_tcp_checksum_errs; 386 uint32_t rx_udp_checksum_errs; 387 uint32_t rx_switched_unicast_packets; 388 uint32_t rx_switched_multicast_packets; 389 uint32_t rx_switched_broadcast_packets; 390 uint32_t tx_pauseframes; 391 uint32_t tx_priority_pauseframes; 392 uint32_t tx_controlframes; 393 uint32_t rxpp_fifo_overflow_drop; 394 uint32_t rx_input_fifo_overflow_drop; 395 uint32_t pmem_fifo_overflow_drop; 396 uint32_t jabber_events; 397 }; 398 399 struct oce_xe201_stats { 400 uint64_t tx_pkts; 401 uint64_t tx_unicast_pkts; 402 uint64_t tx_multicast_pkts; 403 uint64_t tx_broadcast_pkts; 404 uint64_t tx_bytes; 405 uint64_t tx_unicast_bytes; 406 uint64_t tx_multicast_bytes; 407 uint64_t tx_broadcast_bytes; 408 uint64_t tx_discards; 409 uint64_t tx_errors; 410 uint64_t tx_pause_frames; 411 uint64_t tx_pause_on_frames; 412 uint64_t tx_pause_off_frames; 413 uint64_t tx_internal_mac_errors; 414 uint64_t tx_control_frames; 415 uint64_t tx_pkts_64_bytes; 416 uint64_t tx_pkts_65_to_127_bytes; 417 uint64_t tx_pkts_128_to_255_bytes; 418 uint64_t tx_pkts_256_to_511_bytes; 419 uint64_t tx_pkts_512_to_1023_bytes; 420 uint64_t tx_pkts_1024_to_1518_bytes; 421 uint64_t tx_pkts_1519_to_2047_bytes; 422 uint64_t tx_pkts_2048_to_4095_bytes; 423 uint64_t tx_pkts_4096_to_8191_bytes; 424 uint64_t tx_pkts_8192_to_9216_bytes; 425 uint64_t tx_lso_pkts; 426 uint64_t rx_pkts; 427 uint64_t rx_unicast_pkts; 428 uint64_t rx_multicast_pkts; 429 uint64_t rx_broadcast_pkts; 430 uint64_t rx_bytes; 431 uint64_t rx_unicast_bytes; 432 uint64_t rx_multicast_bytes; 433 uint64_t rx_broadcast_bytes; 434 uint32_t rx_unknown_protos; 435 uint64_t rx_discards; 436 uint64_t rx_errors; 437 uint64_t rx_crc_errors; 438 uint64_t rx_alignment_errors; 439 uint64_t rx_symbol_errors; 440 uint64_t rx_pause_frames; 441 uint64_t rx_pause_on_frames; 442 uint64_t rx_pause_off_frames; 443 uint64_t rx_frames_too_long; 444 uint64_t rx_internal_mac_errors; 445 uint32_t rx_undersize_pkts; 446 uint32_t rx_oversize_pkts; 447 uint32_t rx_fragment_pkts; 448 uint32_t rx_jabbers; 449 uint64_t rx_control_frames; 450 uint64_t rx_control_frames_unknown_opcode; 451 uint32_t rx_in_range_errors; 452 uint32_t rx_out_of_range_errors; 453 uint32_t rx_address_match_errors; 454 uint32_t rx_vlan_mismatch_errors; 455 uint32_t rx_dropped_too_small; 456 uint32_t rx_dropped_too_short; 457 uint32_t rx_dropped_header_too_small; 458 uint32_t rx_dropped_invalid_tcp_length; 459 uint32_t rx_dropped_runt; 460 uint32_t rx_ip_checksum_errors; 461 uint32_t rx_tcp_checksum_errors; 462 uint32_t rx_udp_checksum_errors; 463 uint32_t rx_non_rss_pkts; 464 uint64_t rx_ipv4_pkts; 465 uint64_t rx_ipv6_pkts; 466 uint64_t rx_ipv4_bytes; 467 uint64_t rx_ipv6_bytes; 468 uint64_t rx_nic_pkts; 469 uint64_t rx_tcp_pkts; 470 uint64_t rx_iscsi_pkts; 471 uint64_t rx_management_pkts; 472 uint64_t rx_switched_unicast_pkts; 473 uint64_t rx_switched_multicast_pkts; 474 uint64_t rx_switched_broadcast_pkts; 475 uint64_t num_forwards; 476 uint32_t rx_fifo_overflow; 477 uint32_t rx_input_fifo_overflow; 478 uint64_t rx_drops_too_many_frags; 479 uint32_t rx_drops_invalid_queue; 480 uint64_t rx_drops_mtu; 481 uint64_t rx_pkts_64_bytes; 482 uint64_t rx_pkts_65_to_127_bytes; 483 uint64_t rx_pkts_128_to_255_bytes; 484 uint64_t rx_pkts_256_to_511_bytes; 485 uint64_t rx_pkts_512_to_1023_bytes; 486 uint64_t rx_pkts_1024_to_1518_bytes; 487 uint64_t rx_pkts_1519_to_2047_bytes; 488 uint64_t rx_pkts_2048_to_4095_bytes; 489 uint64_t rx_pkts_4096_to_8191_bytes; 490 uint64_t rx_pkts_8192_to_9216_bytes; 491 }; 492 493 struct oce_drv_stats { 494 struct oce_rx_stats rx; 495 struct oce_tx_stats tx; 496 union { 497 struct oce_be_stats be; 498 struct oce_xe201_stats xe201; 499 } u0; 500 }; 501 502 #define INTR_RATE_HWM 15000 503 #define INTR_RATE_LWM 10000 504 505 #define OCE_MAX_EQD 128u 506 #define OCE_MIN_EQD 50u 507 508 struct oce_set_eqd { 509 uint32_t eq_id; 510 uint32_t phase; 511 uint32_t delay_multiplier; 512 }; 513 514 struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 515 boolean_t enable; 516 uint32_t min_eqd; /* in usecs */ 517 uint32_t max_eqd; /* in usecs */ 518 uint32_t cur_eqd; /* in usecs */ 519 uint32_t et_eqd; /* configured value when aic is off */ 520 uint64_t ticks; 521 uint64_t intr_prev; 522 }; 523 524 #define MAX_LOCK_DESC_LEN 32 525 struct oce_lock { 526 struct lock lock; 527 char name[MAX_LOCK_DESC_LEN+1]; 528 }; 529 #define OCE_LOCK struct oce_lock 530 531 #define LOCK_CREATE(ocelock, desc) { \ 532 strncpy((ocelock)->name, (desc), MAX_LOCK_DESC_LEN); \ 533 (ocelock)->name[MAX_LOCK_DESC_LEN] = '\0'; \ 534 lockinit(&(ocelock)->lock, (ocelock)->name, 0, LK_CANRECURSE); \ 535 } 536 #define LOCK_DESTROY(ocelock) \ 537 /* if (mtx_initialized(&(lock)->mutex)) */ \ 538 lockuninit(&(ocelock)->lock) 539 #define LOCK(ocelock) lockmgr(&(ocelock)->lock, LK_EXCLUSIVE) 540 #define LOCKED(ocelock) lockowned(&(ocelock)->lock) 541 #define UNLOCK(ocelock) lockmgr(&(ocelock)->lock, LK_RELEASE) 542 543 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) 544 #define MBX_READY_TIMEOUT (1 * 1000 * 1000) 545 #define DEFAULT_DRAIN_TIME 200 546 #define MBX_TIMEOUT_SEC 5 547 #define STAT_TIMEOUT 2000000 548 549 /* size of the packet descriptor array in a transmit queue */ 550 #define OCE_TX_RING_SIZE 2048 551 #define OCE_RX_RING_SIZE 1024 552 #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2) 553 #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE) 554 555 struct oce_dev; 556 557 enum eq_len { 558 EQ_LEN_256 = 256, 559 EQ_LEN_512 = 512, 560 EQ_LEN_1024 = 1024, 561 EQ_LEN_2048 = 2048, 562 EQ_LEN_4096 = 4096 563 }; 564 565 enum eqe_size { 566 EQE_SIZE_4 = 4, 567 EQE_SIZE_16 = 16 568 }; 569 570 enum qtype { 571 QTYPE_EQ, 572 QTYPE_MQ, 573 QTYPE_WQ, 574 QTYPE_RQ, 575 QTYPE_CQ, 576 QTYPE_RSS 577 }; 578 579 typedef enum qstate_e { 580 QDELETED = 0x0, 581 QCREATED = 0x1 582 } qstate_t; 583 584 struct eq_config { 585 enum eq_len q_len; 586 enum eqe_size item_size; 587 uint32_t q_vector_num; 588 uint8_t min_eqd; 589 uint8_t max_eqd; 590 uint8_t cur_eqd; 591 uint8_t pad; 592 }; 593 594 struct oce_eq { 595 uint32_t eq_id; 596 void *parent; 597 void *cb_context; 598 oce_ring_buffer_t *ring; 599 uint32_t ref_count; 600 qstate_t qstate; 601 struct oce_cq *cq[OCE_MAX_CQ_EQ]; 602 int cq_valid; 603 struct eq_config eq_cfg; 604 int vector; 605 uint64_t intr; 606 }; 607 608 enum cq_len { 609 CQ_LEN_256 = 256, 610 CQ_LEN_512 = 512, 611 CQ_LEN_1024 = 1024 612 }; 613 614 struct cq_config { 615 enum cq_len q_len; 616 uint32_t item_size; 617 boolean_t is_eventable; 618 boolean_t sol_eventable; 619 boolean_t nodelay; 620 uint16_t dma_coalescing; 621 }; 622 623 typedef uint16_t(*cq_handler_t) (void *arg1); 624 625 struct oce_cq { 626 uint32_t cq_id; 627 void *parent; 628 struct oce_eq *eq; 629 cq_handler_t cq_handler; 630 void *cb_arg; 631 oce_ring_buffer_t *ring; 632 qstate_t qstate; 633 struct cq_config cq_cfg; 634 uint32_t ref_count; 635 }; 636 637 638 struct mq_config { 639 uint32_t eqd; 640 uint8_t q_len; 641 uint8_t pad[3]; 642 }; 643 644 645 struct oce_mq { 646 void *parent; 647 oce_ring_buffer_t *ring; 648 uint32_t mq_id; 649 struct oce_cq *cq; 650 struct oce_cq *async_cq; 651 uint32_t mq_free; 652 qstate_t qstate; 653 struct mq_config cfg; 654 }; 655 656 struct oce_mbx_ctx { 657 struct oce_mbx *mbx; 658 void (*cb) (void *ctx); 659 void *cb_ctx; 660 }; 661 662 struct wq_config { 663 uint8_t wq_type; 664 uint16_t buf_size; 665 uint8_t pad[1]; 666 uint32_t q_len; 667 uint16_t pd_id; 668 uint16_t pci_fn_num; 669 uint32_t eqd; /* interrupt delay */ 670 uint32_t nbufs; 671 uint32_t nhdl; 672 }; 673 674 struct oce_tx_queue_stats { 675 uint64_t tx_pkts; 676 uint64_t tx_bytes; 677 uint32_t tx_reqs; 678 uint32_t tx_stops; /* number of times TX Q was stopped */ 679 uint32_t tx_wrbs; 680 uint32_t tx_compl; 681 uint32_t tx_rate; 682 uint32_t ipv6_ext_hdr_tx_drop; 683 }; 684 685 struct oce_wq { 686 OCE_LOCK tx_lock; 687 void *parent; 688 oce_ring_buffer_t *ring; 689 struct oce_cq *cq; 690 bus_dma_tag_t tag; 691 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; 692 uint32_t pkt_desc_tail; 693 uint32_t pkt_desc_head; 694 uint32_t wqm_used; 695 boolean_t resched; 696 uint32_t wq_free; 697 uint32_t tx_deferd; 698 uint32_t pkt_drops; 699 qstate_t qstate; 700 uint16_t wq_id; 701 struct wq_config cfg; 702 int queue_index; 703 struct oce_tx_queue_stats tx_stats; 704 struct buf_ring *br; 705 struct task txtask; 706 uint32_t db_offset; 707 }; 708 709 struct rq_config { 710 uint32_t q_len; 711 uint32_t frag_size; 712 uint32_t mtu; 713 uint32_t if_id; 714 uint32_t is_rss_queue; 715 uint32_t eqd; 716 uint32_t nbufs; 717 }; 718 719 struct oce_rx_queue_stats { 720 uint32_t rx_post_fail; 721 uint32_t rx_ucast_pkts; 722 uint32_t rx_compl; 723 uint64_t rx_bytes; 724 uint64_t rx_bytes_prev; 725 uint64_t rx_pkts; 726 uint32_t rx_rate; 727 uint32_t rx_mcast_pkts; 728 uint32_t rxcp_err; 729 uint32_t rx_frags; 730 uint32_t prev_rx_frags; 731 uint32_t rx_fps; 732 }; 733 734 735 struct oce_rq { 736 struct rq_config cfg; 737 uint32_t rq_id; 738 int queue_index; 739 uint32_t rss_cpuid; 740 void *parent; 741 oce_ring_buffer_t *ring; 742 struct oce_cq *cq; 743 void *pad1; 744 bus_dma_tag_t tag; 745 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE]; 746 uint32_t packets_in; 747 uint32_t packets_out; 748 uint32_t pending; 749 #ifdef notdef 750 struct mbuf *head; 751 struct mbuf *tail; 752 int fragsleft; 753 #endif 754 qstate_t qstate; 755 OCE_LOCK rx_lock; 756 struct oce_rx_queue_stats rx_stats; 757 #if 0 /* XXX swildner: LRO */ 758 struct lro_ctrl lro; 759 int lro_pkts_queued; 760 #endif 761 762 }; 763 764 struct link_status { 765 uint8_t physical_port; 766 uint8_t mac_duplex; 767 uint8_t mac_speed; 768 uint8_t mac_fault; 769 uint8_t mgmt_mac_duplex; 770 uint8_t mgmt_mac_speed; 771 uint16_t qos_link_speed; 772 uint32_t logical_link_status; 773 }; 774 775 776 777 #define OCE_FLAGS_PCIX 0x00000001 778 #define OCE_FLAGS_PCIE 0x00000002 779 #define OCE_FLAGS_MSI_CAPABLE 0x00000004 780 #define OCE_FLAGS_MSIX_CAPABLE 0x00000008 781 #define OCE_FLAGS_USING_MSI 0x00000010 782 #define OCE_FLAGS_USING_MSIX 0x00000020 783 #define OCE_FLAGS_FUNCRESET_RQD 0x00000040 784 #define OCE_FLAGS_VIRTUAL_PORT 0x00000080 785 #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 786 #define OCE_FLAGS_BE3 0x00000200 787 #define OCE_FLAGS_XE201 0x00000400 788 #define OCE_FLAGS_BE2 0x00000800 789 #define OCE_FLAGS_SH 0x00001000 790 791 #define OCE_DEV_BE2_CFG_BAR 1 792 #define OCE_DEV_CFG_BAR 0 793 #define OCE_PCI_CSR_BAR 2 794 #define OCE_PCI_DB_BAR 4 795 796 typedef struct oce_softc { 797 device_t dev; 798 OCE_LOCK dev_lock; 799 800 uint32_t flags; 801 802 uint32_t pcie_link_speed; 803 uint32_t pcie_link_width; 804 805 uint8_t fn; /* PCI function number */ 806 807 struct resource *devcfg_res; 808 bus_space_tag_t devcfg_btag; 809 bus_space_handle_t devcfg_bhandle; 810 void *devcfg_vhandle; 811 812 struct resource *csr_res; 813 bus_space_tag_t csr_btag; 814 bus_space_handle_t csr_bhandle; 815 void *csr_vhandle; 816 817 struct resource *db_res; 818 bus_space_tag_t db_btag; 819 bus_space_handle_t db_bhandle; 820 void *db_vhandle; 821 822 OCE_INTR_INFO intrs[OCE_MAX_EQ]; 823 int intr_count; 824 825 struct ifnet *ifp; 826 827 struct ifmedia media; 828 uint8_t link_status; 829 uint8_t link_speed; 830 uint8_t duplex; 831 uint32_t qos_link_speed; 832 uint32_t speed; 833 834 char fw_version[32]; 835 struct mac_address_format macaddr; 836 837 OCE_DMA_MEM bsmbx; 838 OCE_LOCK bmbx_lock; 839 840 uint32_t config_number; 841 uint32_t asic_revision; 842 uint32_t port_id; 843 uint32_t function_mode; 844 uint32_t function_caps; 845 uint32_t max_tx_rings; 846 uint32_t max_rx_rings; 847 848 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */ 849 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */ 850 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 851 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 852 struct oce_mq *mq; /* Mailbox queue */ 853 854 uint32_t neqs; 855 uint32_t ncqs; 856 uint32_t nrqs; 857 uint32_t nwqs; 858 uint32_t nrssqs; 859 860 uint32_t tx_ring_size; 861 uint32_t rx_ring_size; 862 uint32_t rq_frag_size; 863 864 uint32_t if_id; /* interface ID */ 865 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 866 uint32_t pmac_id; /* PMAC id */ 867 868 uint32_t if_cap_flags; 869 870 uint32_t flow_control; 871 uint32_t promisc; 872 873 struct oce_aic_obj aic_obj[OCE_MAX_EQ]; 874 875 /*Vlan Filtering related */ 876 eventhandler_tag vlan_attach; 877 eventhandler_tag vlan_detach; 878 uint16_t vlans_added; 879 uint8_t vlan_tag[MAX_VLANS]; 880 /*stats */ 881 OCE_DMA_MEM stats_mem; 882 struct oce_drv_stats oce_stats_info; 883 struct callout timer; 884 int8_t be3_native; 885 uint16_t qnq_debug_event; 886 uint16_t qnqid; 887 uint16_t pvid; 888 889 struct sysctl_ctx_list sysctl_ctx; 890 struct sysctl_oid *sysctl_tree; 891 892 } OCE_SOFTC, *POCE_SOFTC; 893 894 895 896 /************************************************** 897 * BUS memory read/write macros 898 * BE3: accesses three BAR spaces (CFG, CSR, DB) 899 * Lancer: accesses one BAR space (CFG) 900 **************************************************/ 901 #define OCE_READ_CSR_MPU(sc, space, o) \ 902 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 903 (sc)->space##_bhandle,o)) \ 904 : (bus_space_read_4((sc)->devcfg_btag, \ 905 (sc)->devcfg_bhandle,o))) 906 #define OCE_READ_REG32(sc, space, o) \ 907 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 908 (sc)->space##_bhandle,o)) \ 909 : (bus_space_read_4((sc)->devcfg_btag, \ 910 (sc)->devcfg_bhandle,o))) 911 #define OCE_READ_REG16(sc, space, o) \ 912 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 913 (sc)->space##_bhandle,o)) \ 914 : (bus_space_read_2((sc)->devcfg_btag, \ 915 (sc)->devcfg_bhandle,o))) 916 #define OCE_READ_REG8(sc, space, o) \ 917 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 918 (sc)->space##_bhandle,o)) \ 919 : (bus_space_read_1((sc)->devcfg_btag, \ 920 (sc)->devcfg_bhandle,o))) 921 922 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \ 923 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 924 (sc)->space##_bhandle,o,v)) \ 925 : (bus_space_write_4((sc)->devcfg_btag, \ 926 (sc)->devcfg_bhandle,o,v))) 927 #define OCE_WRITE_REG32(sc, space, o, v) \ 928 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 929 (sc)->space##_bhandle,o,v)) \ 930 : (bus_space_write_4((sc)->devcfg_btag, \ 931 (sc)->devcfg_bhandle,o,v))) 932 #define OCE_WRITE_REG16(sc, space, o, v) \ 933 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \ 934 (sc)->space##_bhandle,o,v)) \ 935 : (bus_space_write_2((sc)->devcfg_btag, \ 936 (sc)->devcfg_bhandle,o,v))) 937 #define OCE_WRITE_REG8(sc, space, o, v) \ 938 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \ 939 (sc)->space##_bhandle,o,v)) \ 940 : (bus_space_write_1((sc)->devcfg_btag, \ 941 (sc)->devcfg_bhandle,o,v))) 942 943 944 /*********************************************************** 945 * DMA memory functions 946 ***********************************************************/ 947 #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 948 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 949 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); 950 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error); 951 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring); 952 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc, 953 uint32_t q_len, uint32_t num_entries); 954 /************************************************************ 955 * oce_hw_xxx functions 956 ************************************************************/ 957 int oce_clear_rx_buf(struct oce_rq *rq); 958 int oce_hw_pci_alloc(POCE_SOFTC sc); 959 int oce_hw_init(POCE_SOFTC sc); 960 int oce_hw_start(POCE_SOFTC sc); 961 int oce_create_nw_interface(POCE_SOFTC sc); 962 int oce_pci_soft_reset(POCE_SOFTC sc); 963 int oce_hw_update_multicast(POCE_SOFTC sc); 964 void oce_delete_nw_interface(POCE_SOFTC sc); 965 void oce_hw_shutdown(POCE_SOFTC sc); 966 void oce_hw_intr_enable(POCE_SOFTC sc); 967 void oce_hw_intr_disable(POCE_SOFTC sc); 968 void oce_hw_pci_free(POCE_SOFTC sc); 969 970 /*********************************************************** 971 * oce_queue_xxx functions 972 ***********************************************************/ 973 int oce_queue_init_all(POCE_SOFTC sc); 974 int oce_start_rq(struct oce_rq *rq); 975 int oce_start_wq(struct oce_wq *wq); 976 int oce_start_mq(struct oce_mq *mq); 977 int oce_start_rx(POCE_SOFTC sc); 978 void oce_arm_eq(POCE_SOFTC sc, 979 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint); 980 void oce_queue_release_all(POCE_SOFTC sc); 981 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm); 982 void oce_drain_eq(struct oce_eq *eq); 983 void oce_drain_mq_cq(void *arg); 984 void oce_drain_rq_cq(struct oce_rq *rq); 985 void oce_drain_wq_cq(struct oce_wq *wq); 986 987 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list); 988 989 /*********************************************************** 990 * cleanup functions 991 ***********************************************************/ 992 void oce_stop_rx(POCE_SOFTC sc); 993 void oce_intr_free(POCE_SOFTC sc); 994 void oce_free_posted_rxbuf(struct oce_rq *rq); 995 #if defined(INET6) || defined(INET) 996 void oce_free_lro(POCE_SOFTC sc); 997 #endif 998 999 1000 /************************************************************ 1001 * Mailbox functions 1002 ************************************************************/ 1003 int oce_fw_clean(POCE_SOFTC sc); 1004 int oce_reset_fun(POCE_SOFTC sc); 1005 int oce_mbox_init(POCE_SOFTC sc); 1006 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec); 1007 int oce_get_fw_version(POCE_SOFTC sc); 1008 int oce_first_mcc_cmd(POCE_SOFTC sc); 1009 1010 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm, 1011 uint8_t type, struct mac_address_format *mac); 1012 int oce_get_fw_config(POCE_SOFTC sc); 1013 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags, 1014 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 1015 int oce_if_del(POCE_SOFTC sc, uint32_t if_id); 1016 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id, 1017 struct normal_vlan *vtag_arr, uint8_t vtag_cnt, 1018 uint32_t untagged, uint32_t enable_promisc); 1019 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control); 1020 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss); 1021 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable); 1022 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl); 1023 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link); 1024 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1025 int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1026 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1027 uint32_t reset_stats); 1028 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1029 uint32_t req_size, uint32_t reset_stats); 1030 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem); 1031 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size); 1032 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id); 1033 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1034 uint32_t if_id, uint32_t *pmac_id); 1035 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1036 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1037 uint64_t pattern); 1038 1039 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1040 uint8_t loopback_type, uint8_t enable); 1041 1042 int oce_mbox_check_native_mode(POCE_SOFTC sc); 1043 int oce_mbox_post(POCE_SOFTC sc, 1044 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx); 1045 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1046 POCE_DMA_MEM pdma_mem, uint32_t num_bytes); 1047 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1048 uint32_t data_offset,POCE_DMA_MEM pdma_mem, 1049 uint32_t *written_data, uint32_t *additional_status); 1050 1051 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1052 uint32_t offset, uint32_t optype); 1053 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info); 1054 int oce_mbox_create_rq(struct oce_rq *rq); 1055 int oce_mbox_create_wq(struct oce_wq *wq); 1056 int oce_mbox_create_eq(struct oce_eq *eq); 1057 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 1058 uint32_t is_eventable); 1059 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num); 1060 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1061 int num); 1062 int oce_get_profile_config(POCE_SOFTC sc); 1063 int oce_get_func_config(POCE_SOFTC sc); 1064 void mbx_common_req_hdr_init(struct mbx_hdr *hdr, 1065 uint8_t dom, 1066 uint8_t port, 1067 uint8_t subsys, 1068 uint8_t opcode, 1069 uint32_t timeout, uint32_t pyld_len, 1070 uint8_t version); 1071 1072 1073 uint16_t oce_mq_handler(void *arg); 1074 1075 /************************************************************ 1076 * Transmit functions 1077 ************************************************************/ 1078 uint16_t oce_wq_handler(void *arg); 1079 void oce_start_locked(struct ifnet *ifp); 1080 void oce_start(struct ifnet *ifp, struct ifaltq_subque *ifsq); 1081 void oce_tx_task(void *arg, int npending); 1082 1083 /************************************************************ 1084 * Receive functions 1085 ************************************************************/ 1086 int oce_alloc_rx_bufs(struct oce_rq *rq, int count); 1087 uint16_t oce_rq_handler(void *arg); 1088 1089 1090 /* Sysctl functions */ 1091 void oce_add_sysctls(POCE_SOFTC sc); 1092 void oce_refresh_queue_stats(POCE_SOFTC sc); 1093 int oce_refresh_nic_stats(POCE_SOFTC sc); 1094 int oce_stats_init(POCE_SOFTC sc); 1095 void oce_stats_free(POCE_SOFTC sc); 1096 1097 /* Capabilities */ 1098 #define OCE_MODCAP_RSS 1 1099 #define OCE_MAX_RSP_HANDLED 64 1100 extern uint32_t oce_max_rsp_handled; /* max responses */ 1101 1102 #define OCE_MAC_LOOPBACK 0x0 1103 #define OCE_PHY_LOOPBACK 0x1 1104 #define OCE_ONE_PORT_EXT_LOOPBACK 0x2 1105 #define OCE_NO_LOOPBACK 0xff 1106 1107 #define atomic_inc_32(x) atomic_add_32(x, 1) 1108 #define atomic_dec_32(x) atomic_subtract_32(x, 1) 1109 1110 #define LE_64(x) htole64(x) 1111 #define LE_32(x) htole32(x) 1112 #define LE_16(x) htole16(x) 1113 #define HOST_64(x) le64toh(x) 1114 #define HOST_32(x) le32toh(x) 1115 #define HOST_16(x) le16toh(x) 1116 #define DW_SWAP(x, l) 1117 #define IS_ALIGNED(x,a) ((x % a) == 0) 1118 #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 1119 #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 1120 1121 #define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 1122 #define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 1123 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) 1124 1125 #define OCE_LOG2(x) (oce_highbit(x)) 1126 static inline uint32_t oce_highbit(uint32_t x) 1127 { 1128 int i; 1129 int c; 1130 int b; 1131 1132 c = 0; 1133 b = 0; 1134 1135 for (i = 0; i < 32; i++) { 1136 if ((1 << i) & x) { 1137 c++; 1138 b = i; 1139 } 1140 } 1141 1142 if (c == 1) 1143 return b; 1144 1145 return 0; 1146 } 1147 1148 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc) 1149 { 1150 if (IS_BE(sc)) 1151 return MPU_EP_SEMAPHORE_BE3; 1152 else if (IS_SH(sc)) 1153 return MPU_EP_SEMAPHORE_SH; 1154 else 1155 return MPU_EP_SEMAPHORE_XE201; 1156 } 1157 1158 #define TRANSCEIVER_DATA_NUM_ELE 64 1159 #define TRANSCEIVER_DATA_SIZE 256 1160 #define TRANSCEIVER_A0_SIZE 128 1161 #define TRANSCEIVER_A2_SIZE 128 1162 #define PAGE_NUM_A0 0xa0 1163 #define PAGE_NUM_A2 0xa2 1164 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\ 1165 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
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