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sys/dev/netif/re/if_re.c
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1 /* 2 * Copyright (c) 2004 3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 4 * 5 * Copyright (c) 1997, 1998-2003 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ 36 */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7440, so the max MTU possible with this 110 * driver is 7422 bytes. 111 */ 112 113 #define _IP_VHL 114 115 #include "opt_ifpoll.h" 116 117 #include <sys/param.h> 118 #include <sys/bus.h> 119 #include <sys/endian.h> 120 #include <sys/kernel.h> 121 #include <sys/in_cksum.h> 122 #include <sys/interrupt.h> 123 #include <sys/malloc.h> 124 #include <sys/mbuf.h> 125 #include <sys/rman.h> 126 #include <sys/serialize.h> 127 #include <sys/socket.h> 128 #include <sys/sockio.h> 129 #include <sys/sysctl.h> 130 131 #include <net/bpf.h> 132 #include <net/ethernet.h> 133 #include <net/if.h> 134 #include <net/ifq_var.h> 135 #include <net/if_arp.h> 136 #include <net/if_dl.h> 137 #include <net/if_media.h> 138 #include <net/if_poll.h> 139 #include <net/if_types.h> 140 #include <net/vlan/if_vlan_var.h> 141 #include <net/vlan/if_vlan_ether.h> 142 143 #include <netinet/ip.h> 144 145 #include <dev/netif/mii_layer/mii.h> 146 #include <dev/netif/mii_layer/miivar.h> 147 148 #include "pcidevs.h" 149 #include <bus/pci/pcireg.h> 150 #include <bus/pci/pcivar.h> 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 #include <dev/netif/re/if_rereg.h> 156 #include <dev/netif/re/if_revar.h> 157 158 /* 159 * Various supported device vendors/types and their names. 160 */ 161 static const struct re_type { 162 uint16_t re_vid; 163 uint16_t re_did; 164 const char *re_name; 165 } re_devs[] = { 166 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 168 169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 170 "RealTek 8139C+ 10/100BaseTX" }, 171 172 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 173 "RealTek 810x PCIe 10/100baseTX" }, 174 175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 176 "RealTek 8111/8168 PCIe Gigabit Ethernet" }, 177 178 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 179 "RealTek 8110/8169 Gigabit Ethernet" }, 180 181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 184 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, 185 "Corega CG-LAPCIGT Gigabit Ethernet" }, 186 187 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 188 "Linksys EG1032 Gigabit Ethernet" }, 189 190 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, 191 "US Robotics 997902 Gigabit Ethernet" }, 192 193 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322, 194 "TTTech MC322 Gigabit Ethernet" }, 195 196 { 0, 0, NULL } 197 }; 198 199 static const struct re_hwrev re_hwrevs[] = { 200 { RE_HWREV_8139CPLUS, ETHERMTU, 201 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE }, 202 203 { RE_HWREV_8169, ETHERMTU, 204 RE_C_HWCSUM | RE_C_8169 }, 205 206 { RE_HWREV_8110S, RE_MTU_6K, 207 RE_C_HWCSUM | RE_C_8169 }, 208 209 { RE_HWREV_8169S, RE_MTU_6K, 210 RE_C_HWCSUM | RE_C_8169 }, 211 212 { RE_HWREV_8169SB, RE_MTU_6K, 213 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 214 215 { RE_HWREV_8169SC, RE_MTU_6K, 216 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, 217 218 { RE_HWREV_8168B1, RE_MTU_6K, 219 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, 220 221 { RE_HWREV_8168B2, RE_MTU_6K, 222 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, 223 224 { RE_HWREV_8168C, RE_MTU_6K, 225 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 226 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 227 228 { RE_HWREV_8168CP, RE_MTU_6K, 229 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 230 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 231 232 { RE_HWREV_8168D, RE_MTU_9K, 233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 235 236 { RE_HWREV_8168DP, RE_MTU_9K, 237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 239 240 { RE_HWREV_8168E, RE_MTU_9K, 241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 243 244 { RE_HWREV_8168F, RE_MTU_9K, 245 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 246 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 247 248 { RE_HWREV_8111F, RE_MTU_9K, 249 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 250 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 251 252 { RE_HWREV_8411, ETHERMTU, 253 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 254 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 255 256 { RE_HWREV_8168G, ETHERMTU, 257 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 258 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 259 260 { RE_HWREV_8168EP, ETHERMTU, 261 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 262 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 263 264 { RE_HWREV_8168GU, ETHERMTU, 265 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 266 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 267 268 { RE_HWREV_8411B, ETHERMTU, 269 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | 270 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, 271 272 { RE_HWREV_8100E, ETHERMTU, 273 RE_C_HWCSUM | RE_C_FASTE }, 274 275 { RE_HWREV_8101E, ETHERMTU, 276 RE_C_HWCSUM | RE_C_FASTE }, 277 278 { RE_HWREV_8102E, ETHERMTU, 279 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 280 RE_C_FASTE }, 281 282 { RE_HWREV_8102EL, ETHERMTU, 283 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX | 284 RE_C_FASTE }, 285 286 { RE_HWREV_8105E, ETHERMTU, 287 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 288 RE_C_STOP_RXTX | RE_C_FASTE }, 289 290 { RE_HWREV_8401E, ETHERMTU, 291 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 292 RE_C_STOP_RXTX | RE_C_FASTE }, 293 294 { RE_HWREV_8402, ETHERMTU, 295 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 296 RE_C_STOP_RXTX | RE_C_FASTE }, 297 298 { RE_HWREV_8106E, ETHERMTU, 299 RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD | 300 RE_C_STOP_RXTX | RE_C_FASTE }, 301 302 { RE_HWREV_NULL, 0, 0 } 303 }; 304 305 static int re_probe(device_t); 306 static int re_attach(device_t); 307 static int re_detach(device_t); 308 static int re_suspend(device_t); 309 static int re_resume(device_t); 310 static void re_shutdown(device_t); 311 312 static int re_allocmem(device_t); 313 static void re_freemem(device_t); 314 static void re_freebufmem(struct re_softc *, int, int); 315 static int re_encap(struct re_softc *, struct mbuf **, int *); 316 static int re_newbuf_std(struct re_softc *, int, int); 317 static int re_newbuf_jumbo(struct re_softc *, int, int); 318 static void re_setup_rxdesc(struct re_softc *, int); 319 static int re_rx_list_init(struct re_softc *); 320 static int re_tx_list_init(struct re_softc *); 321 static int re_rxeof(struct re_softc *); 322 static int re_txeof(struct re_softc *); 323 static int re_tx_collect(struct re_softc *); 324 static void re_intr(void *); 325 static void re_tick(void *); 326 static void re_tick_serialized(void *); 327 328 static void re_start(struct ifnet *, struct ifaltq_subque *); 329 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 330 static void re_init(void *); 331 static void re_stop(struct re_softc *); 332 static void re_watchdog(struct ifnet *); 333 static int re_ifmedia_upd(struct ifnet *); 334 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 335 336 static void re_eeprom_putbyte(struct re_softc *, int); 337 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); 338 static void re_read_eeprom(struct re_softc *, caddr_t, int, int); 339 static void re_get_eewidth(struct re_softc *); 340 341 static int re_gmii_readreg(device_t, int, int); 342 static int re_gmii_writereg(device_t, int, int, int); 343 344 static int re_miibus_readreg(device_t, int, int); 345 static int re_miibus_writereg(device_t, int, int, int); 346 static void re_miibus_statchg(device_t); 347 348 static void re_setmulti(struct re_softc *); 349 static void re_reset(struct re_softc *, int); 350 static void re_get_eaddr(struct re_softc *, uint8_t *); 351 352 static void re_setup_hw_im(struct re_softc *); 353 static void re_setup_sim_im(struct re_softc *); 354 static void re_disable_hw_im(struct re_softc *); 355 static void re_disable_sim_im(struct re_softc *); 356 static void re_config_imtype(struct re_softc *, int); 357 static void re_setup_intr(struct re_softc *, int, int); 358 359 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); 360 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); 361 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); 362 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); 363 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); 364 365 static int re_jpool_alloc(struct re_softc *); 366 static void re_jpool_free(struct re_softc *); 367 static struct re_jbuf *re_jbuf_alloc(struct re_softc *); 368 static void re_jbuf_free(void *); 369 static void re_jbuf_ref(void *); 370 371 #ifdef RE_DIAG 372 static int re_diag(struct re_softc *); 373 #endif 374 375 #ifdef IFPOLL_ENABLE 376 static void re_npoll(struct ifnet *, struct ifpoll_info *); 377 static void re_npoll_compat(struct ifnet *, void *, int); 378 #endif 379 380 static device_method_t re_methods[] = { 381 /* Device interface */ 382 DEVMETHOD(device_probe, re_probe), 383 DEVMETHOD(device_attach, re_attach), 384 DEVMETHOD(device_detach, re_detach), 385 DEVMETHOD(device_suspend, re_suspend), 386 DEVMETHOD(device_resume, re_resume), 387 DEVMETHOD(device_shutdown, re_shutdown), 388 389 /* bus interface */ 390 DEVMETHOD(bus_print_child, bus_generic_print_child), 391 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 392 393 /* MII interface */ 394 DEVMETHOD(miibus_readreg, re_miibus_readreg), 395 DEVMETHOD(miibus_writereg, re_miibus_writereg), 396 DEVMETHOD(miibus_statchg, re_miibus_statchg), 397 398 DEVMETHOD_END 399 }; 400 401 static driver_t re_driver = { 402 "re", 403 re_methods, 404 sizeof(struct re_softc) 405 }; 406 407 static devclass_t re_devclass; 408 409 DECLARE_DUMMY_MODULE(if_re); 410 MODULE_DEPEND(if_re, miibus, 1, 1, 1); 411 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL); 412 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL); 413 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL); 414 415 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; 416 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; 417 static int re_msi_enable = 0; 418 419 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); 420 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); 421 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable); 422 423 #define EE_SET(x) \ 424 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) 425 426 #define EE_CLR(x) \ 427 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) 428 429 static __inline void 430 re_free_rxchain(struct re_softc *sc) 431 { 432 if (sc->re_head != NULL) { 433 m_freem(sc->re_head); 434 sc->re_head = sc->re_tail = NULL; 435 } 436 } 437 438 /* 439 * Send a read command and address to the EEPROM, check for ACK. 440 */ 441 static void 442 re_eeprom_putbyte(struct re_softc *sc, int addr) 443 { 444 int d, i; 445 446 d = addr | (RE_9346_READ << sc->re_eewidth); 447 448 /* 449 * Feed in each bit and strobe the clock. 450 */ 451 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { 452 if (d & i) 453 EE_SET(RE_EE_DATAIN); 454 else 455 EE_CLR(RE_EE_DATAIN); 456 DELAY(100); 457 EE_SET(RE_EE_CLK); 458 DELAY(150); 459 EE_CLR(RE_EE_CLK); 460 DELAY(100); 461 } 462 } 463 464 /* 465 * Read a word of data stored in the EEPROM at address 'addr.' 466 */ 467 static void 468 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) 469 { 470 int i; 471 uint16_t word = 0; 472 473 /* 474 * Send address of word we want to read. 475 */ 476 re_eeprom_putbyte(sc, addr); 477 478 /* 479 * Start reading bits from EEPROM. 480 */ 481 for (i = 0x8000; i != 0; i >>= 1) { 482 EE_SET(RE_EE_CLK); 483 DELAY(100); 484 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) 485 word |= i; 486 EE_CLR(RE_EE_CLK); 487 DELAY(100); 488 } 489 490 *dest = word; 491 } 492 493 /* 494 * Read a sequence of words from the EEPROM. 495 */ 496 static void 497 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) 498 { 499 int i; 500 uint16_t word = 0, *ptr; 501 502 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 503 DELAY(100); 504 505 for (i = 0; i < cnt; i++) { 506 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); 507 re_eeprom_getword(sc, off + i, &word); 508 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); 509 ptr = (uint16_t *)(dest + (i * 2)); 510 *ptr = word; 511 } 512 513 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); 514 } 515 516 static void 517 re_get_eewidth(struct re_softc *sc) 518 { 519 uint16_t re_did = 0; 520 521 sc->re_eewidth = 6; 522 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 523 if (re_did != 0x8129) 524 sc->re_eewidth = 8; 525 } 526 527 static int 528 re_gmii_readreg(device_t dev, int phy, int reg) 529 { 530 struct re_softc *sc = device_get_softc(dev); 531 u_int32_t rval; 532 int i; 533 534 if (phy != 1) 535 return(0); 536 537 /* Let the rgephy driver read the GMEDIASTAT register */ 538 539 if (reg == RE_GMEDIASTAT) 540 return(CSR_READ_1(sc, RE_GMEDIASTAT)); 541 542 CSR_WRITE_4(sc, RE_PHYAR, reg << 16); 543 DELAY(1000); 544 545 for (i = 0; i < RE_TIMEOUT; i++) { 546 rval = CSR_READ_4(sc, RE_PHYAR); 547 if (rval & RE_PHYAR_BUSY) 548 break; 549 DELAY(100); 550 } 551 552 if (i == RE_TIMEOUT) { 553 device_printf(dev, "PHY read failed\n"); 554 return(0); 555 } 556 557 return(rval & RE_PHYAR_PHYDATA); 558 } 559 560 static int 561 re_gmii_writereg(device_t dev, int phy, int reg, int data) 562 { 563 struct re_softc *sc = device_get_softc(dev); 564 uint32_t rval; 565 int i; 566 567 CSR_WRITE_4(sc, RE_PHYAR, 568 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); 569 DELAY(1000); 570 571 for (i = 0; i < RE_TIMEOUT; i++) { 572 rval = CSR_READ_4(sc, RE_PHYAR); 573 if ((rval & RE_PHYAR_BUSY) == 0) 574 break; 575 DELAY(100); 576 } 577 578 if (i == RE_TIMEOUT) 579 device_printf(dev, "PHY write failed\n"); 580 581 return(0); 582 } 583 584 static int 585 re_miibus_readreg(device_t dev, int phy, int reg) 586 { 587 struct re_softc *sc = device_get_softc(dev); 588 uint16_t rval = 0; 589 uint16_t re8139_reg = 0; 590 591 if (!RE_IS_8139CP(sc)) { 592 rval = re_gmii_readreg(dev, phy, reg); 593 return(rval); 594 } 595 596 /* Pretend the internal PHY is only at address 0 */ 597 if (phy) 598 return(0); 599 600 switch(reg) { 601 case MII_BMCR: 602 re8139_reg = RE_BMCR; 603 break; 604 case MII_BMSR: 605 re8139_reg = RE_BMSR; 606 break; 607 case MII_ANAR: 608 re8139_reg = RE_ANAR; 609 break; 610 case MII_ANER: 611 re8139_reg = RE_ANER; 612 break; 613 case MII_ANLPAR: 614 re8139_reg = RE_LPAR; 615 break; 616 case MII_PHYIDR1: 617 case MII_PHYIDR2: 618 return(0); 619 /* 620 * Allow the rlphy driver to read the media status 621 * register. If we have a link partner which does not 622 * support NWAY, this is the register which will tell 623 * us the results of parallel detection. 624 */ 625 case RE_MEDIASTAT: 626 return(CSR_READ_1(sc, RE_MEDIASTAT)); 627 default: 628 device_printf(dev, "bad phy register\n"); 629 return(0); 630 } 631 rval = CSR_READ_2(sc, re8139_reg); 632 if (re8139_reg == RE_BMCR) { 633 /* 8139C+ has different bit layout. */ 634 rval &= ~(BMCR_LOOP | BMCR_ISO); 635 } 636 return(rval); 637 } 638 639 static int 640 re_miibus_writereg(device_t dev, int phy, int reg, int data) 641 { 642 struct re_softc *sc= device_get_softc(dev); 643 u_int16_t re8139_reg = 0; 644 645 if (!RE_IS_8139CP(sc)) 646 return(re_gmii_writereg(dev, phy, reg, data)); 647 648 /* Pretend the internal PHY is only at address 0 */ 649 if (phy) 650 return(0); 651 652 switch(reg) { 653 case MII_BMCR: 654 re8139_reg = RE_BMCR; 655 /* 8139C+ has different bit layout. */ 656 data &= ~(BMCR_LOOP | BMCR_ISO); 657 break; 658 case MII_BMSR: 659 re8139_reg = RE_BMSR; 660 break; 661 case MII_ANAR: 662 re8139_reg = RE_ANAR; 663 break; 664 case MII_ANER: 665 re8139_reg = RE_ANER; 666 break; 667 case MII_ANLPAR: 668 re8139_reg = RE_LPAR; 669 break; 670 case MII_PHYIDR1: 671 case MII_PHYIDR2: 672 return(0); 673 default: 674 device_printf(dev, "bad phy register\n"); 675 return(0); 676 } 677 CSR_WRITE_2(sc, re8139_reg, data); 678 return(0); 679 } 680 681 static void 682 re_miibus_statchg(device_t dev) 683 { 684 } 685 686 /* 687 * Program the 64-bit multicast hash filter. 688 */ 689 static void 690 re_setmulti(struct re_softc *sc) 691 { 692 struct ifnet *ifp = &sc->arpcom.ac_if; 693 int h = 0; 694 uint32_t hashes[2] = { 0, 0 }; 695 struct ifmultiaddr *ifma; 696 uint32_t rxfilt; 697 int mcnt = 0; 698 699 rxfilt = CSR_READ_4(sc, RE_RXCFG); 700 701 /* Set the individual bit to receive frames for this host only. */ 702 rxfilt |= RE_RXCFG_RX_INDIV; 703 /* Set capture broadcast bit to capture broadcast frames. */ 704 rxfilt |= RE_RXCFG_RX_BROAD; 705 706 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI); 707 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) { 708 rxfilt |= RE_RXCFG_RX_MULTI; 709 710 /* If we want promiscuous mode, set the allframes bit. */ 711 if (ifp->if_flags & IFF_PROMISC) 712 rxfilt |= RE_RXCFG_RX_ALLPHYS; 713 714 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 715 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); 716 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); 717 return; 718 } 719 720 /* first, zot all the existing hash bits */ 721 CSR_WRITE_4(sc, RE_MAR0, 0); 722 CSR_WRITE_4(sc, RE_MAR4, 0); 723 724 /* now program new ones */ 725 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 726 if (ifma->ifma_addr->sa_family != AF_LINK) 727 continue; 728 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 729 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 730 if (h < 32) 731 hashes[0] |= (1 << h); 732 else 733 hashes[1] |= (1 << (h - 32)); 734 mcnt++; 735 } 736 737 if (mcnt) 738 rxfilt |= RE_RXCFG_RX_MULTI; 739 else 740 rxfilt &= ~RE_RXCFG_RX_MULTI; 741 742 CSR_WRITE_4(sc, RE_RXCFG, rxfilt); 743 744 /* 745 * For some unfathomable reason, RealTek decided to reverse 746 * the order of the multicast hash registers in the PCI Express 747 * parts. This means we have to write the hash pattern in reverse 748 * order for those devices. 749 */ 750 if (sc->re_caps & RE_C_PCIE) { 751 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1])); 752 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0])); 753 } else { 754 CSR_WRITE_4(sc, RE_MAR0, hashes[0]); 755 CSR_WRITE_4(sc, RE_MAR4, hashes[1]); 756 } 757 } 758 759 static void 760 re_reset(struct re_softc *sc, int running) 761 { 762 int i; 763 764 if ((sc->re_caps & RE_C_STOP_RXTX) && running) { 765 CSR_WRITE_1(sc, RE_COMMAND, 766 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); 767 DELAY(100); 768 } 769 770 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); 771 772 for (i = 0; i < RE_TIMEOUT; i++) { 773 DELAY(10); 774 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) 775 break; 776 } 777 if (i == RE_TIMEOUT) 778 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 779 } 780 781 #ifdef RE_DIAG 782 /* 783 * The following routine is designed to test for a defect on some 784 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 785 * lines connected to the bus, however for a 32-bit only card, they 786 * should be pulled high. The result of this defect is that the 787 * NIC will not work right if you plug it into a 64-bit slot: DMA 788 * operations will be done with 64-bit transfers, which will fail 789 * because the 64-bit data lines aren't connected. 790 * 791 * There's no way to work around this (short of talking a soldering 792 * iron to the board), however we can detect it. The method we use 793 * here is to put the NIC into digital loopback mode, set the receiver 794 * to promiscuous mode, and then try to send a frame. We then compare 795 * the frame data we sent to what was received. If the data matches, 796 * then the NIC is working correctly, otherwise we know the user has 797 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 798 * slot. In the latter case, there's no way the NIC can work correctly, 799 * so we print out a message on the console and abort the device attach. 800 */ 801 802 static int 803 re_diag(struct re_softc *sc) 804 { 805 struct ifnet *ifp = &sc->arpcom.ac_if; 806 struct mbuf *m0; 807 struct ether_header *eh; 808 struct re_desc *cur_rx; 809 uint16_t status; 810 int total_len, i, error = 0, phyaddr; 811 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 812 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 813 char ethstr[2][ETHER_ADDRSTRLEN + 1]; 814 815 /* Allocate a single mbuf */ 816 817 MGETHDR(m0, MB_DONTWAIT, MT_DATA); 818 if (m0 == NULL) 819 return(ENOBUFS); 820 821 /* 822 * Initialize the NIC in test mode. This sets the chip up 823 * so that it can send and receive frames, but performs the 824 * following special functions: 825 * - Puts receiver in promiscuous mode 826 * - Enables digital loopback mode 827 * - Leaves interrupts turned off 828 */ 829 830 ifp->if_flags |= IFF_PROMISC; 831 sc->re_flags |= RE_F_TESTMODE; 832 re_init(sc); 833 sc->re_flags |= RE_F_LINKED; 834 if (!RE_IS_8139CP(sc)) 835 phyaddr = 1; 836 else 837 phyaddr = 0; 838 839 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); 840 for (i = 0; i < RE_TIMEOUT; i++) { 841 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); 842 if (!(status & BMCR_RESET)) 843 break; 844 } 845 846 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); 847 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); 848 849 DELAY(100000); 850 851 /* Put some data in the mbuf */ 852 853 eh = mtod(m0, struct ether_header *); 854 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); 855 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); 856 eh->ether_type = htons(ETHERTYPE_IP); 857 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 858 859 /* 860 * Queue the packet, start transmission. 861 * Note: ifq_handoff() ultimately calls re_start() for us. 862 */ 863 864 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 865 error = ifq_handoff(ifp, m0, NULL); 866 if (error) { 867 m0 = NULL; 868 goto done; 869 } 870 m0 = NULL; 871 872 /* Wait for it to propagate through the chip */ 873 874 DELAY(100000); 875 for (i = 0; i < RE_TIMEOUT; i++) { 876 status = CSR_READ_2(sc, RE_ISR); 877 CSR_WRITE_2(sc, RE_ISR, status); 878 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == 879 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) 880 break; 881 DELAY(10); 882 } 883 884 if (i == RE_TIMEOUT) { 885 if_printf(ifp, "diagnostic failed to receive packet " 886 "in loopback mode\n"); 887 error = EIO; 888 goto done; 889 } 890 891 /* 892 * The packet should have been dumped into the first 893 * entry in the RX DMA ring. Grab it from there. 894 */ 895 896 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0], 897 BUS_DMASYNC_POSTREAD); 898 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 899 sc->re_ldata.re_rx_dmamap[0]); 900 901 m0 = sc->re_ldata.re_rx_mbuf[0]; 902 sc->re_ldata.re_rx_mbuf[0] = NULL; 903 eh = mtod(m0, struct ether_header *); 904 905 cur_rx = &sc->re_ldata.re_rx_list[0]; 906 total_len = RE_RXBYTES(cur_rx); 907 908 if (total_len != ETHER_MIN_LEN) { 909 if_printf(ifp, "diagnostic failed, received short packet\n"); 910 error = EIO; 911 goto done; 912 } 913 914 /* Test that the received packet data matches what we sent. */ 915 916 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || 917 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || 918 be16toh(eh->ether_type) != ETHERTYPE_IP) { 919 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 920 if_printf(ifp, "expected TX data: %s/%s/0x%x\n", 921 kether_ntoa(dst, ethstr[0]), kether_ntoa(src, ethstr[1]), ETHERTYPE_IP); 922 if_printf(ifp, "received RX data: %s/%s/0x%x\n", 923 kether_ntoa(eh->ether_dhost, ethstr[0]), 924 kether_ntoa(eh->ether_shost, ethstr[1]), 925 ntohs(eh->ether_type)); 926 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 927 "into a 64-bit PCI slot.\n"); 928 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 929 "for proper operation.\n"); 930 if_printf(ifp, "Read the re(4) man page for more details.\n"); 931 error = EIO; 932 } 933 934 done: 935 /* Turn interface off, release resources */ 936 937 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); 938 ifp->if_flags &= ~IFF_PROMISC; 939 re_stop(sc); 940 if (m0 != NULL) 941 m_freem(m0); 942 943 return (error); 944 } 945 #endif /* RE_DIAG */ 946 947 /* 948 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 949 * IDs against our list and return a device name if we find a match. 950 */ 951 static int 952 re_probe(device_t dev) 953 { 954 const struct re_type *t; 955 const struct re_hwrev *hw_rev; 956 struct re_softc *sc; 957 int rid; 958 uint32_t hwrev, macmode, txcfg; 959 uint16_t vendor, product; 960 961 vendor = pci_get_vendor(dev); 962 product = pci_get_device(dev); 963 964 /* 965 * Only attach to rev.3 of the Linksys EG1032 adapter. 966 * Rev.2 is supported by sk(4). 967 */ 968 if (vendor == PCI_VENDOR_LINKSYS && 969 product == PCI_PRODUCT_LINKSYS_EG1032 && 970 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) 971 return ENXIO; 972 973 if (vendor == PCI_VENDOR_REALTEK && 974 product == PCI_PRODUCT_REALTEK_RT8139 && 975 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) { 976 /* Poor 8139 */ 977 return ENXIO; 978 } 979 980 for (t = re_devs; t->re_name != NULL; t++) { 981 if (product == t->re_did && vendor == t->re_vid) 982 break; 983 } 984 985 /* 986 * Check if we found a RealTek device. 987 */ 988 if (t->re_name == NULL) 989 return ENXIO; 990 991 /* 992 * Temporarily map the I/O space so we can read the chip ID register. 993 */ 994 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); 995 rid = RE_PCI_LOIO; 996 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 997 RF_ACTIVE); 998 if (sc->re_res == NULL) { 999 device_printf(dev, "couldn't map ports/memory\n"); 1000 kfree(sc, M_TEMP); 1001 return ENXIO; 1002 } 1003 1004 sc->re_btag = rman_get_bustag(sc->re_res); 1005 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1006 1007 txcfg = CSR_READ_4(sc, RE_TXCFG); 1008 hwrev = txcfg & RE_TXCFG_HWREV; 1009 macmode = txcfg & RE_TXCFG_MACMODE; 1010 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); 1011 kfree(sc, M_TEMP); 1012 1013 /* 1014 * and continue matching for the specific chip... 1015 */ 1016 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { 1017 if (hw_rev->re_hwrev == hwrev) { 1018 sc = device_get_softc(dev); 1019 1020 sc->re_hwrev = hw_rev->re_hwrev; 1021 sc->re_caps = hw_rev->re_caps; 1022 sc->re_maxmtu = hw_rev->re_maxmtu; 1023 1024 /* 1025 * Apply chip property fixup 1026 */ 1027 switch (sc->re_hwrev) { 1028 case RE_HWREV_8168GU: 1029 if (vendor == PCI_VENDOR_REALTEK && 1030 product == PCI_PRODUCT_REALTEK_RT8101E) { 1031 /* 8106EUS */ 1032 sc->re_caps = RE_C_HWCSUM | RE_C_MAC2 | 1033 RE_C_PHYPMGT | RE_C_AUTOPAD | 1034 RE_C_STOP_RXTX | RE_C_FASTE; 1035 sc->re_maxmtu = ETHERMTU; 1036 device_printf(dev, "8106EUS fixup\n"); 1037 } else { 1038 /* 8168GU */ 1039 goto ee_eaddr1; 1040 } 1041 break; 1042 1043 case RE_HWREV_8168E: 1044 if (vendor == PCI_VENDOR_REALTEK && 1045 product == PCI_PRODUCT_REALTEK_RT8101E) { 1046 /* 8105E */ 1047 sc->re_caps = RE_C_HWCSUM | RE_C_MAC2 | 1048 RE_C_PHYPMGT | RE_C_AUTOPAD | 1049 RE_C_STOP_RXTX | RE_C_FASTE; 1050 sc->re_maxmtu = ETHERMTU; 1051 device_printf(dev, "8105E fixup\n"); 1052 goto ee_eaddr0; 1053 } 1054 /* 8168E */ 1055 break; 1056 1057 case RE_HWREV_8101E: 1058 case RE_HWREV_8102E: 1059 case RE_HWREV_8102EL: 1060 case RE_HWREV_8401E: 1061 case RE_HWREV_8105E: 1062 case RE_HWREV_8106E: 1063 ee_eaddr0: 1064 sc->re_caps |= RE_C_EE_EADDR; 1065 sc->re_ee_eaddr = RE_EE_EADDR0; 1066 break; 1067 1068 case RE_HWREV_8168F: 1069 case RE_HWREV_8111F: 1070 case RE_HWREV_8168G: 1071 if (macmode == 0 || 1072 macmode == 0x100000) { 1073 sc->re_caps |= RE_C_EE_EADDR; 1074 sc->re_ee_eaddr = RE_EE_EADDR1; 1075 } 1076 break; 1077 1078 case RE_HWREV_8411: 1079 case RE_HWREV_8168EP: 1080 case RE_HWREV_8411B: 1081 ee_eaddr1: 1082 sc->re_caps |= RE_C_EE_EADDR; 1083 sc->re_ee_eaddr = RE_EE_EADDR1; 1084 break; 1085 } 1086 if (pci_is_pcie(dev)) 1087 sc->re_caps |= RE_C_PCIE; 1088 1089 device_set_desc(dev, t->re_name); 1090 return 0; 1091 } 1092 } 1093 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", 1094 hwrev, macmode); 1095 1096 return ENXIO; 1097 } 1098 1099 static int 1100 re_allocmem(device_t dev) 1101 { 1102 struct re_softc *sc = device_get_softc(dev); 1103 bus_dmamem_t dmem; 1104 int error, i; 1105 1106 /* 1107 * Allocate list data 1108 */ 1109 sc->re_ldata.re_tx_mbuf = 1110 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), 1111 M_DEVBUF, M_ZERO | M_WAITOK); 1112 1113 sc->re_ldata.re_rx_mbuf = 1114 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), 1115 M_DEVBUF, M_ZERO | M_WAITOK); 1116 1117 sc->re_ldata.re_rx_paddr = 1118 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), 1119 M_DEVBUF, M_ZERO | M_WAITOK); 1120 1121 sc->re_ldata.re_tx_dmamap = 1122 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), 1123 M_DEVBUF, M_ZERO | M_WAITOK); 1124 1125 sc->re_ldata.re_rx_dmamap = 1126 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), 1127 M_DEVBUF, M_ZERO | M_WAITOK); 1128 1129 /* 1130 * Allocate the parent bus DMA tag appropriate for PCI. 1131 */ 1132 error = bus_dma_tag_create(NULL, /* parent */ 1133 1, 0, /* alignment, boundary */ 1134 BUS_SPACE_MAXADDR, /* lowaddr */ 1135 BUS_SPACE_MAXADDR, /* highaddr */ 1136 NULL, NULL, /* filter, filterarg */ 1137 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1138 0, /* nsegments */ 1139 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1140 0, /* flags */ 1141 &sc->re_parent_tag); 1142 if (error) { 1143 device_printf(dev, "could not allocate parent dma tag\n"); 1144 return error; 1145 } 1146 1147 /* Allocate TX descriptor list. */ 1148 error = bus_dmamem_coherent(sc->re_parent_tag, 1149 RE_RING_ALIGN, 0, 1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1151 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1152 &dmem); 1153 if (error) { 1154 device_printf(dev, "could not allocate TX ring\n"); 1155 return error; 1156 } 1157 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag; 1158 sc->re_ldata.re_tx_list_map = dmem.dmem_map; 1159 sc->re_ldata.re_tx_list = dmem.dmem_addr; 1160 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr; 1161 1162 /* Allocate RX descriptor list. */ 1163 error = bus_dmamem_coherent(sc->re_parent_tag, 1164 RE_RING_ALIGN, 0, 1165 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1166 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO, 1167 &dmem); 1168 if (error) { 1169 device_printf(dev, "could not allocate RX ring\n"); 1170 return error; 1171 } 1172 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag; 1173 sc->re_ldata.re_rx_list_map = dmem.dmem_map; 1174 sc->re_ldata.re_rx_list = dmem.dmem_addr; 1175 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr; 1176 1177 /* Allocate maps for TX mbufs. */ 1178 error = bus_dma_tag_create(sc->re_parent_tag, 1179 1, 0, 1180 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1181 NULL, NULL, 1182 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, 1183 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1184 &sc->re_ldata.re_tx_mtag); 1185 if (error) { 1186 device_printf(dev, "could not allocate TX buf dma tag\n"); 1187 return(error); 1188 } 1189 1190 /* Create DMA maps for TX buffers */ 1191 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 1192 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag, 1193 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1194 &sc->re_ldata.re_tx_dmamap[i]); 1195 if (error) { 1196 device_printf(dev, "can't create DMA map for TX buf\n"); 1197 re_freebufmem(sc, i, 0); 1198 return(error); 1199 } 1200 } 1201 1202 /* Allocate maps for RX mbufs. */ 1203 error = bus_dma_tag_create(sc->re_parent_tag, 1204 RE_RXBUF_ALIGN, 0, 1205 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1206 NULL, NULL, 1207 MCLBYTES, 1, MCLBYTES, 1208 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED, 1209 &sc->re_ldata.re_rx_mtag); 1210 if (error) { 1211 device_printf(dev, "could not allocate RX buf dma tag\n"); 1212 return(error); 1213 } 1214 1215 /* Create spare DMA map for RX */ 1216 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK, 1217 &sc->re_ldata.re_rx_spare); 1218 if (error) { 1219 device_printf(dev, "can't create spare DMA map for RX\n"); 1220 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1221 sc->re_ldata.re_rx_mtag = NULL; 1222 return error; 1223 } 1224 1225 /* Create DMA maps for RX buffers */ 1226 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1227 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, 1228 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]); 1229 if (error) { 1230 device_printf(dev, "can't create DMA map for RX buf\n"); 1231 re_freebufmem(sc, sc->re_tx_desc_cnt, i); 1232 return(error); 1233 } 1234 } 1235 1236 /* Create jumbo buffer pool for RX if required */ 1237 if (sc->re_caps & RE_C_CONTIGRX) { 1238 error = re_jpool_alloc(sc); 1239 if (error) { 1240 re_jpool_free(sc); 1241 /* Disable jumbo frame support */ 1242 sc->re_maxmtu = ETHERMTU; 1243 } 1244 } 1245 return(0); 1246 } 1247 1248 static void 1249 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) 1250 { 1251 int i; 1252 1253 /* Destroy all the RX and TX buffer maps */ 1254 if (sc->re_ldata.re_tx_mtag) { 1255 for (i = 0; i < tx_cnt; i++) { 1256 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag, 1257 sc->re_ldata.re_tx_dmamap[i]); 1258 } 1259 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag); 1260 sc->re_ldata.re_tx_mtag = NULL; 1261 } 1262 1263 if (sc->re_ldata.re_rx_mtag) { 1264 for (i = 0; i < rx_cnt; i++) { 1265 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1266 sc->re_ldata.re_rx_dmamap[i]); 1267 } 1268 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag, 1269 sc->re_ldata.re_rx_spare); 1270 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag); 1271 sc->re_ldata.re_rx_mtag = NULL; 1272 } 1273 } 1274 1275 static void 1276 re_freemem(device_t dev) 1277 { 1278 struct re_softc *sc = device_get_softc(dev); 1279 1280 /* Unload and free the RX DMA ring memory and map */ 1281 if (sc->re_ldata.re_rx_list_tag) { 1282 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, 1283 sc->re_ldata.re_rx_list_map); 1284 bus_dmamem_free(sc->re_ldata.re_rx_list_tag, 1285 sc->re_ldata.re_rx_list, 1286 sc->re_ldata.re_rx_list_map); 1287 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); 1288 } 1289 1290 /* Unload and free the TX DMA ring memory and map */ 1291 if (sc->re_ldata.re_tx_list_tag) { 1292 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, 1293 sc->re_ldata.re_tx_list_map); 1294 bus_dmamem_free(sc->re_ldata.re_tx_list_tag, 1295 sc->re_ldata.re_tx_list, 1296 sc->re_ldata.re_tx_list_map); 1297 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); 1298 } 1299 1300 /* Free RX/TX buf DMA stuffs */ 1301 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); 1302 1303 /* Unload and free the stats buffer and map */ 1304 if (sc->re_ldata.re_stag) { 1305 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap); 1306 bus_dmamem_free(sc->re_ldata.re_stag, 1307 sc->re_ldata.re_stats, 1308 sc->re_ldata.re_smap); 1309 bus_dma_tag_destroy(sc->re_ldata.re_stag); 1310 } 1311 1312 if (sc->re_caps & RE_C_CONTIGRX) 1313 re_jpool_free(sc); 1314 1315 if (sc->re_parent_tag) 1316 bus_dma_tag_destroy(sc->re_parent_tag); 1317 1318 if (sc->re_ldata.re_tx_mbuf != NULL) 1319 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); 1320 if (sc->re_ldata.re_rx_mbuf != NULL) 1321 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); 1322 if (sc->re_ldata.re_rx_paddr != NULL) 1323 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); 1324 if (sc->re_ldata.re_tx_dmamap != NULL) 1325 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); 1326 if (sc->re_ldata.re_rx_dmamap != NULL) 1327 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); 1328 } 1329 1330 /* 1331 * Attach the interface. Allocate softc structures, do ifmedia 1332 * setup and ethernet/BPF attach. 1333 */ 1334 static int 1335 re_attach(device_t dev) 1336 { 1337 struct re_softc *sc = device_get_softc(dev); 1338 struct ifnet *ifp; 1339 uint8_t eaddr[ETHER_ADDR_LEN]; 1340 int error = 0, qlen, msi_enable; 1341 u_int irq_flags; 1342 1343 callout_init(&sc->re_timer); 1344 sc->re_dev = dev; 1345 1346 if (RE_IS_8139CP(sc)) { 1347 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; 1348 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; 1349 } else { 1350 sc->re_rx_desc_cnt = re_rx_desc_count; 1351 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) 1352 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; 1353 1354 sc->re_tx_desc_cnt = re_tx_desc_count; 1355 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) 1356 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; 1357 } 1358 1359 qlen = RE_IFQ_MAXLEN; 1360 if (sc->re_tx_desc_cnt > qlen) 1361 qlen = sc->re_tx_desc_cnt; 1362 1363 sc->re_rxbuf_size = MCLBYTES; 1364 sc->re_newbuf = re_newbuf_std; 1365 1366 sc->re_tx_time = 5; /* 125us */ 1367 sc->re_rx_time = 2; /* 50us */ 1368 if (sc->re_caps & RE_C_PCIE) 1369 sc->re_sim_time = 75; /* 75us */ 1370 else 1371 sc->re_sim_time = 125; /* 125us */ 1372 if (!RE_IS_8139CP(sc)) { 1373 /* simulated interrupt moderation */ 1374 sc->re_imtype = RE_IMTYPE_SIM; 1375 } else { 1376 sc->re_imtype = RE_IMTYPE_NONE; 1377 } 1378 re_config_imtype(sc, sc->re_imtype); 1379 1380 sysctl_ctx_init(&sc->re_sysctl_ctx); 1381 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, 1382 SYSCTL_STATIC_CHILDREN(_hw), 1383 OID_AUTO, 1384 device_get_nameunit(dev), 1385 CTLFLAG_RD, 0, ""); 1386 if (sc->re_sysctl_tree == NULL) { 1387 device_printf(dev, "can't add sysctl node\n"); 1388 error = ENXIO; 1389 goto fail; 1390 } 1391 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1392 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1393 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, 1394 0, "RX desc count"); 1395 SYSCTL_ADD_INT(&sc->re_sysctl_ctx, 1396 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, 1397 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, 1398 0, "TX desc count"); 1399 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1400 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1401 OID_AUTO, "sim_time", 1402 CTLTYPE_INT | CTLFLAG_RW, 1403 sc, 0, re_sysctl_simtime, "I", 1404 "Simulated interrupt moderation time (usec)."); 1405 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1406 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1407 OID_AUTO, "imtype", 1408 CTLTYPE_INT | CTLFLAG_RW, 1409 sc, 0, re_sysctl_imtype, "I", 1410 "Interrupt moderation type -- " 1411 "0:disable, 1:simulated, " 1412 "2:hardware(if supported)"); 1413 if (sc->re_caps & RE_C_HWIM) { 1414 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1415 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1416 OID_AUTO, "hw_rxtime", 1417 CTLTYPE_INT | CTLFLAG_RW, 1418 sc, 0, re_sysctl_rxtime, "I", 1419 "Hardware interrupt moderation time " 1420 "(unit: 25usec)."); 1421 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, 1422 SYSCTL_CHILDREN(sc->re_sysctl_tree), 1423 OID_AUTO, "hw_txtime", 1424 CTLTYPE_INT | CTLFLAG_RW, 1425 sc, 0, re_sysctl_txtime, "I", 1426 "Hardware interrupt moderation time " 1427 "(unit: 25usec)."); 1428 } 1429 1430 #ifndef BURN_BRIDGES 1431 /* 1432 * Handle power management nonsense. 1433 */ 1434 1435 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1436 uint32_t membase, irq; 1437 1438 /* Save important PCI config data. */ 1439 membase = pci_read_config(dev, RE_PCI_LOMEM, 4); 1440 irq = pci_read_config(dev, PCIR_INTLINE, 4); 1441 1442 /* Reset the power state. */ 1443 device_printf(dev, "chip is in D%d power mode " 1444 "-- setting to D0\n", pci_get_powerstate(dev)); 1445 1446 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1447 1448 /* Restore PCI config data. */ 1449 pci_write_config(dev, RE_PCI_LOMEM, membase, 4); 1450 pci_write_config(dev, PCIR_INTLINE, irq, 4); 1451 } 1452 #endif 1453 /* 1454 * Map control/status registers. 1455 */ 1456 pci_enable_busmaster(dev); 1457 1458 if (pci_is_pcie(dev)) { 1459 sc->re_res_rid = PCIR_BAR(2); 1460 sc->re_res_type = SYS_RES_MEMORY; 1461 } else { 1462 sc->re_res_rid = PCIR_BAR(0); 1463 sc->re_res_type = SYS_RES_IOPORT; 1464 } 1465 sc->re_res = bus_alloc_resource_any(dev, sc->re_res_type, 1466 &sc->re_res_rid, RF_ACTIVE); 1467 if (sc->re_res == NULL) { 1468 device_printf(dev, "couldn't map IO\n"); 1469 error = ENXIO; 1470 goto fail; 1471 } 1472 1473 sc->re_btag = rman_get_bustag(sc->re_res); 1474 sc->re_bhandle = rman_get_bushandle(sc->re_res); 1475 1476 /* 1477 * Allocate interrupt 1478 */ 1479 if (pci_is_pcie(dev)) 1480 msi_enable = re_msi_enable; 1481 else 1482 msi_enable = 0; 1483 sc->re_irq_type = pci_alloc_1intr(dev, msi_enable, 1484 &sc->re_irq_rid, &irq_flags); 1485 1486 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->re_irq_rid, 1487 irq_flags); 1488 if (sc->re_irq == NULL) { 1489 device_printf(dev, "couldn't map interrupt\n"); 1490 error = ENXIO; 1491 goto fail; 1492 } 1493 1494 /* Reset the adapter. */ 1495 re_reset(sc, 0); 1496 1497 if (RE_IS_8139CP(sc)) { 1498 sc->re_bus_speed = 33; /* XXX */ 1499 } else if (sc->re_caps & RE_C_PCIE) { 1500 sc->re_bus_speed = 125; 1501 } else { 1502 uint8_t cfg2; 1503 1504 cfg2 = CSR_READ_1(sc, RE_CFG2); 1505 switch (cfg2 & RE_CFG2_PCICLK_MASK) { 1506 case RE_CFG2_PCICLK_33MHZ: 1507 sc->re_bus_speed = 33; 1508 break; 1509 case RE_CFG2_PCICLK_66MHZ: 1510 sc->re_bus_speed = 66; 1511 break; 1512 default: 1513 device_printf(dev, "unknown bus speed, assume 33MHz\n"); 1514 sc->re_bus_speed = 33; 1515 break; 1516 } 1517 if (cfg2 & RE_CFG2_PCI64) 1518 sc->re_caps |= RE_C_PCI64; 1519 } 1520 device_printf(dev, "Hardware rev. 0x%08x; PCI%s %dMHz\n", 1521 sc->re_hwrev, 1522 (sc->re_caps & RE_C_PCIE) ? 1523 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), 1524 sc->re_bus_speed); 1525 1526 /* 1527 * NOTE: 1528 * DO NOT try to adjust config1 and config5 which was spotted in 1529 * Realtek's Linux drivers. It will _permanently_ damage certain 1530 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... 1531 */ 1532 1533 re_get_eaddr(sc, eaddr); 1534 1535 if (!RE_IS_8139CP(sc)) { 1536 /* Set RX length mask */ 1537 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 1538 sc->re_txstart = RE_GTXSTART; 1539 } else { 1540 /* Set RX length mask */ 1541 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 1542 sc->re_txstart = RE_TXSTART; 1543 } 1544 1545 /* Allocate DMA stuffs */ 1546 error = re_allocmem(dev); 1547 if (error) 1548 goto fail; 1549 1550 /* 1551 * Apply some magic PCI settings from Realtek ... 1552 */ 1553 if (RE_IS_8169(sc)) { 1554 CSR_WRITE_1(sc, 0x82, 1); 1555 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); 1556 } 1557 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); 1558 1559 if (sc->re_caps & RE_C_MAC2) { 1560 /* 1561 * Following part is extracted from Realtek BSD driver v176. 1562 * However, this does _not_ make much/any sense: 1563 * 8168C's PCI Express device control is located at 0x78, 1564 * so the reading from 0x79 (higher part of 0x78) and setting 1565 * the 4~6bits intend to enlarge the "max read request size" 1566 * (we will do it). The content of the rest part of this 1567 * register is not meaningful to other PCI registers, so 1568 * writing the value to 0x54 could be completely wrong. 1569 * 0x80 is the lower part of PCI Express device status, non- 1570 * reserved bits are RW1C, writing 0 to them will not have 1571 * any effect at all. 1572 */ 1573 #ifdef foo 1574 uint8_t val; 1575 1576 val = pci_read_config(dev, 0x79, 1); 1577 val = (val & ~0x70) | 0x50; 1578 pci_write_config(dev, 0x54, val, 1); 1579 pci_write_config(dev, 0x80, 0, 1); 1580 #endif 1581 } 1582 1583 /* 1584 * Apply some PHY fixup from Realtek ... 1585 */ 1586 if (sc->re_hwrev == RE_HWREV_8110S) { 1587 CSR_WRITE_1(sc, 0x82, 1); 1588 re_miibus_writereg(dev, 1, 0xb, 0); 1589 } 1590 if (sc->re_caps & RE_C_PHYPMGT) { 1591 /* Power up PHY */ 1592 re_miibus_writereg(dev, 1, 0x1f, 0); 1593 re_miibus_writereg(dev, 1, 0xe, 0); 1594 } 1595 1596 /* Do MII setup */ 1597 if (mii_phy_probe(dev, &sc->re_miibus, 1598 re_ifmedia_upd, re_ifmedia_sts)) { 1599 device_printf(dev, "MII without any phy!\n"); 1600 error = ENXIO; 1601 goto fail; 1602 } 1603 1604 ifp = &sc->arpcom.ac_if; 1605 ifp->if_softc = sc; 1606 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1607 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1608 ifp->if_ioctl = re_ioctl; 1609 ifp->if_start = re_start; 1610 #ifdef IFPOLL_ENABLE 1611 ifp->if_npoll = re_npoll; 1612 #endif 1613 ifp->if_watchdog = re_watchdog; 1614 ifp->if_init = re_init; 1615 if (!RE_IS_8139CP(sc)) /* XXX */ 1616 ifp->if_baudrate = 1000000000; 1617 else 1618 ifp->if_baudrate = 100000000; 1619 ifq_set_maxlen(&ifp->if_snd, qlen); 1620 ifq_set_ready(&ifp->if_snd); 1621 1622 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1623 if (sc->re_caps & RE_C_HWCSUM) 1624 ifp->if_capabilities |= IFCAP_HWCSUM; 1625 1626 ifp->if_capenable = ifp->if_capabilities; 1627 if (ifp->if_capabilities & IFCAP_HWCSUM) { 1628 /* 1629 * RTL8168/8111C generates wrong IP checksummed frame if the 1630 * packet has IP options so disable TX IP checksum offloading. 1631 */ 1632 if (sc->re_hwrev == RE_HWREV_8168CP || 1633 sc->re_hwrev == RE_HWREV_8168C) 1634 sc->re_hwassist = CSUM_TCP | CSUM_UDP; 1635 else 1636 sc->re_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1637 } 1638 ifp->if_hwassist = sc->re_hwassist; 1639 1640 /* 1641 * Call MI attach routine. 1642 */ 1643 ether_ifattach(ifp, eaddr, NULL); 1644 1645 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq)); 1646 1647 #ifdef IFPOLL_ENABLE 1648 ifpoll_compat_setup(&sc->re_npoll, 1649 &sc->re_sysctl_ctx, sc->re_sysctl_tree, device_get_unit(dev), 1650 ifp->if_serializer); 1651 #endif 1652 1653 #ifdef RE_DIAG 1654 /* 1655 * Perform hardware diagnostic on the original RTL8169. 1656 * Some 32-bit cards were incorrectly wired and would 1657 * malfunction if plugged into a 64-bit slot. 1658 */ 1659 if (sc->re_hwrev == RE_HWREV_8169) { 1660 lwkt_serialize_enter(ifp->if_serializer); 1661 error = re_diag(sc); 1662 lwkt_serialize_exit(ifp->if_serializer); 1663 1664 if (error) { 1665 device_printf(dev, "hardware diagnostic failure\n"); 1666 ether_ifdetach(ifp); 1667 goto fail; 1668 } 1669 } 1670 #endif /* RE_DIAG */ 1671 1672 /* Hook interrupt last to avoid having to lock softc */ 1673 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, 1674 &sc->re_intrhand, ifp->if_serializer); 1675 1676 if (error) { 1677 device_printf(dev, "couldn't set up irq\n"); 1678 ether_ifdetach(ifp); 1679 goto fail; 1680 } 1681 1682 fail: 1683 if (error) 1684 re_detach(dev); 1685 1686 return (error); 1687 } 1688 1689 /* 1690 * Shutdown hardware and free up resources. This can be called any 1691 * time after the mutex has been initialized. It is called in both 1692 * the error case in attach and the normal detach case so it needs 1693 * to be careful about only freeing resources that have actually been 1694 * allocated. 1695 */ 1696 static int 1697 re_detach(device_t dev) 1698 { 1699 struct re_softc *sc = device_get_softc(dev); 1700 struct ifnet *ifp = &sc->arpcom.ac_if; 1701 1702 /* These should only be active if attach succeeded */ 1703 if (device_is_attached(dev)) { 1704 lwkt_serialize_enter(ifp->if_serializer); 1705 re_stop(sc); 1706 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); 1707 lwkt_serialize_exit(ifp->if_serializer); 1708 1709 ether_ifdetach(ifp); 1710 } 1711 if (sc->re_miibus) 1712 device_delete_child(dev, sc->re_miibus); 1713 bus_generic_detach(dev); 1714 1715 if (sc->re_sysctl_tree != NULL) 1716 sysctl_ctx_free(&sc->re_sysctl_ctx); 1717 1718 if (sc->re_irq) 1719 bus_release_resource(dev, SYS_RES_IRQ, sc->re_irq_rid, 1720 sc->re_irq); 1721 1722 if (sc->re_irq_type == PCI_INTR_TYPE_MSI) 1723 pci_release_msi(dev); 1724 1725 if (sc->re_res) { 1726 bus_release_resource(dev, sc->re_res_type, sc->re_res_rid, 1727 sc->re_res); 1728 } 1729 1730 /* Free DMA stuffs */ 1731 re_freemem(dev); 1732 1733 return(0); 1734 } 1735 1736 static void 1737 re_setup_rxdesc(struct re_softc *sc, int idx) 1738 { 1739 bus_addr_t paddr; 1740 uint32_t cmdstat; 1741 struct re_desc *d; 1742 1743 paddr = sc->re_ldata.re_rx_paddr[idx]; 1744 d = &sc->re_ldata.re_rx_list[idx]; 1745 1746 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); 1747 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); 1748 1749 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; 1750 if (idx == (sc->re_rx_desc_cnt - 1)) 1751 cmdstat |= RE_RDESC_CMD_EOR; 1752 d->re_cmdstat = htole32(cmdstat); 1753 } 1754 1755 static int 1756 re_newbuf_std(struct re_softc *sc, int idx, int init) 1757 { 1758 bus_dma_segment_t seg; 1759 bus_dmamap_t map; 1760 struct mbuf *m; 1761 int error, nsegs; 1762 1763 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1764 if (m == NULL) { 1765 error = ENOBUFS; 1766 1767 if (init) { 1768 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); 1769 return error; 1770 } else { 1771 goto back; 1772 } 1773 } 1774 m->m_len = m->m_pkthdr.len = MCLBYTES; 1775 1776 /* 1777 * NOTE: 1778 * re(4) chips need address of the receive buffer to be 8-byte 1779 * aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1780 */ 1781 1782 error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag, 1783 sc->re_ldata.re_rx_spare, m, 1784 &seg, 1, &nsegs, BUS_DMA_NOWAIT); 1785 if (error) { 1786 m_freem(m); 1787 if (init) { 1788 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1789 return error; 1790 } else { 1791 goto back; 1792 } 1793 } 1794 1795 if (!init) { 1796 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, 1797 sc->re_ldata.re_rx_dmamap[idx], 1798 BUS_DMASYNC_POSTREAD); 1799 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 1800 sc->re_ldata.re_rx_dmamap[idx]); 1801 } 1802 sc->re_ldata.re_rx_mbuf[idx] = m; 1803 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; 1804 1805 map = sc->re_ldata.re_rx_dmamap[idx]; 1806 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; 1807 sc->re_ldata.re_rx_spare = map; 1808 back: 1809 re_setup_rxdesc(sc, idx); 1810 return error; 1811 } 1812 1813 static int 1814 re_newbuf_jumbo(struct re_softc *sc, int idx, int init) 1815 { 1816 struct mbuf *m; 1817 struct re_jbuf *jbuf; 1818 int error = 0; 1819 1820 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 1821 if (m == NULL) { 1822 error = ENOBUFS; 1823 if (init) { 1824 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 1825 return error; 1826 } else { 1827 goto back; 1828 } 1829 } 1830 1831 jbuf = re_jbuf_alloc(sc); 1832 if (jbuf == NULL) { 1833 m_freem(m); 1834 1835 error = ENOBUFS; 1836 if (init) { 1837 if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); 1838 return error; 1839 } else { 1840 goto back; 1841 } 1842 } 1843 1844 m->m_ext.ext_arg = jbuf; 1845 m->m_ext.ext_buf = jbuf->re_buf; 1846 m->m_ext.ext_free = re_jbuf_free; 1847 m->m_ext.ext_ref = re_jbuf_ref; 1848 m->m_ext.ext_size = sc->re_rxbuf_size; 1849 1850 m->m_data = m->m_ext.ext_buf; 1851 m->m_flags |= M_EXT; 1852 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1853 1854 /* 1855 * NOTE: 1856 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer 1857 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. 1858 */ 1859 1860 sc->re_ldata.re_rx_mbuf[idx] = m; 1861 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; 1862 back: 1863 re_setup_rxdesc(sc, idx); 1864 return error; 1865 } 1866 1867 static int 1868 re_tx_list_init(struct re_softc *sc) 1869 { 1870 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1871 1872 sc->re_ldata.re_tx_prodidx = 0; 1873 sc->re_ldata.re_tx_considx = 0; 1874 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; 1875 1876 return(0); 1877 } 1878 1879 static int 1880 re_rx_list_init(struct re_softc *sc) 1881 { 1882 int i, error; 1883 1884 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); 1885 1886 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 1887 error = sc->re_newbuf(sc, i, 1); 1888 if (error) 1889 return(error); 1890 } 1891 1892 sc->re_ldata.re_rx_prodidx = 0; 1893 sc->re_head = sc->re_tail = NULL; 1894 1895 return(0); 1896 } 1897 1898 #define RE_IP4_PACKET 0x1 1899 #define RE_TCP_PACKET 0x2 1900 #define RE_UDP_PACKET 0x4 1901 1902 static __inline uint8_t 1903 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) 1904 { 1905 uint8_t packet_type = 0; 1906 1907 if (sc->re_caps & RE_C_MAC2) { 1908 if (rxctrl & RE_RDESC_CTL_PROTOIP4) 1909 packet_type |= RE_IP4_PACKET; 1910 } else { 1911 if (rxstat & RE_RDESC_STAT_PROTOID) 1912 packet_type |= RE_IP4_PACKET; 1913 } 1914 if (RE_TCPPKT(rxstat)) 1915 packet_type |= RE_TCP_PACKET; 1916 else if (RE_UDPPKT(rxstat)) 1917 packet_type |= RE_UDP_PACKET; 1918 return packet_type; 1919 } 1920 1921 /* 1922 * RX handler for C+ and 8169. For the gigE chips, we support 1923 * the reception of jumbo frames that have been fragmented 1924 * across multiple 2K mbuf cluster buffers. 1925 */ 1926 static int 1927 re_rxeof(struct re_softc *sc) 1928 { 1929 struct ifnet *ifp = &sc->arpcom.ac_if; 1930 struct mbuf *m; 1931 struct re_desc *cur_rx; 1932 uint32_t rxstat, rxctrl; 1933 int i, total_len, rx = 0; 1934 1935 for (i = sc->re_ldata.re_rx_prodidx; 1936 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { 1937 cur_rx = &sc->re_ldata.re_rx_list[i]; 1938 m = sc->re_ldata.re_rx_mbuf[i]; 1939 total_len = RE_RXBYTES(cur_rx); 1940 rxstat = le32toh(cur_rx->re_cmdstat); 1941 rxctrl = le32toh(cur_rx->re_control); 1942 1943 rx = 1; 1944 1945 #ifdef INVARIANTS 1946 if (sc->re_flags & RE_F_USE_JPOOL) 1947 KKASSERT(rxstat & RE_RDESC_STAT_EOF); 1948 #endif 1949 1950 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1951 if (sc->re_flags & RE_F_DROP_RXFRAG) { 1952 re_setup_rxdesc(sc, i); 1953 continue; 1954 } 1955 1956 if (sc->re_newbuf(sc, i, 0)) { 1957 /* Drop upcoming fragments */ 1958 sc->re_flags |= RE_F_DROP_RXFRAG; 1959 continue; 1960 } 1961 1962 m->m_len = MCLBYTES; 1963 if (sc->re_head == NULL) { 1964 sc->re_head = sc->re_tail = m; 1965 } else { 1966 sc->re_tail->m_next = m; 1967 sc->re_tail = m; 1968 } 1969 continue; 1970 } else if (sc->re_flags & RE_F_DROP_RXFRAG) { 1971 /* 1972 * Last fragment of a multi-fragment packet. 1973 * 1974 * Since error already happened, this fragment 1975 * must be dropped as well as the fragment chain. 1976 */ 1977 re_setup_rxdesc(sc, i); 1978 re_free_rxchain(sc); 1979 sc->re_flags &= ~RE_F_DROP_RXFRAG; 1980 continue; 1981 } 1982 1983 /* 1984 * NOTE: for the 8139C+, the frame length field 1985 * is always 12 bits in size, but for the gigE chips, 1986 * it is 13 bits (since the max RX frame length is 16K). 1987 * Unfortunately, all 32 bits in the status word 1988 * were already used, so to make room for the extra 1989 * length bit, RealTek took out the 'frame alignment 1990 * error' bit and shifted the other status bits 1991 * over one slot. The OWN, EOR, FS and LS bits are 1992 * still in the same places. We have already extracted 1993 * the frame length and checked the OWN bit, so rather 1994 * than using an alternate bit mapping, we shift the 1995 * status bits one space to the right so we can evaluate 1996 * them using the 8169 status as though it was in the 1997 * same format as that of the 8139C+. 1998 */ 1999 if (!RE_IS_8139CP(sc)) 2000 rxstat >>= 1; 2001 2002 if (rxstat & RE_RDESC_STAT_RXERRSUM) { 2003 IFNET_STAT_INC(ifp, ierrors, 1); 2004 /* 2005 * If this is part of a multi-fragment packet, 2006 * discard all the pieces. 2007 */ 2008 re_free_rxchain(sc); 2009 re_setup_rxdesc(sc, i); 2010 continue; 2011 } 2012 2013 /* 2014 * If allocating a replacement mbuf fails, 2015 * reload the current one. 2016 */ 2017 2018 if (sc->re_newbuf(sc, i, 0)) { 2019 IFNET_STAT_INC(ifp, ierrors, 1); 2020 continue; 2021 } 2022 2023 if (sc->re_head != NULL) { 2024 m->m_len = total_len % MCLBYTES; 2025 /* 2026 * Special case: if there's 4 bytes or less 2027 * in this buffer, the mbuf can be discarded: 2028 * the last 4 bytes is the CRC, which we don't 2029 * care about anyway. 2030 */ 2031 if (m->m_len <= ETHER_CRC_LEN) { 2032 sc->re_tail->m_len -= 2033 (ETHER_CRC_LEN - m->m_len); 2034 m_freem(m); 2035 } else { 2036 m->m_len -= ETHER_CRC_LEN; 2037 sc->re_tail->m_next = m; 2038 } 2039 m = sc->re_head; 2040 sc->re_head = sc->re_tail = NULL; 2041 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2042 } else { 2043 m->m_pkthdr.len = m->m_len = 2044 (total_len - ETHER_CRC_LEN); 2045 } 2046 2047 IFNET_STAT_INC(ifp, ipackets, 1); 2048 m->m_pkthdr.rcvif = ifp; 2049 2050 /* Do RX checksumming if enabled */ 2051 2052 if (ifp->if_capenable & IFCAP_RXCSUM) { 2053 uint8_t packet_type; 2054 2055 packet_type = re_packet_type(sc, rxstat, rxctrl); 2056 2057 /* Check IP header checksum */ 2058 if (packet_type & RE_IP4_PACKET) { 2059 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2060 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) 2061 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2062 } 2063 2064 /* Check TCP/UDP checksum */ 2065 if (((packet_type & RE_TCP_PACKET) && 2066 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || 2067 ((packet_type & RE_UDP_PACKET) && 2068 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { 2069 m->m_pkthdr.csum_flags |= 2070 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 2071 CSUM_FRAG_NOT_CHECKED; 2072 m->m_pkthdr.csum_data = 0xffff; 2073 } 2074 } 2075 2076 if (rxctrl & RE_RDESC_CTL_HASTAG) { 2077 m->m_flags |= M_VLANTAG; 2078 m->m_pkthdr.ether_vlantag = 2079 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); 2080 } 2081 ifp->if_input(ifp, m); 2082 } 2083 2084 sc->re_ldata.re_rx_prodidx = i; 2085 2086 return rx; 2087 } 2088 2089 #undef RE_IP4_PACKET 2090 #undef RE_TCP_PACKET 2091 #undef RE_UDP_PACKET 2092 2093 static int 2094 re_tx_collect(struct re_softc *sc) 2095 { 2096 struct ifnet *ifp = &sc->arpcom.ac_if; 2097 uint32_t txstat; 2098 int idx, tx = 0; 2099 2100 for (idx = sc->re_ldata.re_tx_considx; 2101 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; 2102 RE_TXDESC_INC(sc, idx)) { 2103 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); 2104 if (txstat & RE_TDESC_CMD_OWN) 2105 break; 2106 2107 tx = 1; 2108 2109 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; 2110 2111 /* 2112 * We only stash mbufs in the last descriptor 2113 * in a fragment chain, which also happens to 2114 * be the only place where the TX status bits 2115 * are valid. 2116 */ 2117 if (txstat & RE_TDESC_CMD_EOF) { 2118 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2119 sc->re_ldata.re_tx_dmamap[idx]); 2120 m_freem(sc->re_ldata.re_tx_mbuf[idx]); 2121 sc->re_ldata.re_tx_mbuf[idx] = NULL; 2122 if (txstat & (RE_TDESC_STAT_EXCESSCOL| 2123 RE_TDESC_STAT_COLCNT)) 2124 IFNET_STAT_INC(ifp, collisions, 1); 2125 if (txstat & RE_TDESC_STAT_TXERRSUM) 2126 IFNET_STAT_INC(ifp, oerrors, 1); 2127 else 2128 IFNET_STAT_INC(ifp, opackets, 1); 2129 } 2130 sc->re_ldata.re_tx_free++; 2131 } 2132 sc->re_ldata.re_tx_considx = idx; 2133 2134 return tx; 2135 } 2136 2137 static int 2138 re_txeof(struct re_softc *sc) 2139 { 2140 struct ifnet *ifp = &sc->arpcom.ac_if; 2141 int tx; 2142 2143 tx = re_tx_collect(sc); 2144 2145 /* There is enough free TX descs */ 2146 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) 2147 ifq_clr_oactive(&ifp->if_snd); 2148 2149 /* 2150 * Some chips will ignore a second TX request issued while an 2151 * existing transmission is in progress. If the transmitter goes 2152 * idle but there are still packets waiting to be sent, we need 2153 * to restart the channel here to flush them out. This only seems 2154 * to be required with the PCIe devices. 2155 */ 2156 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) 2157 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2158 else 2159 ifp->if_timer = 0; 2160 2161 return tx; 2162 } 2163 2164 static void 2165 re_tick(void *xsc) 2166 { 2167 struct re_softc *sc = xsc; 2168 2169 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 2170 re_tick_serialized(xsc); 2171 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 2172 } 2173 2174 static void 2175 re_tick_serialized(void *xsc) 2176 { 2177 struct re_softc *sc = xsc; 2178 struct ifnet *ifp = &sc->arpcom.ac_if; 2179 struct mii_data *mii; 2180 2181 ASSERT_SERIALIZED(ifp->if_serializer); 2182 2183 mii = device_get_softc(sc->re_miibus); 2184 mii_tick(mii); 2185 if (sc->re_flags & RE_F_LINKED) { 2186 if (!(mii->mii_media_status & IFM_ACTIVE)) 2187 sc->re_flags &= ~RE_F_LINKED; 2188 } else { 2189 if (mii->mii_media_status & IFM_ACTIVE && 2190 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2191 sc->re_flags |= RE_F_LINKED; 2192 if (!ifq_is_empty(&ifp->if_snd)) 2193 if_devstart(ifp); 2194 } 2195 } 2196 2197 callout_reset(&sc->re_timer, hz, re_tick, sc); 2198 } 2199 2200 #ifdef IFPOLL_ENABLE 2201 2202 static void 2203 re_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 2204 { 2205 struct re_softc *sc = ifp->if_softc; 2206 2207 ASSERT_SERIALIZED(ifp->if_serializer); 2208 2209 if (sc->re_npoll.ifpc_stcount-- == 0) { 2210 uint16_t status; 2211 2212 sc->re_npoll.ifpc_stcount = sc->re_npoll.ifpc_stfrac; 2213 2214 status = CSR_READ_2(sc, RE_ISR); 2215 if (status == 0xffff) 2216 return; 2217 if (status) 2218 CSR_WRITE_2(sc, RE_ISR, status); 2219 2220 /* 2221 * XXX check behaviour on receiver stalls. 2222 */ 2223 2224 if (status & RE_ISR_SYSTEM_ERR) 2225 re_init(sc); 2226 } 2227 2228 sc->rxcycles = count; 2229 re_rxeof(sc); 2230 re_txeof(sc); 2231 2232 if (!ifq_is_empty(&ifp->if_snd)) 2233 if_devstart(ifp); 2234 } 2235 2236 static void 2237 re_npoll(struct ifnet *ifp, struct ifpoll_info *info) 2238 { 2239 struct re_softc *sc = ifp->if_softc; 2240 2241 ASSERT_SERIALIZED(ifp->if_serializer); 2242 2243 if (info != NULL) { 2244 int cpuid = sc->re_npoll.ifpc_cpuid; 2245 2246 info->ifpi_rx[cpuid].poll_func = re_npoll_compat; 2247 info->ifpi_rx[cpuid].arg = NULL; 2248 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 2249 2250 if (ifp->if_flags & IFF_RUNNING) 2251 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2252 ifq_set_cpuid(&ifp->if_snd, cpuid); 2253 } else { 2254 if (ifp->if_flags & IFF_RUNNING) 2255 re_setup_intr(sc, 1, sc->re_imtype); 2256 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->re_irq)); 2257 } 2258 } 2259 #endif /* IFPOLL_ENABLE */ 2260 2261 static void 2262 re_intr(void *arg) 2263 { 2264 struct re_softc *sc = arg; 2265 struct ifnet *ifp = &sc->arpcom.ac_if; 2266 uint16_t status; 2267 int rx, tx; 2268 2269 ASSERT_SERIALIZED(ifp->if_serializer); 2270 2271 if ((sc->re_flags & RE_F_SUSPENDED) || 2272 (ifp->if_flags & IFF_RUNNING) == 0) 2273 return; 2274 2275 rx = tx = 0; 2276 2277 status = CSR_READ_2(sc, RE_ISR); 2278 /* If the card has gone away the read returns 0xffff. */ 2279 if (status == 0xffff) 2280 goto reload; 2281 if (status) 2282 CSR_WRITE_2(sc, RE_ISR, status); 2283 2284 if ((status & sc->re_intrs) == 0) 2285 goto reload; 2286 2287 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) 2288 rx |= re_rxeof(sc); 2289 2290 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) 2291 tx |= re_txeof(sc); 2292 2293 if (status & RE_ISR_SYSTEM_ERR) 2294 re_init(sc); 2295 2296 if (status & RE_ISR_LINKCHG) { 2297 callout_stop(&sc->re_timer); 2298 re_tick_serialized(sc); 2299 } 2300 2301 reload: 2302 if (sc->re_imtype == RE_IMTYPE_SIM) { 2303 if ((sc->re_flags & RE_F_TIMER_INTR)) { 2304 if ((tx | rx) == 0) { 2305 /* 2306 * Nothing needs to be processed, fallback 2307 * to use TX/RX interrupts. 2308 */ 2309 re_setup_intr(sc, 1, RE_IMTYPE_NONE); 2310 2311 /* 2312 * Recollect, mainly to avoid the possible 2313 * race introduced by changing interrupt 2314 * masks. 2315 */ 2316 re_rxeof(sc); 2317 tx = re_txeof(sc); 2318 } else { 2319 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 2320 } 2321 } else if (tx | rx) { 2322 /* 2323 * Assume that using simulated interrupt moderation 2324 * (hardware timer based) could reduce the interript 2325 * rate. 2326 */ 2327 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 2328 } 2329 } 2330 2331 if (tx && !ifq_is_empty(&ifp->if_snd)) 2332 if_devstart(ifp); 2333 } 2334 2335 static int 2336 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) 2337 { 2338 struct mbuf *m = *m_head; 2339 bus_dma_segment_t segs[RE_MAXSEGS]; 2340 bus_dmamap_t map; 2341 int error, maxsegs, idx, i, nsegs; 2342 struct re_desc *d, *tx_ring; 2343 uint32_t cmd_csum, ctl_csum, vlantag; 2344 2345 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, 2346 ("not enough free TX desc")); 2347 2348 map = sc->re_ldata.re_tx_dmamap[*idx0]; 2349 2350 /* 2351 * Set up checksum offload. Note: checksum offload bits must 2352 * appear in all descriptors of a multi-descriptor transmit 2353 * attempt. (This is according to testing done with an 8169 2354 * chip. I'm not sure if this is a requirement or a bug.) 2355 */ 2356 cmd_csum = ctl_csum = 0; 2357 if (m->m_pkthdr.csum_flags & CSUM_IP) { 2358 cmd_csum |= RE_TDESC_CMD_IPCSUM; 2359 ctl_csum |= RE_TDESC_CTL_IPCSUM; 2360 } 2361 if (m->m_pkthdr.csum_flags & CSUM_TCP) { 2362 cmd_csum |= RE_TDESC_CMD_TCPCSUM; 2363 ctl_csum |= RE_TDESC_CTL_TCPCSUM; 2364 } 2365 if (m->m_pkthdr.csum_flags & CSUM_UDP) { 2366 cmd_csum |= RE_TDESC_CMD_UDPCSUM; 2367 ctl_csum |= RE_TDESC_CTL_UDPCSUM; 2368 } 2369 2370 /* For MAC2 chips, csum flags are set on re_control */ 2371 if (sc->re_caps & RE_C_MAC2) 2372 cmd_csum = 0; 2373 else 2374 ctl_csum = 0; 2375 2376 if ((sc->re_caps & RE_C_AUTOPAD) == 0) { 2377 /* 2378 * With some of the RealTek chips, using the checksum offload 2379 * support in conjunction with the autopadding feature results 2380 * in the transmission of corrupt frames. For example, if we 2381 * need to send a really small IP fragment that's less than 60 2382 * bytes in size, and IP header checksumming is enabled, the 2383 * resulting ethernet frame that appears on the wire will 2384 * have garbled payload. To work around this, if TX checksum 2385 * offload is enabled, we always manually pad short frames out 2386 * to the minimum ethernet frame size. 2387 * 2388 * Note: this appears unnecessary for TCP, and doing it for TCP 2389 * with PCIe adapters seems to result in bad checksums. 2390 */ 2391 if ((m->m_pkthdr.csum_flags & 2392 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && 2393 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2394 m->m_pkthdr.len < RE_MIN_FRAMELEN) { 2395 error = m_devpad(m, RE_MIN_FRAMELEN); 2396 if (error) 2397 goto back; 2398 } 2399 } 2400 2401 vlantag = 0; 2402 if (m->m_flags & M_VLANTAG) { 2403 vlantag = htobe16(m->m_pkthdr.ether_vlantag) | 2404 RE_TDESC_CTL_INSTAG; 2405 } 2406 2407 maxsegs = sc->re_ldata.re_tx_free; 2408 if (maxsegs > RE_MAXSEGS) 2409 maxsegs = RE_MAXSEGS; 2410 2411 error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map, 2412 m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 2413 if (error) 2414 goto back; 2415 2416 m = *m_head; 2417 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE); 2418 2419 /* 2420 * Map the segment array into descriptors. We also keep track 2421 * of the end of the ring and set the end-of-ring bits as needed, 2422 * and we set the ownership bits in all except the very first 2423 * descriptor, whose ownership bits will be turned on later. 2424 */ 2425 tx_ring = sc->re_ldata.re_tx_list; 2426 idx = *idx0; 2427 i = 0; 2428 for (;;) { 2429 uint32_t cmdstat; 2430 2431 d = &tx_ring[idx]; 2432 2433 cmdstat = segs[i].ds_len; 2434 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); 2435 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); 2436 if (i == 0) 2437 cmdstat |= RE_TDESC_CMD_SOF; 2438 else 2439 cmdstat |= RE_TDESC_CMD_OWN; 2440 if (idx == (sc->re_tx_desc_cnt - 1)) 2441 cmdstat |= RE_TDESC_CMD_EOR; 2442 d->re_cmdstat = htole32(cmdstat | cmd_csum); 2443 d->re_control = htole32(ctl_csum | vlantag); 2444 2445 i++; 2446 if (i == nsegs) 2447 break; 2448 RE_TXDESC_INC(sc, idx); 2449 } 2450 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); 2451 2452 /* Transfer ownership of packet to the chip. */ 2453 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2454 if (*idx0 != idx) 2455 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); 2456 2457 /* 2458 * Insure that the map for this transmission 2459 * is placed at the array index of the last descriptor 2460 * in this chain. 2461 */ 2462 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; 2463 sc->re_ldata.re_tx_dmamap[idx] = map; 2464 2465 sc->re_ldata.re_tx_mbuf[idx] = m; 2466 sc->re_ldata.re_tx_free -= nsegs; 2467 2468 RE_TXDESC_INC(sc, idx); 2469 *idx0 = idx; 2470 back: 2471 if (error) { 2472 m_freem(*m_head); 2473 *m_head = NULL; 2474 } 2475 return error; 2476 } 2477 2478 /* 2479 * Main transmit routine for C+ and gigE NICs. 2480 */ 2481 2482 static void 2483 re_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2484 { 2485 struct re_softc *sc = ifp->if_softc; 2486 struct mbuf *m_head; 2487 int idx, need_trans, oactive, error; 2488 2489 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2490 ASSERT_SERIALIZED(ifp->if_serializer); 2491 2492 if ((sc->re_flags & RE_F_LINKED) == 0) { 2493 ifq_purge(&ifp->if_snd); 2494 return; 2495 } 2496 2497 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 2498 return; 2499 2500 idx = sc->re_ldata.re_tx_prodidx; 2501 2502 need_trans = 0; 2503 oactive = 0; 2504 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { 2505 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2506 if (!oactive) { 2507 if (re_tx_collect(sc)) { 2508 oactive = 1; 2509 continue; 2510 } 2511 } 2512 ifq_set_oactive(&ifp->if_snd); 2513 break; 2514 } 2515 2516 m_head = ifq_dequeue(&ifp->if_snd); 2517 if (m_head == NULL) 2518 break; 2519 2520 error = re_encap(sc, &m_head, &idx); 2521 if (error) { 2522 /* m_head is freed by re_encap(), if we reach here */ 2523 IFNET_STAT_INC(ifp, oerrors, 1); 2524 2525 if (error == EFBIG && !oactive) { 2526 if (re_tx_collect(sc)) { 2527 oactive = 1; 2528 continue; 2529 } 2530 } 2531 ifq_set_oactive(&ifp->if_snd); 2532 break; 2533 } 2534 2535 oactive = 0; 2536 need_trans = 1; 2537 2538 /* 2539 * If there's a BPF listener, bounce a copy of this frame 2540 * to him. 2541 */ 2542 ETHER_BPF_MTAP(ifp, m_head); 2543 } 2544 2545 /* 2546 * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible 2547 * for OACTIVE to not be properly set when we also do not 2548 * have sufficient free tx descriptors, leaving packet in 2549 * ifp->if_snd. This can cause if_start_dispatch() to loop 2550 * infinitely so make sure OACTIVE is set properly. 2551 */ 2552 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { 2553 if (!ifq_is_oactive(&ifp->if_snd)) { 2554 if_printf(ifp, "Debug: OACTIVE was not set when " 2555 "re_tx_free was below minimum!\n"); 2556 ifq_set_oactive(&ifp->if_snd); 2557 } 2558 } 2559 if (!need_trans) 2560 return; 2561 2562 sc->re_ldata.re_tx_prodidx = idx; 2563 2564 /* 2565 * RealTek put the TX poll request register in a different 2566 * location on the 8169 gigE chip. I don't know why. 2567 */ 2568 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); 2569 2570 /* 2571 * Set a timeout in case the chip goes out to lunch. 2572 */ 2573 ifp->if_timer = 5; 2574 } 2575 2576 static void 2577 re_init(void *xsc) 2578 { 2579 struct re_softc *sc = xsc; 2580 struct ifnet *ifp = &sc->arpcom.ac_if; 2581 struct mii_data *mii; 2582 int error, framelen; 2583 2584 ASSERT_SERIALIZED(ifp->if_serializer); 2585 2586 mii = device_get_softc(sc->re_miibus); 2587 2588 /* 2589 * Cancel pending I/O and free all RX/TX buffers. 2590 */ 2591 re_stop(sc); 2592 2593 if (sc->re_caps & RE_C_CONTIGRX) { 2594 if (ifp->if_mtu > ETHERMTU) { 2595 KKASSERT(sc->re_ldata.re_jbuf != NULL); 2596 sc->re_flags |= RE_F_USE_JPOOL; 2597 sc->re_rxbuf_size = RE_FRAMELEN_MAX; 2598 sc->re_newbuf = re_newbuf_jumbo; 2599 } else { 2600 sc->re_flags &= ~RE_F_USE_JPOOL; 2601 sc->re_rxbuf_size = MCLBYTES; 2602 sc->re_newbuf = re_newbuf_std; 2603 } 2604 } 2605 2606 /* 2607 * Adjust max read request size according to MTU; mainly to 2608 * improve TX performance for common case (ETHERMTU) on GigE 2609 * NICs. However, this could _not_ be done on 10/100 only 2610 * NICs; their DMA engines will malfunction using non-default 2611 * max read request size. 2612 */ 2613 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) { 2614 if (ifp->if_mtu > ETHERMTU) { 2615 /* 2616 * 512 seems to be the only value that works 2617 * reliably with jumbo frame 2618 */ 2619 pcie_set_max_readrq(sc->re_dev, 2620 PCIEM_DEVCTL_MAX_READRQ_512); 2621 } else { 2622 pcie_set_max_readrq(sc->re_dev, 2623 PCIEM_DEVCTL_MAX_READRQ_4096); 2624 } 2625 } 2626 2627 /* 2628 * Enable C+ RX and TX mode, as well as VLAN stripping and 2629 * RX checksum offload. We must configure the C+ register 2630 * before all others. 2631 */ 2632 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | 2633 RE_CPLUSCMD_PCI_MRW | 2634 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 2635 RE_CPLUSCMD_VLANSTRIP : 0) | 2636 (ifp->if_capenable & IFCAP_RXCSUM ? 2637 RE_CPLUSCMD_RXCSUM_ENB : 0)); 2638 2639 /* 2640 * Init our MAC address. Even though the chipset 2641 * documentation doesn't mention it, we need to enter "Config 2642 * register write enable" mode to modify the ID registers. 2643 */ 2644 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); 2645 CSR_WRITE_4(sc, RE_IDR0, 2646 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); 2647 CSR_WRITE_2(sc, RE_IDR4, 2648 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); 2649 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); 2650 2651 /* 2652 * For C+ mode, initialize the RX descriptors and mbufs. 2653 */ 2654 error = re_rx_list_init(sc); 2655 if (error) { 2656 re_stop(sc); 2657 return; 2658 } 2659 error = re_tx_list_init(sc); 2660 if (error) { 2661 re_stop(sc); 2662 return; 2663 } 2664 2665 /* 2666 * Load the addresses of the RX and TX lists into the chip. 2667 */ 2668 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, 2669 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); 2670 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, 2671 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); 2672 2673 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, 2674 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); 2675 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, 2676 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); 2677 2678 /* 2679 * Enable transmit and receive. 2680 */ 2681 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2682 2683 /* 2684 * Set the initial TX and RX configuration. 2685 */ 2686 if (sc->re_flags & RE_F_TESTMODE) { 2687 if (!RE_IS_8139CP(sc)) 2688 CSR_WRITE_4(sc, RE_TXCFG, 2689 RE_TXCFG_CONFIG | RE_LOOPTEST_ON); 2690 else 2691 CSR_WRITE_4(sc, RE_TXCFG, 2692 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); 2693 } else 2694 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); 2695 2696 framelen = RE_FRAMELEN(ifp->if_mtu); 2697 if (framelen < MCLBYTES) 2698 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); 2699 else 2700 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); 2701 2702 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); 2703 2704 /* 2705 * Program the multicast filter, if necessary. 2706 */ 2707 re_setmulti(sc); 2708 2709 #ifdef IFPOLL_ENABLE 2710 /* 2711 * Disable interrupts if we are polling. 2712 */ 2713 if (ifp->if_flags & IFF_NPOLLING) 2714 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 2715 else /* otherwise ... */ 2716 #endif /* IFPOLL_ENABLE */ 2717 /* 2718 * Enable interrupts. 2719 */ 2720 if (sc->re_flags & RE_F_TESTMODE) 2721 CSR_WRITE_2(sc, RE_IMR, 0); 2722 else 2723 re_setup_intr(sc, 1, sc->re_imtype); 2724 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); 2725 2726 /* Start RX/TX process. */ 2727 CSR_WRITE_4(sc, RE_MISSEDPKT, 0); 2728 2729 #ifdef notdef 2730 /* Enable receiver and transmitter. */ 2731 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); 2732 #endif 2733 2734 /* 2735 * For 8169 gigE NICs, set the max allowed RX packet 2736 * size so we can receive jumbo frames. 2737 */ 2738 if (!RE_IS_8139CP(sc)) { 2739 if (sc->re_caps & RE_C_CONTIGRX) 2740 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); 2741 else 2742 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); 2743 } 2744 2745 if (sc->re_flags & RE_F_TESTMODE) 2746 return; 2747 2748 mii_mediachg(mii); 2749 2750 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); 2751 2752 ifp->if_flags |= IFF_RUNNING; 2753 ifq_clr_oactive(&ifp->if_snd); 2754 2755 callout_reset(&sc->re_timer, hz, re_tick, sc); 2756 } 2757 2758 /* 2759 * Set media options. 2760 */ 2761 static int 2762 re_ifmedia_upd(struct ifnet *ifp) 2763 { 2764 struct re_softc *sc = ifp->if_softc; 2765 struct mii_data *mii; 2766 2767 ASSERT_SERIALIZED(ifp->if_serializer); 2768 2769 mii = device_get_softc(sc->re_miibus); 2770 mii_mediachg(mii); 2771 2772 return(0); 2773 } 2774 2775 /* 2776 * Report current media status. 2777 */ 2778 static void 2779 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2780 { 2781 struct re_softc *sc = ifp->if_softc; 2782 struct mii_data *mii; 2783 2784 ASSERT_SERIALIZED(ifp->if_serializer); 2785 2786 mii = device_get_softc(sc->re_miibus); 2787 2788 mii_pollstat(mii); 2789 ifmr->ifm_active = mii->mii_media_active; 2790 ifmr->ifm_status = mii->mii_media_status; 2791 } 2792 2793 static int 2794 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2795 { 2796 struct re_softc *sc = ifp->if_softc; 2797 struct ifreq *ifr = (struct ifreq *) data; 2798 struct mii_data *mii; 2799 int error = 0, mask; 2800 2801 ASSERT_SERIALIZED(ifp->if_serializer); 2802 2803 switch(command) { 2804 case SIOCSIFMTU: 2805 if (ifr->ifr_mtu > sc->re_maxmtu) { 2806 error = EINVAL; 2807 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2808 ifp->if_mtu = ifr->ifr_mtu; 2809 if (ifp->if_flags & IFF_RUNNING) 2810 ifp->if_init(sc); 2811 } 2812 break; 2813 2814 case SIOCSIFFLAGS: 2815 if (ifp->if_flags & IFF_UP) { 2816 if (ifp->if_flags & IFF_RUNNING) { 2817 if ((ifp->if_flags ^ sc->re_if_flags) & 2818 (IFF_PROMISC | IFF_ALLMULTI)) 2819 re_setmulti(sc); 2820 } else { 2821 re_init(sc); 2822 } 2823 } else if (ifp->if_flags & IFF_RUNNING) { 2824 re_stop(sc); 2825 } 2826 sc->re_if_flags = ifp->if_flags; 2827 break; 2828 2829 case SIOCADDMULTI: 2830 case SIOCDELMULTI: 2831 re_setmulti(sc); 2832 break; 2833 2834 case SIOCGIFMEDIA: 2835 case SIOCSIFMEDIA: 2836 mii = device_get_softc(sc->re_miibus); 2837 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2838 break; 2839 2840 case SIOCSIFCAP: 2841 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & 2842 ifp->if_capabilities; 2843 ifp->if_capenable ^= mask; 2844 2845 if (mask & IFCAP_HWCSUM) { 2846 if (ifp->if_capenable & IFCAP_TXCSUM) 2847 ifp->if_hwassist = sc->re_hwassist; 2848 else 2849 ifp->if_hwassist = 0; 2850 } 2851 if (mask && (ifp->if_flags & IFF_RUNNING)) 2852 re_init(sc); 2853 break; 2854 2855 default: 2856 error = ether_ioctl(ifp, command, data); 2857 break; 2858 } 2859 return(error); 2860 } 2861 2862 static void 2863 re_watchdog(struct ifnet *ifp) 2864 { 2865 struct re_softc *sc = ifp->if_softc; 2866 2867 ASSERT_SERIALIZED(ifp->if_serializer); 2868 2869 if_printf(ifp, "watchdog timeout\n"); 2870 2871 IFNET_STAT_INC(ifp, oerrors, 1); 2872 2873 re_txeof(sc); 2874 re_rxeof(sc); 2875 2876 re_init(sc); 2877 2878 if (!ifq_is_empty(&ifp->if_snd)) 2879 if_devstart(ifp); 2880 } 2881 2882 /* 2883 * Stop the adapter and free any mbufs allocated to the 2884 * RX and TX lists. 2885 */ 2886 static void 2887 re_stop(struct re_softc *sc) 2888 { 2889 struct ifnet *ifp = &sc->arpcom.ac_if; 2890 int i; 2891 2892 ASSERT_SERIALIZED(ifp->if_serializer); 2893 2894 /* Reset the adapter. */ 2895 re_reset(sc, ifp->if_flags & IFF_RUNNING); 2896 2897 ifp->if_timer = 0; 2898 callout_stop(&sc->re_timer); 2899 2900 ifp->if_flags &= ~IFF_RUNNING; 2901 ifq_clr_oactive(&ifp->if_snd); 2902 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); 2903 2904 CSR_WRITE_1(sc, RE_COMMAND, 0x00); 2905 CSR_WRITE_2(sc, RE_IMR, 0x0000); 2906 CSR_WRITE_2(sc, RE_ISR, 0xFFFF); 2907 2908 re_free_rxchain(sc); 2909 2910 /* Free the TX list buffers. */ 2911 for (i = 0; i < sc->re_tx_desc_cnt; i++) { 2912 if (sc->re_ldata.re_tx_mbuf[i] != NULL) { 2913 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, 2914 sc->re_ldata.re_tx_dmamap[i]); 2915 m_freem(sc->re_ldata.re_tx_mbuf[i]); 2916 sc->re_ldata.re_tx_mbuf[i] = NULL; 2917 } 2918 } 2919 2920 /* Free the RX list buffers. */ 2921 for (i = 0; i < sc->re_rx_desc_cnt; i++) { 2922 if (sc->re_ldata.re_rx_mbuf[i] != NULL) { 2923 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { 2924 bus_dmamap_unload(sc->re_ldata.re_rx_mtag, 2925 sc->re_ldata.re_rx_dmamap[i]); 2926 } 2927 m_freem(sc->re_ldata.re_rx_mbuf[i]); 2928 sc->re_ldata.re_rx_mbuf[i] = NULL; 2929 } 2930 } 2931 } 2932 2933 /* 2934 * Device suspend routine. Stop the interface and save some PCI 2935 * settings in case the BIOS doesn't restore them properly on 2936 * resume. 2937 */ 2938 static int 2939 re_suspend(device_t dev) 2940 { 2941 #ifndef BURN_BRIDGES 2942 int i; 2943 #endif 2944 struct re_softc *sc = device_get_softc(dev); 2945 struct ifnet *ifp = &sc->arpcom.ac_if; 2946 2947 lwkt_serialize_enter(ifp->if_serializer); 2948 2949 re_stop(sc); 2950 2951 #ifndef BURN_BRIDGES 2952 for (i = 0; i < 5; i++) 2953 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2954 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2955 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2956 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2957 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2958 #endif 2959 2960 sc->re_flags |= RE_F_SUSPENDED; 2961 2962 lwkt_serialize_exit(ifp->if_serializer); 2963 2964 return (0); 2965 } 2966 2967 /* 2968 * Device resume routine. Restore some PCI settings in case the BIOS 2969 * doesn't, re-enable busmastering, and restart the interface if 2970 * appropriate. 2971 */ 2972 static int 2973 re_resume(device_t dev) 2974 { 2975 struct re_softc *sc = device_get_softc(dev); 2976 struct ifnet *ifp = &sc->arpcom.ac_if; 2977 #ifndef BURN_BRIDGES 2978 int i; 2979 #endif 2980 2981 lwkt_serialize_enter(ifp->if_serializer); 2982 2983 #ifndef BURN_BRIDGES 2984 /* better way to do this? */ 2985 for (i = 0; i < 5; i++) 2986 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2987 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2988 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2989 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2990 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2991 2992 /* reenable busmastering */ 2993 pci_enable_busmaster(dev); 2994 pci_enable_io(dev, SYS_RES_IOPORT); 2995 #endif 2996 2997 /* reinitialize interface if necessary */ 2998 if (ifp->if_flags & IFF_UP) 2999 re_init(sc); 3000 3001 sc->re_flags &= ~RE_F_SUSPENDED; 3002 3003 lwkt_serialize_exit(ifp->if_serializer); 3004 3005 return (0); 3006 } 3007 3008 /* 3009 * Stop all chip I/O so that the kernel's probe routines don't 3010 * get confused by errant DMAs when rebooting. 3011 */ 3012 static void 3013 re_shutdown(device_t dev) 3014 { 3015 struct re_softc *sc = device_get_softc(dev); 3016 struct ifnet *ifp = &sc->arpcom.ac_if; 3017 3018 lwkt_serialize_enter(ifp->if_serializer); 3019 re_stop(sc); 3020 lwkt_serialize_exit(ifp->if_serializer); 3021 } 3022 3023 static int 3024 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) 3025 { 3026 struct re_softc *sc = arg1; 3027 3028 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); 3029 } 3030 3031 static int 3032 re_sysctl_txtime(SYSCTL_HANDLER_ARGS) 3033 { 3034 struct re_softc *sc = arg1; 3035 3036 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); 3037 } 3038 3039 static int 3040 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) 3041 { 3042 struct re_softc *sc = arg1; 3043 struct ifnet *ifp = &sc->arpcom.ac_if; 3044 int error, v; 3045 3046 lwkt_serialize_enter(ifp->if_serializer); 3047 3048 v = *hwtime; 3049 error = sysctl_handle_int(oidp, &v, 0, req); 3050 if (error || req->newptr == NULL) 3051 goto back; 3052 3053 if (v <= 0) { 3054 error = EINVAL; 3055 goto back; 3056 } 3057 3058 if (v != *hwtime) { 3059 *hwtime = v; 3060 3061 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3062 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) 3063 re_setup_hw_im(sc); 3064 } 3065 back: 3066 lwkt_serialize_exit(ifp->if_serializer); 3067 return error; 3068 } 3069 3070 static int 3071 re_sysctl_simtime(SYSCTL_HANDLER_ARGS) 3072 { 3073 struct re_softc *sc = arg1; 3074 struct ifnet *ifp = &sc->arpcom.ac_if; 3075 int error, v; 3076 3077 lwkt_serialize_enter(ifp->if_serializer); 3078 3079 v = sc->re_sim_time; 3080 error = sysctl_handle_int(oidp, &v, 0, req); 3081 if (error || req->newptr == NULL) 3082 goto back; 3083 3084 if (v <= 0) { 3085 error = EINVAL; 3086 goto back; 3087 } 3088 3089 if (v != sc->re_sim_time) { 3090 sc->re_sim_time = v; 3091 3092 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3093 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { 3094 #ifdef foo 3095 int reg; 3096 3097 /* 3098 * Following code causes various strange 3099 * performance problems. Hmm ... 3100 */ 3101 CSR_WRITE_2(sc, RE_IMR, 0); 3102 if (!RE_IS_8139CP(sc)) 3103 reg = RE_TIMERINT_8169; 3104 else 3105 reg = RE_TIMERINT; 3106 CSR_WRITE_4(sc, reg, 0); 3107 CSR_READ_4(sc, reg); /* flush */ 3108 3109 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3110 re_setup_sim_im(sc); 3111 #else 3112 re_setup_intr(sc, 0, RE_IMTYPE_NONE); 3113 DELAY(10); 3114 re_setup_intr(sc, 1, RE_IMTYPE_SIM); 3115 #endif 3116 } 3117 } 3118 back: 3119 lwkt_serialize_exit(ifp->if_serializer); 3120 return error; 3121 } 3122 3123 static int 3124 re_sysctl_imtype(SYSCTL_HANDLER_ARGS) 3125 { 3126 struct re_softc *sc = arg1; 3127 struct ifnet *ifp = &sc->arpcom.ac_if; 3128 int error, v; 3129 3130 lwkt_serialize_enter(ifp->if_serializer); 3131 3132 v = sc->re_imtype; 3133 error = sysctl_handle_int(oidp, &v, 0, req); 3134 if (error || req->newptr == NULL) 3135 goto back; 3136 3137 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { 3138 error = EINVAL; 3139 goto back; 3140 } 3141 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { 3142 /* Can't do hardware interrupt moderation */ 3143 error = EOPNOTSUPP; 3144 goto back; 3145 } 3146 3147 if (v != sc->re_imtype) { 3148 sc->re_imtype = v; 3149 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) == 3150 IFF_RUNNING) 3151 re_setup_intr(sc, 1, sc->re_imtype); 3152 } 3153 back: 3154 lwkt_serialize_exit(ifp->if_serializer); 3155 return error; 3156 } 3157 3158 static void 3159 re_setup_hw_im(struct re_softc *sc) 3160 { 3161 KKASSERT(sc->re_caps & RE_C_HWIM); 3162 3163 /* 3164 * Interrupt moderation 3165 * 3166 * 0xABCD 3167 * A - unknown (maybe TX related) 3168 * B - TX timer (unit: 25us) 3169 * C - unknown (maybe RX related) 3170 * D - RX timer (unit: 25us) 3171 * 3172 * 3173 * re(4)'s interrupt moderation is actually controlled by 3174 * two variables, like most other NICs (bge, bce etc.) 3175 * o timer 3176 * o number of packets [P] 3177 * 3178 * The logic relationship between these two variables is 3179 * similar to other NICs too: 3180 * if (timer expire || packets > [P]) 3181 * Interrupt is delivered 3182 * 3183 * Currently we only know how to set 'timer', but not 3184 * 'number of packets', which should be ~30, as far as I 3185 * tested (sink ~900Kpps, interrupt rate is 30KHz) 3186 */ 3187 CSR_WRITE_2(sc, RE_IM, 3188 RE_IM_RXTIME(sc->re_rx_time) | 3189 RE_IM_TXTIME(sc->re_tx_time) | 3190 RE_IM_MAGIC); 3191 } 3192 3193 static void 3194 re_disable_hw_im(struct re_softc *sc) 3195 { 3196 if (sc->re_caps & RE_C_HWIM) 3197 CSR_WRITE_2(sc, RE_IM, 0); 3198 } 3199 3200 static void 3201 re_setup_sim_im(struct re_softc *sc) 3202 { 3203 if (!RE_IS_8139CP(sc)) { 3204 uint32_t ticks; 3205 3206 /* 3207 * Datasheet says tick decreases at bus speed, 3208 * but it seems the clock runs a little bit 3209 * faster, so we do some compensation here. 3210 */ 3211 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; 3212 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); 3213 } else { 3214 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ 3215 } 3216 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ 3217 sc->re_flags |= RE_F_TIMER_INTR; 3218 } 3219 3220 static void 3221 re_disable_sim_im(struct re_softc *sc) 3222 { 3223 if (!RE_IS_8139CP(sc)) 3224 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); 3225 else 3226 CSR_WRITE_4(sc, RE_TIMERINT, 0); 3227 sc->re_flags &= ~RE_F_TIMER_INTR; 3228 } 3229 3230 static void 3231 re_config_imtype(struct re_softc *sc, int imtype) 3232 { 3233 switch (imtype) { 3234 case RE_IMTYPE_HW: 3235 KKASSERT(sc->re_caps & RE_C_HWIM); 3236 /* FALL THROUGH */ 3237 case RE_IMTYPE_NONE: 3238 sc->re_intrs = RE_INTRS; 3239 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | 3240 RE_ISR_RX_OVERRUN; 3241 sc->re_tx_ack = RE_ISR_TX_OK; 3242 break; 3243 3244 case RE_IMTYPE_SIM: 3245 sc->re_intrs = RE_INTRS_TIMER; 3246 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; 3247 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; 3248 break; 3249 3250 default: 3251 panic("%s: unknown imtype %d", 3252 sc->arpcom.ac_if.if_xname, imtype); 3253 } 3254 } 3255 3256 static void 3257 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) 3258 { 3259 re_config_imtype(sc, imtype); 3260 3261 if (enable_intrs) 3262 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); 3263 else 3264 CSR_WRITE_2(sc, RE_IMR, 0); 3265 3266 sc->re_npoll.ifpc_stcount = 0; 3267 3268 switch (imtype) { 3269 case RE_IMTYPE_NONE: 3270 re_disable_sim_im(sc); 3271 re_disable_hw_im(sc); 3272 break; 3273 3274 case RE_IMTYPE_HW: 3275 KKASSERT(sc->re_caps & RE_C_HWIM); 3276 re_disable_sim_im(sc); 3277 re_setup_hw_im(sc); 3278 break; 3279 3280 case RE_IMTYPE_SIM: 3281 re_disable_hw_im(sc); 3282 re_setup_sim_im(sc); 3283 break; 3284 3285 default: 3286 panic("%s: unknown imtype %d", 3287 sc->arpcom.ac_if.if_xname, imtype); 3288 } 3289 } 3290 3291 static void 3292 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) 3293 { 3294 int i; 3295 3296 if (sc->re_caps & RE_C_EE_EADDR) { 3297 uint16_t re_did; 3298 3299 re_get_eewidth(sc); 3300 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 3301 if (re_did == 0x8128) { 3302 uint16_t as[ETHER_ADDR_LEN / 2]; 3303 3304 /* 3305 * Get station address from the EEPROM. 3306 */ 3307 re_read_eeprom(sc, (caddr_t)as, sc->re_ee_eaddr, 3); 3308 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 3309 as[i] = le16toh(as[i]); 3310 bcopy(as, eaddr, ETHER_ADDR_LEN); 3311 return; 3312 } 3313 } 3314 3315 /* 3316 * Get station address from IDRx. 3317 */ 3318 for (i = 0; i < ETHER_ADDR_LEN; ++i) 3319 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); 3320 } 3321 3322 static int 3323 re_jpool_alloc(struct re_softc *sc) 3324 { 3325 struct re_list_data *ldata = &sc->re_ldata; 3326 struct re_jbuf *jbuf; 3327 bus_addr_t paddr; 3328 bus_size_t jpool_size; 3329 bus_dmamem_t dmem; 3330 caddr_t buf; 3331 int i, error; 3332 3333 lwkt_serialize_init(&ldata->re_jbuf_serializer); 3334 3335 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), 3336 M_DEVBUF, M_WAITOK | M_ZERO); 3337 3338 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; 3339 3340 error = bus_dmamem_coherent(sc->re_parent_tag, 3341 RE_RXBUF_ALIGN, 0, 3342 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3343 jpool_size, BUS_DMA_WAITOK, &dmem); 3344 if (error) { 3345 device_printf(sc->re_dev, "could not allocate jumbo memory\n"); 3346 return error; 3347 } 3348 ldata->re_jpool_tag = dmem.dmem_tag; 3349 ldata->re_jpool_map = dmem.dmem_map; 3350 ldata->re_jpool = dmem.dmem_addr; 3351 paddr = dmem.dmem_busaddr; 3352 3353 /* ..and split it into 9KB chunks */ 3354 SLIST_INIT(&ldata->re_jbuf_free); 3355 3356 buf = ldata->re_jpool; 3357 for (i = 0; i < RE_JBUF_COUNT(sc); i++) { 3358 jbuf = &ldata->re_jbuf[i]; 3359 3360 jbuf->re_sc = sc; 3361 jbuf->re_inuse = 0; 3362 jbuf->re_slot = i; 3363 jbuf->re_buf = buf; 3364 jbuf->re_paddr = paddr; 3365 3366 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3367 3368 buf += RE_JBUF_SIZE; 3369 paddr += RE_JBUF_SIZE; 3370 } 3371 return 0; 3372 } 3373 3374 static void 3375 re_jpool_free(struct re_softc *sc) 3376 { 3377 struct re_list_data *ldata = &sc->re_ldata; 3378 3379 if (ldata->re_jpool_tag != NULL) { 3380 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); 3381 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, 3382 ldata->re_jpool_map); 3383 bus_dma_tag_destroy(ldata->re_jpool_tag); 3384 ldata->re_jpool_tag = NULL; 3385 } 3386 3387 if (ldata->re_jbuf != NULL) { 3388 kfree(ldata->re_jbuf, M_DEVBUF); 3389 ldata->re_jbuf = NULL; 3390 } 3391 } 3392 3393 static struct re_jbuf * 3394 re_jbuf_alloc(struct re_softc *sc) 3395 { 3396 struct re_list_data *ldata = &sc->re_ldata; 3397 struct re_jbuf *jbuf; 3398 3399 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3400 3401 jbuf = SLIST_FIRST(&ldata->re_jbuf_free); 3402 if (jbuf != NULL) { 3403 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); 3404 jbuf->re_inuse = 1; 3405 } 3406 3407 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3408 3409 return jbuf; 3410 } 3411 3412 static void 3413 re_jbuf_free(void *arg) 3414 { 3415 struct re_jbuf *jbuf = arg; 3416 struct re_softc *sc = jbuf->re_sc; 3417 struct re_list_data *ldata = &sc->re_ldata; 3418 3419 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3420 panic("%s: free wrong jumbo buffer", 3421 sc->arpcom.ac_if.if_xname); 3422 } else if (jbuf->re_inuse == 0) { 3423 panic("%s: jumbo buffer already freed", 3424 sc->arpcom.ac_if.if_xname); 3425 } 3426 3427 lwkt_serialize_enter(&ldata->re_jbuf_serializer); 3428 atomic_subtract_int(&jbuf->re_inuse, 1); 3429 if (jbuf->re_inuse == 0) 3430 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); 3431 lwkt_serialize_exit(&ldata->re_jbuf_serializer); 3432 } 3433 3434 static void 3435 re_jbuf_ref(void *arg) 3436 { 3437 struct re_jbuf *jbuf = arg; 3438 struct re_softc *sc = jbuf->re_sc; 3439 struct re_list_data *ldata = &sc->re_ldata; 3440 3441 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { 3442 panic("%s: ref wrong jumbo buffer", 3443 sc->arpcom.ac_if.if_xname); 3444 } else if (jbuf->re_inuse == 0) { 3445 panic("%s: jumbo buffer already freed", 3446 sc->arpcom.ac_if.if_xname); 3447 } 3448 atomic_add_int(&jbuf->re_inuse, 1); 3449 }
Cache object: 331611664b952a10b5a263ff7983d7d0
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