The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/rue/if_ruereg.h

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    1 /*-
    2  * Copyright (c) 2001-2003, Shunsuke Akiyama <akiyama@FreeBSD.org>.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: src/sys/dev/usb/if_ruereg.h,v 1.3 2004/05/23 12:35:24 iedowse Exp $
   27  * $DragonFly: src/sys/dev/netif/rue/if_ruereg.h,v 1.2 2007/11/05 13:32:27 hasso Exp $
   28  */
   29 
   30 #ifndef _IF_RUEREG_H_
   31 #define _IF_RUEREG_H_
   32 
   33 #define RUE_INTR_PIPE           1       /* Use INTR PIPE */
   34 
   35 #define RUE_CONFIG_NO           1
   36 #define RUE_IFACE_IDX           0
   37 
   38 #define RUE_ENDPT_RX            0x0
   39 #define RUE_ENDPT_TX            0x1
   40 #define RUE_ENDPT_INTR          0x2
   41 #define RUE_ENDPT_MAX           0x3
   42 
   43 #define RUE_INTR_PKTLEN         0x8
   44 
   45 #define RUE_TIMEOUT             1000
   46 #define RUE_BUFSZ               1536
   47 #define RUE_MIN_FRAMELEN        60
   48 #define RUE_INTR_INTERVAL       100     /* ms */
   49 
   50 /*
   51  * Registers
   52  */
   53 
   54 #define RUE_IDR0                0x0120
   55 #define RUE_IDR1                0x0121
   56 #define RUE_IDR2                0x0122
   57 #define RUE_IDR3                0x0123
   58 #define RUE_IDR4                0x0124
   59 #define RUE_IDR5                0x0125
   60 
   61 #define RUE_MAR0                0x0126
   62 #define RUE_MAR1                0x0127
   63 #define RUE_MAR2                0x0128
   64 #define RUE_MAR3                0x0129
   65 #define RUE_MAR4                0x012A
   66 #define RUE_MAR5                0x012B
   67 #define RUE_MAR6                0x012C
   68 #define RUE_MAR7                0x012D
   69 
   70 #define RUE_CR                  0x012E          /* B, R/W */
   71 #define RUE_CR_SOFT_RST         0x10
   72 #define RUE_CR_RE               0x08
   73 #define RUE_CR_TE               0x04
   74 #define RUE_CR_EP3CLREN         0x02
   75 
   76 #define RUE_TCR                 0x012F          /* B, R/W */
   77 #define RUE_TCR_TXRR1           0x80
   78 #define RUE_TCR_TXRR0           0x40
   79 #define RUE_TCR_IFG1            0x10
   80 #define RUE_TCR_IFG0            0x08
   81 #define RUE_TCR_NOCRC           0x01
   82 #define RUE_TCR_CONFIG          (RUE_TCR_TXRR1|RUE_TCR_TXRR0|RUE_TCR_IFG1|RUE_TCR_IFG0)
   83 
   84 #define RUE_RCR                 0x0130          /* W, R/W */
   85 #define RUE_RCR_TAIL            0x80
   86 #define RUE_RCR_AER             0x40
   87 #define RUE_RCR_AR              0x20
   88 #define RUE_RCR_AM              0x10
   89 #define RUE_RCR_AB              0x08
   90 #define RUE_RCR_AD              0x04
   91 #define RUE_RCR_AAM             0x02
   92 #define RUE_RCR_AAP             0x01
   93 #define RUE_RCR_CONFIG          (RUE_RCR_TAIL|RUE_RCR_AD)
   94 
   95 #define RUE_TSR                 0x0132
   96 #define RUE_RSR                 0x0133
   97 #define RUE_CON0                0x0135
   98 #define RUE_CON1                0x0136
   99 #define RUE_MSR                 0x0137
  100 #define RUE_PHYADD              0x0138
  101 #define RUE_PHYDAT              0x0139
  102 
  103 #define RUE_PHYCNT              0x013B          /* B, R/W */
  104 #define RUE_PHYCNT_PHYOWN       0x40
  105 #define RUE_PHYCNT_RWCR         0x20
  106 
  107 #define RUE_GPPC                0x013D
  108 #define RUE_WAKECNT             0x013E
  109 
  110 #define RUE_BMCR                0x0140
  111 #define RUE_BMCR_SPD_SET        0x2000
  112 #define RUE_BMCR_DUPLEX         0x0100
  113 
  114 #define RUE_BMSR                0x0142
  115 
  116 #define RUE_ANAR                0x0144          /* W, R/W */
  117 #define RUE_ANAR_PAUSE          0x0400
  118 
  119 #define RUE_ANLP                0x0146          /* W, R/O */
  120 #define RUE_ANLP_PAUSE          0x0400
  121 
  122 #define RUE_AER                 0x0148
  123 
  124 #define RUE_NWAYT               0x014A
  125 #define RUE_CSCR                0x014C
  126 
  127 #define RUE_CRC0                0x014E
  128 #define RUE_CRC1                0x0150
  129 #define RUE_CRC2                0x0152
  130 #define RUE_CRC3                0x0154
  131 #define RUE_CRC4                0x0156
  132 
  133 #define RUE_BYTEMASK0           0x0158
  134 #define RUE_BYTEMASK1           0x0160
  135 #define RUE_BYTEMASK2           0x0168
  136 #define RUE_BYTEMASK3           0x0170
  137 #define RUE_BYTEMASK4           0x0178
  138 
  139 #define RUE_PHY1                0x0180
  140 #define RUE_PHY2                0x0184
  141 
  142 #define RUE_TW1                 0x0186
  143 
  144 #define RUE_REG_MIN             0x0120
  145 #define RUE_REG_MAX             0x0189
  146 
  147 /*
  148  * EEPROM address declarations
  149  */
  150 
  151 #define RUE_EEPROM_BASE         0x1200
  152 
  153 #define RUE_EEPROM_IDR0         (RUE_EEPROM_BASE + 0x02)
  154 #define RUE_EEPROM_IDR1         (RUE_EEPROM_BASE + 0x03)
  155 #define RUE_EEPROM_IDR2         (RUE_EEPROM_BASE + 0x03)
  156 #define RUE_EEPROM_IDR3         (RUE_EEPROM_BASE + 0x03)
  157 #define RUE_EEPROM_IDR4         (RUE_EEPROM_BASE + 0x03)
  158 #define RUE_EEPROM_IDR5         (RUE_EEPROM_BASE + 0x03)
  159 
  160 #define RUE_EEPROM_INTERVAL     (RUE_EEPROM_BASE + 0x17)
  161 
  162 struct rue_intrpkt {
  163         uint8_t                 rue_tsr;
  164         uint8_t                 rue_rsr;
  165         uint8_t                 rue_gep_msr;
  166         uint8_t                 rue_waksr;
  167         uint8_t                 rue_txok_cnt;
  168         uint8_t                 rue_rxlost_cnt;
  169         uint8_t                 rue_crcerr_cnt;
  170         uint8_t                 rue_col_cnt;
  171 };
  172 
  173 struct rue_rxpkt {
  174         uint16_t                rue_pktlen : 12;
  175         uint16_t                rue_rxstat : 4;
  176 };
  177 
  178 #define RUE_RXSTAT_VALID        0x01
  179 #define RUE_RXSTAT_RUNT         0x02
  180 #define RUE_RXSTAT_PMATCH       0x04
  181 #define RUE_RXSTAT_MCAST        0x08
  182 
  183 #define RUE_RXSTAT_MASK         RUE_RXSTAT_VALID
  184 
  185 #define RUE_TX_LIST_CNT         1
  186 #define RUE_RX_LIST_CNT         1
  187 
  188 struct rue_softc;
  189 
  190 struct rue_chain {
  191         struct rue_softc        *rue_sc;
  192         usbd_xfer_handle        rue_xfer;
  193         char                    *rue_buf;
  194         struct mbuf             *rue_mbuf;
  195         int                     rue_idx;
  196 };
  197 
  198 struct rue_cdata {
  199         struct rue_chain        rue_tx_chain[RUE_TX_LIST_CNT];
  200         struct rue_chain        rue_rx_chain[RUE_RX_LIST_CNT];
  201         struct rue_intrpkt      *rue_ibuf;
  202         int                     rue_tx_prod;
  203         int                     rue_tx_cons;
  204         int                     rue_tx_cnt;
  205         int                     rue_rx_prod;
  206 };
  207 
  208 struct rue_softc {
  209         struct arpcom           arpcom;
  210         device_t                rue_miibus;
  211         usbd_device_handle      rue_udev;
  212         usbd_interface_handle   rue_iface;
  213         int                     rue_ed[RUE_ENDPT_MAX];
  214         usbd_pipe_handle        rue_ep[RUE_ENDPT_MAX];
  215         uint8_t                 rue_link;
  216         int                     rue_if_flags;
  217         struct rue_cdata        rue_cdata;
  218         struct callout          rue_stat_ch;
  219         char                    rue_dying;
  220         struct timeval          rue_rx_notice;
  221 };
  222 
  223 #define GET_MII(sc)     (device_get_softc((sc)->rue_miibus))
  224 
  225 #define RUE_LOCK(_sc)   crit_enter()
  226 #define RUE_UNLOCK(_sc) crit_exit()
  227 
  228 #endif /* _IF_RUEREG_H_ */

Cache object: 5bcb1b041108f7aed3885275d4068817


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