Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/rum/if_rumreg.h
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1 /* $OpenBSD: if_rumreg.h,v 1.12 2006/08/09 08:21:08 damien Exp $ */ 2 /* $DragonFly: src/sys/dev/netif/rum/if_rumreg.h,v 1.2 2007/02/06 14:33:39 sephe Exp $ */ 3 4 /*- 5 * Copyright (c) 2005, 2006 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2006 Niall O'Higgins <niallo@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define RT2573_NOISE_FLOOR -95 22 23 #define RT2573_TX_DESC_SIZE (sizeof (struct rum_tx_desc)) 24 #define RT2573_RX_DESC_SIZE (sizeof (struct rum_rx_desc)) 25 26 #define RT2573_CONFIG_NO 1 27 #define RT2573_IFACE_INDEX 0 28 29 #define RT2573_MCU_CNTL 0x01 30 #define RT2573_WRITE_MAC 0x02 31 #define RT2573_READ_MAC 0x03 32 #define RT2573_WRITE_MULTI_MAC 0x06 33 #define RT2573_READ_MULTI_MAC 0x07 34 #define RT2573_READ_EEPROM 0x09 35 #define RT2573_WRITE_LED 0x0a 36 37 /* 38 * Control and status registers. 39 */ 40 #define RT2573_AIFSN_CSR 0x0400 41 #define RT2573_CWMIN_CSR 0x0404 42 #define RT2573_CWMAX_CSR 0x0408 43 #define RT2573_MCU_CODE_BASE 0x0800 44 #define RT2573_HW_BEACON_BASE0 0x2400 45 #define RT2573_MAC_CSR0 0x3000 46 #define RT2573_MAC_CSR1 0x3004 47 #define RT2573_MAC_CSR2 0x3008 48 #define RT2573_MAC_CSR3 0x300c 49 #define RT2573_MAC_CSR4 0x3010 50 #define RT2573_MAC_CSR5 0x3014 51 #define RT2573_MAC_CSR6 0x3018 52 #define RT2573_MAC_CSR7 0x301c 53 #define RT2573_MAC_CSR8 0x3020 54 #define RT2573_MAC_CSR9 0x3024 55 #define RT2573_MAC_CSR10 0x3028 56 #define RT2573_MAC_CSR11 0x302c 57 #define RT2573_MAC_CSR12 0x3030 58 #define RT2573_MAC_CSR13 0x3034 59 #define RT2573_MAC_CSR14 0x3038 60 #define RT2573_MAC_CSR15 0x303c 61 #define RT2573_TXRX_CSR0 0x3040 62 #define RT2573_TXRX_CSR1 0x3044 63 #define RT2573_TXRX_CSR2 0x3048 64 #define RT2573_TXRX_CSR3 0x304c 65 #define RT2573_TXRX_CSR4 0x3050 66 #define RT2573_TXRX_CSR5 0x3054 67 #define RT2573_TXRX_CSR6 0x3058 68 #define RT2573_TXRX_CSR7 0x305c 69 #define RT2573_TXRX_CSR8 0x3060 70 #define RT2573_TXRX_CSR9 0x3064 71 #define RT2573_TXRX_CSR10 0x3068 72 #define RT2573_TXRX_CSR11 0x306c 73 #define RT2573_TXRX_CSR12 0x3070 74 #define RT2573_TXRX_CSR13 0x3074 75 #define RT2573_TXRX_CSR14 0x3078 76 #define RT2573_TXRX_CSR15 0x307c 77 #define RT2573_PHY_CSR0 0x3080 78 #define RT2573_PHY_CSR1 0x3084 79 #define RT2573_PHY_CSR2 0x3088 80 #define RT2573_PHY_CSR3 0x308c 81 #define RT2573_PHY_CSR4 0x3090 82 #define RT2573_PHY_CSR5 0x3094 83 #define RT2573_PHY_CSR6 0x3098 84 #define RT2573_PHY_CSR7 0x309c 85 #define RT2573_SEC_CSR0 0x30a0 86 #define RT2573_SEC_CSR1 0x30a4 87 #define RT2573_SEC_CSR2 0x30a8 88 #define RT2573_SEC_CSR3 0x30ac 89 #define RT2573_SEC_CSR4 0x30b0 90 #define RT2573_SEC_CSR5 0x30b4 91 #define RT2573_STA_CSR0 0x30c0 92 #define RT2573_STA_CSR1 0x30c4 93 #define RT2573_STA_CSR2 0x30c8 94 #define RT2573_STA_CSR3 0x30cc 95 #define RT2573_STA_CSR4 0x30d0 96 #define RT2573_STA_CSR5 0x30d4 97 98 99 /* possible flags for register RT2573_MAC_CSR1 */ 100 #define RT2573_RESET_ASIC (1 << 0) 101 #define RT2573_RESET_BBP (1 << 1) 102 #define RT2573_HOST_READY (1 << 2) 103 104 /* possible flags for register MAC_CSR5 */ 105 #define RT2573_ONE_BSSID 3 106 107 /* possible flags for register TXRX_CSR0 */ 108 /* Tx filter flags are in the low 16 bits */ 109 #define RT2573_AUTO_TX_SEQ (1 << 15) 110 /* Rx filter flags are in the high 16 bits */ 111 #define RT2573_DISABLE_RX (1 << 16) 112 #define RT2573_DROP_CRC_ERROR (1 << 17) 113 #define RT2573_DROP_PHY_ERROR (1 << 18) 114 #define RT2573_DROP_CTL (1 << 19) 115 #define RT2573_DROP_NOT_TO_ME (1 << 20) 116 #define RT2573_DROP_TODS (1 << 21) 117 #define RT2573_DROP_VER_ERROR (1 << 22) 118 #define RT2573_DROP_MULTICAST (1 << 23) 119 #define RT2573_DROP_BROADCAST (1 << 24) 120 #define RT2573_DROP_ACKCTS (1 << 25) 121 122 /* possible flags for register TXRX_CSR4 */ 123 #define RT2573_SHORT_PREAMBLE (1 << 18) 124 #define RT2573_MRR_ENABLED (1 << 19) 125 #define RT2573_MRR_CCK_FALLBACK (1 << 22) 126 127 /* possible flags for register TXRX_CSR9 */ 128 #define RT2573_TSF_TICKING (1 << 16) 129 #define RT2573_TSF_MODE(x) (((x) & 0x3) << 17) 130 /* TBTT stands for Target Beacon Transmission Time */ 131 #define RT2573_ENABLE_TBTT (1 << 19) 132 #define RT2573_GENERATE_BEACON (1 << 20) 133 134 /* possible flags for register PHY_CSR0 */ 135 #define RT2573_PA_PE_2GHZ (1 << 16) 136 #define RT2573_PA_PE_5GHZ (1 << 17) 137 138 /* possible flags for register PHY_CSR3 */ 139 #define RT2573_BBP_READ (1 << 15) 140 #define RT2573_BBP_BUSY (1 << 16) 141 /* possible flags for register PHY_CSR4 */ 142 #define RT2573_RF_20BIT (20 << 24) 143 #define RT2573_RF_BUSY (1 << 31) 144 145 /* LED values */ 146 #define RT2573_LED_RADIO (1 << 8) 147 #define RT2573_LED_G (1 << 9) 148 #define RT2573_LED_A (1 << 10) 149 #define RT2573_LED_ON 0x1e1e 150 #define RT2573_LED_OFF 0x0 151 152 #define RT2573_MCU_RUN (1 << 3) 153 154 #define RT2573_SMART_MODE (1 << 0) 155 156 #define RT2573_BBPR94_DEFAULT 6 157 158 #define RT2573_BBP_WRITE (1 << 15) 159 160 /* dual-band RF */ 161 #define RT2573_RF_5226 1 162 #define RT2573_RF_5225 3 163 /* single-band RF */ 164 #define RT2573_RF_2528 2 165 #define RT2573_RF_2527 4 166 167 #define RT2573_BBP_VERSION 0 168 169 struct rum_tx_desc { 170 uint32_t flags; 171 #define RT2573_TX_BURST (1 << 0) 172 #define RT2573_TX_VALID (1 << 1) 173 #define RT2573_TX_MORE_FRAG (1 << 2) 174 #define RT2573_TX_ACK (1 << 3) 175 #define RT2573_TX_TIMESTAMP (1 << 4) 176 #define RT2573_TX_OFDM (1 << 5) 177 #define RT2573_TX_IFS_SIFS (1 << 6) 178 #define RT2573_TX_LONG_RETRY (1 << 7) /* Long retry 4 times, 179 * short retry 7 times 180 */ 181 182 uint16_t wme; 183 #define RT2573_QID(v) (v) 184 #define RT2573_AIFSN(v) ((v) << 4) 185 #define RT2573_LOGCWMIN(v) ((v) << 8) 186 #define RT2573_LOGCWMAX(v) ((v) << 12) 187 188 uint16_t xflags; 189 #define RT2573_TX_HWSEQ (1 << 12) 190 191 uint8_t plcp_signal; 192 uint8_t plcp_service; 193 #define RT2573_PLCP_LENGEXT 0x80 194 195 uint8_t plcp_length_lo; 196 uint8_t plcp_length_hi; 197 198 uint32_t iv; 199 uint32_t eiv; 200 201 uint8_t offset; 202 uint8_t qid; 203 uint8_t txpower; 204 #define RT2573_DEFAULT_TXPOWER 0 205 206 uint8_t reserved; 207 } __packed; 208 209 struct rum_rx_desc { 210 uint32_t flags; 211 #define RT2573_RX_BUSY (1 << 0) 212 #define RT2573_RX_DROP (1 << 1) 213 #define RT2573_RX_CRC_ERROR (1 << 6) 214 #define RT2573_RX_OFDM (1 << 7) 215 216 uint8_t rate; 217 uint8_t rssi; 218 uint8_t reserved1; 219 uint8_t offset; 220 uint32_t iv; 221 uint32_t eiv; 222 uint32_t reserved2[2]; 223 } __packed; 224 225 #define RT2573_RF1 0 226 #define RT2573_RF2 2 227 #define RT2573_RF3 1 228 #define RT2573_RF4 3 229 230 #define RT2573_EEPROM_MACBBP 0x0000 231 #define RT2573_EEPROM_ADDRESS 0x0004 232 #define RT2573_EEPROM_ANTENNA 0x0020 233 #define RT2573_EEPROM_CONFIG2 0x0022 234 #define RT2573_EEPROM_BBP_BASE 0x0026 235 #define RT2573_EEPROM_TXPOWER 0x0046 236 #define RT2573_EEPROM_FREQ_OFFSET 0x005e 237 #define RT2573_EEPROM_RSSI_2GHZ_OFFSET 0x009a 238 #define RT2573_EEPROM_RSSI_5GHZ_OFFSET 0x009c 239 240 /* 241 * Default values for MAC registers; values taken from the reference driver. 242 */ 243 #define RT2573_DEF_MAC \ 244 { RT2573_TXRX_CSR0, 0x025fb032 }, \ 245 { RT2573_TXRX_CSR1, 0x9eaa9eaf }, \ 246 { RT2573_TXRX_CSR2, 0x8a8b8c8d }, \ 247 { RT2573_TXRX_CSR3, 0x00858687 }, \ 248 { RT2573_TXRX_CSR7, 0x2e31353b }, \ 249 { RT2573_TXRX_CSR8, 0x2a2a2a2c }, \ 250 { RT2573_TXRX_CSR15, 0x0000000f }, \ 251 { RT2573_MAC_CSR6, 0x00000fff }, \ 252 { RT2573_MAC_CSR8, 0x016c030a }, \ 253 { RT2573_MAC_CSR10, 0x00000718 }, \ 254 { RT2573_MAC_CSR12, 0x00000004 }, \ 255 { RT2573_MAC_CSR13, 0x00007f00 }, \ 256 { RT2573_SEC_CSR0, 0x00000000 }, \ 257 { RT2573_SEC_CSR1, 0x00000000 }, \ 258 { RT2573_SEC_CSR5, 0x00000000 }, \ 259 { RT2573_PHY_CSR1, 0x000023b0 }, \ 260 { RT2573_PHY_CSR5, 0x00040a06 }, \ 261 { RT2573_PHY_CSR6, 0x00080606 }, \ 262 { RT2573_PHY_CSR7, 0x00000408 }, \ 263 { RT2573_AIFSN_CSR, 0x00002273 }, \ 264 { RT2573_CWMIN_CSR, 0x00002344 }, \ 265 { RT2573_CWMAX_CSR, 0x000034aa } 266 267 /* 268 * Default values for BBP registers; values taken from the reference driver. 269 */ 270 #define RT2573_DEF_BBP \ 271 { 3, 0x80 }, \ 272 { 15, 0x30 }, \ 273 { 17, 0x20 }, \ 274 { 21, 0xc8 }, \ 275 { 22, 0x38 }, \ 276 { 23, 0x06 }, \ 277 { 24, 0xfe }, \ 278 { 25, 0x0a }, \ 279 { 26, 0x0d }, \ 280 { 32, 0x0b }, \ 281 { 34, 0x12 }, \ 282 { 37, 0x07 }, \ 283 { 39, 0xf8 }, \ 284 { 41, 0x60 }, \ 285 { 53, 0x10 }, \ 286 { 54, 0x18 }, \ 287 { 60, 0x10 }, \ 288 { 61, 0x04 }, \ 289 { 62, 0x04 }, \ 290 { 75, 0xfe }, \ 291 { 86, 0xfe }, \ 292 { 88, 0xfe }, \ 293 { 90, 0x0f }, \ 294 { 99, 0x00 }, \ 295 { 102, 0x16 }, \ 296 { 107, 0x04 } 297 298 /* 299 * Default settings for RF registers; values taken from the reference driver. 300 */ 301 #define RT2573_RF5226 \ 302 { 1, 0x00b03, 0x001e1, 0x1a014, 0x30282 }, \ 303 { 2, 0x00b03, 0x001e1, 0x1a014, 0x30287 }, \ 304 { 3, 0x00b03, 0x001e2, 0x1a014, 0x30282 }, \ 305 { 4, 0x00b03, 0x001e2, 0x1a014, 0x30287 }, \ 306 { 5, 0x00b03, 0x001e3, 0x1a014, 0x30282 }, \ 307 { 6, 0x00b03, 0x001e3, 0x1a014, 0x30287 }, \ 308 { 7, 0x00b03, 0x001e4, 0x1a014, 0x30282 }, \ 309 { 8, 0x00b03, 0x001e4, 0x1a014, 0x30287 }, \ 310 { 9, 0x00b03, 0x001e5, 0x1a014, 0x30282 }, \ 311 { 10, 0x00b03, 0x001e5, 0x1a014, 0x30287 }, \ 312 { 11, 0x00b03, 0x001e6, 0x1a014, 0x30282 }, \ 313 { 12, 0x00b03, 0x001e6, 0x1a014, 0x30287 }, \ 314 { 13, 0x00b03, 0x001e7, 0x1a014, 0x30282 }, \ 315 { 14, 0x00b03, 0x001e8, 0x1a014, 0x30284 }, \ 316 \ 317 { 34, 0x00b03, 0x20266, 0x36014, 0x30282 }, \ 318 { 38, 0x00b03, 0x20267, 0x36014, 0x30284 }, \ 319 { 42, 0x00b03, 0x20268, 0x36014, 0x30286 }, \ 320 { 46, 0x00b03, 0x20269, 0x36014, 0x30288 }, \ 321 \ 322 { 36, 0x00b03, 0x00266, 0x26014, 0x30288 }, \ 323 { 40, 0x00b03, 0x00268, 0x26014, 0x30280 }, \ 324 { 44, 0x00b03, 0x00269, 0x26014, 0x30282 }, \ 325 { 48, 0x00b03, 0x0026a, 0x26014, 0x30284 }, \ 326 { 52, 0x00b03, 0x0026b, 0x26014, 0x30286 }, \ 327 { 56, 0x00b03, 0x0026c, 0x26014, 0x30288 }, \ 328 { 60, 0x00b03, 0x0026e, 0x26014, 0x30280 }, \ 329 { 64, 0x00b03, 0x0026f, 0x26014, 0x30282 }, \ 330 \ 331 { 100, 0x00b03, 0x0028a, 0x2e014, 0x30280 }, \ 332 { 104, 0x00b03, 0x0028b, 0x2e014, 0x30282 }, \ 333 { 108, 0x00b03, 0x0028c, 0x2e014, 0x30284 }, \ 334 { 112, 0x00b03, 0x0028d, 0x2e014, 0x30286 }, \ 335 { 116, 0x00b03, 0x0028e, 0x2e014, 0x30288 }, \ 336 { 120, 0x00b03, 0x002a0, 0x2e014, 0x30280 }, \ 337 { 124, 0x00b03, 0x002a1, 0x2e014, 0x30282 }, \ 338 { 128, 0x00b03, 0x002a2, 0x2e014, 0x30284 }, \ 339 { 132, 0x00b03, 0x002a3, 0x2e014, 0x30286 }, \ 340 { 136, 0x00b03, 0x002a4, 0x2e014, 0x30288 }, \ 341 { 140, 0x00b03, 0x002a6, 0x2e014, 0x30280 }, \ 342 \ 343 { 149, 0x00b03, 0x002a8, 0x2e014, 0x30287 }, \ 344 { 153, 0x00b03, 0x002a9, 0x2e014, 0x30289 }, \ 345 { 157, 0x00b03, 0x002ab, 0x2e014, 0x30281 }, \ 346 { 161, 0x00b03, 0x002ac, 0x2e014, 0x30283 }, \ 347 { 165, 0x00b03, 0x002ad, 0x2e014, 0x30285 } 348 349 #define RT2573_RF5225 \ 350 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ 351 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ 352 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ 353 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ 354 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ 355 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ 356 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ 357 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ 358 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ 359 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ 360 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ 361 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ 362 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ 363 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ 364 \ 365 { 34, 0x00b33, 0x01266, 0x26014, 0x30282 }, \ 366 { 38, 0x00b33, 0x01267, 0x26014, 0x30284 }, \ 367 { 42, 0x00b33, 0x01268, 0x26014, 0x30286 }, \ 368 { 46, 0x00b33, 0x01269, 0x26014, 0x30288 }, \ 369 \ 370 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ 371 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ 372 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ 373 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ 374 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ 375 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ 376 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ 377 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ 378 \ 379 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ 380 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ 381 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ 382 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ 383 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ 384 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ 385 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ 386 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ 387 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ 388 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ 389 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ 390 \ 391 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ 392 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ 393 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ 394 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ 395 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
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