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sys/dev/netif/sis/if_sis.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $ 33 */ 34 35 /* 36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 37 * available from http://www.sis.com.tw. 38 * 39 * This driver also supports the NatSemi DP83815. Datasheets are 40 * available from http://www.national.com. 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 49 * simple TX and RX descriptors of 3 longwords in size. The receiver 50 * has a single perfect filter entry for the station address and a 51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 52 * transceiver while the 7016 requires an external transceiver chip. 53 * Both chips offer the standard bit-bang MII interface as well as 54 * an enchanced PHY interface which simplifies accessing MII registers. 55 * 56 * The only downside to this chipset is that RX descriptors must be 57 * longword aligned. 58 */ 59 60 #include "opt_ifpoll.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 #include <sys/sysctl.h> 70 #include <sys/serialize.h> 71 #include <sys/thread2.h> 72 #include <sys/bus.h> 73 #include <sys/rman.h> 74 #include <sys/interrupt.h> 75 76 #include <net/if.h> 77 #include <net/ifq_var.h> 78 #include <net/if_arp.h> 79 #include <net/ethernet.h> 80 #include <net/if_dl.h> 81 #include <net/if_media.h> 82 #include <net/if_poll.h> 83 #include <net/if_types.h> 84 #include <net/vlan/if_vlan_var.h> 85 86 #include <net/bpf.h> 87 88 #include <dev/netif/mii_layer/mii.h> 89 #include <dev/netif/mii_layer/miivar.h> 90 91 #include "pcidevs.h" 92 #include <bus/pci/pcireg.h> 93 #include <bus/pci/pcivar.h> 94 95 #define SIS_USEIOSPACE 96 97 #include "if_sisreg.h" 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 /* 103 * Various supported device vendors/types and their names. 104 */ 105 static struct sis_type sis_devs[] = { 106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" }, 107 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" }, 108 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 109 { 0, 0, NULL } 110 }; 111 112 static int sis_probe(device_t); 113 static int sis_attach(device_t); 114 static int sis_detach(device_t); 115 116 static int sis_newbuf(struct sis_softc *, int, int); 117 static void sis_setup_rxdesc(struct sis_softc *, int); 118 static int sis_encap(struct sis_softc *, struct mbuf **, uint32_t *); 119 static void sis_rxeof(struct sis_softc *); 120 static void sis_rxeoc(struct sis_softc *); 121 static void sis_txeof(struct sis_softc *); 122 static void sis_intr(void *); 123 static void sis_tick(void *); 124 static void sis_start(struct ifnet *, struct ifaltq_subque *); 125 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 126 static void sis_init(void *); 127 static void sis_stop(struct sis_softc *); 128 static void sis_watchdog(struct ifnet *); 129 static void sis_shutdown(device_t); 130 static int sis_ifmedia_upd(struct ifnet *); 131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 132 133 static uint16_t sis_reverse(uint16_t); 134 static void sis_delay(struct sis_softc *); 135 static void sis_eeprom_idle(struct sis_softc *); 136 static void sis_eeprom_putbyte(struct sis_softc *, int); 137 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *); 138 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int); 139 #ifdef __i386__ 140 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int); 141 static void sis_read_mac(struct sis_softc *, device_t, caddr_t); 142 static device_t sis_find_bridge(device_t); 143 #endif 144 145 static void sis_mii_sync(struct sis_softc *); 146 static void sis_mii_send(struct sis_softc *, uint32_t, int); 147 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *); 148 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *); 149 static int sis_miibus_readreg(device_t, int, int); 150 static int sis_miibus_writereg(device_t, int, int, int); 151 static void sis_miibus_statchg(device_t); 152 153 static void sis_setmulti_sis(struct sis_softc *); 154 static void sis_setmulti_ns(struct sis_softc *); 155 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *); 156 static void sis_reset(struct sis_softc *); 157 static int sis_list_rx_init(struct sis_softc *); 158 static int sis_list_tx_init(struct sis_softc *); 159 160 static int sis_dma_alloc(device_t dev); 161 static void sis_dma_free(device_t dev); 162 #ifdef IFPOLL_ENABLE 163 static void sis_npoll(struct ifnet *, struct ifpoll_info *); 164 static void sis_npoll_compat(struct ifnet *, void *, int); 165 #endif 166 #ifdef SIS_USEIOSPACE 167 #define SIS_RES SYS_RES_IOPORT 168 #define SIS_RID SIS_PCI_LOIO 169 #else 170 #define SIS_RES SYS_RES_MEMORY 171 #define SIS_RID SIS_PCI_LOMEM 172 #endif 173 174 static device_method_t sis_methods[] = { 175 /* Device interface */ 176 DEVMETHOD(device_probe, sis_probe), 177 DEVMETHOD(device_attach, sis_attach), 178 DEVMETHOD(device_detach, sis_detach), 179 DEVMETHOD(device_shutdown, sis_shutdown), 180 181 /* bus interface */ 182 DEVMETHOD(bus_print_child, bus_generic_print_child), 183 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 184 185 /* MII interface */ 186 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 187 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 188 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 189 190 DEVMETHOD_END 191 }; 192 193 static driver_t sis_driver = { 194 "sis", 195 sis_methods, 196 sizeof(struct sis_softc) 197 }; 198 199 static devclass_t sis_devclass; 200 201 DECLARE_DUMMY_MODULE(if_sis); 202 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, NULL, NULL); 203 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, NULL, NULL); 204 205 #define SIS_SETBIT(sc, reg, x) \ 206 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 207 208 #define SIS_CLRBIT(sc, reg, x) \ 209 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 210 211 #define SIO_SET(x) \ 212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 213 214 #define SIO_CLR(x) \ 215 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 216 217 /* 218 * Routine to reverse the bits in a word. Stolen almost 219 * verbatim from /usr/games/fortune. 220 */ 221 static uint16_t 222 sis_reverse(uint16_t n) 223 { 224 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 225 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 226 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 227 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 228 229 return(n); 230 } 231 232 static void 233 sis_delay(struct sis_softc *sc) 234 { 235 int idx; 236 237 for (idx = (300 / 33) + 1; idx > 0; idx--) 238 CSR_READ_4(sc, SIS_CSR); 239 } 240 241 static void 242 sis_eeprom_idle(struct sis_softc *sc) 243 { 244 int i; 245 246 SIO_SET(SIS_EECTL_CSEL); 247 sis_delay(sc); 248 SIO_SET(SIS_EECTL_CLK); 249 sis_delay(sc); 250 251 for (i = 0; i < 25; i++) { 252 SIO_CLR(SIS_EECTL_CLK); 253 sis_delay(sc); 254 SIO_SET(SIS_EECTL_CLK); 255 sis_delay(sc); 256 } 257 258 SIO_CLR(SIS_EECTL_CLK); 259 sis_delay(sc); 260 SIO_CLR(SIS_EECTL_CSEL); 261 sis_delay(sc); 262 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 263 } 264 265 /* 266 * Send a read command and address to the EEPROM, check for ACK. 267 */ 268 static void 269 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 270 { 271 int d, i; 272 273 d = addr | SIS_EECMD_READ; 274 275 /* 276 * Feed in each bit and stobe the clock. 277 */ 278 for (i = 0x400; i; i >>= 1) { 279 if (d & i) 280 SIO_SET(SIS_EECTL_DIN); 281 else 282 SIO_CLR(SIS_EECTL_DIN); 283 sis_delay(sc); 284 SIO_SET(SIS_EECTL_CLK); 285 sis_delay(sc); 286 SIO_CLR(SIS_EECTL_CLK); 287 sis_delay(sc); 288 } 289 } 290 291 /* 292 * Read a word of data stored in the EEPROM at address 'addr.' 293 */ 294 static void 295 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 296 { 297 int i; 298 uint16_t word = 0; 299 300 /* Force EEPROM to idle state. */ 301 sis_eeprom_idle(sc); 302 303 /* Enter EEPROM access mode. */ 304 sis_delay(sc); 305 SIO_CLR(SIS_EECTL_CLK); 306 sis_delay(sc); 307 SIO_SET(SIS_EECTL_CSEL); 308 sis_delay(sc); 309 310 /* 311 * Send address of word we want to read. 312 */ 313 sis_eeprom_putbyte(sc, addr); 314 315 /* 316 * Start reading bits from EEPROM. 317 */ 318 for (i = 0x8000; i; i >>= 1) { 319 SIO_SET(SIS_EECTL_CLK); 320 sis_delay(sc); 321 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 322 word |= i; 323 sis_delay(sc); 324 SIO_CLR(SIS_EECTL_CLK); 325 sis_delay(sc); 326 } 327 328 /* Turn off EEPROM access mode. */ 329 sis_eeprom_idle(sc); 330 331 *dest = word; 332 } 333 334 /* 335 * Read a sequence of words from the EEPROM. 336 */ 337 static void 338 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 339 { 340 int i; 341 uint16_t word = 0, *ptr; 342 343 for (i = 0; i < cnt; i++) { 344 sis_eeprom_getword(sc, off + i, &word); 345 ptr = (uint16_t *)(dest + (i * 2)); 346 if (swap) 347 *ptr = ntohs(word); 348 else 349 *ptr = word; 350 } 351 } 352 353 #ifdef __i386__ 354 static device_t 355 sis_find_bridge(device_t dev) 356 { 357 devclass_t pci_devclass; 358 device_t *pci_devices; 359 int pci_count = 0; 360 device_t *pci_children; 361 int pci_childcount = 0; 362 device_t *busp, *childp; 363 device_t child = NULL; 364 int i, j; 365 366 if ((pci_devclass = devclass_find("pci")) == NULL) 367 return(NULL); 368 369 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 370 371 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 372 pci_childcount = 0; 373 device_get_children(*busp, &pci_children, &pci_childcount); 374 for (j = 0, childp = pci_children; j < pci_childcount; 375 j++, childp++) { 376 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS && 377 pci_get_device(*childp) == 0x0008) { 378 child = *childp; 379 goto done; 380 } 381 } 382 } 383 384 done: 385 kfree(pci_devices, M_TEMP); 386 kfree(pci_children, M_TEMP); 387 return(child); 388 } 389 390 static void 391 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, 392 int cnt) 393 { 394 device_t bridge; 395 uint8_t reg; 396 int i; 397 bus_space_tag_t btag; 398 399 bridge = sis_find_bridge(dev); 400 if (bridge == NULL) 401 return; 402 reg = pci_read_config(bridge, 0x48, 1); 403 pci_write_config(bridge, 0x48, reg|0x40, 1); 404 405 /* XXX */ 406 btag = I386_BUS_SPACE_IO; 407 408 for (i = 0; i < cnt; i++) { 409 bus_space_write_1(btag, 0x0, 0x70, i + off); 410 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 411 } 412 413 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 414 } 415 416 static void 417 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 418 { 419 uint32_t filtsave, csrsave; 420 421 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 422 csrsave = CSR_READ_4(sc, SIS_CSR); 423 424 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 425 CSR_WRITE_4(sc, SIS_CSR, 0); 426 427 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 428 429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 430 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 431 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 432 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 433 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 434 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 435 436 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 437 CSR_WRITE_4(sc, SIS_CSR, csrsave); 438 } 439 #endif 440 441 /* 442 * Sync the PHYs by setting data bit and strobing the clock 32 times. 443 */ 444 static void 445 sis_mii_sync(struct sis_softc *sc) 446 { 447 int i; 448 449 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 450 451 for (i = 0; i < 32; i++) { 452 SIO_SET(SIS_MII_CLK); 453 DELAY(1); 454 SIO_CLR(SIS_MII_CLK); 455 DELAY(1); 456 } 457 } 458 459 /* 460 * Clock a series of bits through the MII. 461 */ 462 static void 463 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 464 { 465 int i; 466 467 SIO_CLR(SIS_MII_CLK); 468 469 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 470 if (bits & i) 471 SIO_SET(SIS_MII_DATA); 472 else 473 SIO_CLR(SIS_MII_DATA); 474 DELAY(1); 475 SIO_CLR(SIS_MII_CLK); 476 DELAY(1); 477 SIO_SET(SIS_MII_CLK); 478 } 479 } 480 481 /* 482 * Read an PHY register through the MII. 483 */ 484 static int 485 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 486 { 487 int i, ack; 488 489 /* 490 * Set up frame for RX. 491 */ 492 frame->mii_stdelim = SIS_MII_STARTDELIM; 493 frame->mii_opcode = SIS_MII_READOP; 494 frame->mii_turnaround = 0; 495 frame->mii_data = 0; 496 497 /* 498 * Turn on data xmit. 499 */ 500 SIO_SET(SIS_MII_DIR); 501 502 sis_mii_sync(sc); 503 504 /* 505 * Send command/address info. 506 */ 507 sis_mii_send(sc, frame->mii_stdelim, 2); 508 sis_mii_send(sc, frame->mii_opcode, 2); 509 sis_mii_send(sc, frame->mii_phyaddr, 5); 510 sis_mii_send(sc, frame->mii_regaddr, 5); 511 512 /* Idle bit */ 513 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 514 DELAY(1); 515 SIO_SET(SIS_MII_CLK); 516 DELAY(1); 517 518 /* Turn off xmit. */ 519 SIO_CLR(SIS_MII_DIR); 520 521 /* Check for ack */ 522 SIO_CLR(SIS_MII_CLK); 523 DELAY(1); 524 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 525 SIO_SET(SIS_MII_CLK); 526 DELAY(1); 527 528 /* 529 * Now try reading data bits. If the ack failed, we still 530 * need to clock through 16 cycles to keep the PHY(s) in sync. 531 */ 532 if (ack) { 533 for(i = 0; i < 16; i++) { 534 SIO_CLR(SIS_MII_CLK); 535 DELAY(1); 536 SIO_SET(SIS_MII_CLK); 537 DELAY(1); 538 } 539 goto fail; 540 } 541 542 for (i = 0x8000; i; i >>= 1) { 543 SIO_CLR(SIS_MII_CLK); 544 DELAY(1); 545 if (!ack) { 546 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 547 frame->mii_data |= i; 548 DELAY(1); 549 } 550 SIO_SET(SIS_MII_CLK); 551 DELAY(1); 552 } 553 554 fail: 555 556 SIO_CLR(SIS_MII_CLK); 557 DELAY(1); 558 SIO_SET(SIS_MII_CLK); 559 DELAY(1); 560 561 if (ack) 562 return(1); 563 return(0); 564 } 565 566 /* 567 * Write to a PHY register through the MII. 568 */ 569 static int 570 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 571 { 572 /* 573 * Set up frame for TX. 574 */ 575 576 frame->mii_stdelim = SIS_MII_STARTDELIM; 577 frame->mii_opcode = SIS_MII_WRITEOP; 578 frame->mii_turnaround = SIS_MII_TURNAROUND; 579 580 /* 581 * Turn on data output. 582 */ 583 SIO_SET(SIS_MII_DIR); 584 585 sis_mii_sync(sc); 586 587 sis_mii_send(sc, frame->mii_stdelim, 2); 588 sis_mii_send(sc, frame->mii_opcode, 2); 589 sis_mii_send(sc, frame->mii_phyaddr, 5); 590 sis_mii_send(sc, frame->mii_regaddr, 5); 591 sis_mii_send(sc, frame->mii_turnaround, 2); 592 sis_mii_send(sc, frame->mii_data, 16); 593 594 /* Idle bit. */ 595 SIO_SET(SIS_MII_CLK); 596 DELAY(1); 597 SIO_CLR(SIS_MII_CLK); 598 DELAY(1); 599 600 /* 601 * Turn off xmit. 602 */ 603 SIO_CLR(SIS_MII_DIR); 604 605 return(0); 606 } 607 608 static int 609 sis_miibus_readreg(device_t dev, int phy, int reg) 610 { 611 struct sis_softc *sc; 612 struct sis_mii_frame frame; 613 614 sc = device_get_softc(dev); 615 616 if (sc->sis_type == SIS_TYPE_83815) { 617 if (phy != 0) 618 return(0); 619 /* 620 * The NatSemi chip can take a while after 621 * a reset to come ready, during which the BMSR 622 * returns a value of 0. This is *never* supposed 623 * to happen: some of the BMSR bits are meant to 624 * be hardwired in the on position, and this can 625 * confuse the miibus code a bit during the probe 626 * and attach phase. So we make an effort to check 627 * for this condition and wait for it to clear. 628 */ 629 if (!CSR_READ_4(sc, NS_BMSR)) 630 DELAY(1000); 631 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 632 } 633 /* 634 * Chipsets < SIS_635 seem not to be able to read/write 635 * through mdio. Use the enhanced PHY access register 636 * again for them. 637 */ 638 if (sc->sis_type == SIS_TYPE_900 && 639 sc->sis_rev < SIS_REV_635) { 640 int i, val = 0; 641 642 if (phy != 0) 643 return(0); 644 645 CSR_WRITE_4(sc, SIS_PHYCTL, 646 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 647 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 648 649 for (i = 0; i < SIS_TIMEOUT; i++) { 650 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 651 break; 652 } 653 654 if (i == SIS_TIMEOUT) { 655 device_printf(dev, "PHY failed to come ready\n"); 656 return(0); 657 } 658 659 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 660 661 if (val == 0xFFFF) 662 return(0); 663 664 return(val); 665 } else { 666 bzero((char *)&frame, sizeof(frame)); 667 668 frame.mii_phyaddr = phy; 669 frame.mii_regaddr = reg; 670 sis_mii_readreg(sc, &frame); 671 672 return(frame.mii_data); 673 } 674 } 675 676 static int 677 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 678 { 679 struct sis_softc *sc; 680 struct sis_mii_frame frame; 681 682 sc = device_get_softc(dev); 683 684 if (sc->sis_type == SIS_TYPE_83815) { 685 if (phy != 0) 686 return(0); 687 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 688 return(0); 689 } 690 691 if (sc->sis_type == SIS_TYPE_900 && 692 sc->sis_rev < SIS_REV_635) { 693 int i; 694 695 if (phy != 0) 696 return(0); 697 698 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 699 (reg << 6) | SIS_PHYOP_WRITE); 700 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 701 702 for (i = 0; i < SIS_TIMEOUT; i++) { 703 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 704 break; 705 } 706 707 if (i == SIS_TIMEOUT) 708 device_printf(dev, "PHY failed to come ready\n"); 709 } else { 710 bzero((char *)&frame, sizeof(frame)); 711 712 frame.mii_phyaddr = phy; 713 frame.mii_regaddr = reg; 714 frame.mii_data = data; 715 sis_mii_writereg(sc, &frame); 716 } 717 return(0); 718 } 719 720 static void 721 sis_miibus_statchg(device_t dev) 722 { 723 struct sis_softc *sc; 724 725 sc = device_get_softc(dev); 726 sis_init(sc); 727 } 728 729 static uint32_t 730 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 731 { 732 uint32_t crc, carry; 733 int i, j; 734 uint8_t c; 735 736 /* Compute CRC for the address value. */ 737 crc = 0xFFFFFFFF; /* initial value */ 738 739 for (i = 0; i < 6; i++) { 740 c = *(addr + i); 741 for (j = 0; j < 8; j++) { 742 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 743 crc <<= 1; 744 c >>= 1; 745 if (carry) 746 crc = (crc ^ 0x04c11db6) | carry; 747 } 748 } 749 750 /* 751 * return the filter bit position 752 * 753 * The NatSemi chip has a 512-bit filter, which is 754 * different than the SiS, so we special-case it. 755 */ 756 if (sc->sis_type == SIS_TYPE_83815) 757 return (crc >> 23); 758 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 759 return (crc >> 24); 760 else 761 return (crc >> 25); 762 } 763 764 static void 765 sis_setmulti_ns(struct sis_softc *sc) 766 { 767 struct ifnet *ifp; 768 struct ifmultiaddr *ifma; 769 uint32_t h = 0, i, filtsave; 770 int bit, index; 771 772 ifp = &sc->arpcom.ac_if; 773 774 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 775 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 776 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 777 return; 778 } 779 780 /* 781 * We have to explicitly enable the multicast hash table 782 * on the NatSemi chip if we want to use it, which we do. 783 */ 784 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); 785 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); 786 787 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 788 789 /* first, zot all the existing hash bits */ 790 for (i = 0; i < 32; i++) { 791 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); 792 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 793 } 794 795 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 796 if (ifma->ifma_addr->sa_family != AF_LINK) 797 continue; 798 h = sis_mchash(sc, 799 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 800 index = h >> 3; 801 bit = h & 0x1F; 802 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); 803 if (bit > 0xF) 804 bit -= 0x10; 805 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 806 } 807 808 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 809 } 810 811 static void 812 sis_setmulti_sis(struct sis_softc *sc) 813 { 814 struct ifnet *ifp; 815 struct ifmultiaddr *ifma; 816 uint32_t h, i, n, ctl; 817 uint16_t hashes[16]; 818 819 ifp = &sc->arpcom.ac_if; 820 821 /* hash table size */ 822 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 823 n = 16; 824 else 825 n = 8; 826 827 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; 828 829 if (ifp->if_flags & IFF_BROADCAST) 830 ctl |= SIS_RXFILTCTL_BROAD; 831 832 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 833 ctl |= SIS_RXFILTCTL_ALLMULTI; 834 if (ifp->if_flags & IFF_PROMISC) 835 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; 836 for (i = 0; i < n; i++) 837 hashes[i] = ~0; 838 } else { 839 for (i = 0; i < n; i++) 840 hashes[i] = 0; 841 i = 0; 842 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 843 if (ifma->ifma_addr->sa_family != AF_LINK) 844 continue; 845 h = sis_mchash(sc, 846 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 847 hashes[h >> 4] |= 1 << (h & 0xf); 848 i++; 849 } 850 if (i > n) { 851 ctl |= SIS_RXFILTCTL_ALLMULTI; 852 for (i = 0; i < n; i++) 853 hashes[i] = ~0; 854 } 855 } 856 857 for (i = 0; i < n; i++) { 858 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 859 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 860 } 861 862 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); 863 } 864 865 static void 866 sis_reset(struct sis_softc *sc) 867 { 868 struct ifnet *ifp = &sc->arpcom.ac_if; 869 int i; 870 871 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 872 873 for (i = 0; i < SIS_TIMEOUT; i++) { 874 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 875 break; 876 } 877 878 if (i == SIS_TIMEOUT) 879 if_printf(ifp, "reset never completed\n"); 880 881 /* Wait a little while for the chip to get its brains in order. */ 882 DELAY(1000); 883 884 /* 885 * If this is a NetSemi chip, make sure to clear 886 * PME mode. 887 */ 888 if (sc->sis_type == SIS_TYPE_83815) { 889 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 890 CSR_WRITE_4(sc, NS_CLKRUN, 0); 891 } 892 } 893 894 /* 895 * Probe for an SiS chip. Check the PCI vendor and device 896 * IDs against our list and return a device name if we find a match. 897 */ 898 static int 899 sis_probe(device_t dev) 900 { 901 struct sis_type *t; 902 903 t = sis_devs; 904 905 while(t->sis_name != NULL) { 906 if ((pci_get_vendor(dev) == t->sis_vid) && 907 (pci_get_device(dev) == t->sis_did)) { 908 device_set_desc(dev, t->sis_name); 909 return(0); 910 } 911 t++; 912 } 913 914 return(ENXIO); 915 } 916 917 /* 918 * Attach the interface. Allocate softc structures, do ifmedia 919 * setup and ethernet/BPF attach. 920 */ 921 static int 922 sis_attach(device_t dev) 923 { 924 uint8_t eaddr[ETHER_ADDR_LEN]; 925 uint32_t command; 926 struct sis_softc *sc; 927 struct ifnet *ifp; 928 int error, rid, waittime; 929 930 error = waittime = 0; 931 sc = device_get_softc(dev); 932 933 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900) 934 sc->sis_type = SIS_TYPE_900; 935 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016) 936 sc->sis_type = SIS_TYPE_7016; 937 if (pci_get_vendor(dev) == PCI_VENDOR_NS) 938 sc->sis_type = SIS_TYPE_83815; 939 940 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 941 942 /* 943 * Handle power management nonsense. 944 */ 945 946 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF; 947 if (command == 0x01) { 948 949 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4); 950 if (command & SIS_PSTATE_MASK) { 951 uint32_t iobase, membase, irq; 952 953 /* Save important PCI config data. */ 954 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); 955 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); 956 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); 957 958 /* Reset the power state. */ 959 device_printf(dev, "chip is in D%d power mode " 960 "-- setting to D0\n", command & SIS_PSTATE_MASK); 961 command &= 0xFFFFFFFC; 962 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4); 963 964 /* Restore PCI config data. */ 965 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); 966 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); 967 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); 968 } 969 } 970 971 /* 972 * Map control/status registers. 973 */ 974 command = pci_read_config(dev, PCIR_COMMAND, 4); 975 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 976 pci_write_config(dev, PCIR_COMMAND, command, 4); 977 command = pci_read_config(dev, PCIR_COMMAND, 4); 978 979 #ifdef SIS_USEIOSPACE 980 if (!(command & PCIM_CMD_PORTEN)) { 981 device_printf(dev, "failed to enable I/O ports!\n"); 982 error = ENXIO; 983 goto fail; 984 } 985 #else 986 if (!(command & PCIM_CMD_MEMEN)) { 987 device_printf(dev, "failed to enable memory mapping!\n"); 988 error = ENXIO; 989 goto fail; 990 } 991 #endif 992 993 rid = SIS_RID; 994 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE); 995 996 if (sc->sis_res == NULL) { 997 device_printf(dev, "couldn't map ports/memory\n"); 998 error = ENXIO; 999 goto fail; 1000 } 1001 1002 sc->sis_btag = rman_get_bustag(sc->sis_res); 1003 sc->sis_bhandle = rman_get_bushandle(sc->sis_res); 1004 1005 /* Allocate interrupt */ 1006 rid = 0; 1007 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1008 RF_SHAREABLE | RF_ACTIVE); 1009 1010 if (sc->sis_irq == NULL) { 1011 device_printf(dev, "couldn't map interrupt\n"); 1012 error = ENXIO; 1013 goto fail; 1014 } 1015 1016 /* Reset the adapter. */ 1017 sis_reset(sc); 1018 1019 if (sc->sis_type == SIS_TYPE_900 && 1020 (sc->sis_rev == SIS_REV_635 || 1021 sc->sis_rev == SIS_REV_900B)) { 1022 SIO_SET(SIS_CFG_RND_CNT); 1023 SIO_SET(SIS_CFG_PERR_DETECT); 1024 } 1025 1026 /* 1027 * Get station address from the EEPROM. 1028 */ 1029 switch (pci_get_vendor(dev)) { 1030 case PCI_VENDOR_NS: 1031 /* 1032 * Reading the MAC address out of the EEPROM on 1033 * the NatSemi chip takes a bit more work than 1034 * you'd expect. The address spans 4 16-bit words, 1035 * with the first word containing only a single bit. 1036 * You have to shift everything over one bit to 1037 * get it aligned properly. Also, the bits are 1038 * stored backwards (the LSB is really the MSB, 1039 * and so on) so you have to reverse them in order 1040 * to get the MAC address into the form we want. 1041 * Why? Who the hell knows. 1042 */ 1043 { 1044 uint16_t tmp[4]; 1045 1046 sis_read_eeprom(sc, (caddr_t)&tmp, 1047 NS_EE_NODEADDR, 4, 0); 1048 1049 /* Shift everything over one bit. */ 1050 tmp[3] = tmp[3] >> 1; 1051 tmp[3] |= tmp[2] << 15; 1052 tmp[2] = tmp[2] >> 1; 1053 tmp[2] |= tmp[1] << 15; 1054 tmp[1] = tmp[1] >> 1; 1055 tmp[1] |= tmp[0] << 15; 1056 1057 /* Now reverse all the bits. */ 1058 tmp[3] = sis_reverse(tmp[3]); 1059 tmp[2] = sis_reverse(tmp[2]); 1060 tmp[1] = sis_reverse(tmp[1]); 1061 1062 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); 1063 } 1064 break; 1065 case PCI_VENDOR_SIS: 1066 default: 1067 #ifdef __i386__ 1068 /* 1069 * If this is a SiS 630E chipset with an embedded 1070 * SiS 900 controller, we have to read the MAC address 1071 * from the APC CMOS RAM. Our method for doing this 1072 * is very ugly since we have to reach out and grab 1073 * ahold of hardware for which we cannot properly 1074 * allocate resources. This code is only compiled on 1075 * the i386 architecture since the SiS 630E chipset 1076 * is for x86 motherboards only. Note that there are 1077 * a lot of magic numbers in this hack. These are 1078 * taken from SiS's Linux driver. I'd like to replace 1079 * them with proper symbolic definitions, but that 1080 * requires some datasheets that I don't have access 1081 * to at the moment. 1082 */ 1083 if (sc->sis_rev == SIS_REV_630S || 1084 sc->sis_rev == SIS_REV_630E || 1085 sc->sis_rev == SIS_REV_630EA1) 1086 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1087 1088 else if (sc->sis_rev == SIS_REV_635 || 1089 sc->sis_rev == SIS_REV_630ET) 1090 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1091 else if (sc->sis_rev == SIS_REV_96x) { 1092 /* 1093 * Allow to read EEPROM from LAN. It is shared 1094 * between a 1394 controller and the NIC and each 1095 * time we access it, we need to set SIS_EECMD_REQ. 1096 */ 1097 SIO_SET(SIS_EECMD_REQ); 1098 for (waittime = 0; waittime < SIS_TIMEOUT; 1099 waittime++) { 1100 /* Force EEPROM to idle state. */ 1101 sis_eeprom_idle(sc); 1102 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1103 sis_read_eeprom(sc, (caddr_t)&eaddr, 1104 SIS_EE_NODEADDR, 3, 0); 1105 break; 1106 } 1107 DELAY(1); 1108 } 1109 /* 1110 * Set SIS_EECTL_CLK to high, so a other master 1111 * can operate on the i2c bus. 1112 */ 1113 SIO_SET(SIS_EECTL_CLK); 1114 /* Refuse EEPROM access by LAN */ 1115 SIO_SET(SIS_EECMD_DONE); 1116 } else 1117 #endif 1118 sis_read_eeprom(sc, (caddr_t)&eaddr, 1119 SIS_EE_NODEADDR, 3, 0); 1120 break; 1121 } 1122 1123 callout_init(&sc->sis_timer); 1124 1125 error = sis_dma_alloc(dev); 1126 if (error) 1127 goto fail; 1128 1129 ifp = &sc->arpcom.ac_if; 1130 ifp->if_softc = sc; 1131 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1132 ifp->if_mtu = ETHERMTU; 1133 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1134 ifp->if_ioctl = sis_ioctl; 1135 ifp->if_start = sis_start; 1136 ifp->if_watchdog = sis_watchdog; 1137 ifp->if_init = sis_init; 1138 ifp->if_baudrate = 10000000; 1139 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1140 ifq_set_ready(&ifp->if_snd); 1141 #ifdef IFPOLL_ENABLE 1142 ifp->if_npoll = sis_npoll; 1143 #endif 1144 ifp->if_capenable = ifp->if_capabilities; 1145 1146 /* 1147 * Do MII setup. 1148 */ 1149 if (mii_phy_probe(dev, &sc->sis_miibus, 1150 sis_ifmedia_upd, sis_ifmedia_sts)) { 1151 device_printf(dev, "MII without any PHY!\n"); 1152 error = ENXIO; 1153 goto fail; 1154 } 1155 1156 /* 1157 * Call MI attach routine. 1158 */ 1159 ether_ifattach(ifp, eaddr, NULL); 1160 1161 #ifdef IFPOLL_ENABLE 1162 ifpoll_compat_setup(&sc->sis_npoll, NULL, NULL, device_get_unit(dev), 1163 ifp->if_serializer); 1164 #endif 1165 1166 /* 1167 * Tell the upper layer(s) we support long frames. 1168 */ 1169 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1170 1171 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sis_irq)); 1172 1173 error = bus_setup_intr(dev, sc->sis_irq, INTR_MPSAFE, 1174 sis_intr, sc, 1175 &sc->sis_intrhand, 1176 ifp->if_serializer); 1177 1178 if (error) { 1179 device_printf(dev, "couldn't set up irq\n"); 1180 ether_ifdetach(ifp); 1181 goto fail; 1182 } 1183 1184 fail: 1185 if (error) 1186 sis_detach(dev); 1187 1188 return(error); 1189 } 1190 1191 /* 1192 * Shutdown hardware and free up resources. It is called in both the error case 1193 * and the normal detach case so it needs to be careful about only freeing 1194 * resources that have actually been allocated. 1195 */ 1196 static int 1197 sis_detach(device_t dev) 1198 { 1199 struct sis_softc *sc = device_get_softc(dev); 1200 struct ifnet *ifp = &sc->arpcom.ac_if; 1201 1202 1203 if (device_is_attached(dev)) { 1204 lwkt_serialize_enter(ifp->if_serializer); 1205 sis_reset(sc); 1206 sis_stop(sc); 1207 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); 1208 lwkt_serialize_exit(ifp->if_serializer); 1209 1210 ether_ifdetach(ifp); 1211 } 1212 if (sc->sis_miibus) 1213 device_delete_child(dev, sc->sis_miibus); 1214 bus_generic_detach(dev); 1215 1216 if (sc->sis_irq) 1217 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); 1218 if (sc->sis_res) 1219 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); 1220 1221 sis_dma_free(dev); 1222 1223 return(0); 1224 } 1225 1226 /* 1227 * Initialize the transmit descriptors. 1228 */ 1229 static int 1230 sis_list_tx_init(struct sis_softc *sc) 1231 { 1232 struct sis_list_data *ld = &sc->sis_ldata; 1233 struct sis_chain_data *cd = &sc->sis_cdata; 1234 int i, nexti; 1235 1236 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1237 bus_addr_t paddr; 1238 1239 /* 1240 * Link the TX desc together 1241 */ 1242 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; 1243 paddr = ld->sis_tx_paddr + (nexti * sizeof(struct sis_desc)); 1244 ld->sis_tx_list[i].sis_next = paddr; 1245 } 1246 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; 1247 1248 return 0; 1249 } 1250 1251 /* 1252 * Initialize the RX descriptors and allocate mbufs for them. Note that 1253 * we arrange the descriptors in a closed ring, so that the last descriptor 1254 * points back to the first. 1255 */ 1256 static int 1257 sis_list_rx_init(struct sis_softc *sc) 1258 { 1259 struct sis_list_data *ld = &sc->sis_ldata; 1260 struct sis_chain_data *cd = &sc->sis_cdata; 1261 int i, error; 1262 1263 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1264 bus_addr_t paddr; 1265 int nexti; 1266 1267 error = sis_newbuf(sc, i, 1); 1268 if (error) 1269 return error; 1270 1271 /* 1272 * Link the RX desc together 1273 */ 1274 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; 1275 paddr = ld->sis_rx_paddr + (nexti * sizeof(struct sis_desc)); 1276 ld->sis_rx_list[i].sis_next = paddr; 1277 } 1278 cd->sis_rx_prod = 0; 1279 1280 return 0; 1281 } 1282 1283 /* 1284 * Initialize an RX descriptor and attach an MBUF cluster. 1285 */ 1286 static int 1287 sis_newbuf(struct sis_softc *sc, int idx, int init) 1288 { 1289 struct sis_chain_data *cd = &sc->sis_cdata; 1290 struct sis_rx_data *rd = &cd->sis_rx_data[idx]; 1291 bus_dma_segment_t seg; 1292 bus_dmamap_t map; 1293 struct mbuf *m; 1294 int nseg, error; 1295 1296 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 1297 if (m == NULL) { 1298 if (init) 1299 if_printf(&sc->arpcom.ac_if, "can't alloc RX mbuf\n"); 1300 return ENOBUFS; 1301 } 1302 m->m_len = m->m_pkthdr.len = MCLBYTES; 1303 1304 /* Try loading the mbuf into tmp DMA map */ 1305 error = bus_dmamap_load_mbuf_segment(cd->sis_rxbuf_tag, 1306 cd->sis_rx_tmpmap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT); 1307 if (error) { 1308 m_freem(m); 1309 if (init) 1310 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 1311 return error; 1312 } 1313 1314 /* Unload the currently loaded mbuf */ 1315 if (rd->sis_mbuf != NULL) { 1316 bus_dmamap_sync(cd->sis_rxbuf_tag, rd->sis_map, 1317 BUS_DMASYNC_POSTREAD); 1318 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map); 1319 } 1320 1321 /* Swap DMA maps */ 1322 map = cd->sis_rx_tmpmap; 1323 cd->sis_rx_tmpmap = rd->sis_map; 1324 rd->sis_map = map; 1325 1326 /* Save necessary information */ 1327 rd->sis_mbuf = m; 1328 rd->sis_paddr = seg.ds_addr; 1329 1330 sis_setup_rxdesc(sc, idx); 1331 return 0; 1332 } 1333 1334 static void 1335 sis_setup_rxdesc(struct sis_softc *sc, int idx) 1336 { 1337 struct sis_desc *c = &sc->sis_ldata.sis_rx_list[idx]; 1338 1339 /* Setup the RX desc */ 1340 c->sis_ctl = SIS_RXLEN; 1341 c->sis_ptr = sc->sis_cdata.sis_rx_data[idx].sis_paddr; 1342 } 1343 1344 /* 1345 * A frame has been uploaded: pass the resulting mbuf chain up to 1346 * the higher level protocols. 1347 */ 1348 static void 1349 sis_rxeof(struct sis_softc *sc) 1350 { 1351 struct ifnet *ifp = &sc->arpcom.ac_if; 1352 int i, total_len = 0; 1353 uint32_t rxstat; 1354 1355 i = sc->sis_cdata.sis_rx_prod; 1356 while (SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { 1357 struct sis_desc *cur_rx; 1358 struct sis_rx_data *rd; 1359 struct mbuf *m; 1360 int idx = i; 1361 1362 #ifdef IFPOLL_ENABLE 1363 if (ifp->if_flags & IFF_NPOLLING) { 1364 if (sc->rxcycles <= 0) 1365 break; 1366 sc->rxcycles--; 1367 } 1368 #endif /* IFPOLL_ENABLE */ 1369 1370 cur_rx = &sc->sis_ldata.sis_rx_list[idx]; 1371 rd = &sc->sis_cdata.sis_rx_data[idx]; 1372 1373 rxstat = cur_rx->sis_rxstat; 1374 total_len = SIS_RXBYTES(cur_rx); 1375 1376 m = rd->sis_mbuf; 1377 1378 SIS_INC(i, SIS_RX_LIST_CNT); 1379 1380 /* 1381 * If an error occurs, update stats, clear the 1382 * status word and leave the mbuf cluster in place: 1383 * it should simply get re-used next time this descriptor 1384 * comes up in the ring. 1385 */ 1386 if (!(rxstat & SIS_CMDSTS_PKT_OK)) { 1387 IFNET_STAT_INC(ifp, ierrors, 1); 1388 if (rxstat & SIS_RXSTAT_COLL) 1389 IFNET_STAT_INC(ifp, collisions, 1); 1390 sis_setup_rxdesc(sc, idx); 1391 continue; 1392 } 1393 1394 /* No errors; receive the packet. */ 1395 if (sis_newbuf(sc, idx, 0) == 0) { 1396 m->m_pkthdr.len = m->m_len = total_len; 1397 m->m_pkthdr.rcvif = ifp; 1398 } else { 1399 IFNET_STAT_INC(ifp, ierrors, 1); 1400 sis_setup_rxdesc(sc, idx); 1401 continue; 1402 } 1403 1404 IFNET_STAT_INC(ifp, ipackets, 1); 1405 ifp->if_input(ifp, m); 1406 } 1407 sc->sis_cdata.sis_rx_prod = i; 1408 } 1409 1410 static void 1411 sis_rxeoc(struct sis_softc *sc) 1412 { 1413 sis_rxeof(sc); 1414 sis_init(sc); 1415 } 1416 1417 /* 1418 * A frame was downloaded to the chip. It's safe for us to clean up 1419 * the list buffers. 1420 */ 1421 1422 static void 1423 sis_txeof(struct sis_softc *sc) 1424 { 1425 struct ifnet *ifp = &sc->arpcom.ac_if; 1426 struct sis_chain_data *cd = &sc->sis_cdata; 1427 uint32_t idx; 1428 1429 /* 1430 * Go through our tx list and free mbufs for those 1431 * frames that have been transmitted. 1432 */ 1433 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; 1434 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { 1435 struct sis_desc *cur_tx; 1436 struct sis_tx_data *td; 1437 1438 cur_tx = &sc->sis_ldata.sis_tx_list[idx]; 1439 td = &cd->sis_tx_data[idx]; 1440 1441 if (SIS_OWNDESC(cur_tx)) 1442 break; 1443 1444 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) 1445 continue; 1446 1447 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { 1448 IFNET_STAT_INC(ifp, oerrors, 1); 1449 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) 1450 IFNET_STAT_INC(ifp, collisions, 1); 1451 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) 1452 IFNET_STAT_INC(ifp, collisions, 1); 1453 } 1454 1455 IFNET_STAT_INC(ifp, collisions, 1456 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16); 1457 1458 IFNET_STAT_INC(ifp, opackets, 1); 1459 if (td->sis_mbuf != NULL) { 1460 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map); 1461 m_freem(td->sis_mbuf); 1462 td->sis_mbuf = NULL; 1463 } 1464 } 1465 1466 if (idx != sc->sis_cdata.sis_tx_cons) { 1467 /* we freed up some buffers */ 1468 sc->sis_cdata.sis_tx_cons = idx; 1469 } 1470 1471 if (cd->sis_tx_cnt == 0) 1472 ifp->if_timer = 0; 1473 if (!SIS_IS_OACTIVE(sc)) 1474 ifq_clr_oactive(&ifp->if_snd); 1475 } 1476 1477 static void 1478 sis_tick(void *xsc) 1479 { 1480 struct sis_softc *sc = xsc; 1481 struct mii_data *mii; 1482 struct ifnet *ifp = &sc->arpcom.ac_if; 1483 1484 lwkt_serialize_enter(ifp->if_serializer); 1485 1486 mii = device_get_softc(sc->sis_miibus); 1487 mii_tick(mii); 1488 1489 if (!sc->sis_link) { 1490 mii_pollstat(mii); 1491 if (mii->mii_media_status & IFM_ACTIVE && 1492 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1493 sc->sis_link++; 1494 if (!ifq_is_empty(&ifp->if_snd)) 1495 if_devstart(ifp); 1496 } 1497 1498 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1499 lwkt_serialize_exit(ifp->if_serializer); 1500 } 1501 1502 #ifdef IFPOLL_ENABLE 1503 1504 static void 1505 sis_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1506 { 1507 struct sis_softc *sc = ifp->if_softc; 1508 1509 ASSERT_SERIALIZED(ifp->if_serializer); 1510 1511 /* 1512 * On the sis, reading the status register also clears it. 1513 * So before returning to intr mode we must make sure that all 1514 * possible pending sources of interrupts have been served. 1515 * In practice this means run to completion the *eof routines, 1516 * and then call the interrupt routine 1517 */ 1518 sc->rxcycles = count; 1519 sis_rxeof(sc); 1520 sis_txeof(sc); 1521 if (!ifq_is_empty(&ifp->if_snd)) 1522 if_devstart(ifp); 1523 1524 if (sc->sis_npoll.ifpc_stcount-- == 0) { 1525 uint32_t status; 1526 1527 sc->sis_npoll.ifpc_stcount = sc->sis_npoll.ifpc_stfrac; 1528 1529 /* Reading the ISR register clears all interrupts. */ 1530 status = CSR_READ_4(sc, SIS_ISR); 1531 1532 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1533 sis_rxeoc(sc); 1534 1535 if (status & (SIS_ISR_RX_IDLE)) 1536 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1537 1538 if (status & SIS_ISR_SYSERR) { 1539 sis_reset(sc); 1540 sis_init(sc); 1541 } 1542 } 1543 } 1544 1545 static void 1546 sis_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1547 { 1548 struct sis_softc *sc = ifp->if_softc; 1549 1550 ASSERT_SERIALIZED(ifp->if_serializer); 1551 1552 if (info != NULL) { 1553 int cpuid = sc->sis_npoll.ifpc_cpuid; 1554 1555 info->ifpi_rx[cpuid].poll_func = sis_npoll_compat; 1556 info->ifpi_rx[cpuid].arg = NULL; 1557 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1558 1559 if (ifp->if_flags & IFF_RUNNING) { 1560 /* disable interrupts */ 1561 CSR_WRITE_4(sc, SIS_IER, 0); 1562 sc->sis_npoll.ifpc_stcount = 0; 1563 } 1564 ifq_set_cpuid(&ifp->if_snd, cpuid); 1565 } else { 1566 if (ifp->if_flags & IFF_RUNNING) { 1567 /* enable interrupts */ 1568 CSR_WRITE_4(sc, SIS_IER, 1); 1569 } 1570 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sis_irq)); 1571 } 1572 } 1573 1574 #endif /* IFPOLL_ENABLE */ 1575 1576 static void 1577 sis_intr(void *arg) 1578 { 1579 struct sis_softc *sc; 1580 struct ifnet *ifp; 1581 uint32_t status; 1582 1583 sc = arg; 1584 ifp = &sc->arpcom.ac_if; 1585 1586 /* Supress unwanted interrupts */ 1587 if (!(ifp->if_flags & IFF_UP)) { 1588 sis_stop(sc); 1589 return; 1590 } 1591 1592 /* Disable interrupts. */ 1593 CSR_WRITE_4(sc, SIS_IER, 0); 1594 1595 for (;;) { 1596 /* Reading the ISR register clears all interrupts. */ 1597 status = CSR_READ_4(sc, SIS_ISR); 1598 1599 if ((status & SIS_INTRS) == 0) 1600 break; 1601 1602 if (status & 1603 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | 1604 SIS_ISR_TX_IDLE) ) 1605 sis_txeof(sc); 1606 1607 if (status & 1608 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE)) 1609 sis_rxeof(sc); 1610 1611 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) 1612 sis_rxeoc(sc); 1613 1614 if (status & (SIS_ISR_RX_IDLE)) 1615 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1616 1617 if (status & SIS_ISR_SYSERR) { 1618 sis_reset(sc); 1619 sis_init(sc); 1620 } 1621 } 1622 1623 /* Re-enable interrupts. */ 1624 CSR_WRITE_4(sc, SIS_IER, 1); 1625 1626 if (!ifq_is_empty(&ifp->if_snd)) 1627 if_devstart(ifp); 1628 } 1629 1630 /* 1631 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1632 * pointers to the fragment pointers. 1633 */ 1634 static int 1635 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) 1636 { 1637 struct sis_chain_data *cd = &sc->sis_cdata; 1638 struct sis_list_data *ld = &sc->sis_ldata; 1639 bus_dma_segment_t segs[SIS_NSEGS]; 1640 bus_dmamap_t map; 1641 int frag, cur, maxsegs, nsegs, error, i; 1642 1643 maxsegs = SIS_TX_LIST_CNT - SIS_NSEGS_RESERVED - cd->sis_tx_cnt; 1644 KASSERT(maxsegs >= 1, ("not enough TX descs")); 1645 if (maxsegs > SIS_NSEGS) 1646 maxsegs = SIS_NSEGS; 1647 1648 map = cd->sis_tx_data[*txidx].sis_map; 1649 error = bus_dmamap_load_mbuf_defrag(cd->sis_txbuf_tag, map, m_head, 1650 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1651 if (error) { 1652 m_freem(*m_head); 1653 *m_head = NULL; 1654 return error; 1655 } 1656 bus_dmamap_sync(cd->sis_txbuf_tag, map, BUS_DMASYNC_PREWRITE); 1657 1658 cur = frag = *txidx; 1659 for (i = 0; i < nsegs; ++i) { 1660 struct sis_desc *f = &ld->sis_tx_list[frag]; 1661 1662 f->sis_ctl = SIS_CMDSTS_MORE | segs[i].ds_len; 1663 f->sis_ptr = segs[i].ds_addr; 1664 if (i != 0) 1665 f->sis_ctl |= SIS_CMDSTS_OWN; 1666 1667 cur = frag; 1668 SIS_INC(frag, SIS_TX_LIST_CNT); 1669 } 1670 ld->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; 1671 ld->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; 1672 1673 /* Swap DMA map */ 1674 cd->sis_tx_data[*txidx].sis_map = cd->sis_tx_data[cur].sis_map; 1675 cd->sis_tx_data[cur].sis_map = map; 1676 1677 cd->sis_tx_data[cur].sis_mbuf = *m_head; 1678 1679 cd->sis_tx_cnt += nsegs; 1680 *txidx = frag; 1681 1682 return 0; 1683 } 1684 1685 /* 1686 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1687 * to the mbuf data regions directly in the transmit lists. We also save a 1688 * copy of the pointers since the transmit list fragment pointers are 1689 * physical addresses. 1690 */ 1691 1692 static void 1693 sis_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1694 { 1695 struct sis_softc *sc = ifp->if_softc; 1696 int need_trans, error; 1697 uint32_t idx; 1698 1699 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1700 1701 if (!sc->sis_link) { 1702 ifq_purge(&ifp->if_snd); 1703 return; 1704 } 1705 1706 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1707 return; 1708 1709 idx = sc->sis_cdata.sis_tx_prod; 1710 need_trans = 0; 1711 1712 while (sc->sis_cdata.sis_tx_data[idx].sis_mbuf == NULL) { 1713 struct mbuf *m_head; 1714 1715 /* 1716 * If there's no way we can send any packets, return now. 1717 */ 1718 if (SIS_IS_OACTIVE(sc)) { 1719 ifq_set_oactive(&ifp->if_snd); 1720 break; 1721 } 1722 1723 m_head = ifq_dequeue(&ifp->if_snd); 1724 if (m_head == NULL) 1725 break; 1726 1727 error = sis_encap(sc, &m_head, &idx); 1728 if (error) { 1729 IFNET_STAT_INC(ifp, oerrors, 1); 1730 if (sc->sis_cdata.sis_tx_cnt == 0) { 1731 continue; 1732 } else { 1733 ifq_set_oactive(&ifp->if_snd); 1734 break; 1735 } 1736 } 1737 need_trans = 1; 1738 1739 /* 1740 * If there's a BPF listener, bounce a copy of this frame 1741 * to him. 1742 */ 1743 BPF_MTAP(ifp, m_head); 1744 } 1745 1746 if (!need_trans) 1747 return; 1748 1749 /* Transmit */ 1750 sc->sis_cdata.sis_tx_prod = idx; 1751 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 1752 1753 /* 1754 * Set a timeout in case the chip goes out to lunch. 1755 */ 1756 ifp->if_timer = 5; 1757 } 1758 1759 static void 1760 sis_init(void *xsc) 1761 { 1762 struct sis_softc *sc = xsc; 1763 struct ifnet *ifp = &sc->arpcom.ac_if; 1764 struct mii_data *mii; 1765 1766 /* 1767 * Cancel pending I/O and free all RX/TX buffers. 1768 */ 1769 sis_stop(sc); 1770 1771 mii = device_get_softc(sc->sis_miibus); 1772 1773 /* Set MAC address */ 1774 if (sc->sis_type == SIS_TYPE_83815) { 1775 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 1776 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1777 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1778 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 1779 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1780 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1781 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 1782 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1783 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1784 } else { 1785 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 1786 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1787 ((uint16_t *)sc->arpcom.ac_enaddr)[0]); 1788 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 1789 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1790 ((uint16_t *)sc->arpcom.ac_enaddr)[1]); 1791 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 1792 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 1793 ((uint16_t *)sc->arpcom.ac_enaddr)[2]); 1794 } 1795 1796 /* Init circular RX list. */ 1797 if (sis_list_rx_init(sc)) { 1798 if_printf(ifp, "initialization failed: " 1799 "no memory for rx buffers\n"); 1800 sis_stop(sc); 1801 return; 1802 } 1803 1804 /* 1805 * Init tx descriptors. 1806 */ 1807 sis_list_tx_init(sc); 1808 1809 /* 1810 * For the NatSemi chip, we have to explicitly enable the 1811 * reception of ARP frames, as well as turn on the 'perfect 1812 * match' filter where we store the station address, otherwise 1813 * we won't receive unicasts meant for this host. 1814 */ 1815 if (sc->sis_type == SIS_TYPE_83815) { 1816 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); 1817 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); 1818 } 1819 1820 /* If we want promiscuous mode, set the allframes bit. */ 1821 if (ifp->if_flags & IFF_PROMISC) 1822 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1823 else 1824 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); 1825 1826 /* 1827 * Set the capture broadcast bit to capture broadcast frames. 1828 */ 1829 if (ifp->if_flags & IFF_BROADCAST) 1830 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1831 else 1832 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); 1833 1834 /* 1835 * Load the multicast filter. 1836 */ 1837 if (sc->sis_type == SIS_TYPE_83815) 1838 sis_setmulti_ns(sc); 1839 else 1840 sis_setmulti_sis(sc); 1841 1842 /* Turn the receive filter on */ 1843 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 1844 1845 /* 1846 * Load the address of the RX and TX lists. 1847 */ 1848 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_ldata.sis_rx_paddr); 1849 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_ldata.sis_tx_paddr); 1850 1851 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 1852 * the PCI bus. When this bit is set, the Max DMA Burst Size 1853 * for TX/RX DMA should be no larger than 16 double words. 1854 */ 1855 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) 1856 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 1857 else 1858 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 1859 1860 /* Accept Long Packets for VLAN support */ 1861 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 1862 1863 /* Set TX configuration */ 1864 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 1865 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 1866 else 1867 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 1868 1869 /* Set full/half duplex mode. */ 1870 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1871 SIS_SETBIT(sc, SIS_TX_CFG, 1872 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1873 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1874 } else { 1875 SIS_CLRBIT(sc, SIS_TX_CFG, 1876 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); 1877 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 1878 } 1879 1880 /* 1881 * Enable interrupts. 1882 */ 1883 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 1884 #ifdef IFPOLL_ENABLE 1885 /* 1886 * ... only enable interrupts if we are not polling, make sure 1887 * they are off otherwise. 1888 */ 1889 if (ifp->if_flags & IFF_NPOLLING) { 1890 CSR_WRITE_4(sc, SIS_IER, 0); 1891 sc->sis_npoll.ifpc_stcount = 0; 1892 } else 1893 #endif /* IFPOLL_ENABLE */ 1894 CSR_WRITE_4(sc, SIS_IER, 1); 1895 1896 /* Enable receiver and transmitter. */ 1897 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 1898 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1899 1900 #ifdef notdef 1901 mii_mediachg(mii); 1902 #endif 1903 1904 /* 1905 * Page 75 of the DP83815 manual recommends the 1906 * following register settings "for optimum 1907 * performance." Note however that at least three 1908 * of the registers are listed as "reserved" in 1909 * the register map, so who knows what they do. 1910 */ 1911 if (sc->sis_type == SIS_TYPE_83815) { 1912 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 1913 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 1914 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 1915 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 1916 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 1917 } 1918 1919 ifp->if_flags |= IFF_RUNNING; 1920 ifq_clr_oactive(&ifp->if_snd); 1921 1922 callout_reset(&sc->sis_timer, hz, sis_tick, sc); 1923 } 1924 1925 /* 1926 * Set media options. 1927 */ 1928 static int 1929 sis_ifmedia_upd(struct ifnet *ifp) 1930 { 1931 struct sis_softc *sc; 1932 struct mii_data *mii; 1933 1934 sc = ifp->if_softc; 1935 1936 mii = device_get_softc(sc->sis_miibus); 1937 sc->sis_link = 0; 1938 if (mii->mii_instance) { 1939 struct mii_softc *miisc; 1940 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1941 mii_phy_reset(miisc); 1942 } 1943 mii_mediachg(mii); 1944 1945 return(0); 1946 } 1947 1948 /* 1949 * Report current media status. 1950 */ 1951 static void 1952 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1953 { 1954 struct sis_softc *sc; 1955 struct mii_data *mii; 1956 1957 sc = ifp->if_softc; 1958 1959 mii = device_get_softc(sc->sis_miibus); 1960 mii_pollstat(mii); 1961 ifmr->ifm_active = mii->mii_media_active; 1962 ifmr->ifm_status = mii->mii_media_status; 1963 } 1964 1965 static int 1966 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1967 { 1968 struct sis_softc *sc = ifp->if_softc; 1969 struct ifreq *ifr = (struct ifreq *) data; 1970 struct mii_data *mii; 1971 int error = 0; 1972 1973 switch(command) { 1974 case SIOCSIFFLAGS: 1975 if (ifp->if_flags & IFF_UP) { 1976 sis_init(sc); 1977 } else { 1978 if (ifp->if_flags & IFF_RUNNING) 1979 sis_stop(sc); 1980 } 1981 error = 0; 1982 break; 1983 case SIOCADDMULTI: 1984 case SIOCDELMULTI: 1985 if (sc->sis_type == SIS_TYPE_83815) 1986 sis_setmulti_ns(sc); 1987 else 1988 sis_setmulti_sis(sc); 1989 error = 0; 1990 break; 1991 case SIOCGIFMEDIA: 1992 case SIOCSIFMEDIA: 1993 mii = device_get_softc(sc->sis_miibus); 1994 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1995 break; 1996 default: 1997 error = ether_ioctl(ifp, command, data); 1998 break; 1999 } 2000 return(error); 2001 } 2002 2003 static void 2004 sis_watchdog(struct ifnet *ifp) 2005 { 2006 struct sis_softc *sc; 2007 2008 sc = ifp->if_softc; 2009 2010 IFNET_STAT_INC(ifp, oerrors, 1); 2011 if_printf(ifp, "watchdog timeout\n"); 2012 2013 sis_stop(sc); 2014 sis_reset(sc); 2015 sis_init(sc); 2016 2017 if (!ifq_is_empty(&ifp->if_snd)) 2018 if_devstart(ifp); 2019 } 2020 2021 /* 2022 * Stop the adapter and free any mbufs allocated to the 2023 * RX and TX lists. 2024 */ 2025 static void 2026 sis_stop(struct sis_softc *sc) 2027 { 2028 struct ifnet *ifp = &sc->arpcom.ac_if; 2029 struct sis_list_data *ld = &sc->sis_ldata; 2030 struct sis_chain_data *cd = &sc->sis_cdata; 2031 int i; 2032 2033 callout_stop(&sc->sis_timer); 2034 2035 ifp->if_flags &= ~IFF_RUNNING; 2036 ifq_clr_oactive(&ifp->if_snd); 2037 ifp->if_timer = 0; 2038 2039 CSR_WRITE_4(sc, SIS_IER, 0); 2040 CSR_WRITE_4(sc, SIS_IMR, 0); 2041 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2042 DELAY(1000); 2043 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2044 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2045 2046 sc->sis_link = 0; 2047 2048 /* 2049 * Free data in the RX lists. 2050 */ 2051 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2052 struct sis_rx_data *rd = &cd->sis_rx_data[i]; 2053 2054 if (rd->sis_mbuf != NULL) { 2055 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map); 2056 m_freem(rd->sis_mbuf); 2057 rd->sis_mbuf = NULL; 2058 } 2059 } 2060 bzero(ld->sis_rx_list, SIS_RX_LIST_SZ); 2061 2062 /* 2063 * Free the TX list buffers. 2064 */ 2065 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2066 struct sis_tx_data *td = &cd->sis_tx_data[i]; 2067 2068 if (td->sis_mbuf != NULL) { 2069 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map); 2070 m_freem(td->sis_mbuf); 2071 td->sis_mbuf = NULL; 2072 } 2073 } 2074 bzero(ld->sis_tx_list, SIS_TX_LIST_SZ); 2075 } 2076 2077 /* 2078 * Stop all chip I/O so that the kernel's probe routines don't 2079 * get confused by errant DMAs when rebooting. 2080 */ 2081 static void 2082 sis_shutdown(device_t dev) 2083 { 2084 struct sis_softc *sc; 2085 struct ifnet *ifp; 2086 2087 sc = device_get_softc(dev); 2088 ifp = &sc->arpcom.ac_if; 2089 lwkt_serialize_enter(ifp->if_serializer); 2090 sis_reset(sc); 2091 sis_stop(sc); 2092 lwkt_serialize_exit(ifp->if_serializer); 2093 } 2094 2095 static int 2096 sis_dma_alloc(device_t dev) 2097 { 2098 struct sis_softc *sc = device_get_softc(dev); 2099 struct sis_chain_data *cd = &sc->sis_cdata; 2100 struct sis_list_data *ld = &sc->sis_ldata; 2101 int i, error; 2102 2103 /* Create top level DMA tag */ 2104 error = bus_dma_tag_create(NULL, /* parent */ 2105 1, 0, /* alignment, boundary */ 2106 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2107 BUS_SPACE_MAXADDR, /* highaddr */ 2108 NULL, NULL, /* filter, filterarg */ 2109 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2110 0, /* nsegments */ 2111 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2112 0, /* flags */ 2113 &sc->sis_parent_tag); 2114 if (error) { 2115 device_printf(dev, "could not create parent DMA tag\n"); 2116 return error; 2117 } 2118 2119 /* Allocate RX ring */ 2120 ld->sis_rx_list = bus_dmamem_coherent_any(sc->sis_parent_tag, 2121 SIS_RING_ALIGN, SIS_RX_LIST_SZ, 2122 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2123 &ld->sis_rx_tag, &ld->sis_rx_dmamap, 2124 &ld->sis_rx_paddr); 2125 if (ld->sis_rx_list == NULL) { 2126 device_printf(dev, "could not allocate RX ring\n"); 2127 return ENOMEM; 2128 } 2129 2130 /* Allocate TX ring */ 2131 ld->sis_tx_list = bus_dmamem_coherent_any(sc->sis_parent_tag, 2132 SIS_RING_ALIGN, SIS_TX_LIST_SZ, 2133 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2134 &ld->sis_tx_tag, &ld->sis_tx_dmamap, 2135 &ld->sis_tx_paddr); 2136 if (ld->sis_tx_list == NULL) { 2137 device_printf(dev, "could not allocate TX ring\n"); 2138 return ENOMEM; 2139 } 2140 2141 /* Create DMA tag for TX mbuf */ 2142 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */ 2143 1, 0, /* alignment, boundary */ 2144 BUS_SPACE_MAXADDR, /* lowaddr */ 2145 BUS_SPACE_MAXADDR, /* highaddr */ 2146 NULL, NULL, /* filter, filterarg */ 2147 MCLBYTES, /* maxsize */ 2148 SIS_NSEGS, /* nsegments */ 2149 MCLBYTES, /* maxsegsize */ 2150 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */ 2151 &cd->sis_txbuf_tag); 2152 if (error) { 2153 device_printf(dev, "could not create TX buf DMA tag\n"); 2154 return error; 2155 } 2156 2157 /* Create DMA maps for TX mbufs */ 2158 for (i = 0; i < SIS_TX_LIST_CNT; ++i) { 2159 error = bus_dmamap_create(cd->sis_txbuf_tag, BUS_DMA_WAITOK, 2160 &cd->sis_tx_data[i].sis_map); 2161 if (error) { 2162 int j; 2163 2164 for (j = 0; j < i; ++j) { 2165 bus_dmamap_destroy(cd->sis_txbuf_tag, 2166 cd->sis_tx_data[j].sis_map); 2167 } 2168 bus_dma_tag_destroy(cd->sis_txbuf_tag); 2169 cd->sis_txbuf_tag = NULL; 2170 2171 device_printf(dev, "could not create %dth " 2172 "TX buf DMA map\n", i); 2173 return error; 2174 } 2175 } 2176 2177 /* Create DMA tag for RX mbuf */ 2178 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */ 2179 SIS_RXBUF_ALIGN, 0, /* alignment, boundary */ 2180 BUS_SPACE_MAXADDR, /* lowaddr */ 2181 BUS_SPACE_MAXADDR, /* highaddr */ 2182 NULL, NULL, /* filter, filterarg */ 2183 MCLBYTES, /* maxsize */ 2184 1, /* nsegments */ 2185 MCLBYTES, /* maxsegsize */ 2186 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 2187 BUS_DMA_ALIGNED, /* flags */ 2188 &cd->sis_rxbuf_tag); 2189 if (error) { 2190 device_printf(dev, "could not create RX buf DMA tag\n"); 2191 return error; 2192 } 2193 2194 /* Create tmp DMA map for loading RX mbuf */ 2195 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK, 2196 &cd->sis_rx_tmpmap); 2197 if (error) { 2198 device_printf(dev, "could not create RX buf tmp DMA map\n"); 2199 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2200 cd->sis_rxbuf_tag = NULL; 2201 return error; 2202 } 2203 2204 /* Create DMA maps for RX mbufs */ 2205 for (i = 0; i < SIS_RX_LIST_CNT; ++i) { 2206 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK, 2207 &cd->sis_rx_data[i].sis_map); 2208 if (error) { 2209 int j; 2210 2211 for (j = 0; j < i; ++j) { 2212 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2213 cd->sis_rx_data[j].sis_map); 2214 } 2215 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2216 cd->sis_rx_tmpmap); 2217 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2218 cd->sis_rxbuf_tag = NULL; 2219 2220 device_printf(dev, "could not create %dth " 2221 "RX buf DMA map\n", i); 2222 return error; 2223 } 2224 } 2225 return 0; 2226 } 2227 2228 static void 2229 sis_dma_free(device_t dev) 2230 { 2231 struct sis_softc *sc = device_get_softc(dev); 2232 struct sis_list_data *ld = &sc->sis_ldata; 2233 struct sis_chain_data *cd = &sc->sis_cdata; 2234 int i; 2235 2236 /* Free TX ring */ 2237 if (ld->sis_tx_list != NULL) { 2238 bus_dmamap_unload(ld->sis_tx_tag, ld->sis_tx_dmamap); 2239 bus_dmamem_free(ld->sis_tx_tag, ld->sis_tx_list, 2240 ld->sis_tx_dmamap); 2241 bus_dma_tag_destroy(ld->sis_tx_tag); 2242 } 2243 2244 /* Free RX ring */ 2245 if (ld->sis_rx_list != NULL) { 2246 bus_dmamap_unload(ld->sis_rx_tag, ld->sis_rx_dmamap); 2247 bus_dmamem_free(ld->sis_rx_tag, ld->sis_rx_list, 2248 ld->sis_rx_dmamap); 2249 bus_dma_tag_destroy(ld->sis_rx_tag); 2250 } 2251 2252 /* Destroy DMA stuffs for TX mbufs */ 2253 if (cd->sis_txbuf_tag != NULL) { 2254 for (i = 0; i < SIS_TX_LIST_CNT; ++i) { 2255 KKASSERT(cd->sis_tx_data[i].sis_mbuf == NULL); 2256 bus_dmamap_destroy(cd->sis_txbuf_tag, 2257 cd->sis_tx_data[i].sis_map); 2258 } 2259 bus_dma_tag_destroy(cd->sis_txbuf_tag); 2260 } 2261 2262 /* Destroy DMA stuffs for RX mbufs */ 2263 if (cd->sis_rxbuf_tag != NULL) { 2264 for (i = 0; i < SIS_RX_LIST_CNT; ++i) { 2265 KKASSERT(cd->sis_rx_data[i].sis_mbuf == NULL); 2266 bus_dmamap_destroy(cd->sis_rxbuf_tag, 2267 cd->sis_rx_data[i].sis_map); 2268 } 2269 bus_dmamap_destroy(cd->sis_rxbuf_tag, cd->sis_rx_tmpmap); 2270 bus_dma_tag_destroy(cd->sis_rxbuf_tag); 2271 } 2272 }
Cache object: d7ff87ad61f66c20e0905fa574e28afd
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