The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/dev/netif/stge/if_stge.c

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    1 /*      $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $    */
    2 /*      $FreeBSD: src/sys/dev/stge/if_stge.c,v 1.2 2006/08/12 01:21:36 yongari Exp $    */
    3 
    4 /*-
    5  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 /*
   41  * Device driver for the Sundance Tech. TC9021 10/100/1000
   42  * Ethernet controller.
   43  */
   44 
   45 #include "opt_ifpoll.h"
   46 
   47 #include <sys/param.h>
   48 #include <sys/bus.h>
   49 #include <sys/endian.h>
   50 #include <sys/kernel.h>
   51 #include <sys/interrupt.h>
   52 #include <sys/malloc.h>
   53 #include <sys/mbuf.h>
   54 #include <sys/module.h>
   55 #include <sys/rman.h>
   56 #include <sys/serialize.h>
   57 #include <sys/socket.h>
   58 #include <sys/sockio.h>
   59 #include <sys/sysctl.h>
   60 
   61 #include <net/bpf.h>
   62 #include <net/ethernet.h>
   63 #include <net/if.h>
   64 #include <net/if_arp.h>
   65 #include <net/if_dl.h>
   66 #include <net/if_media.h>
   67 #include <net/if_poll.h>
   68 #include <net/if_types.h>
   69 #include <net/ifq_var.h>
   70 #include <net/vlan/if_vlan_var.h>
   71 #include <net/vlan/if_vlan_ether.h>
   72 
   73 #include <dev/netif/mii_layer/mii.h>
   74 #include <dev/netif/mii_layer/miivar.h>
   75 
   76 #include <bus/pci/pcireg.h>
   77 #include <bus/pci/pcivar.h>
   78 
   79 #include "if_stgereg.h"
   80 #include "if_stgevar.h"
   81 
   82 #define STGE_CSUM_FEATURES      (CSUM_IP | CSUM_TCP | CSUM_UDP)
   83 
   84 /* "device miibus" required.  See GENERIC if you get errors here. */
   85 #include "miibus_if.h"
   86 
   87 /*
   88  * Devices supported by this driver.
   89  */
   90 static struct stge_product {
   91         uint16_t        stge_vendorid;
   92         uint16_t        stge_deviceid;
   93         const char      *stge_name;
   94 } stge_products[] = {
   95         { VENDOR_SUNDANCETI,    DEVICEID_SUNDANCETI_ST1023,
   96           "Sundance ST-1023 Gigabit Ethernet" },
   97 
   98         { VENDOR_SUNDANCETI,    DEVICEID_SUNDANCETI_ST2021,
   99           "Sundance ST-2021 Gigabit Ethernet" },
  100 
  101         { VENDOR_TAMARACK,      DEVICEID_TAMARACK_TC9021,
  102           "Tamarack TC9021 Gigabit Ethernet" },
  103 
  104         { VENDOR_TAMARACK,      DEVICEID_TAMARACK_TC9021_ALT,
  105           "Tamarack TC9021 Gigabit Ethernet" },
  106 
  107         /*
  108          * The Sundance sample boards use the Sundance vendor ID,
  109          * but the Tamarack product ID.
  110          */
  111         { VENDOR_SUNDANCETI,    DEVICEID_TAMARACK_TC9021,
  112           "Sundance TC9021 Gigabit Ethernet" },
  113 
  114         { VENDOR_SUNDANCETI,    DEVICEID_TAMARACK_TC9021_ALT,
  115           "Sundance TC9021 Gigabit Ethernet" },
  116 
  117         { VENDOR_DLINK,         DEVICEID_DLINK_DL2000,
  118           "D-Link DL-2000 Gigabit Ethernet" },
  119 
  120         { VENDOR_ANTARES,       DEVICEID_ANTARES_TC9021,
  121           "Antares Gigabit Ethernet" },
  122 
  123         { 0, 0, NULL }
  124 };
  125 
  126 static int      stge_probe(device_t);
  127 static int      stge_attach(device_t);
  128 static int      stge_detach(device_t);
  129 static void     stge_shutdown(device_t);
  130 static int      stge_suspend(device_t);
  131 static int      stge_resume(device_t);
  132 
  133 static int      stge_encap(struct stge_softc *, struct mbuf **);
  134 static void     stge_start(struct ifnet *, struct ifaltq_subque *);
  135 static void     stge_watchdog(struct ifnet *);
  136 static int      stge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
  137 static void     stge_init(void *);
  138 static void     stge_vlan_setup(struct stge_softc *);
  139 static void     stge_stop(struct stge_softc *);
  140 static void     stge_start_tx(struct stge_softc *);
  141 static void     stge_start_rx(struct stge_softc *);
  142 static void     stge_stop_tx(struct stge_softc *);
  143 static void     stge_stop_rx(struct stge_softc *);
  144 
  145 static void     stge_reset(struct stge_softc *, uint32_t);
  146 static int      stge_eeprom_wait(struct stge_softc *);
  147 static void     stge_read_eeprom(struct stge_softc *, int, uint16_t *);
  148 static void     stge_tick(void *);
  149 static void     stge_stats_update(struct stge_softc *);
  150 static void     stge_set_filter(struct stge_softc *);
  151 static void     stge_set_multi(struct stge_softc *);
  152 
  153 static void     stge_link(struct stge_softc *);
  154 static void     stge_intr(void *);
  155 static __inline int stge_tx_error(struct stge_softc *);
  156 static void     stge_txeof(struct stge_softc *);
  157 static void     stge_rxeof(struct stge_softc *, int);
  158 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
  159 static int      stge_newbuf(struct stge_softc *, int, int);
  160 #ifndef __i386__
  161 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
  162 #endif
  163 
  164 static void     stge_mii_sync(struct stge_softc *);
  165 static void     stge_mii_send(struct stge_softc *, uint32_t, int);
  166 static int      stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *);
  167 static int      stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *);
  168 static int      stge_miibus_readreg(device_t, int, int);
  169 static int      stge_miibus_writereg(device_t, int, int, int);
  170 static void     stge_miibus_statchg(device_t);
  171 static int      stge_mediachange(struct ifnet *);
  172 static void     stge_mediastatus(struct ifnet *, struct ifmediareq *);
  173 
  174 static int      stge_dma_alloc(struct stge_softc *);
  175 static void     stge_dma_free(struct stge_softc *);
  176 static void     stge_dma_wait(struct stge_softc *);
  177 static void     stge_init_tx_ring(struct stge_softc *);
  178 static int      stge_init_rx_ring(struct stge_softc *);
  179 #ifdef IFPOLL_ENABLE
  180 static void     stge_npoll(struct ifnet *, struct ifpoll_info *);
  181 static void     stge_npoll_compat(struct ifnet *, void *, int);
  182 #endif
  183 
  184 static int      sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
  185 static int      sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
  186 
  187 static device_method_t stge_methods[] = {
  188         /* Device interface */
  189         DEVMETHOD(device_probe,         stge_probe),
  190         DEVMETHOD(device_attach,        stge_attach),
  191         DEVMETHOD(device_detach,        stge_detach),
  192         DEVMETHOD(device_shutdown,      stge_shutdown),
  193         DEVMETHOD(device_suspend,       stge_suspend),
  194         DEVMETHOD(device_resume,        stge_resume),
  195 
  196         /* MII interface */
  197         DEVMETHOD(miibus_readreg,       stge_miibus_readreg),
  198         DEVMETHOD(miibus_writereg,      stge_miibus_writereg),
  199         DEVMETHOD(miibus_statchg,       stge_miibus_statchg),
  200 
  201         DEVMETHOD_END
  202 
  203 };
  204 
  205 static driver_t stge_driver = {
  206         "stge",
  207         stge_methods,
  208         sizeof(struct stge_softc)
  209 };
  210 
  211 static devclass_t stge_devclass;
  212 
  213 DECLARE_DUMMY_MODULE(if_stge);
  214 MODULE_DEPEND(if_stge, miibus, 1, 1, 1);
  215 DRIVER_MODULE(if_stge, pci, stge_driver, stge_devclass, NULL, NULL);
  216 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, NULL, NULL);
  217 
  218 #define MII_SET(x)      \
  219         CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
  220 #define MII_CLR(x)      \
  221         CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
  222 
  223 /*
  224  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  225  */
  226 static void
  227 stge_mii_sync(struct stge_softc *sc)
  228 {
  229         int i;
  230 
  231         MII_SET(PC_MgmtDir | PC_MgmtData);
  232 
  233         for (i = 0; i < 32; i++) {
  234                 MII_SET(PC_MgmtClk);
  235                 DELAY(1);
  236                 MII_CLR(PC_MgmtClk);
  237                 DELAY(1);
  238         }
  239 }
  240 
  241 /*
  242  * Clock a series of bits through the MII.
  243  */
  244 static void
  245 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt)
  246 {
  247         int i;
  248 
  249         MII_CLR(PC_MgmtClk);
  250 
  251         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  252                 if (bits & i)
  253                         MII_SET(PC_MgmtData);
  254                 else
  255                         MII_CLR(PC_MgmtData);
  256                 DELAY(1);
  257                 MII_CLR(PC_MgmtClk);
  258                 DELAY(1);
  259                 MII_SET(PC_MgmtClk);
  260         }
  261 }
  262 
  263 /*
  264  * Read an PHY register through the MII.
  265  */
  266 static int
  267 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame)
  268 {
  269         int i, ack;
  270 
  271         /*
  272          * Set up frame for RX.
  273          */
  274         frame->mii_stdelim = STGE_MII_STARTDELIM;
  275         frame->mii_opcode = STGE_MII_READOP;
  276         frame->mii_turnaround = 0;
  277         frame->mii_data = 0;
  278 
  279         CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl);
  280         /*
  281          * Turn on data xmit.
  282          */
  283         MII_SET(PC_MgmtDir);
  284 
  285         stge_mii_sync(sc);
  286 
  287         /*
  288          * Send command/address info.
  289          */
  290         stge_mii_send(sc, frame->mii_stdelim, 2);
  291         stge_mii_send(sc, frame->mii_opcode, 2);
  292         stge_mii_send(sc, frame->mii_phyaddr, 5);
  293         stge_mii_send(sc, frame->mii_regaddr, 5);
  294 
  295         /* Turn off xmit. */
  296         MII_CLR(PC_MgmtDir);
  297 
  298         /* Idle bit */
  299         MII_CLR((PC_MgmtClk | PC_MgmtData));
  300         DELAY(1);
  301         MII_SET(PC_MgmtClk);
  302         DELAY(1);
  303 
  304         /* Check for ack */
  305         MII_CLR(PC_MgmtClk);
  306         DELAY(1);
  307         ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData;
  308         MII_SET(PC_MgmtClk);
  309         DELAY(1);
  310 
  311         /*
  312          * Now try reading data bits. If the ack failed, we still
  313          * need to clock through 16 cycles to keep the PHY(s) in sync.
  314          */
  315         if (ack) {
  316                 for(i = 0; i < 16; i++) {
  317                         MII_CLR(PC_MgmtClk);
  318                         DELAY(1);
  319                         MII_SET(PC_MgmtClk);
  320                         DELAY(1);
  321                 }
  322                 goto fail;
  323         }
  324 
  325         for (i = 0x8000; i; i >>= 1) {
  326                 MII_CLR(PC_MgmtClk);
  327                 DELAY(1);
  328                 if (!ack) {
  329                         if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData)
  330                                 frame->mii_data |= i;
  331                         DELAY(1);
  332                 }
  333                 MII_SET(PC_MgmtClk);
  334                 DELAY(1);
  335         }
  336 
  337 fail:
  338         MII_CLR(PC_MgmtClk);
  339         DELAY(1);
  340         MII_SET(PC_MgmtClk);
  341         DELAY(1);
  342 
  343         if (ack)
  344                 return(1);
  345         return(0);
  346 }
  347 
  348 /*
  349  * Write to a PHY register through the MII.
  350  */
  351 static int
  352 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame)
  353 {
  354 
  355         /*
  356          * Set up frame for TX.
  357          */
  358         frame->mii_stdelim = STGE_MII_STARTDELIM;
  359         frame->mii_opcode = STGE_MII_WRITEOP;
  360         frame->mii_turnaround = STGE_MII_TURNAROUND;
  361 
  362         /*
  363          * Turn on data output.
  364          */
  365         MII_SET(PC_MgmtDir);
  366 
  367         stge_mii_sync(sc);
  368 
  369         stge_mii_send(sc, frame->mii_stdelim, 2);
  370         stge_mii_send(sc, frame->mii_opcode, 2);
  371         stge_mii_send(sc, frame->mii_phyaddr, 5);
  372         stge_mii_send(sc, frame->mii_regaddr, 5);
  373         stge_mii_send(sc, frame->mii_turnaround, 2);
  374         stge_mii_send(sc, frame->mii_data, 16);
  375 
  376         /* Idle bit. */
  377         MII_SET(PC_MgmtClk);
  378         DELAY(1);
  379         MII_CLR(PC_MgmtClk);
  380         DELAY(1);
  381 
  382         /*
  383          * Turn off xmit.
  384          */
  385         MII_CLR(PC_MgmtDir);
  386 
  387         return(0);
  388 }
  389 
  390 /*
  391  * sc_miibus_readreg:   [mii interface function]
  392  *
  393  *      Read a PHY register on the MII of the TC9021.
  394  */
  395 static int
  396 stge_miibus_readreg(device_t dev, int phy, int reg)
  397 {
  398         struct stge_softc *sc;
  399         struct stge_mii_frame frame;
  400         int error;
  401 
  402         sc = device_get_softc(dev);
  403 
  404         if (reg == STGE_PhyCtrl) {
  405                 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
  406                 error = CSR_READ_1(sc, STGE_PhyCtrl);
  407                 return (error);
  408         }
  409         bzero(&frame, sizeof(frame));
  410         frame.mii_phyaddr = phy;
  411         frame.mii_regaddr = reg;
  412 
  413         error = stge_mii_readreg(sc, &frame);
  414 
  415         if (error != 0) {
  416                 /* Don't show errors for PHY probe request */
  417                 if (reg != 1)
  418                         device_printf(sc->sc_dev, "phy read fail\n");
  419                 return (0);
  420         }
  421         return (frame.mii_data);
  422 }
  423 
  424 /*
  425  * stge_miibus_writereg:        [mii interface function]
  426  *
  427  *      Write a PHY register on the MII of the TC9021.
  428  */
  429 static int
  430 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
  431 {
  432         struct stge_softc *sc;
  433         struct stge_mii_frame frame;
  434         int error;
  435 
  436         sc = device_get_softc(dev);
  437 
  438         bzero(&frame, sizeof(frame));
  439         frame.mii_phyaddr = phy;
  440         frame.mii_regaddr = reg;
  441         frame.mii_data = val;
  442 
  443         error = stge_mii_writereg(sc, &frame);
  444 
  445         if (error != 0)
  446                 device_printf(sc->sc_dev, "phy write fail\n");
  447         return (0);
  448 }
  449 
  450 /*
  451  * stge_miibus_statchg: [mii interface function]
  452  *
  453  *      Callback from MII layer when media changes.
  454  */
  455 static void
  456 stge_miibus_statchg(device_t dev)
  457 {
  458         struct stge_softc *sc;
  459         struct mii_data *mii;
  460 
  461         sc = device_get_softc(dev);
  462         mii = device_get_softc(sc->sc_miibus);
  463 
  464         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)
  465                 return;
  466 
  467         sc->sc_MACCtrl = 0;
  468         if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
  469                 sc->sc_MACCtrl |= MC_DuplexSelect;
  470         if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0)
  471                 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
  472         if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0)
  473                 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
  474 
  475         stge_link(sc);
  476 }
  477 
  478 /*
  479  * stge_mediastatus:    [ifmedia interface function]
  480  *
  481  *      Get the current interface media status.
  482  */
  483 static void
  484 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
  485 {
  486         struct stge_softc *sc;
  487         struct mii_data *mii;
  488 
  489         sc = ifp->if_softc;
  490         mii = device_get_softc(sc->sc_miibus);
  491 
  492         mii_pollstat(mii);
  493         ifmr->ifm_status = mii->mii_media_status;
  494         ifmr->ifm_active = mii->mii_media_active;
  495 }
  496 
  497 /*
  498  * stge_mediachange:    [ifmedia interface function]
  499  *
  500  *      Set hardware to newly-selected media.
  501  */
  502 static int
  503 stge_mediachange(struct ifnet *ifp)
  504 {
  505         struct stge_softc *sc;
  506         struct mii_data *mii;
  507 
  508         sc = ifp->if_softc;
  509         mii = device_get_softc(sc->sc_miibus);
  510         mii_mediachg(mii);
  511 
  512         return (0);
  513 }
  514 
  515 static int
  516 stge_eeprom_wait(struct stge_softc *sc)
  517 {
  518         int i;
  519 
  520         for (i = 0; i < STGE_TIMEOUT; i++) {
  521                 DELAY(1000);
  522                 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
  523                         return (0);
  524         }
  525         return (1);
  526 }
  527 
  528 /*
  529  * stge_read_eeprom:
  530  *
  531  *      Read data from the serial EEPROM.
  532  */
  533 static void
  534 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
  535 {
  536 
  537         if (stge_eeprom_wait(sc))
  538                 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
  539 
  540         CSR_WRITE_2(sc, STGE_EepromCtrl,
  541             EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
  542         if (stge_eeprom_wait(sc))
  543                 device_printf(sc->sc_dev, "EEPROM read timed out\n");
  544         *data = CSR_READ_2(sc, STGE_EepromData);
  545 }
  546 
  547 
  548 static int
  549 stge_probe(device_t dev)
  550 {
  551         struct stge_product *sp;
  552         uint16_t vendor, devid;
  553 
  554         vendor = pci_get_vendor(dev);
  555         devid = pci_get_device(dev);
  556         
  557         for (sp = stge_products; sp->stge_name != NULL; sp++) {
  558                 if (vendor == sp->stge_vendorid &&
  559                     devid == sp->stge_deviceid) {
  560                         device_set_desc(dev, sp->stge_name);
  561                         return (0);
  562                 }
  563         }
  564 
  565         return (ENXIO);
  566 }
  567 
  568 static int
  569 stge_attach(device_t dev)
  570 {
  571         struct stge_softc *sc;
  572         struct ifnet *ifp;
  573         uint8_t enaddr[ETHER_ADDR_LEN];
  574         int error, i;
  575         uint16_t cmd;
  576         uint32_t val;
  577 
  578         error = 0;
  579         sc = device_get_softc(dev);
  580         sc->sc_dev = dev;
  581         ifp = &sc->arpcom.ac_if;
  582 
  583         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
  584 
  585         callout_init(&sc->sc_tick_ch);
  586 
  587 #ifndef BURN_BRIDGES
  588         /*
  589          * Handle power management nonsense.
  590          */
  591         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
  592                 uint32_t iobase, membase, irq;
  593 
  594                 /* Save important PCI config data. */
  595                 iobase = pci_read_config(dev, STGE_PCIR_LOIO, 4);
  596                 membase = pci_read_config(dev, STGE_PCIR_LOMEM, 4);
  597                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
  598 
  599                 /* Reset the power state. */
  600                 device_printf(dev, "chip is in D%d power mode "
  601                               "-- setting to D0\n", pci_get_powerstate(dev));
  602 
  603                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
  604 
  605                 /* Restore PCI config data. */
  606                 pci_write_config(dev, STGE_PCIR_LOIO, iobase, 4);
  607                 pci_write_config(dev, STGE_PCIR_LOMEM, membase, 4);
  608                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
  609         }
  610 #endif
  611 
  612         /*
  613          * Map the device.
  614          */
  615         pci_enable_busmaster(dev);
  616         cmd = pci_read_config(dev, PCIR_COMMAND, 2);
  617         val = pci_read_config(dev, STGE_PCIR_LOMEM, 4);
  618 
  619         if ((val & 0x01) != 0) {
  620                 sc->sc_res_rid = STGE_PCIR_LOMEM;
  621                 sc->sc_res_type = SYS_RES_MEMORY;
  622         } else {
  623                 sc->sc_res_rid = STGE_PCIR_LOIO;
  624                 sc->sc_res_type = SYS_RES_IOPORT;
  625 
  626                 val = pci_read_config(dev, sc->sc_res_rid, 4);
  627                 if ((val & 0x01) == 0) {
  628                         device_printf(dev, "couldn't locate IO BAR\n");
  629                         return ENXIO;
  630                 }
  631         }
  632 
  633         sc->sc_res = bus_alloc_resource_any(dev, sc->sc_res_type,
  634                                             &sc->sc_res_rid, RF_ACTIVE);
  635         if (sc->sc_res == NULL) {
  636                 device_printf(dev, "couldn't allocate resource\n");
  637                 return ENXIO;
  638         }
  639         sc->sc_btag = rman_get_bustag(sc->sc_res);
  640         sc->sc_bhandle = rman_get_bushandle(sc->sc_res);
  641 
  642         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  643                                             &sc->sc_irq_rid,
  644                                             RF_ACTIVE | RF_SHAREABLE);
  645         if (sc->sc_irq == NULL) {
  646                 device_printf(dev, "couldn't allocate IRQ\n");
  647                 error = ENXIO;
  648                 goto fail;
  649         }
  650 
  651         sc->sc_rev = pci_get_revid(dev);
  652 
  653         sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
  654         sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
  655 
  656         sysctl_ctx_init(&sc->sc_sysctl_ctx);
  657         sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
  658                                              SYSCTL_STATIC_CHILDREN(_hw),
  659                                              OID_AUTO,
  660                                              device_get_nameunit(dev),
  661                                              CTLFLAG_RD, 0, "");
  662         if (sc->sc_sysctl_tree == NULL) {
  663                 device_printf(dev, "can't add sysctl node\n");
  664                 error = ENXIO;
  665                 goto fail;
  666         }
  667 
  668         SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
  669             SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
  670             "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
  671             sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
  672 
  673         SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
  674             SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
  675             "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
  676             sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
  677 
  678         error = stge_dma_alloc(sc);
  679         if (error != 0)
  680                 goto fail;
  681 
  682         /*
  683          * Determine if we're copper or fiber.  It affects how we
  684          * reset the card.
  685          */
  686         if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
  687                 sc->sc_usefiber = 1;
  688         else
  689                 sc->sc_usefiber = 0;
  690 
  691         /* Load LED configuration from EEPROM. */
  692         stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
  693 
  694         /*
  695          * Reset the chip to a known state.
  696          */
  697         stge_reset(sc, STGE_RESET_FULL);
  698 
  699         /*
  700          * Reading the station address from the EEPROM doesn't seem
  701          * to work, at least on my sample boards.  Instead, since
  702          * the reset sequence does AutoInit, read it from the station
  703          * address registers. For Sundance 1023 you can only read it
  704          * from EEPROM.
  705          */
  706         if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
  707                 uint16_t v;
  708 
  709                 v = CSR_READ_2(sc, STGE_StationAddress0);
  710                 enaddr[0] = v & 0xff;
  711                 enaddr[1] = v >> 8;
  712                 v = CSR_READ_2(sc, STGE_StationAddress1);
  713                 enaddr[2] = v & 0xff;
  714                 enaddr[3] = v >> 8;
  715                 v = CSR_READ_2(sc, STGE_StationAddress2);
  716                 enaddr[4] = v & 0xff;
  717                 enaddr[5] = v >> 8;
  718                 sc->sc_stge1023 = 0;
  719         } else {
  720                 uint16_t myaddr[ETHER_ADDR_LEN / 2];
  721                 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
  722                         stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
  723                             &myaddr[i]);
  724                         myaddr[i] = le16toh(myaddr[i]);
  725                 }
  726                 bcopy(myaddr, enaddr, sizeof(enaddr));
  727                 sc->sc_stge1023 = 1;
  728         }
  729 
  730         ifp->if_softc = sc;
  731         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  732         ifp->if_ioctl = stge_ioctl;
  733         ifp->if_start = stge_start;
  734         ifp->if_watchdog = stge_watchdog;
  735         ifp->if_init = stge_init;
  736 #ifdef IFPOLL_ENABLE
  737         ifp->if_npoll = stge_npoll;
  738 #endif
  739         ifp->if_mtu = ETHERMTU;
  740         ifq_set_maxlen(&ifp->if_snd, STGE_TX_RING_CNT - 1);
  741         ifq_set_ready(&ifp->if_snd);
  742         /* Revision B3 and earlier chips have checksum bug. */
  743         if (sc->sc_rev >= 0x0c) {
  744                 ifp->if_hwassist = STGE_CSUM_FEATURES;
  745                 ifp->if_capabilities = IFCAP_HWCSUM;
  746         } else {
  747                 ifp->if_hwassist = 0;
  748                 ifp->if_capabilities = 0;
  749         }
  750         ifp->if_capenable = ifp->if_capabilities;
  751 
  752         /*
  753          * Read some important bits from the PhyCtrl register.
  754          */
  755         sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
  756             (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
  757 
  758         /* Set up MII bus. */
  759         if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange,
  760             stge_mediastatus)) != 0) {
  761                 device_printf(sc->sc_dev, "no PHY found!\n");
  762                 goto fail;
  763         }
  764 
  765         ether_ifattach(ifp, enaddr, NULL);
  766 
  767 #ifdef IFPOLL_ENABLE
  768         ifpoll_compat_setup(&sc->sc_npoll,
  769             &sc->sc_sysctl_ctx, sc->sc_sysctl_tree, device_get_unit(dev),
  770             ifp->if_serializer);
  771 #endif
  772 
  773         /* VLAN capability setup */
  774         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
  775 #ifdef notyet
  776         if (sc->sc_rev >= 0x0c)
  777                 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
  778 #endif
  779         ifp->if_capenable = ifp->if_capabilities;
  780 
  781         /*
  782          * Tell the upper layer(s) we support long frames.
  783          * Must appear after the call to ether_ifattach() because
  784          * ether_ifattach() sets ifi_hdrlen to the default value.
  785          */
  786         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
  787 
  788         /*
  789          * The manual recommends disabling early transmit, so we
  790          * do.  It's disabled anyway, if using IP checksumming,
  791          * since the entire packet must be in the FIFO in order
  792          * for the chip to perform the checksum.
  793          */
  794         sc->sc_txthresh = 0x0fff;
  795 
  796         /*
  797          * Disable MWI if the PCI layer tells us to.
  798          */
  799         sc->sc_DMACtrl = 0;
  800         if ((cmd & PCIM_CMD_MWRICEN) == 0)
  801                 sc->sc_DMACtrl |= DMAC_MWIDisable;
  802 
  803         ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq));
  804 
  805         /*
  806          * Hookup IRQ
  807          */
  808         error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, stge_intr, sc,
  809                                &sc->sc_ih, ifp->if_serializer);
  810         if (error != 0) {
  811                 ether_ifdetach(ifp);
  812                 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
  813                 goto fail;
  814         }
  815 
  816 fail:
  817         if (error != 0)
  818                 stge_detach(dev);
  819 
  820         return (error);
  821 }
  822 
  823 static int
  824 stge_detach(device_t dev)
  825 {
  826         struct stge_softc *sc = device_get_softc(dev);
  827         struct ifnet *ifp = &sc->arpcom.ac_if;
  828 
  829         if (device_is_attached(dev)) {
  830                 lwkt_serialize_enter(ifp->if_serializer);
  831                 /* XXX */
  832                 sc->sc_detach = 1;
  833                 stge_stop(sc);
  834                 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
  835                 lwkt_serialize_exit(ifp->if_serializer);
  836 
  837                 ether_ifdetach(ifp);
  838         }
  839 
  840         if (sc->sc_sysctl_tree != NULL)
  841                 sysctl_ctx_free(&sc->sc_sysctl_ctx);
  842 
  843         if (sc->sc_miibus != NULL)
  844                 device_delete_child(dev, sc->sc_miibus);
  845         bus_generic_detach(dev);
  846 
  847         stge_dma_free(sc);
  848 
  849         if (sc->sc_irq != NULL) {
  850                 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
  851                                      sc->sc_irq);
  852         }
  853         if (sc->sc_res != NULL) {
  854                 bus_release_resource(dev, sc->sc_res_type, sc->sc_res_rid,
  855                                      sc->sc_res);
  856         }
  857 
  858         return (0);
  859 }
  860 
  861 static int
  862 stge_dma_alloc(struct stge_softc *sc)
  863 {
  864         struct stge_txdesc *txd;
  865         struct stge_rxdesc *rxd;
  866         int error, i;
  867 
  868         /* create parent tag. */
  869         error = bus_dma_tag_create(NULL,        /* parent */
  870                     1, 0,                       /* algnmnt, boundary */
  871                     STGE_DMA_MAXADDR,           /* lowaddr */
  872                     BUS_SPACE_MAXADDR,          /* highaddr */
  873                     NULL, NULL,                 /* filter, filterarg */
  874                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
  875                     0,                          /* nsegments */
  876                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
  877                     0,                          /* flags */
  878                     &sc->sc_cdata.stge_parent_tag);
  879         if (error != 0) {
  880                 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
  881                 return error;
  882         }
  883 
  884         /* allocate Tx ring. */
  885         sc->sc_rdata.stge_tx_ring =
  886                 bus_dmamem_coherent_any(sc->sc_cdata.stge_parent_tag,
  887                         STGE_RING_ALIGN, STGE_TX_RING_SZ,
  888                         BUS_DMA_WAITOK | BUS_DMA_ZERO,
  889                         &sc->sc_cdata.stge_tx_ring_tag,
  890                         &sc->sc_cdata.stge_tx_ring_map,
  891                         &sc->sc_rdata.stge_tx_ring_paddr);
  892         if (sc->sc_rdata.stge_tx_ring == NULL) {
  893                 device_printf(sc->sc_dev,
  894                     "failed to allocate Tx ring\n");
  895                 return ENOMEM;
  896         }
  897 
  898         /* allocate Rx ring. */
  899         sc->sc_rdata.stge_rx_ring =
  900                 bus_dmamem_coherent_any(sc->sc_cdata.stge_parent_tag,
  901                         STGE_RING_ALIGN, STGE_RX_RING_SZ,
  902                         BUS_DMA_WAITOK | BUS_DMA_ZERO,
  903                         &sc->sc_cdata.stge_rx_ring_tag,
  904                         &sc->sc_cdata.stge_rx_ring_map,
  905                         &sc->sc_rdata.stge_rx_ring_paddr);
  906         if (sc->sc_rdata.stge_rx_ring == NULL) {
  907                 device_printf(sc->sc_dev,
  908                     "failed to allocate Rx ring\n");
  909                 return ENOMEM;
  910         }
  911 
  912         /* create tag for Tx buffers. */
  913         error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
  914                     1, 0,                       /* algnmnt, boundary */
  915                     BUS_SPACE_MAXADDR,          /* lowaddr */
  916                     BUS_SPACE_MAXADDR,          /* highaddr */
  917                     NULL, NULL,                 /* filter, filterarg */
  918                     STGE_JUMBO_FRAMELEN,        /* maxsize */
  919                     STGE_MAXTXSEGS,             /* nsegments */
  920                     STGE_MAXSGSIZE,             /* maxsegsize */
  921                     BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
  922                     &sc->sc_cdata.stge_tx_tag);
  923         if (error != 0) {
  924                 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
  925                 return error;
  926         }
  927 
  928         /* create DMA maps for Tx buffers. */
  929         for (i = 0; i < STGE_TX_RING_CNT; i++) {
  930                 txd = &sc->sc_cdata.stge_txdesc[i];
  931                 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag,
  932                                 BUS_DMA_WAITOK, &txd->tx_dmamap);
  933                 if (error != 0) {
  934                         int j;
  935 
  936                         for (j = 0; j < i; ++j) {
  937                                 txd = &sc->sc_cdata.stge_txdesc[j];
  938                                 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
  939                                         txd->tx_dmamap);
  940                         }
  941                         bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
  942                         sc->sc_cdata.stge_tx_tag = NULL;
  943 
  944                         device_printf(sc->sc_dev,
  945                             "failed to create Tx dmamap\n");
  946                         return error;
  947                 }
  948         }
  949 
  950         /* create tag for Rx buffers. */
  951         error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
  952                     1, 0,                       /* algnmnt, boundary */
  953                     BUS_SPACE_MAXADDR,          /* lowaddr */
  954                     BUS_SPACE_MAXADDR,          /* highaddr */
  955                     NULL, NULL,                 /* filter, filterarg */
  956                     MCLBYTES,                   /* maxsize */
  957                     1,                          /* nsegments */
  958                     MCLBYTES,                   /* maxsegsize */
  959                     BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
  960                     &sc->sc_cdata.stge_rx_tag);
  961         if (error != 0) {
  962                 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
  963                 return error;
  964         }
  965 
  966         /* create DMA maps for Rx buffers. */
  967         error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, BUS_DMA_WAITOK,
  968                         &sc->sc_cdata.stge_rx_sparemap);
  969         if (error != 0) {
  970                 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
  971                 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
  972                 sc->sc_cdata.stge_rx_tag = NULL;
  973                 return error;
  974         }
  975         for (i = 0; i < STGE_RX_RING_CNT; i++) {
  976                 rxd = &sc->sc_cdata.stge_rxdesc[i];
  977                 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag,
  978                                 BUS_DMA_WAITOK, &rxd->rx_dmamap);
  979                 if (error != 0) {
  980                         int j;
  981 
  982                         for (j = 0; j < i; ++j) {
  983                                 rxd = &sc->sc_cdata.stge_rxdesc[j];
  984                                 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
  985                                         rxd->rx_dmamap);
  986                         }
  987                         bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
  988                                 sc->sc_cdata.stge_rx_sparemap);
  989                         bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
  990                         sc->sc_cdata.stge_rx_tag = NULL;
  991 
  992                         device_printf(sc->sc_dev,
  993                             "failed to create Rx dmamap\n");
  994                         return error;
  995                 }
  996         }
  997         return 0;
  998 }
  999 
 1000 static void
 1001 stge_dma_free(struct stge_softc *sc)
 1002 {
 1003         struct stge_txdesc *txd;
 1004         struct stge_rxdesc *rxd;
 1005         int i;
 1006 
 1007         /* Tx ring */
 1008         if (sc->sc_cdata.stge_tx_ring_tag) {
 1009                 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
 1010                     sc->sc_cdata.stge_tx_ring_map);
 1011                 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
 1012                     sc->sc_rdata.stge_tx_ring,
 1013                     sc->sc_cdata.stge_tx_ring_map);
 1014                 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
 1015         }
 1016 
 1017         /* Rx ring */
 1018         if (sc->sc_cdata.stge_rx_ring_tag) {
 1019                 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
 1020                     sc->sc_cdata.stge_rx_ring_map);
 1021                 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
 1022                     sc->sc_rdata.stge_rx_ring,
 1023                     sc->sc_cdata.stge_rx_ring_map);
 1024                 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
 1025         }
 1026 
 1027         /* Tx buffers */
 1028         if (sc->sc_cdata.stge_tx_tag) {
 1029                 for (i = 0; i < STGE_TX_RING_CNT; i++) {
 1030                         txd = &sc->sc_cdata.stge_txdesc[i];
 1031                         bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
 1032                             txd->tx_dmamap);
 1033                 }
 1034                 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
 1035         }
 1036 
 1037         /* Rx buffers */
 1038         if (sc->sc_cdata.stge_rx_tag) {
 1039                 for (i = 0; i < STGE_RX_RING_CNT; i++) {
 1040                         rxd = &sc->sc_cdata.stge_rxdesc[i];
 1041                         bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
 1042                             rxd->rx_dmamap);
 1043                 }
 1044                 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
 1045                     sc->sc_cdata.stge_rx_sparemap);
 1046                 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
 1047         }
 1048 
 1049         /* Top level tag */
 1050         if (sc->sc_cdata.stge_parent_tag)
 1051                 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
 1052 }
 1053 
 1054 /*
 1055  * stge_shutdown:
 1056  *
 1057  *      Make sure the interface is stopped at reboot time.
 1058  */
 1059 static void
 1060 stge_shutdown(device_t dev)
 1061 {
 1062         struct stge_softc *sc = device_get_softc(dev);
 1063         struct ifnet *ifp = &sc->arpcom.ac_if;
 1064 
 1065         lwkt_serialize_enter(ifp->if_serializer);
 1066         stge_stop(sc);
 1067         lwkt_serialize_exit(ifp->if_serializer);
 1068 }
 1069 
 1070 static int
 1071 stge_suspend(device_t dev)
 1072 {
 1073         struct stge_softc *sc = device_get_softc(dev);
 1074         struct ifnet *ifp = &sc->arpcom.ac_if;
 1075 
 1076         lwkt_serialize_enter(ifp->if_serializer);
 1077         stge_stop(sc);
 1078         sc->sc_suspended = 1;
 1079         lwkt_serialize_exit(ifp->if_serializer);
 1080 
 1081         return (0);
 1082 }
 1083 
 1084 static int
 1085 stge_resume(device_t dev)
 1086 {
 1087         struct stge_softc *sc = device_get_softc(dev);
 1088         struct ifnet *ifp = &sc->arpcom.ac_if;
 1089 
 1090         lwkt_serialize_enter(ifp->if_serializer);
 1091         if (ifp->if_flags & IFF_UP)
 1092                 stge_init(sc);
 1093         sc->sc_suspended = 0;
 1094         lwkt_serialize_exit(ifp->if_serializer);
 1095 
 1096         return (0);
 1097 }
 1098 
 1099 static void
 1100 stge_dma_wait(struct stge_softc *sc)
 1101 {
 1102         int i;
 1103 
 1104         for (i = 0; i < STGE_TIMEOUT; i++) {
 1105                 DELAY(2);
 1106                 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
 1107                         break;
 1108         }
 1109 
 1110         if (i == STGE_TIMEOUT)
 1111                 device_printf(sc->sc_dev, "DMA wait timed out\n");
 1112 }
 1113 
 1114 static int
 1115 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
 1116 {
 1117         struct stge_txdesc *txd;
 1118         struct stge_tfd *tfd;
 1119         struct mbuf *m;
 1120         bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
 1121         int error, i, si, nsegs;
 1122         uint64_t csum_flags, tfc;
 1123 
 1124         txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq);
 1125         KKASSERT(txd != NULL);
 1126 
 1127         error =  bus_dmamap_load_mbuf_defrag(sc->sc_cdata.stge_tx_tag,
 1128                         txd->tx_dmamap, m_head,
 1129                         txsegs, STGE_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT);
 1130         if (error) {
 1131                 m_freem(*m_head);
 1132                 *m_head = NULL;
 1133                 return (error);
 1134         }
 1135         bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
 1136             BUS_DMASYNC_PREWRITE);
 1137 
 1138         m = *m_head;
 1139 
 1140         csum_flags = 0;
 1141         if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
 1142                 if (m->m_pkthdr.csum_flags & CSUM_IP)
 1143                         csum_flags |= TFD_IPChecksumEnable;
 1144                 if (m->m_pkthdr.csum_flags & CSUM_TCP)
 1145                         csum_flags |= TFD_TCPChecksumEnable;
 1146                 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
 1147                         csum_flags |= TFD_UDPChecksumEnable;
 1148         }
 1149 
 1150         si = sc->sc_cdata.stge_tx_prod;
 1151         tfd = &sc->sc_rdata.stge_tx_ring[si];
 1152         for (i = 0; i < nsegs; i++) {
 1153                 tfd->tfd_frags[i].frag_word0 =
 1154                     htole64(FRAG_ADDR(txsegs[i].ds_addr) |
 1155                     FRAG_LEN(txsegs[i].ds_len));
 1156         }
 1157         sc->sc_cdata.stge_tx_cnt++;
 1158 
 1159         tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
 1160             TFD_FragCount(nsegs) | csum_flags;
 1161         if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
 1162                 tfc |= TFD_TxDMAIndicate;
 1163 
 1164         /* Update producer index. */
 1165         sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
 1166 
 1167         /* Check if we have a VLAN tag to insert. */
 1168         if (m->m_flags & M_VLANTAG)
 1169                 tfc |= TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vlantag);
 1170         tfd->tfd_control = htole64(tfc);
 1171 
 1172         /* Update Tx Queue. */
 1173         STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
 1174         STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
 1175         txd->tx_m = m;
 1176 
 1177         return (0);
 1178 }
 1179 
 1180 /*
 1181  * stge_start:          [ifnet interface function]
 1182  *
 1183  *      Start packet transmission on the interface.
 1184  */
 1185 static void
 1186 stge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
 1187 {
 1188         struct stge_softc *sc;
 1189         struct mbuf *m_head;
 1190         int enq;
 1191 
 1192         sc = ifp->if_softc;
 1193 
 1194         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
 1195         ASSERT_SERIALIZED(ifp->if_serializer);
 1196 
 1197         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
 1198                 return;
 1199 
 1200         enq = 0;
 1201         while (!ifq_is_empty(&ifp->if_snd)) {
 1202                 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
 1203                         ifq_set_oactive(&ifp->if_snd);
 1204                         break;
 1205                 }
 1206 
 1207                 m_head = ifq_dequeue(&ifp->if_snd);
 1208                 if (m_head == NULL)
 1209                         break;
 1210 
 1211                 /*
 1212                  * Pack the data into the transmit ring. If we
 1213                  * don't have room, set the OACTIVE flag and wait
 1214                  * for the NIC to drain the ring.
 1215                  */
 1216                 if (stge_encap(sc, &m_head)) {
 1217                         if (sc->sc_cdata.stge_tx_cnt == 0) {
 1218                                 continue;
 1219                         } else {
 1220                                 ifq_set_oactive(&ifp->if_snd);
 1221                                 break;
 1222                         }
 1223                 }
 1224                 enq = 1;
 1225 
 1226                 /*
 1227                  * If there's a BPF listener, bounce a copy of this frame
 1228                  * to him.
 1229                  */
 1230                 ETHER_BPF_MTAP(ifp, m_head);
 1231         }
 1232 
 1233         if (enq) {
 1234                 /* Transmit */
 1235                 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
 1236 
 1237                 /* Set a timeout in case the chip goes out to lunch. */
 1238                 ifp->if_timer = 5;
 1239         }
 1240 }
 1241 
 1242 /*
 1243  * stge_watchdog:       [ifnet interface function]
 1244  *
 1245  *      Watchdog timer handler.
 1246  */
 1247 static void
 1248 stge_watchdog(struct ifnet *ifp)
 1249 {
 1250         ASSERT_SERIALIZED(ifp->if_serializer);
 1251 
 1252         if_printf(ifp, "device timeout\n");
 1253         IFNET_STAT_INC(ifp, oerrors, 1);
 1254         stge_init(ifp->if_softc);
 1255 }
 1256 
 1257 /*
 1258  * stge_ioctl:          [ifnet interface function]
 1259  *
 1260  *      Handle control requests from the operator.
 1261  */
 1262 static int
 1263 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
 1264 {
 1265         struct stge_softc *sc;
 1266         struct ifreq *ifr;
 1267         struct mii_data *mii;
 1268         int error, mask;
 1269 
 1270         ASSERT_SERIALIZED(ifp->if_serializer);
 1271 
 1272         sc = ifp->if_softc;
 1273         ifr = (struct ifreq *)data;
 1274         error = 0;
 1275         switch (cmd) {
 1276         case SIOCSIFMTU:
 1277                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
 1278                         error = EINVAL;
 1279                 else if (ifp->if_mtu != ifr->ifr_mtu) {
 1280                         ifp->if_mtu = ifr->ifr_mtu;
 1281                         stge_init(sc);
 1282                 }
 1283                 break;
 1284         case SIOCSIFFLAGS:
 1285                 if ((ifp->if_flags & IFF_UP) != 0) {
 1286                         if ((ifp->if_flags & IFF_RUNNING) != 0) {
 1287                                 if (((ifp->if_flags ^ sc->sc_if_flags)
 1288                                     & IFF_PROMISC) != 0)
 1289                                         stge_set_filter(sc);
 1290                         } else {
 1291                                 if (sc->sc_detach == 0)
 1292                                         stge_init(sc);
 1293                         }
 1294                 } else {
 1295                         if ((ifp->if_flags & IFF_RUNNING) != 0)
 1296                                 stge_stop(sc);
 1297                 }
 1298                 sc->sc_if_flags = ifp->if_flags;
 1299                 break;
 1300         case SIOCADDMULTI:
 1301         case SIOCDELMULTI:
 1302                 if ((ifp->if_flags & IFF_RUNNING) != 0)
 1303                         stge_set_multi(sc);
 1304                 break;
 1305         case SIOCSIFMEDIA:
 1306         case SIOCGIFMEDIA:
 1307                 mii = device_get_softc(sc->sc_miibus);
 1308                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
 1309                 break;
 1310         case SIOCSIFCAP:
 1311                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 1312                 if ((mask & IFCAP_HWCSUM) != 0) {
 1313                         ifp->if_capenable ^= IFCAP_HWCSUM;
 1314                         if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
 1315                             (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
 1316                                 ifp->if_hwassist = STGE_CSUM_FEATURES;
 1317                         else
 1318                                 ifp->if_hwassist = 0;
 1319                 }
 1320                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
 1321                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 1322                         if (ifp->if_flags & IFF_RUNNING)
 1323                                 stge_vlan_setup(sc);
 1324                 }
 1325 #if 0
 1326                 VLAN_CAPABILITIES(ifp);
 1327 #endif
 1328                 break;
 1329         default:
 1330                 error = ether_ioctl(ifp, cmd, data);
 1331                 break;
 1332         }
 1333 
 1334         return (error);
 1335 }
 1336 
 1337 static void
 1338 stge_link(struct stge_softc *sc)
 1339 {
 1340         uint32_t v, ac;
 1341         int i;
 1342 
 1343         /*
 1344          * Update STGE_MACCtrl register depending on link status.
 1345          * (duplex, flow control etc)
 1346          */
 1347         v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 1348         v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
 1349         v |= sc->sc_MACCtrl;
 1350         CSR_WRITE_4(sc, STGE_MACCtrl, v);
 1351         if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
 1352                 /* Duplex setting changed, reset Tx/Rx functions. */
 1353                 ac = CSR_READ_4(sc, STGE_AsicCtrl);
 1354                 ac |= AC_TxReset | AC_RxReset;
 1355                 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
 1356                 for (i = 0; i < STGE_TIMEOUT; i++) {
 1357                         DELAY(100);
 1358                         if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
 1359                                 break;
 1360                 }
 1361                 if (i == STGE_TIMEOUT)
 1362                         device_printf(sc->sc_dev, "reset failed to complete\n");
 1363         }
 1364 }
 1365 
 1366 static __inline int
 1367 stge_tx_error(struct stge_softc *sc)
 1368 {
 1369         uint32_t txstat;
 1370         int error;
 1371 
 1372         for (error = 0;;) {
 1373                 txstat = CSR_READ_4(sc, STGE_TxStatus);
 1374                 if ((txstat & TS_TxComplete) == 0)
 1375                         break;
 1376                 /* Tx underrun */
 1377                 if ((txstat & TS_TxUnderrun) != 0) {
 1378                         /*
 1379                          * XXX
 1380                          * There should be a more better way to recover
 1381                          * from Tx underrun instead of a full reset.
 1382                          */
 1383                         if (sc->sc_nerr++ < STGE_MAXERR)
 1384                                 device_printf(sc->sc_dev, "Tx underrun, "
 1385                                     "resetting...\n");
 1386                         if (sc->sc_nerr == STGE_MAXERR)
 1387                                 device_printf(sc->sc_dev, "too many errors; "
 1388                                     "not reporting any more\n");
 1389                         error = -1;
 1390                         break;
 1391                 }
 1392                 /* Maximum/Late collisions, Re-enable Tx MAC. */
 1393                 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
 1394                         CSR_WRITE_4(sc, STGE_MACCtrl,
 1395                             (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
 1396                             MC_TxEnable);
 1397         }
 1398 
 1399         return (error);
 1400 }
 1401 
 1402 /*
 1403  * stge_intr:
 1404  *
 1405  *      Interrupt service routine.
 1406  */
 1407 static void
 1408 stge_intr(void *arg)
 1409 {
 1410         struct stge_softc *sc = arg;
 1411         struct ifnet *ifp = &sc->arpcom.ac_if;
 1412         int reinit;
 1413         uint16_t status;
 1414 
 1415         ASSERT_SERIALIZED(ifp->if_serializer);
 1416 
 1417         status = CSR_READ_2(sc, STGE_IntStatus);
 1418         if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
 1419                 return;
 1420 
 1421         /* Disable interrupts. */
 1422         for (reinit = 0;;) {
 1423                 status = CSR_READ_2(sc, STGE_IntStatusAck);
 1424                 status &= sc->sc_IntEnable;
 1425                 if (status == 0)
 1426                         break;
 1427                 /* Host interface errors. */
 1428                 if ((status & IS_HostError) != 0) {
 1429                         device_printf(sc->sc_dev,
 1430                             "Host interface error, resetting...\n");
 1431                         reinit = 1;
 1432                         goto force_init;
 1433                 }
 1434 
 1435                 /* Receive interrupts. */
 1436                 if ((status & IS_RxDMAComplete) != 0) {
 1437                         stge_rxeof(sc, -1);
 1438                         if ((status & IS_RFDListEnd) != 0)
 1439                                 CSR_WRITE_4(sc, STGE_DMACtrl,
 1440                                     DMAC_RxDMAPollNow);
 1441                 }
 1442 
 1443                 /* Transmit interrupts. */
 1444                 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
 1445                         stge_txeof(sc);
 1446 
 1447                 /* Transmission errors.*/
 1448                 if ((status & IS_TxComplete) != 0) {
 1449                         if ((reinit = stge_tx_error(sc)) != 0)
 1450                                 break;
 1451                 }
 1452         }
 1453 
 1454 force_init:
 1455         if (reinit != 0)
 1456                 stge_init(sc);
 1457 
 1458         /* Re-enable interrupts. */
 1459         CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
 1460 
 1461         /* Try to get more packets going. */
 1462         if (!ifq_is_empty(&ifp->if_snd))
 1463                 if_devstart(ifp);
 1464 }
 1465 
 1466 /*
 1467  * stge_txeof:
 1468  *
 1469  *      Helper; handle transmit interrupts.
 1470  */
 1471 static void
 1472 stge_txeof(struct stge_softc *sc)
 1473 {
 1474         struct ifnet *ifp = &sc->arpcom.ac_if;
 1475         struct stge_txdesc *txd;
 1476         uint64_t control;
 1477         int cons;
 1478 
 1479         txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
 1480         if (txd == NULL)
 1481                 return;
 1482 
 1483         /*
 1484          * Go through our Tx list and free mbufs for those
 1485          * frames which have been transmitted.
 1486          */
 1487         for (cons = sc->sc_cdata.stge_tx_cons;;
 1488             cons = (cons + 1) % STGE_TX_RING_CNT) {
 1489                 if (sc->sc_cdata.stge_tx_cnt <= 0)
 1490                         break;
 1491                 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
 1492                 if ((control & TFD_TFDDone) == 0)
 1493                         break;
 1494                 sc->sc_cdata.stge_tx_cnt--;
 1495 
 1496                 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
 1497 
 1498                 /* Output counter is updated with statistics register */
 1499                 m_freem(txd->tx_m);
 1500                 txd->tx_m = NULL;
 1501                 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
 1502                 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
 1503                 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
 1504         }
 1505         sc->sc_cdata.stge_tx_cons = cons;
 1506 
 1507         if (sc->sc_cdata.stge_tx_cnt < STGE_TX_HIWAT)
 1508                 ifq_clr_oactive(&ifp->if_snd);
 1509         if (sc->sc_cdata.stge_tx_cnt == 0)
 1510                 ifp->if_timer = 0;
 1511 }
 1512 
 1513 static __inline void
 1514 stge_discard_rxbuf(struct stge_softc *sc, int idx)
 1515 {
 1516         struct stge_rfd *rfd;
 1517 
 1518         rfd = &sc->sc_rdata.stge_rx_ring[idx];
 1519         rfd->rfd_status = 0;
 1520 }
 1521 
 1522 #ifndef __i386__
 1523 /*
 1524  * It seems that TC9021's DMA engine has alignment restrictions in
 1525  * DMA scatter operations. The first DMA segment has no address
 1526  * alignment restrictins but the rest should be aligned on 4(?) bytes
 1527  * boundary. Otherwise it would corrupt random memory. Since we don't
 1528  * know which one is used for the first segment in advance we simply
 1529  * don't align at all.
 1530  * To avoid copying over an entire frame to align, we allocate a new
 1531  * mbuf and copy ethernet header to the new mbuf. The new mbuf is
 1532  * prepended into the existing mbuf chain.
 1533  */
 1534 static __inline struct mbuf *
 1535 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
 1536 {
 1537         struct mbuf *n;
 1538 
 1539         n = NULL;
 1540         if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
 1541                 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
 1542                 m->m_data += ETHER_HDR_LEN;
 1543                 n = m;
 1544         } else {
 1545                 MGETHDR(n, MB_DONTWAIT, MT_DATA);
 1546                 if (n != NULL) {
 1547                         bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
 1548                         m->m_data += ETHER_HDR_LEN;
 1549                         m->m_len -= ETHER_HDR_LEN;
 1550                         n->m_len = ETHER_HDR_LEN;
 1551                         M_MOVE_PKTHDR(n, m);
 1552                         n->m_next = m;
 1553                 } else
 1554                         m_freem(m);
 1555         }
 1556 
 1557         return (n);
 1558 }
 1559 #endif
 1560 
 1561 /*
 1562  * stge_rxeof:
 1563  *
 1564  *      Helper; handle receive interrupts.
 1565  */
 1566 static void
 1567 stge_rxeof(struct stge_softc *sc, int count)
 1568 {
 1569         struct ifnet *ifp = &sc->arpcom.ac_if;
 1570         struct stge_rxdesc *rxd;
 1571         struct mbuf *mp, *m;
 1572         uint64_t status64;
 1573         uint32_t status;
 1574         int cons, prog;
 1575 
 1576         prog = 0;
 1577         for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
 1578             prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
 1579 #ifdef IFPOLL_ENABLE
 1580                 if (count >= 0 && count-- == 0)
 1581                         break;
 1582 #endif
 1583 
 1584                 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
 1585                 status = RFD_RxStatus(status64);
 1586                 if ((status & RFD_RFDDone) == 0)
 1587                         break;
 1588 
 1589                 prog++;
 1590                 rxd = &sc->sc_cdata.stge_rxdesc[cons];
 1591                 mp = rxd->rx_m;
 1592 
 1593                 /*
 1594                  * If the packet had an error, drop it.  Note we count
 1595                  * the error later in the periodic stats update.
 1596                  */
 1597                 if ((status & RFD_FrameEnd) != 0 && (status &
 1598                     (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
 1599                     RFD_RxAlignmentError | RFD_RxFCSError |
 1600                     RFD_RxLengthError)) != 0) {
 1601                         stge_discard_rxbuf(sc, cons);
 1602                         if (sc->sc_cdata.stge_rxhead != NULL) {
 1603                                 m_freem(sc->sc_cdata.stge_rxhead);
 1604                                 STGE_RXCHAIN_RESET(sc);
 1605                         }
 1606                         continue;
 1607                 }
 1608                 /*
 1609                  * Add a new receive buffer to the ring.
 1610                  */
 1611                 if (stge_newbuf(sc, cons, 0) != 0) {
 1612                         IFNET_STAT_INC(ifp, iqdrops, 1);
 1613                         stge_discard_rxbuf(sc, cons);
 1614                         if (sc->sc_cdata.stge_rxhead != NULL) {
 1615                                 m_freem(sc->sc_cdata.stge_rxhead);
 1616                                 STGE_RXCHAIN_RESET(sc);
 1617                         }
 1618                         continue;
 1619                 }
 1620 
 1621                 if ((status & RFD_FrameEnd) != 0)
 1622                         mp->m_len = RFD_RxDMAFrameLen(status) -
 1623                             sc->sc_cdata.stge_rxlen;
 1624                 sc->sc_cdata.stge_rxlen += mp->m_len;
 1625 
 1626                 /* Chain mbufs. */
 1627                 if (sc->sc_cdata.stge_rxhead == NULL) {
 1628                         sc->sc_cdata.stge_rxhead = mp;
 1629                         sc->sc_cdata.stge_rxtail = mp;
 1630                 } else {
 1631                         mp->m_flags &= ~M_PKTHDR;
 1632                         sc->sc_cdata.stge_rxtail->m_next = mp;
 1633                         sc->sc_cdata.stge_rxtail = mp;
 1634                 }
 1635 
 1636                 if ((status & RFD_FrameEnd) != 0) {
 1637                         m = sc->sc_cdata.stge_rxhead;
 1638                         m->m_pkthdr.rcvif = ifp;
 1639                         m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
 1640 
 1641                         if (m->m_pkthdr.len > sc->sc_if_framesize) {
 1642                                 m_freem(m);
 1643                                 STGE_RXCHAIN_RESET(sc);
 1644                                 continue;
 1645                         }
 1646                         /*
 1647                          * Set the incoming checksum information for
 1648                          * the packet.
 1649                          */
 1650                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
 1651                                 if ((status & RFD_IPDetected) != 0) {
 1652                                         m->m_pkthdr.csum_flags |=
 1653                                                 CSUM_IP_CHECKED;
 1654                                         if ((status & RFD_IPError) == 0)
 1655                                                 m->m_pkthdr.csum_flags |=
 1656                                                     CSUM_IP_VALID;
 1657                                 }
 1658                                 if (((status & RFD_TCPDetected) != 0 &&
 1659                                     (status & RFD_TCPError) == 0) ||
 1660                                     ((status & RFD_UDPDetected) != 0 &&
 1661                                     (status & RFD_UDPError) == 0)) {
 1662                                         m->m_pkthdr.csum_flags |=
 1663                                             (CSUM_DATA_VALID |
 1664                                              CSUM_PSEUDO_HDR |
 1665                                              CSUM_FRAG_NOT_CHECKED);
 1666                                         m->m_pkthdr.csum_data = 0xffff;
 1667                                 }
 1668                         }
 1669 
 1670 #ifndef __i386__
 1671                         if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
 1672                                 if ((m = stge_fixup_rx(sc, m)) == NULL) {
 1673                                         STGE_RXCHAIN_RESET(sc);
 1674                                         continue;
 1675                                 }
 1676                         }
 1677 #endif
 1678 
 1679                         /* Check for VLAN tagged packets. */
 1680                         if ((status & RFD_VLANDetected) != 0 &&
 1681                             (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
 1682                                 m->m_flags |= M_VLANTAG;
 1683                                 m->m_pkthdr.ether_vlantag = RFD_TCI(status64);
 1684                         }
 1685                         /* Pass it on. */
 1686                         ifp->if_input(ifp, m);
 1687 
 1688                         STGE_RXCHAIN_RESET(sc);
 1689                 }
 1690         }
 1691 
 1692         if (prog > 0) {
 1693                 /* Update the consumer index. */
 1694                 sc->sc_cdata.stge_rx_cons = cons;
 1695         }
 1696 }
 1697 
 1698 #ifdef IFPOLL_ENABLE
 1699 
 1700 static void
 1701 stge_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
 1702 {
 1703         struct stge_softc *sc = ifp->if_softc;
 1704 
 1705         ASSERT_SERIALIZED(ifp->if_serializer);
 1706 
 1707         if (sc->sc_npoll.ifpc_stcount-- == 0) {
 1708                 uint16_t status;
 1709 
 1710                 sc->sc_npoll.ifpc_stcount = sc->sc_npoll.ifpc_stfrac;
 1711 
 1712                 status = CSR_READ_2(sc, STGE_IntStatus);
 1713                 status &= sc->sc_IntEnable;
 1714                 if (status != 0) {
 1715                         if (status & IS_HostError) {
 1716                                 device_printf(sc->sc_dev,
 1717                                 "Host interface error, "
 1718                                 "resetting...\n");
 1719                                 stge_init(sc);
 1720                         }
 1721                         if ((status & IS_TxComplete) != 0 &&
 1722                             stge_tx_error(sc) != 0)
 1723                                 stge_init(sc);
 1724                 }
 1725         }
 1726 
 1727         stge_rxeof(sc, count);
 1728         stge_txeof(sc);
 1729 
 1730         if (!ifq_is_empty(&ifp->if_snd))
 1731                 if_devstart(ifp);
 1732 }
 1733 
 1734 static void
 1735 stge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
 1736 {
 1737         struct stge_softc *sc = ifp->if_softc;
 1738 
 1739         ASSERT_SERIALIZED(ifp->if_serializer);
 1740 
 1741         if (info != NULL) {
 1742                 int cpuid = sc->sc_npoll.ifpc_cpuid;
 1743 
 1744                 info->ifpi_rx[cpuid].poll_func = stge_npoll_compat;
 1745                 info->ifpi_rx[cpuid].arg = NULL;
 1746                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
 1747 
 1748                 if (ifp->if_flags & IFF_RUNNING) {
 1749                         CSR_WRITE_2(sc, STGE_IntEnable, 0);
 1750                         sc->sc_npoll.ifpc_stcount = 0;
 1751                 }
 1752                 ifq_set_cpuid(&ifp->if_snd, cpuid);
 1753         } else {
 1754                 if (ifp->if_flags & IFF_RUNNING)
 1755                         CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
 1756                 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq));
 1757         }
 1758 }
 1759 
 1760 #endif  /* IFPOLL_ENABLE */
 1761 
 1762 /*
 1763  * stge_tick:
 1764  *
 1765  *      One second timer, used to tick the MII.
 1766  */
 1767 static void
 1768 stge_tick(void *arg)
 1769 {
 1770         struct stge_softc *sc = arg;
 1771         struct ifnet *ifp = &sc->arpcom.ac_if;
 1772         struct mii_data *mii;
 1773 
 1774         lwkt_serialize_enter(ifp->if_serializer);
 1775 
 1776         mii = device_get_softc(sc->sc_miibus);
 1777         mii_tick(mii);
 1778 
 1779         /* Update statistics counters. */
 1780         stge_stats_update(sc);
 1781 
 1782         /*
 1783          * Relcaim any pending Tx descriptors to release mbufs in a
 1784          * timely manner as we don't generate Tx completion interrupts
 1785          * for every frame. This limits the delay to a maximum of one
 1786          * second.
 1787          */
 1788         if (sc->sc_cdata.stge_tx_cnt != 0)
 1789                 stge_txeof(sc);
 1790 
 1791         callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
 1792 
 1793         lwkt_serialize_exit(ifp->if_serializer);
 1794 }
 1795 
 1796 /*
 1797  * stge_stats_update:
 1798  *
 1799  *      Read the TC9021 statistics counters.
 1800  */
 1801 static void
 1802 stge_stats_update(struct stge_softc *sc)
 1803 {
 1804         struct ifnet *ifp = &sc->arpcom.ac_if;
 1805 
 1806         CSR_READ_4(sc,STGE_OctetRcvOk);
 1807 
 1808         IFNET_STAT_INC(ifp, ipackets, CSR_READ_4(sc, STGE_FramesRcvdOk));
 1809 
 1810         IFNET_STAT_INC(ifp, ierrors, CSR_READ_2(sc, STGE_FramesLostRxErrors));
 1811 
 1812         CSR_READ_4(sc, STGE_OctetXmtdOk);
 1813 
 1814         IFNET_STAT_INC(ifp, opackets, CSR_READ_4(sc, STGE_FramesXmtdOk));
 1815 
 1816         IFNET_STAT_INC(ifp, collisions,
 1817             CSR_READ_4(sc, STGE_LateCollisions) +
 1818             CSR_READ_4(sc, STGE_MultiColFrames) +
 1819             CSR_READ_4(sc, STGE_SingleColFrames));
 1820 
 1821         IFNET_STAT_INC(ifp, oerrors,
 1822             CSR_READ_2(sc, STGE_FramesAbortXSColls) +
 1823             CSR_READ_2(sc, STGE_FramesWEXDeferal));
 1824 }
 1825 
 1826 /*
 1827  * stge_reset:
 1828  *
 1829  *      Perform a soft reset on the TC9021.
 1830  */
 1831 static void
 1832 stge_reset(struct stge_softc *sc, uint32_t how)
 1833 {
 1834         uint32_t ac;
 1835         uint8_t v;
 1836         int i, dv;
 1837 
 1838         dv = 5000;
 1839         ac = CSR_READ_4(sc, STGE_AsicCtrl);
 1840         switch (how) {
 1841         case STGE_RESET_TX:
 1842                 ac |= AC_TxReset | AC_FIFO;
 1843                 dv = 100;
 1844                 break;
 1845         case STGE_RESET_RX:
 1846                 ac |= AC_RxReset | AC_FIFO;
 1847                 dv = 100;
 1848                 break;
 1849         case STGE_RESET_FULL:
 1850         default:
 1851                 /*
 1852                  * Only assert RstOut if we're fiber.  We need GMII clocks
 1853                  * to be present in order for the reset to complete on fiber
 1854                  * cards.
 1855                  */
 1856                 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
 1857                     AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
 1858                     (sc->sc_usefiber ? AC_RstOut : 0);
 1859                 break;
 1860         }
 1861 
 1862         CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
 1863 
 1864         /* Account for reset problem at 10Mbps. */
 1865         DELAY(dv);
 1866 
 1867         for (i = 0; i < STGE_TIMEOUT; i++) {
 1868                 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
 1869                         break;
 1870                 DELAY(dv);
 1871         }
 1872 
 1873         if (i == STGE_TIMEOUT)
 1874                 device_printf(sc->sc_dev, "reset failed to complete\n");
 1875 
 1876         /* Set LED, from Linux IPG driver. */
 1877         ac = CSR_READ_4(sc, STGE_AsicCtrl);
 1878         ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
 1879         if ((sc->sc_led & 0x01) != 0)
 1880                 ac |= AC_LEDMode;
 1881         if ((sc->sc_led & 0x03) != 0)
 1882                 ac |= AC_LEDModeBit1;
 1883         if ((sc->sc_led & 0x08) != 0)
 1884                 ac |= AC_LEDSpeed;
 1885         CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
 1886 
 1887         /* Set PHY, from Linux IPG driver */
 1888         v = CSR_READ_1(sc, STGE_PhySet);
 1889         v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
 1890         v |= ((sc->sc_led & 0x70) >> 4);
 1891         CSR_WRITE_1(sc, STGE_PhySet, v);
 1892 }
 1893 
 1894 /*
 1895  * stge_init:           [ ifnet interface function ]
 1896  *
 1897  *      Initialize the interface.
 1898  */
 1899 static void
 1900 stge_init(void *xsc)
 1901 {
 1902         struct stge_softc *sc = xsc;
 1903         struct ifnet *ifp = &sc->arpcom.ac_if;
 1904         struct mii_data *mii;
 1905         uint16_t eaddr[3];
 1906         uint32_t v;
 1907         int error;
 1908 
 1909         ASSERT_SERIALIZED(ifp->if_serializer);
 1910 
 1911         mii = device_get_softc(sc->sc_miibus);
 1912 
 1913         /*
 1914          * Cancel any pending I/O.
 1915          */
 1916         stge_stop(sc);
 1917 
 1918         /* Init descriptors. */
 1919         error = stge_init_rx_ring(sc);
 1920         if (error != 0) {
 1921                 device_printf(sc->sc_dev,
 1922                     "initialization failed: no memory for rx buffers\n");
 1923                 stge_stop(sc);
 1924                 goto out;
 1925         }
 1926         stge_init_tx_ring(sc);
 1927 
 1928         /* Set the station address. */
 1929         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
 1930         CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
 1931         CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
 1932         CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
 1933 
 1934         /*
 1935          * Set the statistics masks.  Disable all the RMON stats,
 1936          * and disable selected stats in the non-RMON stats registers.
 1937          */
 1938         CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
 1939         CSR_WRITE_4(sc, STGE_StatisticsMask,
 1940             (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
 1941             (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
 1942             (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
 1943             (1U << 21));
 1944 
 1945         /* Set up the receive filter. */
 1946         stge_set_filter(sc);
 1947         /* Program multicast filter. */
 1948         stge_set_multi(sc);
 1949 
 1950         /*
 1951          * Give the transmit and receive ring to the chip.
 1952          */
 1953         CSR_WRITE_4(sc, STGE_TFDListPtrHi,
 1954             STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
 1955         CSR_WRITE_4(sc, STGE_TFDListPtrLo,
 1956             STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
 1957 
 1958         CSR_WRITE_4(sc, STGE_RFDListPtrHi,
 1959             STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
 1960         CSR_WRITE_4(sc, STGE_RFDListPtrLo,
 1961             STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
 1962 
 1963         /*
 1964          * Initialize the Tx auto-poll period.  It's OK to make this number
 1965          * large (255 is the max, but we use 127) -- we explicitly kick the
 1966          * transmit engine when there's actually a packet.
 1967          */
 1968         CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
 1969 
 1970         /* ..and the Rx auto-poll period. */
 1971         CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
 1972 
 1973         /* Initialize the Tx start threshold. */
 1974         CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
 1975 
 1976         /* Rx DMA thresholds, from Linux */
 1977         CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
 1978         CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
 1979 
 1980         /* Rx early threhold, from Linux */
 1981         CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
 1982 
 1983         /* Tx DMA thresholds, from Linux */
 1984         CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
 1985         CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
 1986 
 1987         /*
 1988          * Initialize the Rx DMA interrupt control register.  We
 1989          * request an interrupt after every incoming packet, but
 1990          * defer it for sc_rxint_dmawait us. When the number of
 1991          * interrupts pending reaches STGE_RXINT_NFRAME, we stop
 1992          * deferring the interrupt, and signal it immediately.
 1993          */
 1994         CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
 1995             RDIC_RxFrameCount(sc->sc_rxint_nframe) |
 1996             RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
 1997 
 1998         /*
 1999          * Initialize the interrupt mask.
 2000          */
 2001         sc->sc_IntEnable = IS_HostError | IS_TxComplete |
 2002             IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
 2003 #ifdef IFPOLL_ENABLE
 2004         /* Disable interrupts if we are polling. */
 2005         if (ifp->if_flags & IFF_NPOLLING) {
 2006                 CSR_WRITE_2(sc, STGE_IntEnable, 0);
 2007                 sc->sc_npoll.ifpc_stcount = 0;
 2008         } else
 2009 #endif
 2010         CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
 2011 
 2012         /*
 2013          * Configure the DMA engine.
 2014          * XXX Should auto-tune TxBurstLimit.
 2015          */
 2016         CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
 2017 
 2018         /*
 2019          * Send a PAUSE frame when we reach 29,696 bytes in the Rx
 2020          * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
 2021          * in the Rx FIFO.
 2022          */
 2023         CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
 2024         CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
 2025 
 2026         /*
 2027          * Set the maximum frame size.
 2028          */
 2029         sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 2030         CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
 2031 
 2032         /*
 2033          * Initialize MacCtrl -- do it before setting the media,
 2034          * as setting the media will actually program the register.
 2035          *
 2036          * Note: We have to poke the IFS value before poking
 2037          * anything else.
 2038          */
 2039         /* Tx/Rx MAC should be disabled before programming IFS.*/
 2040         CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
 2041 
 2042         stge_vlan_setup(sc);
 2043 
 2044         if (sc->sc_rev >= 6) {          /* >= B.2 */
 2045                 /* Multi-frag frame bug work-around. */
 2046                 CSR_WRITE_2(sc, STGE_DebugCtrl,
 2047                     CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
 2048 
 2049                 /* Tx Poll Now bug work-around. */
 2050                 CSR_WRITE_2(sc, STGE_DebugCtrl,
 2051                     CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
 2052                 /* Tx Poll Now bug work-around. */
 2053                 CSR_WRITE_2(sc, STGE_DebugCtrl,
 2054                     CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
 2055         }
 2056 
 2057         v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2058         v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
 2059         CSR_WRITE_4(sc, STGE_MACCtrl, v);
 2060         /*
 2061          * It seems that transmitting frames without checking the state of
 2062          * Rx/Tx MAC wedge the hardware.
 2063          */
 2064         stge_start_tx(sc);
 2065         stge_start_rx(sc);
 2066 
 2067         /*
 2068          * Set the current media.
 2069          */
 2070         mii_mediachg(mii);
 2071 
 2072         /*
 2073          * Start the one second MII clock.
 2074          */
 2075         callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
 2076 
 2077         /*
 2078          * ...all done!
 2079          */
 2080         ifp->if_flags |= IFF_RUNNING;
 2081         ifq_clr_oactive(&ifp->if_snd);
 2082 
 2083  out:
 2084         if (error != 0)
 2085                 device_printf(sc->sc_dev, "interface not running\n");
 2086 }
 2087 
 2088 static void
 2089 stge_vlan_setup(struct stge_softc *sc)
 2090 {
 2091         struct ifnet *ifp = &sc->arpcom.ac_if;
 2092         uint32_t v;
 2093 
 2094         /*
 2095          * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
 2096          * MC_AutoVLANuntagging bit.
 2097          * MC_AutoVLANtagging bit selects which VLAN source to use
 2098          * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
 2099          * bit has priority over MC_AutoVLANtagging bit. So we always
 2100          * use TFC instead of STGE_VLANTag register.
 2101          */
 2102         v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2103         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
 2104                 v |= MC_AutoVLANuntagging;
 2105         else
 2106                 v &= ~MC_AutoVLANuntagging;
 2107         CSR_WRITE_4(sc, STGE_MACCtrl, v);
 2108 }
 2109 
 2110 /*
 2111  *      Stop transmission on the interface.
 2112  */
 2113 static void
 2114 stge_stop(struct stge_softc *sc)
 2115 {
 2116         struct ifnet *ifp = &sc->arpcom.ac_if;
 2117         struct stge_txdesc *txd;
 2118         struct stge_rxdesc *rxd;
 2119         uint32_t v;
 2120         int i;
 2121 
 2122         ASSERT_SERIALIZED(ifp->if_serializer);
 2123 
 2124         /*
 2125          * Stop the one second clock.
 2126          */
 2127         callout_stop(&sc->sc_tick_ch);
 2128 
 2129         /*
 2130          * Reset the chip to a known state.
 2131          */
 2132         stge_reset(sc, STGE_RESET_FULL);
 2133 
 2134         /*
 2135          * Disable interrupts.
 2136          */
 2137         CSR_WRITE_2(sc, STGE_IntEnable, 0);
 2138 
 2139         /*
 2140          * Stop receiver, transmitter, and stats update.
 2141          */
 2142         stge_stop_rx(sc);
 2143         stge_stop_tx(sc);
 2144         v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2145         v |= MC_StatisticsDisable;
 2146         CSR_WRITE_4(sc, STGE_MACCtrl, v);
 2147 
 2148         /*
 2149          * Stop the transmit and receive DMA.
 2150          */
 2151         stge_dma_wait(sc);
 2152         CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
 2153         CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
 2154         CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
 2155         CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
 2156 
 2157         /*
 2158          * Free RX and TX mbufs still in the queues.
 2159          */
 2160         for (i = 0; i < STGE_RX_RING_CNT; i++) {
 2161                 rxd = &sc->sc_cdata.stge_rxdesc[i];
 2162                 if (rxd->rx_m != NULL) {
 2163                         bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
 2164                             rxd->rx_dmamap);
 2165                         m_freem(rxd->rx_m);
 2166                         rxd->rx_m = NULL;
 2167                 }
 2168         }
 2169         for (i = 0; i < STGE_TX_RING_CNT; i++) {
 2170                 txd = &sc->sc_cdata.stge_txdesc[i];
 2171                 if (txd->tx_m != NULL) {
 2172                         bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
 2173                             txd->tx_dmamap);
 2174                         m_freem(txd->tx_m);
 2175                         txd->tx_m = NULL;
 2176                 }
 2177         }
 2178 
 2179         /*
 2180          * Mark the interface down and cancel the watchdog timer.
 2181          */
 2182         ifp->if_flags &= ~IFF_RUNNING;
 2183         ifq_clr_oactive(&ifp->if_snd);
 2184         ifp->if_timer = 0;
 2185 }
 2186 
 2187 static void
 2188 stge_start_tx(struct stge_softc *sc)
 2189 {
 2190         uint32_t v;
 2191         int i;
 2192 
 2193         v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2194         if ((v & MC_TxEnabled) != 0)
 2195                 return;
 2196         v |= MC_TxEnable;
 2197         CSR_WRITE_4(sc, STGE_MACCtrl, v);
 2198         CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
 2199         for (i = STGE_TIMEOUT; i > 0; i--) {
 2200                 DELAY(10);
 2201                 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2202                 if ((v & MC_TxEnabled) != 0)
 2203                         break;
 2204         }
 2205         if (i == 0)
 2206                 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
 2207 }
 2208 
 2209 static void
 2210 stge_start_rx(struct stge_softc *sc)
 2211 {
 2212         uint32_t v;
 2213         int i;
 2214 
 2215         v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2216         if ((v & MC_RxEnabled) != 0)
 2217                 return;
 2218         v |= MC_RxEnable;
 2219         CSR_WRITE_4(sc, STGE_MACCtrl, v);
 2220         CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
 2221         for (i = STGE_TIMEOUT; i > 0; i--) {
 2222                 DELAY(10);
 2223                 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2224                 if ((v & MC_RxEnabled) != 0)
 2225                         break;
 2226         }
 2227         if (i == 0)
 2228                 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
 2229 }
 2230 
 2231 static void
 2232 stge_stop_tx(struct stge_softc *sc)
 2233 {
 2234         uint32_t v;
 2235         int i;
 2236 
 2237         v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2238         if ((v & MC_TxEnabled) == 0)
 2239                 return;
 2240         v |= MC_TxDisable;
 2241         CSR_WRITE_4(sc, STGE_MACCtrl, v);
 2242         for (i = STGE_TIMEOUT; i > 0; i--) {
 2243                 DELAY(10);
 2244                 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2245                 if ((v & MC_TxEnabled) == 0)
 2246                         break;
 2247         }
 2248         if (i == 0)
 2249                 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
 2250 }
 2251 
 2252 static void
 2253 stge_stop_rx(struct stge_softc *sc)
 2254 {
 2255         uint32_t v;
 2256         int i;
 2257 
 2258         v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2259         if ((v & MC_RxEnabled) == 0)
 2260                 return;
 2261         v |= MC_RxDisable;
 2262         CSR_WRITE_4(sc, STGE_MACCtrl, v);
 2263         for (i = STGE_TIMEOUT; i > 0; i--) {
 2264                 DELAY(10);
 2265                 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
 2266                 if ((v & MC_RxEnabled) == 0)
 2267                         break;
 2268         }
 2269         if (i == 0)
 2270                 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
 2271 }
 2272 
 2273 static void
 2274 stge_init_tx_ring(struct stge_softc *sc)
 2275 {
 2276         struct stge_ring_data *rd;
 2277         struct stge_txdesc *txd;
 2278         bus_addr_t addr;
 2279         int i;
 2280 
 2281         STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
 2282         STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
 2283 
 2284         sc->sc_cdata.stge_tx_prod = 0;
 2285         sc->sc_cdata.stge_tx_cons = 0;
 2286         sc->sc_cdata.stge_tx_cnt = 0;
 2287 
 2288         rd = &sc->sc_rdata;
 2289         bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
 2290         for (i = 0; i < STGE_TX_RING_CNT; i++) {
 2291                 if (i == (STGE_TX_RING_CNT - 1))
 2292                         addr = STGE_TX_RING_ADDR(sc, 0);
 2293                 else
 2294                         addr = STGE_TX_RING_ADDR(sc, i + 1);
 2295                 rd->stge_tx_ring[i].tfd_next = htole64(addr);
 2296                 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
 2297                 txd = &sc->sc_cdata.stge_txdesc[i];
 2298                 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
 2299         }
 2300 }
 2301 
 2302 static int
 2303 stge_init_rx_ring(struct stge_softc *sc)
 2304 {
 2305         struct stge_ring_data *rd;
 2306         bus_addr_t addr;
 2307         int i;
 2308 
 2309         sc->sc_cdata.stge_rx_cons = 0;
 2310         STGE_RXCHAIN_RESET(sc);
 2311 
 2312         rd = &sc->sc_rdata;
 2313         bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
 2314         for (i = 0; i < STGE_RX_RING_CNT; i++) {
 2315                 if (stge_newbuf(sc, i, 1) != 0)
 2316                         return (ENOBUFS);
 2317                 if (i == (STGE_RX_RING_CNT - 1))
 2318                         addr = STGE_RX_RING_ADDR(sc, 0);
 2319                 else
 2320                         addr = STGE_RX_RING_ADDR(sc, i + 1);
 2321                 rd->stge_rx_ring[i].rfd_next = htole64(addr);
 2322                 rd->stge_rx_ring[i].rfd_status = 0;
 2323         }
 2324         return (0);
 2325 }
 2326 
 2327 /*
 2328  * stge_newbuf:
 2329  *
 2330  *      Add a receive buffer to the indicated descriptor.
 2331  */
 2332 static int
 2333 stge_newbuf(struct stge_softc *sc, int idx, int waitok)
 2334 {
 2335         struct stge_rxdesc *rxd;
 2336         struct stge_rfd *rfd;
 2337         struct mbuf *m;
 2338         bus_dma_segment_t seg;
 2339         bus_dmamap_t map;
 2340         int error, nseg;
 2341 
 2342         m = m_getcl(waitok ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 2343         if (m == NULL)
 2344                 return ENOBUFS;
 2345         m->m_len = m->m_pkthdr.len = MCLBYTES;
 2346 
 2347         /*
 2348          * The hardware requires 4bytes aligned DMA address when JUMBO
 2349          * frame is used.
 2350          */
 2351         if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
 2352                 m_adj(m, ETHER_ALIGN);
 2353 
 2354         error = bus_dmamap_load_mbuf_segment(sc->sc_cdata.stge_rx_tag,
 2355                         sc->sc_cdata.stge_rx_sparemap, m,
 2356                         &seg, 1, &nseg, BUS_DMA_NOWAIT);
 2357         if (error) {
 2358                 m_freem(m);
 2359                 return error;
 2360         }
 2361 
 2362         rxd = &sc->sc_cdata.stge_rxdesc[idx];
 2363         if (rxd->rx_m != NULL) {
 2364                 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
 2365                     BUS_DMASYNC_POSTREAD);
 2366                 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
 2367         }
 2368 
 2369         map = rxd->rx_dmamap;
 2370         rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
 2371         sc->sc_cdata.stge_rx_sparemap = map;
 2372 
 2373         rxd->rx_m = m;
 2374 
 2375         rfd = &sc->sc_rdata.stge_rx_ring[idx];
 2376         rfd->rfd_frag.frag_word0 =
 2377             htole64(FRAG_ADDR(seg.ds_addr) | FRAG_LEN(seg.ds_len));
 2378         rfd->rfd_status = 0;
 2379 
 2380         return 0;
 2381 }
 2382 
 2383 /*
 2384  * stge_set_filter:
 2385  *
 2386  *      Set up the receive filter.
 2387  */
 2388 static void
 2389 stge_set_filter(struct stge_softc *sc)
 2390 {
 2391         struct ifnet *ifp = &sc->arpcom.ac_if;
 2392         uint16_t mode;
 2393 
 2394         mode = CSR_READ_2(sc, STGE_ReceiveMode);
 2395         mode |= RM_ReceiveUnicast;
 2396         if ((ifp->if_flags & IFF_BROADCAST) != 0)
 2397                 mode |= RM_ReceiveBroadcast;
 2398         else
 2399                 mode &= ~RM_ReceiveBroadcast;
 2400         if ((ifp->if_flags & IFF_PROMISC) != 0)
 2401                 mode |= RM_ReceiveAllFrames;
 2402         else
 2403                 mode &= ~RM_ReceiveAllFrames;
 2404 
 2405         CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
 2406 }
 2407 
 2408 static void
 2409 stge_set_multi(struct stge_softc *sc)
 2410 {
 2411         struct ifnet *ifp = &sc->arpcom.ac_if;
 2412         struct ifmultiaddr *ifma;
 2413         uint32_t crc;
 2414         uint32_t mchash[2];
 2415         uint16_t mode;
 2416         int count;
 2417 
 2418         mode = CSR_READ_2(sc, STGE_ReceiveMode);
 2419         if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
 2420                 if ((ifp->if_flags & IFF_PROMISC) != 0)
 2421                         mode |= RM_ReceiveAllFrames;
 2422                 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
 2423                         mode |= RM_ReceiveMulticast;
 2424                 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
 2425                 return;
 2426         }
 2427 
 2428         /* clear existing filters. */
 2429         CSR_WRITE_4(sc, STGE_HashTable0, 0);
 2430         CSR_WRITE_4(sc, STGE_HashTable1, 0);
 2431 
 2432         /*
 2433          * Set up the multicast address filter by passing all multicast
 2434          * addresses through a CRC generator, and then using the low-order
 2435          * 6 bits as an index into the 64 bit multicast hash table.  The
 2436          * high order bits select the register, while the rest of the bits
 2437          * select the bit within the register.
 2438          */
 2439 
 2440         bzero(mchash, sizeof(mchash));
 2441 
 2442         count = 0;
 2443         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 2444                 if (ifma->ifma_addr->sa_family != AF_LINK)
 2445                         continue;
 2446                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 2447                     ifma->ifma_addr), ETHER_ADDR_LEN);
 2448 
 2449                 /* Just want the 6 least significant bits. */
 2450                 crc &= 0x3f;
 2451 
 2452                 /* Set the corresponding bit in the hash table. */
 2453                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
 2454                 count++;
 2455         }
 2456 
 2457         mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
 2458         if (count > 0)
 2459                 mode |= RM_ReceiveMulticastHash;
 2460         else
 2461                 mode &= ~RM_ReceiveMulticastHash;
 2462 
 2463         CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
 2464         CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
 2465         CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
 2466 }
 2467 
 2468 static int
 2469 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
 2470 {
 2471         return (sysctl_int_range(oidp, arg1, arg2, req,
 2472             STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
 2473 }
 2474 
 2475 static int
 2476 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
 2477 {
 2478         return (sysctl_int_range(oidp, arg1, arg2, req,
 2479             STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));
 2480 }

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