The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/tx/if_txvar.h

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    1 /*-
    2  * Copyright (c) 1997 Semen Ustimenko
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: src/sys/dev/tx/if_txvar.h,v 1.14.2.1 2002/10/29 01:43:50 semenu Exp $
   27  * $DragonFly: src/sys/dev/netif/tx/if_txvar.h,v 1.7 2005/11/20 13:08:35 sephe Exp $
   28  */
   29 
   30 /*
   31  * Configuration
   32  */
   33 /*#define       EPIC_DIAG       1*/
   34 /*#define       EPIC_USEIOSPACE 1*/
   35 /*#define       EPIC_EARLY_RX   1*/
   36 
   37 #define TX_RING_SIZE            16              /* Leave this a power of 2 */
   38 #define RX_RING_SIZE            16              /* And this too, to do not */
   39                                                 /* confuse RX(TX)_RING_MASK */
   40 #define TX_RING_MASK            (TX_RING_SIZE - 1)
   41 #define RX_RING_MASK            (RX_RING_SIZE - 1)
   42 #define ETHER_MAX_FRAME_LEN     (ETHER_MAX_LEN + ETHER_CRC_LEN)
   43 
   44 /* This is driver's structure to define EPIC descriptors */
   45 struct epic_rx_buffer {
   46         struct mbuf             *mbuf;          /* mbuf receiving packet */
   47 };
   48 
   49 struct epic_tx_buffer {
   50         struct mbuf             *mbuf;          /* mbuf contained packet */
   51 };
   52 
   53 /* PHY, known by tx driver */
   54 #define EPIC_UNKN_PHY           0x0000
   55 #define EPIC_QS6612_PHY         0x0001
   56 #define EPIC_AC101_PHY          0x0002
   57 #define EPIC_LXT970_PHY         0x0003
   58 #define EPIC_SERIAL             0x0004
   59 
   60 /* Driver status structure */
   61 typedef struct {
   62         struct arpcom           arpcom;
   63         struct resource         *res;
   64         struct resource         *irq;
   65 
   66         device_t                miibus;
   67         device_t                dev;
   68         struct callout          tx_stat_timer;
   69 
   70         void                    *sc_ih;
   71         bus_space_tag_t         sc_st;
   72         bus_space_handle_t      sc_sh;
   73 
   74         struct epic_rx_buffer   rx_buffer[RX_RING_SIZE];
   75         struct epic_tx_buffer   tx_buffer[TX_RING_SIZE];
   76 
   77         /* Each element of array MUST be aligned on dword  */
   78         /* and bounded on PAGE_SIZE                        */
   79         struct epic_rx_desc     *rx_desc;
   80         struct epic_tx_desc     *tx_desc;
   81         struct epic_frag_list   *tx_flist;
   82         u_int32_t               flags;
   83         u_int32_t               tx_threshold;
   84         u_int32_t               txcon;
   85         u_int32_t               miicfg;
   86         u_int32_t               cur_tx;
   87         u_int32_t               cur_rx;
   88         u_int32_t               dirty_tx;
   89         u_int32_t               pending_txs;
   90         struct mii_softc        *physc;
   91         u_int32_t               phyid;
   92         int                     serinst;
   93         void                    *pool;
   94         u_int16_t               cardid;
   95 } epic_softc_t;
   96 
   97 struct epic_type {
   98         u_int16_t       ven_id;
   99         u_int16_t       dev_id;
  100         char            *name;
  101 };
  102 
  103 #define sc_if arpcom.ac_if
  104 #define sc_macaddr arpcom.ac_enaddr
  105 
  106 #define CSR_WRITE_4(sc, reg, val)                                       \
  107         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  108 #define CSR_WRITE_2(sc, reg, val)                                       \
  109         bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  110 #define CSR_WRITE_1(sc, reg, val)                                       \
  111         bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  112 #define CSR_READ_4(sc, reg)                                             \
  113         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
  114 #define CSR_READ_2(sc, reg)                                             \
  115         bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
  116 #define CSR_READ_1(sc, reg)                                             \
  117         bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
  118 
  119 #define PHY_READ_2(sc, phy, reg)                                        \
  120         epic_read_phy_reg((sc), (phy), (reg))
  121 #define PHY_WRITE_2(sc, phy, reg, val)                                  \
  122         epic_write_phy_reg((sc), (phy), (reg), (val))

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