Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/nfe/if_nfereg.h
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1 /* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $FreeBSD$ 19 */ 20 21 #define NFE_RX_RING_COUNT 256 22 #define NFE_JUMBO_RX_RING_COUNT NFE_RX_RING_COUNT 23 #define NFE_TX_RING_COUNT 256 24 25 #define NFE_PROC_DEFAULT ((NFE_RX_RING_COUNT * 3) / 4) 26 #define NFE_PROC_MIN 50 27 #define NFE_PROC_MAX (NFE_RX_RING_COUNT - 1) 28 29 #define NFE_INC(x, y) (x) = ((x) + 1) % y 30 31 /* RX/TX MAC addr + type + VLAN + align + slack */ 32 #define NFE_RX_HEADERS 64 33 34 /* Maximum MTU size. */ 35 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */ 36 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */ 37 38 #define NFE_JUMBO_FRAMELEN NV_PKTLIMIT_2 39 #define NFE_JUMBO_MTU \ 40 (NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS) 41 #define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 42 43 #define NFE_MAX_SCATTER 35 44 #define NFE_TSO_MAXSGSIZE 4096 45 #define NFE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 46 47 #define NFE_IRQ_STATUS 0x000 48 #define NFE_IRQ_MASK 0x004 49 #define NFE_SETUP_R6 0x008 50 #define NFE_IMTIMER 0x00c 51 #define NFE_MSI_MAP0 0x020 52 #define NFE_MSI_MAP1 0x024 53 #define NFE_MSI_IRQ_MASK 0x030 54 #define NFE_MAC_RESET 0x03c 55 #define NFE_MISC1 0x080 56 #define NFE_TX_CTL 0x084 57 #define NFE_TX_STATUS 0x088 58 #define NFE_RXFILTER 0x08c 59 #define NFE_RXBUFSZ 0x090 60 #define NFE_RX_CTL 0x094 61 #define NFE_RX_STATUS 0x098 62 #define NFE_RNDSEED 0x09c 63 #define NFE_SETUP_R1 0x0a0 64 #define NFE_SETUP_R2 0x0a4 65 #define NFE_MACADDR_HI 0x0a8 66 #define NFE_MACADDR_LO 0x0ac 67 #define NFE_MULTIADDR_HI 0x0b0 68 #define NFE_MULTIADDR_LO 0x0b4 69 #define NFE_MULTIMASK_HI 0x0b8 70 #define NFE_MULTIMASK_LO 0x0bc 71 #define NFE_PHY_IFACE 0x0c0 72 #define NFE_TX_RING_ADDR_LO 0x100 73 #define NFE_RX_RING_ADDR_LO 0x104 74 #define NFE_RING_SIZE 0x108 75 #define NFE_TX_UNK 0x10c 76 #define NFE_LINKSPEED 0x110 77 #define NFE_SETUP_R5 0x130 78 #define NFE_SETUP_R3 0x13C 79 #define NFE_SETUP_R7 0x140 80 #define NFE_RXTX_CTL 0x144 81 #define NFE_TX_RING_ADDR_HI 0x148 82 #define NFE_RX_RING_ADDR_HI 0x14c 83 #define NFE_TX_PAUSE_FRAME 0x170 84 #define NFE_PHY_STATUS 0x180 85 #define NFE_SETUP_R4 0x184 86 #define NFE_STATUS 0x188 87 #define NFE_PHY_SPEED 0x18c 88 #define NFE_PHY_CTL 0x190 89 #define NFE_PHY_DATA 0x194 90 #define NFE_TX_UNICAST 0x1a0 91 #define NFE_TX_MULTICAST 0x1a4 92 #define NFE_TX_BROADCAST 0x1a8 93 #define NFE_WOL_CTL 0x200 94 #define NFE_PATTERN_CRC 0x204 95 #define NFE_PATTERN_MASK 0x208 96 #define NFE_PWR_CAP 0x268 97 #define NFE_PWR_STATE 0x26c 98 #define NFE_TX_OCTET 0x280 99 #define NFE_TX_ZERO_REXMIT 0x284 100 #define NFE_TX_ONE_REXMIT 0x288 101 #define NFE_TX_MULTI_REXMIT 0x28c 102 #define NFE_TX_LATE_COL 0x290 103 #define NFE_TX_FIFO_UNDERUN 0x294 104 #define NFE_TX_CARRIER_LOST 0x298 105 #define NFE_TX_EXCESS_DEFERRAL 0x29c 106 #define NFE_TX_RETRY_ERROR 0x2a0 107 #define NFE_RX_FRAME_ERROR 0x2a4 108 #define NFE_RX_EXTRA_BYTES 0x2a8 109 #define NFE_RX_LATE_COL 0x2ac 110 #define NFE_RX_RUNT 0x2b0 111 #define NFE_RX_JUMBO 0x2b4 112 #define NFE_RX_FIFO_OVERUN 0x2b8 113 #define NFE_RX_CRC_ERROR 0x2bc 114 #define NFE_RX_FAE 0x2c0 115 #define NFE_RX_LEN_ERROR 0x2c4 116 #define NFE_RX_UNICAST 0x2c8 117 #define NFE_RX_MULTICAST 0x2cc 118 #define NFE_RX_BROADCAST 0x2d0 119 #define NFE_TX_DEFERAL 0x2d4 120 #define NFE_TX_FRAME 0x2d8 121 #define NFE_RX_OCTET 0x2dc 122 #define NFE_TX_PAUSE 0x2e0 123 #define NFE_RX_PAUSE 0x2e4 124 #define NFE_RX_DROP 0x2e8 125 #define NFE_VTAG_CTL 0x300 126 #define NFE_MSIX_MAP0 0x3e0 127 #define NFE_MSIX_MAP1 0x3e4 128 #define NFE_MSIX_IRQ_STATUS 0x3f0 129 #define NFE_PWR2_CTL 0x600 130 131 #define NFE_MAC_RESET_MAGIC 0x00f3 132 133 #define NFE_MAC_ADDR_INORDER 0x8000 134 135 #define NFE_PHY_ERROR 0x00001 136 #define NFE_PHY_WRITE 0x00400 137 #define NFE_PHY_BUSY 0x08000 138 #define NFE_PHYADD_SHIFT 5 139 140 #define NFE_STATUS_MAGIC 0x140000 141 142 #define NFE_R1_MAGIC_1000 0x14050f 143 #define NFE_R1_MAGIC_10_100 0x16070f 144 #define NFE_R1_MAGIC_DEFAULT 0x15050f 145 #define NFE_R2_MAGIC 0x16 146 #define NFE_R4_MAGIC 0x08 147 #define NFE_R6_MAGIC 0x03 148 #define NFE_WOL_MAGIC 0x1111 149 #define NFE_RX_START 0x01 150 #define NFE_TX_START 0x01 151 152 #define NFE_IRQ_RXERR 0x0001 153 #define NFE_IRQ_RX 0x0002 154 #define NFE_IRQ_RX_NOBUF 0x0004 155 #define NFE_IRQ_TXERR 0x0008 156 #define NFE_IRQ_TX_DONE 0x0010 157 #define NFE_IRQ_TIMER 0x0020 158 #define NFE_IRQ_LINK 0x0040 159 #define NFE_IRQ_TXERR2 0x0080 160 #define NFE_IRQ_TX1 0x0100 161 162 #define NFE_IRQ_WANTED \ 163 (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \ 164 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \ 165 NFE_IRQ_LINK) 166 167 #define NFE_RXTX_KICKTX 0x0001 168 #define NFE_RXTX_BIT1 0x0002 169 #define NFE_RXTX_BIT2 0x0004 170 #define NFE_RXTX_RESET 0x0010 171 #define NFE_RXTX_VTAG_STRIP 0x0040 172 #define NFE_RXTX_VTAG_INSERT 0x0080 173 #define NFE_RXTX_RXCSUM 0x0400 174 #define NFE_RXTX_V2MAGIC 0x2100 175 #define NFE_RXTX_V3MAGIC 0x2200 176 #define NFE_RXFILTER_MAGIC 0x007f0000 177 #define NFE_PFF_RX_PAUSE (1 << 3) 178 #define NFE_PFF_LOOPBACK (1 << 4) 179 #define NFE_PFF_U2M (1 << 5) 180 #define NFE_PFF_PROMISC (1 << 7) 181 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 182 183 /* default interrupt moderation timer of 128us */ 184 #define NFE_IM_DEFAULT ((128 * 100) / 1024) 185 186 #define NFE_VTAG_ENABLE (1 << 13) 187 188 #define NFE_PWR_VALID (1 << 8) 189 #define NFE_PWR_WAKEUP (1 << 15) 190 191 #define NFE_PWR2_WAKEUP_MASK 0x0f11 192 #define NFE_PWR2_REVA3 (1 << 0) 193 #define NFE_PWR2_GATE_CLOCKS 0x0f00 194 195 #define NFE_MEDIA_SET 0x10000 196 #define NFE_MEDIA_1000T 0x00032 197 #define NFE_MEDIA_100TX 0x00064 198 #define NFE_MEDIA_10T 0x003e8 199 200 #define NFE_PHY_100TX (1 << 0) 201 #define NFE_PHY_1000T (1 << 1) 202 #define NFE_PHY_HDX (1 << 8) 203 204 #define NFE_MISC1_MAGIC 0x003b0f3c 205 #define NFE_MISC1_TX_PAUSE (1 << 0) 206 #define NFE_MISC1_HDX (1 << 1) 207 208 #define NFE_TX_PAUSE_FRAME_DISABLE 0x1ff0080 209 #define NFE_TX_PAUSE_FRAME_ENABLE 0x0c00030 210 211 #define NFE_SEED_MASK 0x0003ff00 212 #define NFE_SEED_10T 0x00007f00 213 #define NFE_SEED_100TX 0x00002d00 214 #define NFE_SEED_1000T 0x00007400 215 216 #define NFE_NUM_MIB_STATV1 21 217 #define NFE_NUM_MIB_STATV2 27 218 #define NFE_NUM_MIB_STATV3 30 219 220 #define NFE_MSI_MESSAGES 8 221 #define NFE_MSI_VECTOR_0_ENABLED 0x01 222 223 /* 224 * It seems that nForce supports only the lower 40 bits of a DMA address. 225 */ 226 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 227 #define NFE_DMA_MAXADDR BUS_SPACE_MAXADDR 228 #else 229 #define NFE_DMA_MAXADDR 0xFFFFFFFFFF 230 #endif 231 232 #define NFE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 233 #define NFE_ADDR_HI(x) ((u_int64_t) (x) >> 32) 234 235 /* Rx/Tx descriptor */ 236 struct nfe_desc32 { 237 uint32_t physaddr; 238 uint16_t length; 239 uint16_t flags; 240 #define NFE_RX_FIXME_V1 0x6004 241 #define NFE_RX_VALID_V1 (1 << 0) 242 #define NFE_TX_ERROR_V1 0x7808 243 #define NFE_TX_LASTFRAG_V1 (1 << 0) 244 #define NFE_RX_ERROR1_V1 (1<<7) 245 #define NFE_RX_ERROR2_V1 (1<<8) 246 #define NFE_RX_ERROR3_V1 (1<<9) 247 #define NFE_RX_ERROR4_V1 (1<<10) 248 } __packed; 249 250 #define NFE_V1_TXERR "\020" \ 251 "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \ 252 "\08FORCEDINT\03RETRY\00LASTPACKET" 253 254 /* V2 Rx/Tx descriptor */ 255 struct nfe_desc64 { 256 uint32_t physaddr[2]; 257 uint32_t vtag; 258 #define NFE_RX_VTAG (1 << 16) 259 #define NFE_TX_VTAG (1 << 18) 260 uint16_t length; 261 uint16_t flags; 262 #define NFE_RX_FIXME_V2 0x4300 263 #define NFE_RX_VALID_V2 (1 << 13) 264 #define NFE_TX_ERROR_V2 0x5c04 265 #define NFE_TX_LASTFRAG_V2 (1 << 13) 266 #define NFE_RX_ERROR1_V2 (1<<2) 267 #define NFE_RX_ERROR2_V2 (1<<3) 268 #define NFE_RX_ERROR3_V2 (1<<4) 269 #define NFE_RX_ERROR4_V2 (1<<5) 270 } __packed; 271 272 #define NFE_V2_TXERR "\020" \ 273 "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY" 274 275 #define NFE_RING_ALIGN (sizeof(struct nfe_desc64)) 276 277 /* flags common to V1/V2 descriptors */ 278 #define NFE_RX_UDP_CSUMOK (1 << 10) 279 #define NFE_RX_TCP_CSUMOK (1 << 11) 280 #define NFE_RX_IP_CSUMOK (1 << 12) 281 #define NFE_RX_ERROR (1 << 14) 282 #define NFE_RX_READY (1 << 15) 283 #define NFE_RX_LEN_MASK 0x3fff 284 #define NFE_TX_TCP_UDP_CSUM (1 << 10) 285 #define NFE_TX_IP_CSUM (1 << 11) 286 #define NFE_TX_TSO (1 << 12) 287 #define NFE_TX_TSO_SHIFT 14 288 #define NFE_TX_VALID (1 << 15) 289 290 #define NFE_READ(sc, reg) \ 291 bus_read_4((sc)->nfe_res[0], (reg)) 292 293 #define NFE_WRITE(sc, reg, val) \ 294 bus_write_4((sc)->nfe_res[0], (reg), (val)) 295 296 #define NFE_TIMEOUT 1000 297 298 #ifndef PCI_VENDOR_NVIDIA 299 #define PCI_VENDOR_NVIDIA 0x10DE 300 #endif 301 302 #define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3 303 #define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066 304 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6 305 #define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086 306 #define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C 307 #define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6 308 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF 309 #define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056 310 #define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057 311 #define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037 312 #define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038 313 #define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268 314 #define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269 315 #define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372 316 #define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373 317 #define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5 318 #define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6 319 #define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee 320 #define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef 321 #define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450 322 #define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451 323 #define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452 324 #define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453 325 #define PCI_PRODUCT_NVIDIA_MCP67_LAN1 0x054c 326 #define PCI_PRODUCT_NVIDIA_MCP67_LAN2 0x054d 327 #define PCI_PRODUCT_NVIDIA_MCP67_LAN3 0x054e 328 #define PCI_PRODUCT_NVIDIA_MCP67_LAN4 0x054f 329 #define PCI_PRODUCT_NVIDIA_MCP73_LAN1 0x07dc 330 #define PCI_PRODUCT_NVIDIA_MCP73_LAN2 0x07dd 331 #define PCI_PRODUCT_NVIDIA_MCP73_LAN3 0x07de 332 #define PCI_PRODUCT_NVIDIA_MCP73_LAN4 0x07df 333 #define PCI_PRODUCT_NVIDIA_MCP77_LAN1 0x0760 334 #define PCI_PRODUCT_NVIDIA_MCP77_LAN2 0x0761 335 #define PCI_PRODUCT_NVIDIA_MCP77_LAN3 0x0762 336 #define PCI_PRODUCT_NVIDIA_MCP77_LAN4 0x0763 337 #define PCI_PRODUCT_NVIDIA_MCP79_LAN1 0x0ab0 338 #define PCI_PRODUCT_NVIDIA_MCP79_LAN2 0x0ab1 339 #define PCI_PRODUCT_NVIDIA_MCP79_LAN3 0x0ab2 340 #define PCI_PRODUCT_NVIDIA_MCP79_LAN4 0x0ab3 341 #define PCI_PRODUCT_NVIDIA_MCP89_LAN 0x0d7d 342 343 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 344 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 345 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 346 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 347 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 348 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 349 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 350 351 #define NFE_DEBUG 0x0000 352 #define NFE_DEBUG_INIT 0x0001 353 #define NFE_DEBUG_RUNNING 0x0002 354 #define NFE_DEBUG_DEINIT 0x0004 355 #define NFE_DEBUG_IOCTL 0x0008 356 #define NFE_DEBUG_INTERRUPT 0x0010 357 #define NFE_DEBUG_API 0x0020 358 #define NFE_DEBUG_LOCK 0x0040 359 #define NFE_DEBUG_BROKEN 0x0080 360 #define NFE_DEBUG_MII 0x0100 361 #define NFE_DEBUG_ALL 0xFFFF
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