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sys/dev/nsp/nsp.c
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1 /* $NecBSD: nsp.c,v 1.21.12.6 2001/06/29 06:27:52 honda Exp $ */ 2 /* $NetBSD$ */ 3 4 #define NSP_DEBUG 5 #define NSP_STATICS 6 #define NSP_IO_CONTROL_FLAGS \ 7 (NSP_READ_SUSPEND_IO | NSP_WRITE_SUSPEND_IO | \ 8 NSP_READ_FIFO_INTERRUPTS | NSP_WRITE_FIFO_INTERRUPTS | \ 9 NSP_USE_MEMIO | NSP_WAIT_FOR_SELECT) 10 11 /*- 12 * SPDX-License-Identifier: BSD-3-Clause 13 * 14 * Copyright (c) 1998, 1999, 2000, 2001 15 * NetBSD/pc98 porting staff. All rights reserved. 16 * 17 * Copyright (c) 1998, 1999, 2000, 2001 18 * Naofumi HONDA. All rights reserved. 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 1. Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * 2. Redistributions in binary form must reproduce the above copyright 26 * notice, this list of conditions and the following disclaimer in the 27 * documentation and/or other materials provided with the distribution. 28 * 3. The name of the author may not be used to endorse or promote products 29 * derived from this software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 34 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 35 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 40 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/bio.h> 51 #include <sys/buf.h> 52 #include <sys/queue.h> 53 #include <sys/malloc.h> 54 #include <sys/errno.h> 55 #include <sys/rman.h> 56 57 #include <machine/cpu.h> 58 #include <machine/bus.h> 59 60 #include <cam/scsi/scsi_low.h> 61 #include <dev/nsp/nspreg.h> 62 #include <dev/nsp/nspvar.h> 63 64 /*************************************************** 65 * USER SETTINGS 66 ***************************************************/ 67 /* DEVICE CONFIGURATION FLAGS (MINOR) 68 * 69 * 0x01 DISCONNECT OFF 70 * 0x02 PARITY LINE OFF 71 * 0x04 IDENTIFY MSG OFF ( = single lun) 72 * 0x08 SYNC TRANSFER OFF 73 */ 74 75 /*************************************************** 76 * PARAMS 77 ***************************************************/ 78 #define NSP_NTARGETS 8 79 #define NSP_NLUNS 8 80 81 #define NSP_MAX_DATA_SIZE (64 * 1024) 82 #define NSP_SELTIMEOUT (200) 83 #define NSP_DELAY_MAX (2 * 1000 * 1000) 84 #define NSP_DELAY_INTERVAL (1) 85 #define NSP_TIMER_1MS (1000 / 51) 86 87 /*************************************************** 88 * DEBUG 89 ***************************************************/ 90 #ifdef NSP_DEBUG 91 int nsp_debug; 92 #endif /* NSP_DEBUG */ 93 94 #ifdef NSP_STATICS 95 struct nsp_statics { 96 int arbit_conflict_1; 97 int arbit_conflict_2; 98 int device_data_write; 99 int device_busy; 100 int disconnect; 101 int reselect; 102 int data_phase_bypass; 103 } nsp_statics; 104 #endif /* NSP_STATICS */ 105 106 /*************************************************** 107 * IO control 108 ***************************************************/ 109 #define NSP_READ_SUSPEND_IO 0x0001 110 #define NSP_WRITE_SUSPEND_IO 0x0002 111 #define NSP_USE_MEMIO 0x0004 112 #define NSP_READ_FIFO_INTERRUPTS 0x0010 113 #define NSP_WRITE_FIFO_INTERRUPTS 0x0020 114 #define NSP_WAIT_FOR_SELECT 0x0100 115 116 u_int nsp_io_control = NSP_IO_CONTROL_FLAGS; 117 int nsp_read_suspend_bytes = DEV_BSIZE; 118 int nsp_write_suspend_bytes = DEV_BSIZE; 119 int nsp_read_interrupt_bytes = 4096; 120 int nsp_write_interrupt_bytes = 4096; 121 122 /*************************************************** 123 * DEVICE STRUCTURE 124 ***************************************************/ 125 extern struct cfdriver nsp_cd; 126 127 /************************************************************** 128 * DECLARE 129 **************************************************************/ 130 #define NSP_FIFO_ON 1 131 #define NSP_FIFO_OFF 0 132 static void nsp_pio_read(struct nsp_softc *, int); 133 static void nsp_pio_write(struct nsp_softc *, int); 134 static int nsp_xfer(struct nsp_softc *, u_int8_t *, int, int, int); 135 static int nsp_msg(struct nsp_softc *, struct targ_info *, u_int); 136 static int nsp_reselected(struct nsp_softc *); 137 static int nsp_disconnected(struct nsp_softc *, struct targ_info *); 138 static void nsp_pdma_end(struct nsp_softc *, struct targ_info *); 139 static void nsphw_init(struct nsp_softc *); 140 static int nsp_target_nexus_establish(struct nsp_softc *); 141 static int nsp_lun_nexus_establish(struct nsp_softc *); 142 static int nsp_ccb_nexus_establish(struct nsp_softc *); 143 static int nsp_world_start(struct nsp_softc *, int); 144 static int nsphw_start_selection(struct nsp_softc *sc, struct slccb *); 145 static void nsphw_bus_reset(struct nsp_softc *); 146 static void nsphw_attention(struct nsp_softc *); 147 static u_int nsp_fifo_count(struct nsp_softc *); 148 static u_int nsp_request_count(struct nsp_softc *); 149 static int nsp_negate_signal(struct nsp_softc *, u_int8_t, u_char *); 150 static int nsp_expect_signal(struct nsp_softc *, u_int8_t, u_int8_t); 151 static void nsp_start_timer(struct nsp_softc *, int); 152 static void nsp_setup_fifo(struct nsp_softc *, int, int, int); 153 static int nsp_targ_init(struct nsp_softc *, struct targ_info *, int); 154 static void nsphw_selection_done_and_expect_msgout(struct nsp_softc *); 155 static void nsp_data_padding(struct nsp_softc *, int, u_int); 156 static int nsp_timeout(struct nsp_softc *); 157 static int nsp_read_fifo(struct nsp_softc *, int); 158 static int nsp_write_fifo(struct nsp_softc *, int); 159 static int nsp_phase_match(struct nsp_softc *, u_int8_t, u_int8_t); 160 static int nsp_wait_interrupt(struct nsp_softc *); 161 162 struct scsi_low_funcs nspfuncs = { 163 SC_LOW_INIT_T nsp_world_start, 164 SC_LOW_BUSRST_T nsphw_bus_reset, 165 SC_LOW_TARG_INIT_T nsp_targ_init, 166 SC_LOW_LUN_INIT_T NULL, 167 168 SC_LOW_SELECT_T nsphw_start_selection, 169 SC_LOW_NEXUS_T nsp_lun_nexus_establish, 170 SC_LOW_NEXUS_T nsp_ccb_nexus_establish, 171 172 SC_LOW_ATTEN_T nsphw_attention, 173 SC_LOW_MSG_T nsp_msg, 174 175 SC_LOW_TIMEOUT_T nsp_timeout, 176 SC_LOW_POLL_T nspintr, 177 178 NULL, 179 }; 180 181 /**************************************************** 182 * hwfuncs 183 ****************************************************/ 184 static __inline uint8_t 185 nsp_cr_read_1(struct resource *res, bus_addr_t ofs) 186 { 187 188 bus_write_1(res, nsp_idxr, ofs); 189 return bus_read_1(res, nsp_datar); 190 } 191 192 static __inline void 193 nsp_cr_write_1(struct resource *res, bus_addr_t ofs, uint8_t va) 194 { 195 196 bus_write_1(res, nsp_idxr, ofs); 197 bus_write_1(res, nsp_datar, va); 198 } 199 200 static int 201 nsp_expect_signal(struct nsp_softc *sc, u_int8_t curphase, u_int8_t mask) 202 { 203 struct scsi_low_softc *slp = &sc->sc_sclow; 204 int wc; 205 u_int8_t ph, isrc; 206 207 for (wc = 0; wc < NSP_DELAY_MAX / NSP_DELAY_INTERVAL; wc ++) 208 { 209 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 210 if (ph == (u_int8_t) -1) 211 return -1; 212 213 isrc = bus_read_1(sc->port_res, nsp_irqsr); 214 if (isrc & IRQSR_SCSI) 215 return 0; 216 217 if ((ph & mask) != 0 && (ph & SCBUSMON_PHMASK) == curphase) 218 return 1; 219 220 DELAY(NSP_DELAY_INTERVAL); 221 } 222 223 device_printf(slp->sl_dev, "nsp_expect_signal timeout\n"); 224 return -1; 225 } 226 227 static void 228 nsphw_init(sc) 229 struct nsp_softc *sc; 230 { 231 232 /* block all interrupts */ 233 bus_write_1(sc->port_res, nsp_irqcr, IRQCR_ALLMASK); 234 235 /* setup SCSI interface */ 236 bus_write_1(sc->port_res, nsp_ifselr, IFSELR_IFSEL); 237 238 nsp_cr_write_1(sc->port_res, NSPR_SCIENR, 0); 239 240 nsp_cr_write_1(sc->port_res, NSPR_XFERMR, XFERMR_IO8); 241 nsp_cr_write_1(sc->port_res, NSPR_CLKDIVR, sc->sc_iclkdiv); 242 243 nsp_cr_write_1(sc->port_res, NSPR_SCIENR, sc->sc_icr); 244 nsp_cr_write_1(sc->port_res, NSPR_PARITYR, sc->sc_parr); 245 nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, 246 PTCLRR_ACK | PTCLRR_REQ | PTCLRR_HOST | PTCLRR_RSS); 247 248 /* setup fifo asic */ 249 bus_write_1(sc->port_res, nsp_ifselr, IFSELR_REGSEL); 250 nsp_cr_write_1(sc->port_res, NSPR_TERMPWRC, 0); 251 if ((nsp_cr_read_1(sc->port_res, NSPR_OCR) & OCR_TERMPWRS) == 0) 252 nsp_cr_write_1(sc->port_res, NSPR_TERMPWRC, TERMPWRC_POWON); 253 254 nsp_cr_write_1(sc->port_res, NSPR_XFERMR, XFERMR_IO8); 255 nsp_cr_write_1(sc->port_res, NSPR_CLKDIVR, sc->sc_clkdiv); 256 nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, 0); 257 nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, 0); 258 259 nsp_cr_write_1(sc->port_res, NSPR_SYNCR, 0); 260 nsp_cr_write_1(sc->port_res, NSPR_ACKWIDTH, 0); 261 262 /* enable interrupts and ack them */ 263 nsp_cr_write_1(sc->port_res, NSPR_SCIENR, sc->sc_icr); 264 bus_write_1(sc->port_res, nsp_irqcr, IRQSR_MASK); 265 266 nsp_setup_fifo(sc, NSP_FIFO_OFF, SCSI_LOW_READ, 0); 267 } 268 269 /**************************************************** 270 * scsi low interface 271 ****************************************************/ 272 static void 273 nsphw_attention(sc) 274 struct nsp_softc *sc; 275 { 276 u_int8_t cr; 277 278 cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR)/* & ~SCBUSCR_ACK */; 279 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr | SCBUSCR_ATN); 280 DELAY(10); 281 } 282 283 static void 284 nsphw_bus_reset(sc) 285 struct nsp_softc *sc; 286 { 287 int i; 288 289 bus_write_1(sc->port_res, nsp_irqcr, IRQCR_ALLMASK); 290 291 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, SCBUSCR_RST); 292 DELAY(100 * 1000); /* 100ms */ 293 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, 0); 294 for (i = 0; i < 5; i ++) 295 (void) nsp_cr_read_1(sc->port_res, NSPR_IRQPHS); 296 297 bus_write_1(sc->port_res, nsp_irqcr, IRQSR_MASK); 298 } 299 300 static void 301 nsphw_selection_done_and_expect_msgout(sc) 302 struct nsp_softc *sc; 303 { 304 struct scsi_low_softc *slp = &sc->sc_sclow; 305 306 /* clear ack counter */ 307 sc->sc_cnt = 0; 308 nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, PTCLRR_PT | PTCLRR_ACK | 309 PTCLRR_REQ | PTCLRR_HOST); 310 311 /* deassert sel and assert atten */ 312 sc->sc_seltout = 0; 313 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, sc->sc_busc); 314 DELAY(1); 315 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, 316 sc->sc_busc | SCBUSCR_ADIR | SCBUSCR_ACKEN); 317 SCSI_LOW_ASSERT_ATN(slp); 318 } 319 320 static int 321 nsphw_start_selection(sc, cb) 322 struct nsp_softc *sc; 323 struct slccb *cb; 324 { 325 struct scsi_low_softc *slp = &sc->sc_sclow; 326 struct targ_info *ti = cb->ti; 327 register u_int8_t arbs, ph; 328 int wc; 329 330 wc = sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 331 sc->sc_dataout_timeout = 0; 332 333 /* check bus free */ 334 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 335 if (ph != SCBUSMON_FREE) 336 { 337 #ifdef NSP_STATICS 338 nsp_statics.arbit_conflict_1 ++; 339 #endif /* NSP_STATICS */ 340 return SCSI_LOW_START_FAIL; 341 } 342 343 /* start arbitration */ 344 nsp_cr_write_1(sc->port_res, NSPR_ARBITS, ARBITS_EXEC); 345 346 SCSI_LOW_SETUP_PHASE(ti, PH_ARBSTART); 347 do 348 { 349 /* XXX: what a stupid chip! */ 350 arbs = nsp_cr_read_1(sc->port_res, NSPR_ARBITS); 351 DELAY(1); 352 } 353 while ((arbs & (ARBITS_WIN | ARBITS_FAIL)) == 0 && wc -- > 0); 354 355 if ((arbs & ARBITS_WIN) == 0) 356 { 357 nsp_cr_write_1(sc->port_res, NSPR_ARBITS, ARBITS_CLR); 358 #ifdef NSP_STATICS 359 nsp_statics.arbit_conflict_2 ++; 360 #endif /* NSP_STATICS */ 361 return SCSI_LOW_START_FAIL; 362 } 363 364 /* assert select line */ 365 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART); 366 scsi_low_arbit_win(slp); 367 368 DELAY(3); 369 nsp_cr_write_1(sc->port_res, NSPR_DATA, 370 sc->sc_idbit | (1 << ti->ti_id)); 371 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, 372 SCBUSCR_SEL | SCBUSCR_BSY | sc->sc_busc); 373 DELAY(3); 374 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, SCBUSCR_SEL | 375 SCBUSCR_BSY | SCBUSCR_DOUT | sc->sc_busc); 376 nsp_cr_write_1(sc->port_res, NSPR_ARBITS, ARBITS_CLR); 377 DELAY(3); 378 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, 379 SCBUSCR_SEL | SCBUSCR_DOUT | sc->sc_busc); 380 DELAY(1); 381 382 if ((nsp_io_control & NSP_WAIT_FOR_SELECT) != 0) 383 { 384 #define NSP_FIRST_SEL_WAIT 300 385 #define NSP_SEL_CHECK_INTERVAL 10 386 387 /* wait for a selection response */ 388 for (wc = 0; wc < NSP_FIRST_SEL_WAIT / NSP_SEL_CHECK_INTERVAL; 389 wc ++) 390 { 391 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 392 if ((ph & SCBUSMON_BSY) == 0) 393 { 394 DELAY(NSP_SEL_CHECK_INTERVAL); 395 continue; 396 } 397 398 DELAY(1); 399 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 400 if ((ph & SCBUSMON_BSY) != 0) 401 { 402 nsphw_selection_done_and_expect_msgout(sc); 403 404 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED); 405 return SCSI_LOW_START_OK; 406 } 407 } 408 } 409 410 /* check a selection timeout */ 411 nsp_start_timer(sc, NSP_TIMER_1MS); 412 sc->sc_seltout = 1; 413 return SCSI_LOW_START_OK; 414 } 415 416 static int 417 nsp_world_start(sc, fdone) 418 struct nsp_softc *sc; 419 int fdone; 420 { 421 struct scsi_low_softc *slp = &sc->sc_sclow; 422 423 sc->sc_cnt = 0; 424 sc->sc_seltout = 0; 425 426 if ((slp->sl_cfgflags & CFG_NOATTEN) == 0) 427 sc->sc_busc = SCBUSCR_ATN; 428 else 429 sc->sc_busc = 0; 430 431 if ((slp->sl_cfgflags & CFG_NOPARITY) == 0) 432 sc->sc_parr = PARITYR_ENABLE | PARITYR_CLEAR; 433 else 434 sc->sc_parr = 0; 435 436 sc->sc_icr = (SCIENR_SCCHG | SCIENR_RESEL | SCIENR_RST); 437 438 nsphw_init(sc); 439 scsi_low_bus_reset(slp); 440 441 return 0; 442 } 443 444 struct ncp_synch_data { 445 u_int min_period; 446 u_int max_period; 447 u_int chip_period; 448 u_int ack_width; 449 }; 450 451 static struct ncp_synch_data ncp_sync_data_40M[] = { 452 {0x0c,0x0c,0x1,0}, /* 20MB 50ns*/ 453 {0x19,0x19,0x3,1}, /* 10MB 100ns*/ 454 {0x1a,0x25,0x5,2}, /* 7.5MB 150ns*/ 455 {0x26,0x32,0x7,3}, /* 5MB 200ns*/ 456 {0x0, 0, 0, 0} 457 }; 458 459 static struct ncp_synch_data ncp_sync_data_20M[] = { 460 {0x19,0x19,0x1,0}, /* 10MB 100ns*/ 461 {0x1a,0x25,0x2,0}, /* 7.5MB 150ns*/ 462 {0x26,0x32,0x3,1}, /* 5MB 200ns*/ 463 {0x0, 0, 0, 0} 464 }; 465 466 static int 467 nsp_msg(sc, ti, msg) 468 struct nsp_softc *sc; 469 struct targ_info *ti; 470 u_int msg; 471 { 472 struct ncp_synch_data *sdp; 473 struct nsp_targ_info *nti = (void *) ti; 474 u_int period, offset; 475 int i, error; 476 477 if ((msg & SCSI_LOW_MSG_WIDE) != 0) 478 { 479 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8) 480 { 481 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 482 return EINVAL; 483 } 484 return 0; 485 } 486 487 if ((msg & SCSI_LOW_MSG_SYNCH) == 0) 488 return 0; 489 490 period = ti->ti_maxsynch.period; 491 offset = ti->ti_maxsynch.offset; 492 if (sc->sc_iclkdiv == CLKDIVR_20M) 493 sdp = &ncp_sync_data_20M[0]; 494 else 495 sdp = &ncp_sync_data_40M[0]; 496 497 for (i = 0; sdp->max_period != 0; i ++, sdp ++) 498 { 499 if (period >= sdp->min_period && period <= sdp->max_period) 500 break; 501 } 502 503 if (period != 0 && sdp->max_period == 0) 504 { 505 /* 506 * NO proper period/offset found, 507 * Retry neg with the target. 508 */ 509 ti->ti_maxsynch.period = 0; 510 ti->ti_maxsynch.offset = 0; 511 nti->nti_reg_syncr = 0; 512 nti->nti_reg_ackwidth = 0; 513 error = EINVAL; 514 } 515 else 516 { 517 nti->nti_reg_syncr = (sdp->chip_period << SYNCR_PERS) | 518 (offset & SYNCR_OFFM); 519 nti->nti_reg_ackwidth = sdp->ack_width; 520 error = 0; 521 } 522 523 nsp_cr_write_1(sc->port_res, NSPR_SYNCR, nti->nti_reg_syncr); 524 nsp_cr_write_1(sc->port_res, NSPR_ACKWIDTH, nti->nti_reg_ackwidth); 525 return error; 526 } 527 528 static int 529 nsp_targ_init(sc, ti, action) 530 struct nsp_softc *sc; 531 struct targ_info *ti; 532 int action; 533 { 534 struct nsp_targ_info *nti = (void *) ti; 535 536 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE) 537 { 538 ti->ti_width = SCSI_LOW_BUS_WIDTH_8; 539 ti->ti_maxsynch.period = 100 / 4; 540 ti->ti_maxsynch.offset = 15; 541 nti->nti_reg_syncr = 0; 542 nti->nti_reg_ackwidth = 0; 543 } 544 return 0; 545 } 546 547 static void 548 nsp_start_timer(sc, time) 549 struct nsp_softc *sc; 550 int time; 551 { 552 553 sc->sc_timer = time; 554 nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, time); 555 } 556 557 /************************************************************** 558 * General probe attach 559 **************************************************************/ 560 int 561 nspprobesubr(struct resource *res, u_int dvcfg) 562 { 563 u_int8_t regv; 564 565 regv = bus_read_1(res, nsp_fifosr); 566 if (regv < 0x11 || regv >= 0x20) 567 return 0; 568 return 1; 569 } 570 571 void 572 nspattachsubr(sc) 573 struct nsp_softc *sc; 574 { 575 struct scsi_low_softc *slp = &sc->sc_sclow; 576 577 sc->sc_idbit = (1 << slp->sl_hostid); 578 slp->sl_flags |= HW_READ_PADDING; 579 slp->sl_funcs = &nspfuncs; 580 sc->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */ 581 582 (void) scsi_low_attach(slp, 0, NSP_NTARGETS, NSP_NLUNS, 583 sizeof(struct nsp_targ_info), 0); 584 } 585 586 /************************************************************** 587 * PDMA functions 588 **************************************************************/ 589 static u_int 590 nsp_fifo_count(sc) 591 struct nsp_softc *sc; 592 { 593 u_int count; 594 595 nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, PTCLRR_RSS_ACK | PTCLRR_PT); 596 count = bus_read_1(sc->port_res, nsp_datar); 597 count += (((u_int) bus_read_1(sc->port_res, nsp_datar)) << 8); 598 count += (((u_int) bus_read_1(sc->port_res, nsp_datar)) << 16); 599 return count; 600 } 601 602 static u_int 603 nsp_request_count(sc) 604 struct nsp_softc *sc; 605 { 606 u_int count; 607 608 nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, PTCLRR_RSS_REQ | PTCLRR_PT); 609 count = bus_read_1(sc->port_res, nsp_datar); 610 count += (((u_int) bus_read_1(sc->port_res, nsp_datar)) << 8); 611 count += (((u_int) bus_read_1(sc->port_res, nsp_datar)) << 16); 612 return count; 613 } 614 615 static void 616 nsp_setup_fifo(sc, on, direction, datalen) 617 struct nsp_softc *sc; 618 int on; 619 int direction; 620 int datalen; 621 { 622 u_int8_t xfermode; 623 624 sc->sc_suspendio = 0; 625 if (on == NSP_FIFO_OFF) 626 { 627 xfermode = XFERMR_IO8; 628 goto out; 629 } 630 631 /* check if suspend io OK ? */ 632 if (datalen > 0) 633 { 634 if (direction == SCSI_LOW_READ) 635 { 636 if ((nsp_io_control & NSP_READ_SUSPEND_IO) != 0 && 637 (datalen % nsp_read_suspend_bytes) == 0) 638 sc->sc_suspendio = nsp_read_suspend_bytes; 639 } 640 else 641 { 642 if ((nsp_io_control & NSP_WRITE_SUSPEND_IO) != 0 && 643 (datalen % nsp_write_suspend_bytes) == 0) 644 sc->sc_suspendio = nsp_write_suspend_bytes; 645 } 646 } 647 648 /* determine a transfer type */ 649 if (datalen < DEV_BSIZE || (datalen & 3) != 0) 650 { 651 if (sc->mem_res != NULL && 652 (nsp_io_control & NSP_USE_MEMIO) != 0) 653 xfermode = XFERMR_XEN | XFERMR_MEM8; 654 else 655 xfermode = XFERMR_XEN | XFERMR_IO8; 656 } 657 else 658 { 659 if (sc->mem_res != NULL && 660 (nsp_io_control & NSP_USE_MEMIO) != 0) 661 xfermode = XFERMR_XEN | XFERMR_MEM32; 662 else 663 xfermode = XFERMR_XEN | XFERMR_IO32; 664 665 if (sc->sc_suspendio > 0) 666 xfermode |= XFERMR_FIFOEN; 667 } 668 669 out: 670 sc->sc_xfermr = xfermode; 671 nsp_cr_write_1(sc->port_res, NSPR_XFERMR, sc->sc_xfermr); 672 } 673 674 static void 675 nsp_pdma_end(sc, ti) 676 struct nsp_softc *sc; 677 struct targ_info *ti; 678 { 679 struct scsi_low_softc *slp = &sc->sc_sclow; 680 struct slccb *cb = slp->sl_Qnexus; 681 u_int len = 0, cnt; 682 683 sc->sc_dataout_timeout = 0; 684 slp->sl_flags &= ~HW_PDMASTART; 685 nsp_setup_fifo(sc, NSP_FIFO_OFF, SCSI_LOW_READ, 0); 686 if ((sc->sc_icr & SCIENR_FIFO) != 0) 687 { 688 sc->sc_icr &= ~SCIENR_FIFO; 689 nsp_cr_write_1(sc->port_res, NSPR_SCIENR, sc->sc_icr); 690 } 691 692 if (cb == NULL) 693 { 694 slp->sl_error |= PDMAERR; 695 return; 696 } 697 698 if (ti->ti_phase == PH_DATA) 699 { 700 cnt = nsp_fifo_count(sc); 701 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE) 702 { 703 len = sc->sc_cnt - cnt; 704 if (sc->sc_cnt >= cnt && 705 slp->sl_scp.scp_datalen + len <= 706 cb->ccb_scp.scp_datalen) 707 { 708 slp->sl_scp.scp_data -= len; 709 slp->sl_scp.scp_datalen += len; 710 } 711 else 712 { 713 slp->sl_error |= PDMAERR; 714 device_printf(slp->sl_dev, 715 "len %x >= datalen %x\n", 716 len, slp->sl_scp.scp_datalen); 717 } 718 } 719 else if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 720 { 721 if (sc->sc_cnt != cnt || 722 sc->sc_cnt > cb->ccb_scp.scp_datalen) 723 { 724 slp->sl_error |= PDMAERR; 725 device_printf(slp->sl_dev, 726 "data read count error %x != %x (%x)\n", 727 sc->sc_cnt, cnt, 728 cb->ccb_scp.scp_datalen); 729 } 730 } 731 sc->sc_cnt = cnt; 732 scsi_low_data_finish(slp); 733 } 734 else 735 { 736 737 device_printf(slp->sl_dev, "data phase miss\n"); 738 slp->sl_error |= PDMAERR; 739 } 740 } 741 742 #define RFIFO_CRIT 64 743 #define WFIFO_CRIT 32 744 745 static void 746 nsp_data_padding(sc, direction, count) 747 struct nsp_softc *sc; 748 int direction; 749 u_int count; 750 { 751 752 if (count > NSP_MAX_DATA_SIZE) 753 count = NSP_MAX_DATA_SIZE; 754 755 nsp_cr_write_1(sc->port_res, NSPR_XFERMR, XFERMR_XEN | XFERMR_IO8); 756 if (direction == SCSI_LOW_READ) 757 { 758 while (count -- > 0) 759 (void) bus_read_1(sc->port_res, nsp_fifodr); 760 } 761 else 762 { 763 while (count -- > 0) 764 (void) bus_write_1(sc->port_res, nsp_fifodr, 0); 765 } 766 nsp_cr_write_1(sc->port_res, NSPR_XFERMR, sc->sc_xfermr); 767 } 768 769 static int 770 nsp_read_fifo(sc, suspendio) 771 struct nsp_softc *sc; 772 int suspendio; 773 { 774 struct scsi_low_softc *slp = &sc->sc_sclow; 775 u_int res; 776 777 res = nsp_fifo_count(sc); 778 if (res == sc->sc_cnt) 779 return 0; 780 781 #ifdef NSP_DEBUG 782 if (res < sc->sc_cnt || res == (u_int) -1) 783 { 784 device_printf(slp->sl_dev, 785 "strange fifo ack count 0x%x < 0x%x\n", res, sc->sc_cnt); 786 return 0; 787 } 788 #endif /* NSP_DEBUG */ 789 790 res = res - sc->sc_cnt; 791 if (res > slp->sl_scp.scp_datalen) 792 { 793 if ((slp->sl_error & PDMAERR) == 0) 794 { 795 device_printf(slp->sl_dev, "data overrun 0x%x > 0x%x\n", 796 res, slp->sl_scp.scp_datalen); 797 } 798 799 slp->sl_error |= PDMAERR; 800 slp->sl_scp.scp_datalen = 0; 801 802 if ((slp->sl_flags & HW_READ_PADDING) == 0) 803 { 804 device_printf(slp->sl_dev, "read padding required\n"); 805 return 0; 806 } 807 808 nsp_data_padding(sc, SCSI_LOW_READ, res); 809 sc->sc_cnt += res; 810 return 1; /* padding start */ 811 } 812 813 if (suspendio > 0 && slp->sl_scp.scp_datalen >= suspendio) 814 res = suspendio; 815 816 if ((sc->sc_xfermr & (XFERMR_MEM32 | XFERMR_MEM8)) != 0) 817 { 818 if ((sc->sc_xfermr & XFERMR_MEM32) != 0) 819 { 820 res &= ~3; 821 bus_read_region_4(sc->mem_res, 0, 822 (u_int32_t *) slp->sl_scp.scp_data, res >> 2); 823 } 824 else 825 { 826 bus_read_region_1(sc->mem_res, 0, 827 (u_int8_t *) slp->sl_scp.scp_data, res); 828 } 829 } 830 else 831 { 832 if ((sc->sc_xfermr & XFERMR_IO32) != 0) 833 { 834 res &= ~3; 835 bus_read_multi_4(sc->port_res, nsp_fifodr, 836 (u_int32_t *) slp->sl_scp.scp_data, res >> 2); 837 } 838 else 839 { 840 bus_read_multi_1(sc->port_res, nsp_fifodr, 841 (u_int8_t *) slp->sl_scp.scp_data, res); 842 } 843 } 844 845 if (nsp_cr_read_1(sc->port_res, NSPR_PARITYR) & PARITYR_PE) 846 { 847 nsp_cr_write_1(sc->port_res, NSPR_PARITYR, 848 PARITYR_ENABLE | PARITYR_CLEAR); 849 scsi_low_assert_msg(slp, slp->sl_Tnexus, SCSI_LOW_MSG_ERROR, 1); 850 } 851 852 slp->sl_scp.scp_data += res; 853 slp->sl_scp.scp_datalen -= res; 854 sc->sc_cnt += res; 855 return 0; 856 } 857 858 static int 859 nsp_write_fifo(sc, suspendio) 860 struct nsp_softc *sc; 861 int suspendio; 862 { 863 struct scsi_low_softc *slp = &sc->sc_sclow; 864 u_int res; 865 register u_int8_t stat; 866 867 if (suspendio > 0) 868 { 869 #ifdef NSP_DEBUG 870 if ((slp->sl_scp.scp_datalen % WFIFO_CRIT) != 0) 871 { 872 device_printf(slp->sl_dev, 873 "strange write length 0x%x\n", 874 slp->sl_scp.scp_datalen); 875 } 876 #endif /* NSP_DEBUG */ 877 res = slp->sl_scp.scp_datalen % suspendio; 878 if (res == 0) 879 { 880 res = suspendio; 881 } 882 } 883 else 884 { 885 res = WFIFO_CRIT; 886 } 887 888 if (res > slp->sl_scp.scp_datalen) 889 res = slp->sl_scp.scp_datalen; 890 891 /* XXX: reconfirm! */ 892 stat = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON) & SCBUSMON_PHMASK; 893 if (stat != PHASE_DATAOUT) 894 return 0; 895 896 if ((sc->sc_xfermr & (XFERMR_MEM32 | XFERMR_MEM8)) != 0) 897 { 898 if ((sc->sc_xfermr & XFERMR_MEM32) != 0) 899 { 900 bus_write_region_4(sc->mem_res, 0, 901 (u_int32_t *) slp->sl_scp.scp_data, res >> 2); 902 } 903 else 904 { 905 bus_write_region_1(sc->mem_res, 0, 906 (u_int8_t *) slp->sl_scp.scp_data, res); 907 } 908 } 909 else 910 { 911 if ((sc->sc_xfermr & XFERMR_IO32) != 0) 912 { 913 bus_write_multi_4(sc->port_res, nsp_fifodr, 914 (u_int32_t *) slp->sl_scp.scp_data, res >> 2); 915 } 916 else 917 { 918 bus_write_multi_1(sc->port_res, nsp_fifodr, 919 (u_int8_t *) slp->sl_scp.scp_data, res); 920 } 921 } 922 923 slp->sl_scp.scp_datalen -= res; 924 slp->sl_scp.scp_data += res; 925 sc->sc_cnt += res; 926 return 0; 927 } 928 929 static int 930 nsp_wait_interrupt(sc) 931 struct nsp_softc *sc; 932 { 933 int tout; 934 register u_int8_t isrc; 935 936 for (tout = 0; tout < DEV_BSIZE / 10; tout ++) 937 { 938 isrc = bus_read_1(sc->port_res, nsp_irqsr); 939 if ((isrc & (IRQSR_SCSI | IRQSR_FIFO)) != 0) 940 { 941 if ((isrc & IRQSR_FIFO) != 0) 942 { 943 bus_write_1(sc->port_res, 944 nsp_irqcr, IRQCR_FIFOCL); 945 } 946 return 1; 947 } 948 DELAY(1); 949 } 950 return 0; 951 } 952 953 static void 954 nsp_pio_read(sc, suspendio) 955 struct nsp_softc *sc; 956 int suspendio; 957 { 958 struct scsi_low_softc *slp = &sc->sc_sclow; 959 int tout, padding, datalen; 960 register u_int8_t stat, fstat; 961 962 padding = 0; 963 tout = sc->sc_tmaxcnt; 964 slp->sl_flags |= HW_PDMASTART; 965 datalen = slp->sl_scp.scp_datalen; 966 967 ReadLoop: 968 while (1) 969 { 970 stat = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 971 if (stat == (u_int8_t) -1) 972 return; 973 974 /* out of data phase */ 975 if ((stat & SCBUSMON_PHMASK) != PHASE_DATAIN) 976 { 977 nsp_read_fifo(sc, 0); 978 return; 979 } 980 981 /* data phase */ 982 fstat = bus_read_1(sc->port_res, nsp_fifosr); 983 if ((fstat & FIFOSR_FULLEMP) != 0) 984 { 985 if ((sc->sc_icr & SCIENR_FIFO) != 0) 986 { 987 bus_write_1(sc->port_res, nsp_irqcr, 988 IRQCR_FIFOCL); 989 } 990 991 if (suspendio > 0) 992 { 993 padding |= nsp_read_fifo(sc, suspendio); 994 } 995 else 996 { 997 padding |= nsp_read_fifo(sc, 0); 998 } 999 1000 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1001 break; 1002 } 1003 else 1004 { 1005 if (padding == 0 && slp->sl_scp.scp_datalen <= 0) 1006 return; 1007 1008 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1009 break; 1010 1011 DELAY(1); 1012 } 1013 1014 if ((-- tout) <= 0) 1015 { 1016 device_printf(slp->sl_dev, "nsp_pio_read: timeout\n"); 1017 return; 1018 } 1019 } 1020 1021 1022 if (slp->sl_scp.scp_datalen > 0 && 1023 slp->sl_scp.scp_datalen > datalen - nsp_read_interrupt_bytes) 1024 { 1025 if (nsp_wait_interrupt(sc) != 0) 1026 goto ReadLoop; 1027 } 1028 } 1029 1030 static void 1031 nsp_pio_write(sc, suspendio) 1032 struct nsp_softc *sc; 1033 int suspendio; 1034 { 1035 struct scsi_low_softc *slp = &sc->sc_sclow; 1036 u_int rcount, acount; 1037 int tout, datalen; 1038 register u_int8_t stat, fstat; 1039 1040 tout = sc->sc_tmaxcnt; 1041 slp->sl_flags |= HW_PDMASTART; 1042 datalen = slp->sl_scp.scp_datalen; 1043 1044 WriteLoop: 1045 while (1) 1046 { 1047 stat = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON) & SCBUSMON_PHMASK; 1048 if (stat != PHASE_DATAOUT) 1049 return; 1050 1051 if (slp->sl_scp.scp_datalen <= 0) 1052 { 1053 if (sc->sc_dataout_timeout == 0) 1054 sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ; 1055 return; 1056 } 1057 1058 fstat = bus_read_1(sc->port_res, nsp_fifosr); 1059 if ((fstat & FIFOSR_FULLEMP) != 0) 1060 { 1061 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1062 { 1063 bus_write_1(sc->port_res, nsp_irqcr, 1064 IRQCR_FIFOCL); 1065 } 1066 1067 if (suspendio > 0) 1068 { 1069 /* XXX:IMPORTANT: 1070 * To avoid timeout of pcmcia bus 1071 * (not scsi bus!), we should check 1072 * the scsi device sends us request 1073 * signals, which means the scsi device 1074 * is ready to receive data without 1075 * heavy delays. 1076 */ 1077 if ((slp->sl_scp.scp_datalen % suspendio) == 0) 1078 { 1079 /* Step I: 1080 * fill the nsp fifo, and waiting for 1081 * the fifo empty. 1082 */ 1083 nsp_write_fifo(sc, 0); 1084 } 1085 else 1086 { 1087 /* Step II: 1088 * check the request singals. 1089 */ 1090 acount = nsp_fifo_count(sc); 1091 rcount = nsp_request_count(sc); 1092 if (rcount <= acount) 1093 { 1094 nsp_write_fifo(sc, 0); 1095 #ifdef NSP_STATICS 1096 nsp_statics.device_busy ++; 1097 #endif /* NSP_STATICS */ 1098 } 1099 else 1100 { 1101 nsp_write_fifo(sc, suspendio); 1102 #ifdef NSP_STATICS 1103 nsp_statics.device_data_write ++; 1104 #endif /* NSP_STATICS */ 1105 } 1106 } 1107 } 1108 else 1109 { 1110 nsp_write_fifo(sc, 0); 1111 } 1112 1113 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1114 break; 1115 } 1116 else 1117 { 1118 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1119 break; 1120 1121 DELAY(1); 1122 } 1123 1124 if ((-- tout) <= 0) 1125 { 1126 device_printf(slp->sl_dev, "nsp_pio_write: timeout\n"); 1127 return; 1128 } 1129 } 1130 1131 if (slp->sl_scp.scp_datalen > 0 && 1132 slp->sl_scp.scp_datalen > datalen - nsp_write_interrupt_bytes) 1133 { 1134 if (nsp_wait_interrupt(sc) != 0) 1135 goto WriteLoop; 1136 } 1137 } 1138 1139 static int 1140 nsp_negate_signal(struct nsp_softc *sc, u_int8_t mask, u_char *s) 1141 { 1142 struct scsi_low_softc *slp = &sc->sc_sclow; 1143 int wc; 1144 u_int8_t regv; 1145 1146 for (wc = 0; wc < NSP_DELAY_MAX / NSP_DELAY_INTERVAL; wc ++) 1147 { 1148 regv = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 1149 if (regv == (u_int8_t) -1) 1150 return -1; 1151 if ((regv & mask) == 0) 1152 return 1; 1153 DELAY(NSP_DELAY_INTERVAL); 1154 } 1155 1156 device_printf(slp->sl_dev, "%s nsp_negate_signal timeout\n", s); 1157 return -1; 1158 } 1159 1160 static int 1161 nsp_xfer(sc, buf, len, phase, clear_atn) 1162 struct nsp_softc *sc; 1163 u_int8_t *buf; 1164 int len; 1165 int phase; 1166 int clear_atn; 1167 { 1168 int ptr, rv; 1169 1170 for (ptr = 0; len > 0; len --, ptr ++) 1171 { 1172 rv = nsp_expect_signal(sc, phase, SCBUSMON_REQ); 1173 if (rv <= 0) 1174 goto out; 1175 1176 if (len == 1 && clear_atn != 0) 1177 { 1178 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, 1179 SCBUSCR_ADIR | SCBUSCR_ACKEN); 1180 SCSI_LOW_DEASSERT_ATN(&sc->sc_sclow); 1181 } 1182 1183 if (phase & SCBUSMON_IO) 1184 { 1185 buf[ptr] = nsp_cr_read_1(sc->port_res, NSPR_DATAACK); 1186 } 1187 else 1188 { 1189 nsp_cr_write_1(sc->port_res, NSPR_DATAACK, buf[ptr]); 1190 } 1191 nsp_negate_signal(sc, SCBUSMON_ACK, "xfer<ACK>"); 1192 } 1193 1194 out: 1195 return len; 1196 } 1197 1198 /************************************************************** 1199 * disconnect & reselect (HW low) 1200 **************************************************************/ 1201 static int 1202 nsp_reselected(sc) 1203 struct nsp_softc *sc; 1204 { 1205 struct scsi_low_softc *slp = &sc->sc_sclow; 1206 struct targ_info *ti; 1207 u_int sid; 1208 u_int8_t cr; 1209 1210 sid = (u_int) nsp_cr_read_1(sc->port_res, NSPR_RESELR); 1211 sid &= ~sc->sc_idbit; 1212 sid = ffs(sid) - 1; 1213 if ((ti = scsi_low_reselected(slp, sid)) == NULL) 1214 return EJUSTRETURN; 1215 1216 nsp_negate_signal(sc, SCBUSMON_SEL, "reselect<SEL>"); 1217 1218 cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR); 1219 cr &= ~(SCBUSCR_BSY | SCBUSCR_ATN); 1220 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr); 1221 cr |= SCBUSCR_ADIR | SCBUSCR_ACKEN; 1222 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr); 1223 1224 #ifdef NSP_STATICS 1225 nsp_statics.reselect ++; 1226 #endif /* NSP_STATCIS */ 1227 return EJUSTRETURN; 1228 } 1229 1230 static int 1231 nsp_disconnected(sc, ti) 1232 struct nsp_softc *sc; 1233 struct targ_info *ti; 1234 { 1235 struct scsi_low_softc *slp = &sc->sc_sclow; 1236 1237 nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, PTCLRR_PT | PTCLRR_ACK | 1238 PTCLRR_REQ | PTCLRR_HOST); 1239 if ((sc->sc_icr & SCIENR_FIFO) != 0) 1240 { 1241 sc->sc_icr &= ~SCIENR_FIFO; 1242 nsp_cr_write_1(sc->port_res, NSPR_SCIENR, sc->sc_icr); 1243 } 1244 sc->sc_cnt = 0; 1245 sc->sc_dataout_timeout = 0; 1246 #ifdef NSP_STATICS 1247 nsp_statics.disconnect ++; 1248 #endif /* NSP_STATICS */ 1249 scsi_low_disconnected(slp, ti); 1250 return 1; 1251 } 1252 1253 /************************************************************** 1254 * SEQUENCER 1255 **************************************************************/ 1256 static void nsp_error(struct nsp_softc *, u_char *, u_int8_t, u_int8_t, u_int8_t); 1257 1258 static void 1259 nsp_error(struct nsp_softc * sc, u_char *s, u_int8_t isrc, u_int8_t ph, 1260 u_int8_t irqphs) 1261 { 1262 struct scsi_low_softc *slp = &sc->sc_sclow; 1263 1264 device_printf(slp->sl_dev, "%s\n", s); 1265 device_printf(slp->sl_dev, "isrc 0x%x scmon 0x%x irqphs 0x%x\n", 1266 (u_int) isrc, (u_int) ph, (u_int) irqphs); 1267 } 1268 1269 static int 1270 nsp_target_nexus_establish(sc) 1271 struct nsp_softc *sc; 1272 { 1273 struct scsi_low_softc *slp = &sc->sc_sclow; 1274 struct targ_info *ti = slp->sl_Tnexus; 1275 struct nsp_targ_info *nti = (void *) ti; 1276 1277 /* setup synch transfer registers */ 1278 nsp_cr_write_1(sc->port_res, NSPR_SYNCR, nti->nti_reg_syncr); 1279 nsp_cr_write_1(sc->port_res, NSPR_ACKWIDTH, nti->nti_reg_ackwidth); 1280 1281 /* setup pdma fifo (minimum) */ 1282 nsp_setup_fifo(sc, NSP_FIFO_ON, SCSI_LOW_READ, 0); 1283 return 0; 1284 } 1285 1286 static int 1287 nsp_lun_nexus_establish(sc) 1288 struct nsp_softc *sc; 1289 { 1290 1291 return 0; 1292 } 1293 1294 static int 1295 nsp_ccb_nexus_establish(sc) 1296 struct nsp_softc *sc; 1297 { 1298 struct scsi_low_softc *slp = &sc->sc_sclow; 1299 struct slccb *cb = slp->sl_Qnexus; 1300 1301 sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000; 1302 1303 /* setup pdma fifo */ 1304 nsp_setup_fifo(sc, NSP_FIFO_ON, 1305 slp->sl_scp.scp_direction, slp->sl_scp.scp_datalen); 1306 1307 if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 1308 { 1309 if (sc->sc_suspendio > 0 && 1310 (nsp_io_control & NSP_READ_FIFO_INTERRUPTS) != 0) 1311 { 1312 sc->sc_icr |= SCIENR_FIFO; 1313 nsp_cr_write_1(sc->port_res, 1314 NSPR_SCIENR, sc->sc_icr); 1315 } 1316 } 1317 else 1318 { 1319 if (sc->sc_suspendio > 0 && 1320 (nsp_io_control & NSP_WRITE_FIFO_INTERRUPTS) != 0) 1321 { 1322 sc->sc_icr |= SCIENR_FIFO; 1323 nsp_cr_write_1(sc->port_res, 1324 NSPR_SCIENR, sc->sc_icr); 1325 } 1326 } 1327 return 0; 1328 } 1329 1330 static int 1331 nsp_phase_match(struct nsp_softc *sc, u_int8_t phase, u_int8_t stat) 1332 { 1333 struct scsi_low_softc *slp = &sc->sc_sclow; 1334 1335 if ((stat & SCBUSMON_PHMASK) != phase) 1336 { 1337 device_printf(slp->sl_dev, "phase mismatch 0x%x != 0x%x\n", 1338 (u_int) phase, (u_int) stat); 1339 return EINVAL; 1340 } 1341 1342 if ((stat & SCBUSMON_REQ) == 0) 1343 return EINVAL; 1344 1345 return 0; 1346 } 1347 1348 int 1349 nspintr(arg) 1350 void *arg; 1351 { 1352 struct nsp_softc *sc = arg; 1353 struct scsi_low_softc *slp = &sc->sc_sclow; 1354 struct targ_info *ti; 1355 struct buf *bp; 1356 u_int derror, flags; 1357 int len, rv; 1358 u_int8_t isrc, ph, irqphs, cr, regv; 1359 1360 /******************************************* 1361 * interrupt check 1362 *******************************************/ 1363 if (slp->sl_flags & HW_INACTIVE) 1364 return 0; 1365 1366 bus_write_1(sc->port_res, nsp_irqcr, IRQCR_IRQDIS); 1367 isrc = bus_read_1(sc->port_res, nsp_irqsr); 1368 if (isrc == (u_int8_t) -1 || (isrc & IRQSR_MASK) == 0) 1369 { 1370 bus_write_1(sc->port_res, nsp_irqcr, 0); 1371 return 0; 1372 } 1373 1374 /* XXX: IMPORTANT 1375 * Do not read an irqphs register if no scsi phase interrupt. 1376 * Unless, you should lose a scsi phase interrupt. 1377 */ 1378 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 1379 if ((isrc & IRQSR_SCSI) != 0) 1380 { 1381 irqphs = nsp_cr_read_1(sc->port_res, NSPR_IRQPHS); 1382 } 1383 else 1384 irqphs = 0; 1385 1386 /* 1387 * timer interrupt handler (scsi vs timer interrupts) 1388 */ 1389 if (sc->sc_timer != 0) 1390 { 1391 nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, 0); 1392 nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, 0); 1393 sc->sc_timer = 0; 1394 } 1395 1396 /* check a timer interrupt */ 1397 regv = 0; 1398 if ((isrc & IRQSR_TIMER) != 0) 1399 { 1400 if ((isrc & IRQSR_MASK) == IRQSR_TIMER && sc->sc_seltout == 0) 1401 { 1402 bus_write_1(sc->port_res, nsp_irqcr, IRQCR_TIMERCL); 1403 return 1; 1404 } 1405 regv |= IRQCR_TIMERCL; 1406 } 1407 1408 /* check a fifo interrupt */ 1409 if ((isrc & IRQSR_FIFO) != 0) 1410 { 1411 regv |= IRQCR_FIFOCL; 1412 } 1413 1414 /* OK. enable all interrupts */ 1415 bus_write_1(sc->port_res, nsp_irqcr, regv); 1416 1417 /******************************************* 1418 * debug section 1419 *******************************************/ 1420 #ifdef NSP_DEBUG 1421 if (nsp_debug) 1422 { 1423 nsp_error(sc, "current status", isrc, ph, irqphs); 1424 scsi_low_print(slp, NULL); 1425 #ifdef KDB 1426 if (nsp_debug > 1) 1427 kdb_enter(KDB_WHY_CAM, "nsp"); 1428 #endif /* KDB */ 1429 } 1430 #endif /* NSP_DEBUG */ 1431 1432 /******************************************* 1433 * Parse hardware SCSI irq reasons register 1434 *******************************************/ 1435 if ((isrc & IRQSR_SCSI) != 0) 1436 { 1437 if ((irqphs & IRQPHS_RST) != 0) 1438 { 1439 scsi_low_restart(slp, SCSI_LOW_RESTART_SOFT, 1440 "bus reset (power off?)"); 1441 return 1; 1442 } 1443 1444 if ((irqphs & IRQPHS_RSEL) != 0) 1445 { 1446 bus_write_1(sc->port_res, nsp_irqcr, IRQCR_RESCL); 1447 if (nsp_reselected(sc) == EJUSTRETURN) 1448 return 1; 1449 } 1450 1451 if ((irqphs & (IRQPHS_PCHG | IRQPHS_LBF)) == 0) 1452 return 1; 1453 } 1454 1455 /******************************************* 1456 * nexus check 1457 *******************************************/ 1458 if ((ti = slp->sl_Tnexus) == NULL) 1459 { 1460 /* unknown scsi phase changes */ 1461 nsp_error(sc, "unknown scsi phase changes", isrc, ph, irqphs); 1462 return 0; 1463 } 1464 1465 /******************************************* 1466 * aribitration & selection 1467 *******************************************/ 1468 switch (ti->ti_phase) 1469 { 1470 case PH_SELSTART: 1471 if ((ph & SCBUSMON_BSY) == 0) 1472 { 1473 if (sc->sc_seltout >= NSP_SELTIMEOUT) 1474 { 1475 sc->sc_seltout = 0; 1476 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, 0); 1477 return nsp_disconnected(sc, ti); 1478 } 1479 sc->sc_seltout ++; 1480 nsp_start_timer(sc, NSP_TIMER_1MS); 1481 return 1; 1482 } 1483 1484 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED); 1485 nsphw_selection_done_and_expect_msgout(sc); 1486 return 1; 1487 1488 case PH_SELECTED: 1489 if ((isrc & IRQSR_SCSI) == 0) 1490 return 1; 1491 1492 nsp_target_nexus_establish(sc); 1493 break; 1494 1495 case PH_RESEL: 1496 if ((isrc & IRQSR_SCSI) == 0) 1497 return 1; 1498 1499 nsp_target_nexus_establish(sc); 1500 if ((ph & SCBUSMON_PHMASK) != PHASE_MSGIN) 1501 { 1502 device_printf(slp->sl_dev, 1503 "unexpected phase after reselect\n"); 1504 slp->sl_error |= FATALIO; 1505 scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_ABORT, 1); 1506 return 1; 1507 } 1508 break; 1509 1510 case PH_DATA: 1511 if ((isrc & IRQSR_SCSI) != 0) 1512 break; 1513 if ((isrc & IRQSR_FIFO) != 0) 1514 { 1515 if (NSP_IS_PHASE_DATA(ph) == 0) 1516 return 1; 1517 irqphs = (ph & IRQPHS_PHMASK); 1518 break; 1519 } 1520 return 1; 1521 1522 default: 1523 if ((isrc & IRQSR_SCSI) == 0) 1524 return 1; 1525 break; 1526 } 1527 1528 /******************************************* 1529 * data phase control 1530 *******************************************/ 1531 if (slp->sl_flags & HW_PDMASTART) 1532 { 1533 if ((isrc & IRQSR_SCSI) != 0 && 1534 NSP_IS_IRQPHS_DATA(irqphs) == 0) 1535 { 1536 if (slp->sl_scp.scp_direction == SCSI_LOW_READ) 1537 nsp_pio_read(sc, 0); 1538 nsp_pdma_end(sc, ti); 1539 } 1540 } 1541 1542 /******************************************* 1543 * scsi seq 1544 *******************************************/ 1545 if (slp->sl_msgphase != 0 && (irqphs & IRQPHS_LBF) != 0) 1546 return nsp_disconnected(sc, ti); 1547 1548 /* check unexpected bus free state */ 1549 if (ph == 0) 1550 { 1551 nsp_error(sc, "unexpected bus free", isrc, ph, irqphs); 1552 return nsp_disconnected(sc, ti); 1553 } 1554 1555 /* check normal scsi phase */ 1556 switch (irqphs & IRQPHS_PHMASK) 1557 { 1558 case IRQPHS_CMD: 1559 if (nsp_phase_match(sc, PHASE_CMD, ph) != 0) 1560 return 1; 1561 1562 SCSI_LOW_SETUP_PHASE(ti, PH_CMD); 1563 if (scsi_low_cmd(slp, ti) != 0) 1564 { 1565 scsi_low_attention(slp); 1566 } 1567 1568 nsp_cr_write_1(sc->port_res, NSPR_CMDCR, CMDCR_PTCLR); 1569 for (len = 0; len < slp->sl_scp.scp_cmdlen; len ++) 1570 nsp_cr_write_1(sc->port_res, NSPR_CMDDR, 1571 slp->sl_scp.scp_cmd[len]); 1572 1573 nsp_cr_write_1(sc->port_res, NSPR_CMDCR, CMDCR_PTCLR | CMDCR_EXEC); 1574 break; 1575 1576 case IRQPHS_DATAOUT: 1577 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1578 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0) 1579 { 1580 scsi_low_attention(slp); 1581 } 1582 1583 nsp_pio_write(sc, sc->sc_suspendio); 1584 break; 1585 1586 case IRQPHS_DATAIN: 1587 SCSI_LOW_SETUP_PHASE(ti, PH_DATA); 1588 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0) 1589 { 1590 scsi_low_attention(slp); 1591 } 1592 1593 nsp_pio_read(sc, sc->sc_suspendio); 1594 break; 1595 1596 case IRQPHS_STATUS: 1597 if (nsp_phase_match(sc, PHASE_STATUS, ph) != 0) 1598 return 1; 1599 1600 SCSI_LOW_SETUP_PHASE(ti, PH_STAT); 1601 regv = nsp_cr_read_1(sc->port_res, NSPR_DATA); 1602 if (nsp_cr_read_1(sc->port_res, NSPR_PARITYR) & PARITYR_PE) 1603 { 1604 nsp_cr_write_1(sc->port_res, NSPR_PARITYR, 1605 PARITYR_ENABLE | PARITYR_CLEAR); 1606 derror = SCSI_LOW_DATA_PE; 1607 } 1608 else 1609 derror = 0; 1610 1611 /* assert ACK */ 1612 cr = SCBUSCR_ACK | nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR); 1613 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr); 1614 1615 if (scsi_low_statusin(slp, ti, derror | regv) != 0) 1616 { 1617 scsi_low_attention(slp); 1618 } 1619 1620 /* check REQ nagated */ 1621 nsp_negate_signal(sc, SCBUSMON_REQ, "statin<REQ>"); 1622 1623 /* deassert ACK */ 1624 cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR) & (~SCBUSCR_ACK); 1625 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr); 1626 break; 1627 1628 case IRQPHS_MSGOUT: 1629 if (nsp_phase_match(sc, PHASE_MSGOUT, ph) != 0) 1630 return 1; 1631 1632 #ifdef NSP_MSGOUT_SERIALIZE 1633 /* 1634 * XXX: NSP QUIRK 1635 * NSP invoke interrupts only in the case of scsi phase changes, 1636 * therefore we should poll the scsi phase here to catch 1637 * the next "msg out" if exists (no scsi phase changes). 1638 */ 1639 rv = len = 16; 1640 do { 1641 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); 1642 flags = (ti->ti_ophase != ti->ti_phase) ? 1643 SCSI_LOW_MSGOUT_INIT : 0; 1644 len = scsi_low_msgout(slp, ti, flags); 1645 1646 if (len > 1 && slp->sl_atten == 0) 1647 { 1648 scsi_low_attention(slp); 1649 } 1650 1651 if (nsp_xfer(sc, ti->ti_msgoutstr, len, PHASE_MSGOUT, 1652 slp->sl_clear_atten) != 0) 1653 { 1654 slp->sl_error |= FATALIO; 1655 nsp_error(sc, "MSGOUT: xfer short", 1656 isrc, ph, irqphs); 1657 } 1658 1659 /* catch a next signal */ 1660 rv = nsp_expect_signal(sc, PHASE_MSGOUT, SCBUSMON_REQ); 1661 } 1662 while (rv > 0 && len -- > 0); 1663 1664 #else /* !NSP_MSGOUT_SERIALIZE */ 1665 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); 1666 flags = SCSI_LOW_MSGOUT_UNIFY; 1667 if (ti->ti_ophase != ti->ti_phase) 1668 flags |= SCSI_LOW_MSGOUT_INIT; 1669 len = scsi_low_msgout(slp, ti, flags); 1670 1671 if (len > 1 && slp->sl_atten == 0) 1672 { 1673 scsi_low_attention(slp); 1674 } 1675 1676 if (nsp_xfer(sc, ti->ti_msgoutstr, len, PHASE_MSGOUT, 1677 slp->sl_clear_atten) != 0) 1678 { 1679 nsp_error(sc, "MSGOUT: xfer short", isrc, ph, irqphs); 1680 } 1681 1682 #endif /* !NSP_MSGOUT_SERIALIZE */ 1683 break; 1684 1685 case IRQPHS_MSGIN: 1686 if (nsp_phase_match(sc, PHASE_MSGIN, ph) != 0) 1687 return 1; 1688 1689 /* 1690 * XXX: NSP QUIRK 1691 * NSP invoke interrupts only in the case of scsi phase changes, 1692 * therefore we should poll the scsi phase here to catch 1693 * the next "msg in" if exists (no scsi phase changes). 1694 */ 1695 rv = len = 16; 1696 do { 1697 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN); 1698 1699 /* read a data */ 1700 regv = nsp_cr_read_1(sc->port_res, NSPR_DATA); 1701 if (nsp_cr_read_1(sc->port_res, NSPR_PARITYR) & PARITYR_PE) 1702 { 1703 nsp_cr_write_1(sc->port_res, 1704 NSPR_PARITYR, 1705 PARITYR_ENABLE | PARITYR_CLEAR); 1706 derror = SCSI_LOW_DATA_PE; 1707 } 1708 else 1709 { 1710 derror = 0; 1711 } 1712 1713 /* assert ack */ 1714 cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR) | SCBUSCR_ACK; 1715 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr); 1716 1717 if (scsi_low_msgin(slp, ti, regv | derror) == 0) 1718 { 1719 if (scsi_low_is_msgout_continue(ti, 0) != 0) 1720 { 1721 scsi_low_attention(slp); 1722 } 1723 } 1724 1725 /* check REQ nagated */ 1726 nsp_negate_signal(sc, SCBUSMON_REQ, "msgin<REQ>"); 1727 1728 /* deassert ack */ 1729 cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR) & (~SCBUSCR_ACK); 1730 nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr); 1731 1732 /* catch a next signal */ 1733 rv = nsp_expect_signal(sc, PHASE_MSGIN, SCBUSMON_REQ); 1734 } 1735 while (rv > 0 && len -- > 0); 1736 break; 1737 1738 default: 1739 slp->sl_error |= FATALIO; 1740 nsp_error(sc, "unknown scsi phase", isrc, ph, irqphs); 1741 break; 1742 } 1743 1744 return 1; 1745 1746 #if 0 1747 timerout: 1748 nsp_start_timer(sc, NSP_TIMER_1MS); 1749 return 0; 1750 #endif 1751 } 1752 1753 static int 1754 nsp_timeout(sc) 1755 struct nsp_softc *sc; 1756 { 1757 struct scsi_low_softc *slp = &sc->sc_sclow; 1758 int tout; 1759 u_int8_t ph, regv; 1760 1761 if (slp->sl_Tnexus == NULL) 1762 return 0; 1763 1764 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 1765 switch (ph & SCBUSMON_PHMASK) 1766 { 1767 case PHASE_DATAOUT: 1768 if (sc->sc_dataout_timeout == 0) 1769 break; 1770 1771 /* check a fifo empty */ 1772 regv = bus_read_1(sc->port_res, nsp_fifosr); 1773 if ((regv & FIFOSR_FULLEMP) == 0) 1774 break; 1775 bus_write_1(sc->port_res, nsp_irqcr, IRQCR_FIFOCL); 1776 1777 /* check still requested */ 1778 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 1779 if ((ph & SCBUSMON_REQ) == 0) 1780 break; 1781 /* check timeout */ 1782 if ((-- sc->sc_dataout_timeout) > 0) 1783 break; 1784 1785 slp->sl_error |= PDMAERR; 1786 if ((slp->sl_flags & HW_WRITE_PADDING) == 0) 1787 { 1788 device_printf(slp->sl_dev, "write padding required\n"); 1789 break; 1790 } 1791 1792 tout = NSP_DELAY_MAX; 1793 while (tout -- > 0) 1794 { 1795 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 1796 if ((ph & SCBUSMON_PHMASK) != PHASE_DATAOUT) 1797 break; 1798 regv = bus_read_1(sc->port_res, nsp_fifosr); 1799 if ((regv & FIFOSR_FULLEMP) == 0) 1800 { 1801 DELAY(1); 1802 continue; 1803 } 1804 1805 bus_write_1(sc->port_res, nsp_irqcr, IRQCR_FIFOCL); 1806 nsp_data_padding(sc, SCSI_LOW_WRITE, 32); 1807 } 1808 ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON); 1809 if ((ph & SCBUSMON_PHMASK) == PHASE_DATAOUT) 1810 sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ; 1811 break; 1812 1813 default: 1814 break; 1815 } 1816 return 0; 1817 }
Cache object: 6f8b1ae803720f875181bc3171bd6578
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