FreeBSD/Linux Kernel Cross Reference
sys/dev/nve/if_nve.c
1 /*-
2 * Copyright (c) 2005 by David E. O'Brien <obrien@FreeBSD.org>.
3 * Copyright (c) 2003,2004 by Quinton Dolan <q@onthenet.com.au>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
16 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: if_nv.c,v 1.19 2004/08/12 14:00:05 q Exp $
28 */
29 /*
30 * NVIDIA nForce MCP Networking Adapter driver
31 *
32 * This is a port of the NVIDIA MCP Linux ethernet driver distributed by NVIDIA
33 * through their web site.
34 *
35 * All mainstream nForce and nForce2 motherboards are supported. This module
36 * is as stable, sometimes more stable, than the linux version. (Recent
37 * Linux stability issues seem to be related to some issues with newer
38 * distributions using GCC 3.x, however this don't appear to effect FreeBSD
39 * 5.x).
40 *
41 * In accordance with the NVIDIA distribution license it is necessary to
42 * link this module against the nvlibnet.o binary object included in the
43 * Linux driver source distribution. The binary component is not modified in
44 * any way and is simply linked against a FreeBSD equivalent of the nvnet.c
45 * linux kernel module "wrapper".
46 *
47 * The Linux driver uses a common code API that is shared between Win32 and
48 * i386 Linux. This abstracts the low level driver functions and uses
49 * callbacks and hooks to access the underlying hardware device. By using
50 * this same API in a FreeBSD kernel module it is possible to support the
51 * hardware without breaching the Linux source distributions licensing
52 * requirements, or obtaining the hardware programming specifications.
53 *
54 * Although not conventional, it works, and given the relatively small
55 * amount of hardware centric code, it's hopefully no more buggy than its
56 * linux counterpart.
57 *
58 * NVIDIA now support the nForce3 AMD64 platform, however I have been
59 * unable to access such a system to verify support. However, the code is
60 * reported to work with little modification when compiled with the AMD64
61 * version of the NVIDIA Linux library. All that should be necessary to make
62 * the driver work is to link it directly into the kernel, instead of as a
63 * module, and apply the docs/amd64.diff patch in this source distribution to
64 * the NVIDIA Linux driver source.
65 *
66 * This driver should work on all versions of FreeBSD since 4.9/5.1 as well
67 * as recent versions of DragonFly.
68 *
69 * Written by Quinton Dolan <q@onthenet.com.au>
70 * Portions based on existing FreeBSD network drivers.
71 * NVIDIA API usage derived from distributed NVIDIA NVNET driver source files.
72 */
73
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD$");
76
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/sockio.h>
80 #include <sys/mbuf.h>
81 #include <sys/malloc.h>
82 #include <sys/kernel.h>
83 #include <sys/socket.h>
84 #include <sys/sysctl.h>
85 #include <sys/queue.h>
86 #include <sys/module.h>
87
88 #include <net/if.h>
89 #include <net/if_arp.h>
90 #include <net/ethernet.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/if_types.h>
94 #include <net/bpf.h>
95 #include <net/if_vlan_var.h>
96
97 #include <machine/bus.h>
98 #include <machine/resource.h>
99
100 #include <vm/vm.h> /* for vtophys */
101 #include <vm/pmap.h> /* for vtophys */
102 #include <sys/bus.h>
103 #include <sys/rman.h>
104
105 #include <dev/pci/pcireg.h>
106 #include <dev/pci/pcivar.h>
107 #include <dev/mii/mii.h>
108 #include <dev/mii/miivar.h>
109 #include "miibus_if.h"
110
111 /* Include NVIDIA Linux driver header files */
112 #include <contrib/dev/nve/nvenet_version.h>
113 #define linux
114 #include <contrib/dev/nve/basetype.h>
115 #include <contrib/dev/nve/phy.h>
116 #include "os+%DIKED-nve.h"
117 #include <contrib/dev/nve/drvinfo.h>
118 #include <contrib/dev/nve/adapter.h>
119 #undef linux
120
121 #include <dev/nve/if_nvereg.h>
122
123 MODULE_DEPEND(nve, pci, 1, 1, 1);
124 MODULE_DEPEND(nve, ether, 1, 1, 1);
125 MODULE_DEPEND(nve, miibus, 1, 1, 1);
126
127 static int nve_probe(device_t);
128 static int nve_attach(device_t);
129 static int nve_detach(device_t);
130 static void nve_init(void *);
131 static void nve_init_locked(struct nve_softc *);
132 static void nve_stop(struct nve_softc *);
133 static void nve_shutdown(device_t);
134 static int nve_init_rings(struct nve_softc *);
135 static void nve_free_rings(struct nve_softc *);
136
137 static void nve_ifstart(struct ifnet *);
138 static void nve_ifstart_locked(struct ifnet *);
139 static int nve_ioctl(struct ifnet *, u_long, caddr_t);
140 static void nve_intr(void *);
141 static void nve_tick(void *);
142 static void nve_setmulti(struct nve_softc *);
143 static void nve_watchdog(struct ifnet *);
144 static void nve_update_stats(struct nve_softc *);
145
146 static int nve_ifmedia_upd(struct ifnet *);
147 static void nve_ifmedia_upd_locked(struct ifnet *);
148 static void nve_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149 static int nve_miibus_readreg(device_t, int, int);
150 static void nve_miibus_writereg(device_t, int, int, int);
151
152 static void nve_dmamap_cb(void *, bus_dma_segment_t *, int, int);
153 static void nve_dmamap_tx_cb(void *, bus_dma_segment_t *, int, bus_size_t, int);
154
155 static NV_SINT32 nve_osalloc(PNV_VOID, PMEMORY_BLOCK);
156 static NV_SINT32 nve_osfree(PNV_VOID, PMEMORY_BLOCK);
157 static NV_SINT32 nve_osallocex(PNV_VOID, PMEMORY_BLOCKEX);
158 static NV_SINT32 nve_osfreeex(PNV_VOID, PMEMORY_BLOCKEX);
159 static NV_SINT32 nve_osclear(PNV_VOID, PNV_VOID, NV_SINT32);
160 static NV_SINT32 nve_osdelay(PNV_VOID, NV_UINT32);
161 static NV_SINT32 nve_osallocrxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID *);
162 static NV_SINT32 nve_osfreerxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID);
163 static NV_SINT32 nve_ospackettx(PNV_VOID, PNV_VOID, NV_UINT32);
164 static NV_SINT32 nve_ospacketrx(PNV_VOID, PNV_VOID, NV_UINT32, NV_UINT8 *, NV_UINT8);
165 static NV_SINT32 nve_oslinkchg(PNV_VOID, NV_SINT32);
166 static NV_SINT32 nve_osalloctimer(PNV_VOID, PNV_VOID *);
167 static NV_SINT32 nve_osfreetimer(PNV_VOID, PNV_VOID);
168 static NV_SINT32 nve_osinittimer(PNV_VOID, PNV_VOID, PTIMER_FUNC, PNV_VOID);
169 static NV_SINT32 nve_ossettimer(PNV_VOID, PNV_VOID, NV_UINT32);
170 static NV_SINT32 nve_oscanceltimer(PNV_VOID, PNV_VOID);
171
172 static NV_SINT32 nve_ospreprocpkt(PNV_VOID, PNV_VOID, PNV_VOID *, NV_UINT8 *, NV_UINT8);
173 static PNV_VOID nve_ospreprocpktnopq(PNV_VOID, PNV_VOID);
174 static NV_SINT32 nve_osindicatepkt(PNV_VOID, PNV_VOID *, NV_UINT32);
175 static NV_SINT32 nve_oslockalloc(PNV_VOID, NV_SINT32, PNV_VOID *);
176 static NV_SINT32 nve_oslockacquire(PNV_VOID, NV_SINT32, PNV_VOID);
177 static NV_SINT32 nve_oslockrelease(PNV_VOID, NV_SINT32, PNV_VOID);
178 static PNV_VOID nve_osreturnbufvirt(PNV_VOID, PNV_VOID);
179
180 static device_method_t nve_methods[] = {
181 /* Device interface */
182 DEVMETHOD(device_probe, nve_probe),
183 DEVMETHOD(device_attach, nve_attach),
184 DEVMETHOD(device_detach, nve_detach),
185 DEVMETHOD(device_shutdown, nve_shutdown),
186
187 /* Bus interface */
188 DEVMETHOD(bus_print_child, bus_generic_print_child),
189 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
190
191 /* MII interface */
192 DEVMETHOD(miibus_readreg, nve_miibus_readreg),
193 DEVMETHOD(miibus_writereg, nve_miibus_writereg),
194
195 {0, 0}
196 };
197
198 static driver_t nve_driver = {
199 "nve",
200 nve_methods,
201 sizeof(struct nve_softc)
202 };
203
204 static devclass_t nve_devclass;
205
206 static int nve_pollinterval = 0;
207 SYSCTL_INT(_hw, OID_AUTO, nve_pollinterval, CTLFLAG_RW,
208 &nve_pollinterval, 0, "delay between interface polls");
209
210 DRIVER_MODULE(nve, pci, nve_driver, nve_devclass, 0, 0);
211 DRIVER_MODULE(miibus, nve, miibus_driver, miibus_devclass, 0, 0);
212
213 static struct nve_type nve_devs[] = {
214 {NVIDIA_VENDORID, NFORCE_MCPNET1_DEVICEID,
215 "NVIDIA nForce MCP Networking Adapter"},
216 {NVIDIA_VENDORID, NFORCE_MCPNET2_DEVICEID,
217 "NVIDIA nForce MCP2 Networking Adapter"},
218 {NVIDIA_VENDORID, NFORCE_MCPNET3_DEVICEID,
219 "NVIDIA nForce MCP3 Networking Adapter"},
220 {NVIDIA_VENDORID, NFORCE_MCPNET4_DEVICEID,
221 "NVIDIA nForce MCP4 Networking Adapter"},
222 {NVIDIA_VENDORID, NFORCE_MCPNET5_DEVICEID,
223 "NVIDIA nForce MCP5 Networking Adapter"},
224 {NVIDIA_VENDORID, NFORCE_MCPNET6_DEVICEID,
225 "NVIDIA nForce MCP6 Networking Adapter"},
226 {NVIDIA_VENDORID, NFORCE_MCPNET7_DEVICEID,
227 "NVIDIA nForce MCP7 Networking Adapter"},
228 {NVIDIA_VENDORID, NFORCE_MCPNET8_DEVICEID,
229 "NVIDIA nForce MCP8 Networking Adapter"},
230 {NVIDIA_VENDORID, NFORCE_MCPNET9_DEVICEID,
231 "NVIDIA nForce MCP9 Networking Adapter"},
232 {NVIDIA_VENDORID, NFORCE_MCPNET10_DEVICEID,
233 "NVIDIA nForce MCP10 Networking Adapter"},
234 {NVIDIA_VENDORID, NFORCE_MCPNET11_DEVICEID,
235 "NVIDIA nForce MCP11 Networking Adapter"},
236 {NVIDIA_VENDORID, NFORCE_MCPNET12_DEVICEID,
237 "NVIDIA nForce MCP12 Networking Adapter"},
238 {NVIDIA_VENDORID, NFORCE_MCPNET13_DEVICEID,
239 "NVIDIA nForce MCP13 Networking Adapter"},
240 {0, 0, NULL}
241 };
242
243 /* DMA MEM map callback function to get data segment physical address */
244 static void
245 nve_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nsegs, int error)
246 {
247 if (error)
248 return;
249
250 KASSERT(nsegs == 1,
251 ("Too many DMA segments returned when mapping DMA memory"));
252 *(bus_addr_t *)arg = segs->ds_addr;
253 }
254
255 /* DMA RX map callback function to get data segment physical address */
256 static void
257 nve_dmamap_rx_cb(void *arg, bus_dma_segment_t * segs, int nsegs,
258 bus_size_t mapsize, int error)
259 {
260 if (error)
261 return;
262 *(bus_addr_t *)arg = segs->ds_addr;
263 }
264
265 /*
266 * DMA TX buffer callback function to allocate fragment data segment
267 * addresses
268 */
269 static void
270 nve_dmamap_tx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, bus_size_t mapsize, int error)
271 {
272 struct nve_tx_desc *info;
273
274 info = arg;
275 if (error)
276 return;
277 KASSERT(nsegs < NV_MAX_FRAGS,
278 ("Too many DMA segments returned when mapping mbuf"));
279 info->numfrags = nsegs;
280 bcopy(segs, info->frags, nsegs * sizeof(bus_dma_segment_t));
281 }
282
283 /* Probe for supported hardware ID's */
284 static int
285 nve_probe(device_t dev)
286 {
287 struct nve_type *t;
288
289 t = nve_devs;
290 /* Check for matching PCI DEVICE ID's */
291 while (t->name != NULL) {
292 if ((pci_get_vendor(dev) == t->vid_id) &&
293 (pci_get_device(dev) == t->dev_id)) {
294 device_set_desc(dev, t->name);
295 return (BUS_PROBE_LOW_PRIORITY);
296 }
297 t++;
298 }
299
300 return (ENXIO);
301 }
302
303 /* Attach driver and initialise hardware for use */
304 static int
305 nve_attach(device_t dev)
306 {
307 u_char eaddr[ETHER_ADDR_LEN];
308 struct nve_softc *sc;
309 struct ifnet *ifp;
310 OS_API *osapi;
311 ADAPTER_OPEN_PARAMS OpenParams;
312 int error = 0, i, rid;
313
314 if (bootverbose)
315 device_printf(dev, "nvenetlib.o version %s\n", DRIVER_VERSION);
316
317 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_attach - entry\n");
318
319 sc = device_get_softc(dev);
320
321 /* Allocate mutex */
322 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
323 MTX_DEF);
324 callout_init_mtx(&sc->stat_callout, &sc->mtx, 0);
325
326 sc->dev = dev;
327
328 /* Preinitialize data structures */
329 bzero(&OpenParams, sizeof(ADAPTER_OPEN_PARAMS));
330
331 /* Enable bus mastering */
332 pci_enable_busmaster(dev);
333
334 /* Allocate memory mapped address space */
335 rid = NV_RID;
336 sc->res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1,
337 RF_ACTIVE);
338
339 if (sc->res == NULL) {
340 device_printf(dev, "couldn't map memory\n");
341 error = ENXIO;
342 goto fail;
343 }
344 sc->sc_st = rman_get_bustag(sc->res);
345 sc->sc_sh = rman_get_bushandle(sc->res);
346
347 /* Allocate interrupt */
348 rid = 0;
349 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
350 RF_SHAREABLE | RF_ACTIVE);
351
352 if (sc->irq == NULL) {
353 device_printf(dev, "couldn't map interrupt\n");
354 error = ENXIO;
355 goto fail;
356 }
357 /* Allocate DMA tags */
358 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
359 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * NV_MAX_FRAGS,
360 NV_MAX_FRAGS, MCLBYTES, 0,
361 busdma_lock_mutex, &Giant,
362 &sc->mtag);
363 if (error) {
364 device_printf(dev, "couldn't allocate dma tag\n");
365 goto fail;
366 }
367 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
368 BUS_SPACE_MAXADDR, NULL, NULL,
369 sizeof(struct nve_rx_desc) * RX_RING_SIZE, 1,
370 sizeof(struct nve_rx_desc) * RX_RING_SIZE, 0,
371 busdma_lock_mutex, &Giant,
372 &sc->rtag);
373 if (error) {
374 device_printf(dev, "couldn't allocate dma tag\n");
375 goto fail;
376 }
377 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
378 BUS_SPACE_MAXADDR, NULL, NULL,
379 sizeof(struct nve_tx_desc) * TX_RING_SIZE, 1,
380 sizeof(struct nve_tx_desc) * TX_RING_SIZE, 0,
381 busdma_lock_mutex, &Giant,
382 &sc->ttag);
383 if (error) {
384 device_printf(dev, "couldn't allocate dma tag\n");
385 goto fail;
386 }
387 /* Allocate DMA safe memory and get the DMA addresses. */
388 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
389 BUS_DMA_WAITOK, &sc->tmap);
390 if (error) {
391 device_printf(dev, "couldn't allocate dma memory\n");
392 goto fail;
393 }
394 bzero(sc->tx_desc, sizeof(struct nve_tx_desc) * TX_RING_SIZE);
395 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
396 sizeof(struct nve_tx_desc) * TX_RING_SIZE, nve_dmamap_cb,
397 &sc->tx_addr, 0);
398 if (error) {
399 device_printf(dev, "couldn't map dma memory\n");
400 goto fail;
401 }
402 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
403 BUS_DMA_WAITOK, &sc->rmap);
404 if (error) {
405 device_printf(dev, "couldn't allocate dma memory\n");
406 goto fail;
407 }
408 bzero(sc->rx_desc, sizeof(struct nve_rx_desc) * RX_RING_SIZE);
409 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
410 sizeof(struct nve_rx_desc) * RX_RING_SIZE, nve_dmamap_cb,
411 &sc->rx_addr, 0);
412 if (error) {
413 device_printf(dev, "couldn't map dma memory\n");
414 goto fail;
415 }
416 /* Initialize rings. */
417 if (nve_init_rings(sc)) {
418 device_printf(dev, "failed to init rings\n");
419 error = ENXIO;
420 goto fail;
421 }
422 /* Setup NVIDIA API callback routines */
423 osapi = &sc->osapi;
424 osapi->pOSCX = sc;
425 osapi->pfnAllocMemory = nve_osalloc;
426 osapi->pfnFreeMemory = nve_osfree;
427 osapi->pfnAllocMemoryEx = nve_osallocex;
428 osapi->pfnFreeMemoryEx = nve_osfreeex;
429 osapi->pfnClearMemory = nve_osclear;
430 osapi->pfnStallExecution = nve_osdelay;
431 osapi->pfnAllocReceiveBuffer = nve_osallocrxbuf;
432 osapi->pfnFreeReceiveBuffer = nve_osfreerxbuf;
433 osapi->pfnPacketWasSent = nve_ospackettx;
434 osapi->pfnPacketWasReceived = nve_ospacketrx;
435 osapi->pfnLinkStateHasChanged = nve_oslinkchg;
436 osapi->pfnAllocTimer = nve_osalloctimer;
437 osapi->pfnFreeTimer = nve_osfreetimer;
438 osapi->pfnInitializeTimer = nve_osinittimer;
439 osapi->pfnSetTimer = nve_ossettimer;
440 osapi->pfnCancelTimer = nve_oscanceltimer;
441 osapi->pfnPreprocessPacket = nve_ospreprocpkt;
442 osapi->pfnPreprocessPacketNopq = nve_ospreprocpktnopq;
443 osapi->pfnIndicatePackets = nve_osindicatepkt;
444 osapi->pfnLockAlloc = nve_oslockalloc;
445 osapi->pfnLockAcquire = nve_oslockacquire;
446 osapi->pfnLockRelease = nve_oslockrelease;
447 osapi->pfnReturnBufferVirtual = nve_osreturnbufvirt;
448
449 sc->linkup = FALSE;
450 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + FCS_LEN;
451
452 /* TODO - We don't support hardware offload yet */
453 sc->hwmode = 1;
454 sc->media = 0;
455
456 /* Set NVIDIA API startup parameters */
457 OpenParams.MaxDpcLoop = 2;
458 OpenParams.MaxRxPkt = RX_RING_SIZE;
459 OpenParams.MaxTxPkt = TX_RING_SIZE;
460 OpenParams.SentPacketStatusSuccess = 1;
461 OpenParams.SentPacketStatusFailure = 0;
462 OpenParams.MaxRxPktToAccumulate = 6;
463 OpenParams.ulPollInterval = nve_pollinterval;
464 OpenParams.SetForcedModeEveryNthRxPacket = 0;
465 OpenParams.SetForcedModeEveryNthTxPacket = 0;
466 OpenParams.RxForcedInterrupt = 0;
467 OpenParams.TxForcedInterrupt = 0;
468 OpenParams.pOSApi = osapi;
469 OpenParams.pvHardwareBaseAddress = rman_get_virtual(sc->res);
470 OpenParams.bASFEnabled = 0;
471 OpenParams.ulDescriptorVersion = sc->hwmode;
472 OpenParams.ulMaxPacketSize = sc->max_frame_size;
473 OpenParams.DeviceId = pci_get_device(dev);
474
475 /* Open NVIDIA Hardware API */
476 error = ADAPTER_Open(&OpenParams, (void **)&(sc->hwapi), &sc->phyaddr);
477 if (error) {
478 device_printf(dev,
479 "failed to open NVIDIA Hardware API: 0x%x\n", error);
480 goto fail;
481 }
482
483 /* TODO - Add support for MODE2 hardware offload */
484
485 bzero(&sc->adapterdata, sizeof(sc->adapterdata));
486
487 sc->adapterdata.ulMediaIF = sc->media;
488 sc->adapterdata.ulModeRegTxReadCompleteEnable = 1;
489 sc->hwapi->pfnSetCommonData(sc->hwapi->pADCX, &sc->adapterdata);
490
491 /* MAC is loaded backwards into h/w reg */
492 sc->hwapi->pfnGetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr);
493 for (i = 0; i < 6; i++) {
494 eaddr[i] = sc->original_mac_addr[5 - i];
495 }
496 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, eaddr);
497
498 /* Display ethernet address ,... */
499 device_printf(dev, "Ethernet address %6D\n", eaddr, ":");
500
501 /* Allocate interface structures */
502 ifp = sc->ifp = if_alloc(IFT_ETHER);
503 if (ifp == NULL) {
504 device_printf(dev, "can not if_alloc()\n");
505 error = ENOSPC;
506 goto fail;
507 }
508
509 /* Probe device for MII interface to PHY */
510 DEBUGOUT(NVE_DEBUG_INIT, "nve: do mii_phy_probe\n");
511 if (mii_phy_probe(dev, &sc->miibus, nve_ifmedia_upd, nve_ifmedia_sts)) {
512 device_printf(dev, "MII without any phy!\n");
513 error = ENXIO;
514 goto fail;
515 }
516
517 /* Setup interface parameters */
518 ifp->if_softc = sc;
519 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
521 ifp->if_ioctl = nve_ioctl;
522 ifp->if_output = ether_output;
523 ifp->if_start = nve_ifstart;
524 ifp->if_watchdog = nve_watchdog;
525 ifp->if_timer = 0;
526 ifp->if_init = nve_init;
527 ifp->if_mtu = ETHERMTU;
528 ifp->if_baudrate = IF_Mbps(100);
529 IFQ_SET_MAXLEN(&ifp->if_snd, TX_RING_SIZE - 1);
530 ifp->if_snd.ifq_drv_maxlen = TX_RING_SIZE - 1;
531 IFQ_SET_READY(&ifp->if_snd);
532 ifp->if_capabilities |= IFCAP_VLAN_MTU;
533 ifp->if_capenable |= IFCAP_VLAN_MTU;
534
535 /* Attach to OS's managers. */
536 ether_ifattach(ifp, eaddr);
537
538 /* Activate our interrupt handler. - attach last to avoid lock */
539 error = bus_setup_intr(sc->dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
540 NULL, nve_intr, sc, &sc->sc_ih);
541 if (error) {
542 device_printf(sc->dev, "couldn't set up interrupt handler\n");
543 goto fail;
544 }
545 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_attach - exit\n");
546
547 fail:
548 if (error)
549 nve_detach(dev);
550
551 return (error);
552 }
553
554 /* Detach interface for module unload */
555 static int
556 nve_detach(device_t dev)
557 {
558 struct nve_softc *sc = device_get_softc(dev);
559 struct ifnet *ifp;
560
561 KASSERT(mtx_initialized(&sc->mtx), ("mutex not initialized"));
562
563 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_detach - entry\n");
564
565 ifp = sc->ifp;
566
567 if (device_is_attached(dev)) {
568 NVE_LOCK(sc);
569 nve_stop(sc);
570 NVE_UNLOCK(sc);
571 callout_drain(&sc->stat_callout);
572 ether_ifdetach(ifp);
573 }
574
575 if (sc->miibus)
576 device_delete_child(dev, sc->miibus);
577 bus_generic_detach(dev);
578
579 /* Reload unreversed address back into MAC in original state */
580 if (sc->original_mac_addr)
581 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX,
582 sc->original_mac_addr);
583
584 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: do pfnClose\n");
585 /* Detach from NVIDIA hardware API */
586 if (sc->hwapi->pfnClose)
587 sc->hwapi->pfnClose(sc->hwapi->pADCX, FALSE);
588 /* Release resources */
589 if (sc->sc_ih)
590 bus_teardown_intr(sc->dev, sc->irq, sc->sc_ih);
591 if (sc->irq)
592 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
593 if (sc->res)
594 bus_release_resource(sc->dev, SYS_RES_MEMORY, NV_RID, sc->res);
595
596 nve_free_rings(sc);
597
598 if (sc->tx_desc) {
599 bus_dmamap_unload(sc->rtag, sc->rmap);
600 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
601 bus_dmamap_destroy(sc->rtag, sc->rmap);
602 }
603 if (sc->mtag)
604 bus_dma_tag_destroy(sc->mtag);
605 if (sc->ttag)
606 bus_dma_tag_destroy(sc->ttag);
607 if (sc->rtag)
608 bus_dma_tag_destroy(sc->rtag);
609
610 if (ifp)
611 if_free(ifp);
612 mtx_destroy(&sc->mtx);
613
614 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_detach - exit\n");
615
616 return (0);
617 }
618
619 /* Initialise interface and start it "RUNNING" */
620 static void
621 nve_init(void *xsc)
622 {
623 struct nve_softc *sc = xsc;
624
625 NVE_LOCK(sc);
626 nve_init_locked(sc);
627 NVE_UNLOCK(sc);
628 }
629
630 static void
631 nve_init_locked(struct nve_softc *sc)
632 {
633 struct ifnet *ifp;
634 int error;
635
636 NVE_LOCK_ASSERT(sc);
637 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init - entry (%d)\n", sc->linkup);
638
639 ifp = sc->ifp;
640
641 /* Do nothing if already running */
642 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
643 return;
644
645 nve_stop(sc);
646 DEBUGOUT(NVE_DEBUG_INIT, "nve: do pfnInit\n");
647
648 nve_ifmedia_upd_locked(ifp);
649
650 /* Setup Hardware interface and allocate memory structures */
651 error = sc->hwapi->pfnInit(sc->hwapi->pADCX,
652 0, /* force speed */
653 0, /* force full duplex */
654 0, /* force mode */
655 0, /* force async mode */
656 &sc->linkup);
657
658 if (error) {
659 device_printf(sc->dev,
660 "failed to start NVIDIA Hardware interface\n");
661 return;
662 }
663 /* Set the MAC address */
664 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, IF_LLADDR(sc->ifp));
665 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
666 sc->hwapi->pfnStart(sc->hwapi->pADCX);
667
668 /* Setup multicast filter */
669 nve_setmulti(sc);
670
671 /* Update interface parameters */
672 ifp->if_drv_flags |= IFF_DRV_RUNNING;
673 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
674
675 callout_reset(&sc->stat_callout, hz, nve_tick, sc);
676
677 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init - exit\n");
678
679 return;
680 }
681
682 /* Stop interface activity ie. not "RUNNING" */
683 static void
684 nve_stop(struct nve_softc *sc)
685 {
686 struct ifnet *ifp;
687
688 NVE_LOCK_ASSERT(sc);
689
690 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_stop - entry\n");
691
692 ifp = sc->ifp;
693 ifp->if_timer = 0;
694
695 /* Cancel tick timer */
696 callout_stop(&sc->stat_callout);
697
698 /* Stop hardware activity */
699 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
700 sc->hwapi->pfnStop(sc->hwapi->pADCX, 0);
701
702 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: do pfnDeinit\n");
703 /* Shutdown interface and deallocate memory buffers */
704 if (sc->hwapi->pfnDeinit)
705 sc->hwapi->pfnDeinit(sc->hwapi->pADCX, 0);
706
707 sc->linkup = 0;
708 sc->cur_rx = 0;
709 sc->pending_rxs = 0;
710 sc->pending_txs = 0;
711
712 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
713
714 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_stop - exit\n");
715
716 return;
717 }
718
719 /* Shutdown interface for unload/reboot */
720 static void
721 nve_shutdown(device_t dev)
722 {
723 struct nve_softc *sc;
724
725 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_shutdown\n");
726
727 sc = device_get_softc(dev);
728
729 /* Stop hardware activity */
730 NVE_LOCK(sc);
731 nve_stop(sc);
732 NVE_UNLOCK(sc);
733 }
734
735 /* Allocate TX ring buffers */
736 static int
737 nve_init_rings(struct nve_softc *sc)
738 {
739 int error, i;
740
741 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init_rings - entry\n");
742
743 sc->cur_rx = sc->cur_tx = sc->pending_rxs = sc->pending_txs = 0;
744 /* Initialise RX ring */
745 for (i = 0; i < RX_RING_SIZE; i++) {
746 struct nve_rx_desc *desc = sc->rx_desc + i;
747 struct nve_map_buffer *buf = &desc->buf;
748
749 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
750 if (buf->mbuf == NULL) {
751 device_printf(sc->dev, "couldn't allocate mbuf\n");
752 nve_free_rings(sc);
753 return (ENOBUFS);
754 }
755 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
756 m_adj(buf->mbuf, ETHER_ALIGN);
757
758 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
759 if (error) {
760 device_printf(sc->dev, "couldn't create dma map\n");
761 nve_free_rings(sc);
762 return (error);
763 }
764 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
765 nve_dmamap_rx_cb, &desc->paddr, 0);
766 if (error) {
767 device_printf(sc->dev, "couldn't dma map mbuf\n");
768 nve_free_rings(sc);
769 return (error);
770 }
771 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
772
773 desc->buflength = buf->mbuf->m_len;
774 desc->vaddr = mtod(buf->mbuf, caddr_t);
775 }
776 bus_dmamap_sync(sc->rtag, sc->rmap,
777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
778
779 /* Initialize TX ring */
780 for (i = 0; i < TX_RING_SIZE; i++) {
781 struct nve_tx_desc *desc = sc->tx_desc + i;
782 struct nve_map_buffer *buf = &desc->buf;
783
784 buf->mbuf = NULL;
785
786 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
787 if (error) {
788 device_printf(sc->dev, "couldn't create dma map\n");
789 nve_free_rings(sc);
790 return (error);
791 }
792 }
793 bus_dmamap_sync(sc->ttag, sc->tmap,
794 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
795
796 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init_rings - exit\n");
797
798 return (error);
799 }
800
801 /* Free the TX ring buffers */
802 static void
803 nve_free_rings(struct nve_softc *sc)
804 {
805 int i;
806
807 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_free_rings - entry\n");
808
809 for (i = 0; i < RX_RING_SIZE; i++) {
810 struct nve_rx_desc *desc = sc->rx_desc + i;
811 struct nve_map_buffer *buf = &desc->buf;
812
813 if (buf->mbuf) {
814 bus_dmamap_unload(sc->mtag, buf->map);
815 bus_dmamap_destroy(sc->mtag, buf->map);
816 m_freem(buf->mbuf);
817 }
818 buf->mbuf = NULL;
819 }
820
821 for (i = 0; i < TX_RING_SIZE; i++) {
822 struct nve_tx_desc *desc = sc->tx_desc + i;
823 struct nve_map_buffer *buf = &desc->buf;
824
825 if (buf->mbuf) {
826 bus_dmamap_unload(sc->mtag, buf->map);
827 bus_dmamap_destroy(sc->mtag, buf->map);
828 m_freem(buf->mbuf);
829 }
830 buf->mbuf = NULL;
831 }
832
833 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_free_rings - exit\n");
834 }
835
836 /* Main loop for sending packets from OS to interface */
837 static void
838 nve_ifstart(struct ifnet *ifp)
839 {
840 struct nve_softc *sc = ifp->if_softc;
841
842 NVE_LOCK(sc);
843 nve_ifstart_locked(ifp);
844 NVE_UNLOCK(sc);
845 }
846
847 static void
848 nve_ifstart_locked(struct ifnet *ifp)
849 {
850 struct nve_softc *sc = ifp->if_softc;
851 struct nve_map_buffer *buf;
852 struct mbuf *m0, *m;
853 struct nve_tx_desc *desc;
854 ADAPTER_WRITE_DATA txdata;
855 int error, i;
856
857 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_ifstart - entry\n");
858
859 NVE_LOCK_ASSERT(sc);
860
861 /* If link is down/busy or queue is empty do nothing */
862 if (ifp->if_drv_flags & IFF_DRV_OACTIVE ||
863 IFQ_DRV_IS_EMPTY(&ifp->if_snd))
864 return;
865
866 /* Transmit queued packets until sent or TX ring is full */
867 while (sc->pending_txs < TX_RING_SIZE) {
868 desc = sc->tx_desc + sc->cur_tx;
869 buf = &desc->buf;
870
871 /* Get next packet to send. */
872 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
873
874 /* If nothing to send, return. */
875 if (m0 == NULL)
876 return;
877
878 /*
879 * On nForce4, the chip doesn't interrupt on transmit,
880 * so try to flush transmitted packets from the queue
881 * if it's getting large (see note in nve_watchdog).
882 */
883 if (sc->pending_txs > TX_RING_SIZE/2) {
884 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
885 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
886 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
887 }
888
889 /* Map MBUF for DMA access */
890 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
891 nve_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
892
893 if (error && error != EFBIG) {
894 m_freem(m0);
895 sc->tx_errors++;
896 continue;
897 }
898 /*
899 * Packet has too many fragments - defrag into new mbuf
900 * cluster
901 */
902 if (error) {
903 m = m_defrag(m0, M_DONTWAIT);
904 if (m == NULL) {
905 m_freem(m0);
906 sc->tx_errors++;
907 continue;
908 }
909 m0 = m;
910
911 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
912 nve_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
913 if (error) {
914 m_freem(m);
915 sc->tx_errors++;
916 continue;
917 }
918 }
919 /* Do sync on DMA bounce buffer */
920 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
921
922 buf->mbuf = m0;
923 txdata.ulNumberOfElements = desc->numfrags;
924 txdata.pvID = (PVOID)desc;
925
926 /* Put fragments into API element list */
927 txdata.ulTotalLength = buf->mbuf->m_len;
928 for (i = 0; i < desc->numfrags; i++) {
929 txdata.sElement[i].ulLength =
930 (ulong)desc->frags[i].ds_len;
931 txdata.sElement[i].pPhysical =
932 (PVOID)desc->frags[i].ds_addr;
933 }
934
935 /* Send packet to Nvidia API for transmission */
936 error = sc->hwapi->pfnWrite(sc->hwapi->pADCX, &txdata);
937
938 switch (error) {
939 case ADAPTERERR_NONE:
940 /* Packet was queued in API TX queue successfully */
941 sc->pending_txs++;
942 sc->cur_tx = (sc->cur_tx + 1) % TX_RING_SIZE;
943 break;
944
945 case ADAPTERERR_TRANSMIT_QUEUE_FULL:
946 /* The API TX queue is full - requeue the packet */
947 device_printf(sc->dev,
948 "nve_ifstart: transmit queue is full\n");
949 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
950 bus_dmamap_unload(sc->mtag, buf->map);
951 IFQ_DRV_PREPEND(&ifp->if_snd, buf->mbuf);
952 buf->mbuf = NULL;
953 return;
954
955 default:
956 /* The API failed to queue/send the packet so dump it */
957 device_printf(sc->dev, "nve_ifstart: transmit error\n");
958 bus_dmamap_unload(sc->mtag, buf->map);
959 m_freem(buf->mbuf);
960 buf->mbuf = NULL;
961 sc->tx_errors++;
962 return;
963 }
964 /* Set watchdog timer. */
965 ifp->if_timer = 8;
966
967 /* Copy packet to BPF tap */
968 BPF_MTAP(ifp, m0);
969 }
970 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
971
972 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_ifstart - exit\n");
973 }
974
975 /* Handle IOCTL events */
976 static int
977 nve_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
978 {
979 struct nve_softc *sc = ifp->if_softc;
980 struct ifreq *ifr = (struct ifreq *) data;
981 struct mii_data *mii;
982 int error = 0;
983
984 DEBUGOUT(NVE_DEBUG_IOCTL, "nve: nve_ioctl - entry\n");
985
986 switch (command) {
987 case SIOCSIFMTU:
988 /* Set MTU size */
989 NVE_LOCK(sc);
990 if (ifp->if_mtu == ifr->ifr_mtu) {
991 NVE_UNLOCK(sc);
992 break;
993 }
994 if (ifr->ifr_mtu + ifp->if_hdrlen <= MAX_PACKET_SIZE_1518) {
995 ifp->if_mtu = ifr->ifr_mtu;
996 nve_stop(sc);
997 nve_init_locked(sc);
998 } else
999 error = EINVAL;
1000 NVE_UNLOCK(sc);
1001 break;
1002
1003 case SIOCSIFFLAGS:
1004 /* Setup interface flags */
1005 NVE_LOCK(sc);
1006 if (ifp->if_flags & IFF_UP) {
1007 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1008 nve_init_locked(sc);
1009 NVE_UNLOCK(sc);
1010 break;
1011 }
1012 } else {
1013 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1014 nve_stop(sc);
1015 NVE_UNLOCK(sc);
1016 break;
1017 }
1018 }
1019 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
1020 nve_setmulti(sc);
1021 NVE_UNLOCK(sc);
1022 break;
1023
1024 case SIOCADDMULTI:
1025 case SIOCDELMULTI:
1026 /* Setup multicast filter */
1027 NVE_LOCK(sc);
1028 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1029 nve_setmulti(sc);
1030 }
1031 NVE_UNLOCK(sc);
1032 break;
1033
1034 case SIOCGIFMEDIA:
1035 case SIOCSIFMEDIA:
1036 /* Get/Set interface media parameters */
1037 mii = device_get_softc(sc->miibus);
1038 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1039 break;
1040
1041 default:
1042 /* Everything else we forward to generic ether ioctl */
1043 error = ether_ioctl(ifp, command, data);
1044 break;
1045 }
1046
1047 DEBUGOUT(NVE_DEBUG_IOCTL, "nve: nve_ioctl - exit\n");
1048
1049 return (error);
1050 }
1051
1052 /* Interrupt service routine */
1053 static void
1054 nve_intr(void *arg)
1055 {
1056 struct nve_softc *sc = arg;
1057 struct ifnet *ifp = sc->ifp;
1058
1059 DEBUGOUT(NVE_DEBUG_INTERRUPT, "nve: nve_intr - entry\n");
1060
1061 NVE_LOCK(sc);
1062 if (!ifp->if_flags & IFF_UP) {
1063 nve_stop(sc);
1064 NVE_UNLOCK(sc);
1065 return;
1066 }
1067 /* Handle interrupt event */
1068 if (sc->hwapi->pfnQueryInterrupt(sc->hwapi->pADCX)) {
1069 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
1070 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
1071 }
1072 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1073 nve_ifstart_locked(ifp);
1074
1075 /* If no pending packets we don't need a timeout */
1076 if (sc->pending_txs == 0)
1077 sc->ifp->if_timer = 0;
1078 NVE_UNLOCK(sc);
1079
1080 DEBUGOUT(NVE_DEBUG_INTERRUPT, "nve: nve_intr - exit\n");
1081
1082 return;
1083 }
1084
1085 /* Setup multicast filters */
1086 static void
1087 nve_setmulti(struct nve_softc *sc)
1088 {
1089 struct ifnet *ifp;
1090 struct ifmultiaddr *ifma;
1091 PACKET_FILTER hwfilter;
1092 int i;
1093 u_int8_t andaddr[6], oraddr[6];
1094
1095 NVE_LOCK_ASSERT(sc);
1096
1097 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_setmulti - entry\n");
1098
1099 ifp = sc->ifp;
1100
1101 /* Initialize filter */
1102 hwfilter.ulFilterFlags = 0;
1103 for (i = 0; i < 6; i++) {
1104 hwfilter.acMulticastAddress[i] = 0;
1105 hwfilter.acMulticastMask[i] = 0;
1106 }
1107
1108 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1109 /* Accept all packets */
1110 hwfilter.ulFilterFlags |= ACCEPT_ALL_PACKETS;
1111 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
1112 return;
1113 }
1114 /* Setup multicast filter */
1115 IF_ADDR_LOCK(ifp);
1116 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1117 u_char *addrp;
1118
1119 if (ifma->ifma_addr->sa_family != AF_LINK)
1120 continue;
1121
1122 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1123 for (i = 0; i < 6; i++) {
1124 u_int8_t mcaddr = addrp[i];
1125 andaddr[i] &= mcaddr;
1126 oraddr[i] |= mcaddr;
1127 }
1128 }
1129 IF_ADDR_UNLOCK(ifp);
1130 for (i = 0; i < 6; i++) {
1131 hwfilter.acMulticastAddress[i] = andaddr[i] & oraddr[i];
1132 hwfilter.acMulticastMask[i] = andaddr[i] | (~oraddr[i]);
1133 }
1134
1135 /* Send filter to NVIDIA API */
1136 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
1137
1138 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_setmulti - exit\n");
1139
1140 return;
1141 }
1142
1143 /* Change the current media/mediaopts */
1144 static int
1145 nve_ifmedia_upd(struct ifnet *ifp)
1146 {
1147 struct nve_softc *sc = ifp->if_softc;
1148
1149 NVE_LOCK(sc);
1150 nve_ifmedia_upd_locked(ifp);
1151 NVE_UNLOCK(sc);
1152 return (0);
1153 }
1154
1155 static void
1156 nve_ifmedia_upd_locked(struct ifnet *ifp)
1157 {
1158 struct nve_softc *sc = ifp->if_softc;
1159 struct mii_data *mii;
1160
1161 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_ifmedia_upd\n");
1162
1163 NVE_LOCK_ASSERT(sc);
1164 mii = device_get_softc(sc->miibus);
1165
1166 if (mii->mii_instance) {
1167 struct mii_softc *miisc;
1168 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1169 miisc = LIST_NEXT(miisc, mii_list)) {
1170 mii_phy_reset(miisc);
1171 }
1172 }
1173 mii_mediachg(mii);
1174 }
1175
1176 /* Update current miibus PHY status of media */
1177 static void
1178 nve_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1179 {
1180 struct nve_softc *sc;
1181 struct mii_data *mii;
1182
1183 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_ifmedia_sts\n");
1184
1185 sc = ifp->if_softc;
1186 NVE_LOCK(sc);
1187 mii = device_get_softc(sc->miibus);
1188 mii_pollstat(mii);
1189 NVE_UNLOCK(sc);
1190
1191 ifmr->ifm_active = mii->mii_media_active;
1192 ifmr->ifm_status = mii->mii_media_status;
1193
1194 return;
1195 }
1196
1197 /* miibus tick timer - maintain link status */
1198 static void
1199 nve_tick(void *xsc)
1200 {
1201 struct nve_softc *sc = xsc;
1202 struct mii_data *mii;
1203 struct ifnet *ifp;
1204
1205 NVE_LOCK_ASSERT(sc);
1206
1207 ifp = sc->ifp;
1208 nve_update_stats(sc);
1209
1210 mii = device_get_softc(sc->miibus);
1211 mii_tick(mii);
1212
1213 if (mii->mii_media_status & IFM_ACTIVE &&
1214 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1215 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1216 nve_ifstart_locked(ifp);
1217 }
1218 callout_reset(&sc->stat_callout, hz, nve_tick, sc);
1219
1220 return;
1221 }
1222
1223 /* Update ifnet data structure with collected interface stats from API */
1224 static void
1225 nve_update_stats(struct nve_softc *sc)
1226 {
1227 struct ifnet *ifp = sc->ifp;
1228 ADAPTER_STATS stats;
1229
1230 NVE_LOCK_ASSERT(sc);
1231
1232 if (sc->hwapi) {
1233 sc->hwapi->pfnGetStatistics(sc->hwapi->pADCX, &stats);
1234
1235 ifp->if_ipackets = stats.ulSuccessfulReceptions;
1236 ifp->if_ierrors = stats.ulMissedFrames +
1237 stats.ulFailedReceptions +
1238 stats.ulCRCErrors +
1239 stats.ulFramingErrors +
1240 stats.ulOverFlowErrors;
1241
1242 ifp->if_opackets = stats.ulSuccessfulTransmissions;
1243 ifp->if_oerrors = sc->tx_errors +
1244 stats.ulFailedTransmissions +
1245 stats.ulRetryErrors +
1246 stats.ulUnderflowErrors +
1247 stats.ulLossOfCarrierErrors +
1248 stats.ulLateCollisionErrors;
1249
1250 ifp->if_collisions = stats.ulLateCollisionErrors;
1251 }
1252
1253 return;
1254 }
1255
1256 /* miibus Read PHY register wrapper - calls Nvidia API entry point */
1257 static int
1258 nve_miibus_readreg(device_t dev, int phy, int reg)
1259 {
1260 struct nve_softc *sc = device_get_softc(dev);
1261 ULONG data;
1262
1263 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_readreg - entry\n");
1264
1265 ADAPTER_ReadPhy(sc->hwapi->pADCX, phy, reg, &data);
1266
1267 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_readreg - exit\n");
1268
1269 return (data);
1270 }
1271
1272 /* miibus Write PHY register wrapper - calls Nvidia API entry point */
1273 static void
1274 nve_miibus_writereg(device_t dev, int phy, int reg, int data)
1275 {
1276 struct nve_softc *sc = device_get_softc(dev);
1277
1278 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_writereg - entry\n");
1279
1280 ADAPTER_WritePhy(sc->hwapi->pADCX, phy, reg, (ulong)data);
1281
1282 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_writereg - exit\n");
1283
1284 return;
1285 }
1286
1287 /* Watchdog timer to prevent PHY lockups */
1288 static void
1289 nve_watchdog(struct ifnet *ifp)
1290 {
1291 struct nve_softc *sc = ifp->if_softc;
1292 int pending_txs_start;
1293
1294 NVE_LOCK(sc);
1295
1296 /*
1297 * The nvidia driver blob defers tx completion notifications.
1298 * Thus, sometimes the watchdog timer will go off when the
1299 * tx engine is fine, but the tx completions are just deferred.
1300 * Try kicking the driver blob to clear out any pending tx
1301 * completions. If that clears up any of the pending tx
1302 * operations, then just return without printing the warning
1303 * message or resetting the adapter, as we can then conclude
1304 * the chip hasn't actually crashed (it's still sending packets).
1305 */
1306 pending_txs_start = sc->pending_txs;
1307 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
1308 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
1309 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
1310 if (sc->pending_txs < pending_txs_start) {
1311 NVE_UNLOCK(sc);
1312 return;
1313 }
1314
1315 device_printf(sc->dev, "device timeout (%d)\n", sc->pending_txs);
1316
1317 sc->tx_errors++;
1318
1319 nve_stop(sc);
1320 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1321 nve_init_locked(sc);
1322
1323 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1324 nve_ifstart_locked(ifp);
1325 NVE_UNLOCK(sc);
1326
1327 return;
1328 }
1329
1330 /* --- Start of NVOSAPI interface --- */
1331
1332 /* Allocate DMA enabled general use memory for API */
1333 static NV_SINT32
1334 nve_osalloc(PNV_VOID ctx, PMEMORY_BLOCK mem)
1335 {
1336 struct nve_softc *sc;
1337 bus_addr_t mem_physical;
1338
1339 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osalloc - %d\n", mem->uiLength);
1340
1341 sc = (struct nve_softc *)ctx;
1342
1343 mem->pLogical = (PVOID)contigmalloc(mem->uiLength, M_DEVBUF,
1344 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
1345
1346 if (!mem->pLogical) {
1347 device_printf(sc->dev, "memory allocation failed\n");
1348 return (0);
1349 }
1350 memset(mem->pLogical, 0, (ulong)mem->uiLength);
1351 mem_physical = vtophys(mem->pLogical);
1352 mem->pPhysical = (PVOID)mem_physical;
1353
1354 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osalloc 0x%x/0x%x - %d\n",
1355 (uint)mem->pLogical, (uint)mem->pPhysical, (uint)mem->uiLength);
1356
1357 return (1);
1358 }
1359
1360 /* Free allocated memory */
1361 static NV_SINT32
1362 nve_osfree(PNV_VOID ctx, PMEMORY_BLOCK mem)
1363 {
1364 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfree - 0x%x - %d\n",
1365 (uint)mem->pLogical, (uint) mem->uiLength);
1366
1367 contigfree(mem->pLogical, PAGE_SIZE, M_DEVBUF);
1368 return (1);
1369 }
1370
1371 /* Copied directly from nvnet.c */
1372 static NV_SINT32
1373 nve_osallocex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
1374 {
1375 MEMORY_BLOCK mem_block;
1376
1377 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osallocex\n");
1378
1379 mem_block_ex->pLogical = NULL;
1380 mem_block_ex->uiLengthOrig = mem_block_ex->uiLength;
1381
1382 if ((mem_block_ex->AllocFlags & ALLOC_MEMORY_ALIGNED) &&
1383 (mem_block_ex->AlignmentSize > 1)) {
1384 DEBUGOUT(NVE_DEBUG_API, " aligning on %d\n",
1385 mem_block_ex->AlignmentSize);
1386 mem_block_ex->uiLengthOrig += mem_block_ex->AlignmentSize;
1387 }
1388 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1389
1390 if (nve_osalloc(ctx, &mem_block) == 0) {
1391 return (0);
1392 }
1393 mem_block_ex->pLogicalOrig = mem_block.pLogical;
1394 mem_block_ex->pPhysicalOrigLow = (unsigned long)mem_block.pPhysical;
1395 mem_block_ex->pPhysicalOrigHigh = 0;
1396
1397 mem_block_ex->pPhysical = mem_block.pPhysical;
1398 mem_block_ex->pLogical = mem_block.pLogical;
1399
1400 if (mem_block_ex->uiLength != mem_block_ex->uiLengthOrig) {
1401 unsigned int offset;
1402 offset = mem_block_ex->pPhysicalOrigLow &
1403 (mem_block_ex->AlignmentSize - 1);
1404
1405 if (offset) {
1406 mem_block_ex->pPhysical =
1407 (PVOID)((ulong)mem_block_ex->pPhysical +
1408 mem_block_ex->AlignmentSize - offset);
1409 mem_block_ex->pLogical =
1410 (PVOID)((ulong)mem_block_ex->pLogical +
1411 mem_block_ex->AlignmentSize - offset);
1412 } /* if (offset) */
1413 } /* if (mem_block_ex->uiLength != *mem_block_ex->uiLengthOrig) */
1414 return (1);
1415 }
1416
1417 /* Copied directly from nvnet.c */
1418 static NV_SINT32
1419 nve_osfreeex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
1420 {
1421 MEMORY_BLOCK mem_block;
1422
1423 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfreeex\n");
1424
1425 mem_block.pLogical = mem_block_ex->pLogicalOrig;
1426 mem_block.pPhysical = (PVOID)((ulong)mem_block_ex->pPhysicalOrigLow);
1427 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1428
1429 return (nve_osfree(ctx, &mem_block));
1430 }
1431
1432 /* Clear memory region */
1433 static NV_SINT32
1434 nve_osclear(PNV_VOID ctx, PNV_VOID mem, NV_SINT32 length)
1435 {
1436 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osclear\n");
1437 memset(mem, 0, length);
1438 return (1);
1439 }
1440
1441 /* Sleep for a tick */
1442 static NV_SINT32
1443 nve_osdelay(PNV_VOID ctx, NV_UINT32 usec)
1444 {
1445 DELAY(usec);
1446 return (1);
1447 }
1448
1449 /* Allocate memory for rx buffer */
1450 static NV_SINT32
1451 nve_osallocrxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID *id)
1452 {
1453 struct nve_softc *sc = ctx;
1454 struct nve_rx_desc *desc;
1455 struct nve_map_buffer *buf;
1456 int error;
1457
1458 if (device_is_attached(sc->dev))
1459 NVE_LOCK_ASSERT(sc);
1460
1461 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osallocrxbuf\n");
1462
1463 if (sc->pending_rxs == RX_RING_SIZE) {
1464 device_printf(sc->dev, "rx ring buffer is full\n");
1465 goto fail;
1466 }
1467 desc = sc->rx_desc + sc->cur_rx;
1468 buf = &desc->buf;
1469
1470 if (buf->mbuf == NULL) {
1471 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1472 if (buf->mbuf == NULL) {
1473 device_printf(sc->dev, "failed to allocate memory\n");
1474 goto fail;
1475 }
1476 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1477 m_adj(buf->mbuf, ETHER_ALIGN);
1478
1479 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1480 nve_dmamap_rx_cb, &desc->paddr, 0);
1481 if (error) {
1482 device_printf(sc->dev, "failed to dmamap mbuf\n");
1483 m_freem(buf->mbuf);
1484 buf->mbuf = NULL;
1485 goto fail;
1486 }
1487 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1488 desc->buflength = buf->mbuf->m_len;
1489 desc->vaddr = mtod(buf->mbuf, caddr_t);
1490 }
1491 sc->pending_rxs++;
1492 sc->cur_rx = (sc->cur_rx + 1) % RX_RING_SIZE;
1493
1494 mem->pLogical = (void *)desc->vaddr;
1495 mem->pPhysical = (void *)desc->paddr;
1496 mem->uiLength = desc->buflength;
1497 *id = (void *)desc;
1498
1499 return (1);
1500
1501 fail:
1502 return (0);
1503 }
1504
1505 /* Free the rx buffer */
1506 static NV_SINT32
1507 nve_osfreerxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID id)
1508 {
1509 struct nve_softc *sc = ctx;
1510 struct nve_rx_desc *desc;
1511 struct nve_map_buffer *buf;
1512
1513 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfreerxbuf\n");
1514
1515 desc = (struct nve_rx_desc *) id;
1516 buf = &desc->buf;
1517
1518 if (buf->mbuf) {
1519 bus_dmamap_unload(sc->mtag, buf->map);
1520 bus_dmamap_destroy(sc->mtag, buf->map);
1521 m_freem(buf->mbuf);
1522 }
1523 sc->pending_rxs--;
1524 buf->mbuf = NULL;
1525
1526 return (1);
1527 }
1528
1529 /* This gets called by the Nvidia API after our TX packet has been sent */
1530 static NV_SINT32
1531 nve_ospackettx(PNV_VOID ctx, PNV_VOID id, NV_UINT32 success)
1532 {
1533 struct nve_softc *sc = ctx;
1534 struct nve_map_buffer *buf;
1535 struct nve_tx_desc *desc = (struct nve_tx_desc *) id;
1536 struct ifnet *ifp;
1537
1538 NVE_LOCK_ASSERT(sc);
1539
1540 DEBUGOUT(NVE_DEBUG_API, "nve: nve_ospackettx\n");
1541
1542 ifp = sc->ifp;
1543 buf = &desc->buf;
1544 sc->pending_txs--;
1545
1546 /* Unload and free mbuf cluster */
1547 if (buf->mbuf == NULL)
1548 goto fail;
1549
1550 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
1551 bus_dmamap_unload(sc->mtag, buf->map);
1552 m_freem(buf->mbuf);
1553 buf->mbuf = NULL;
1554
1555 /* Send more packets if we have them */
1556 if (sc->pending_txs < TX_RING_SIZE)
1557 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1558
1559 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->pending_txs < TX_RING_SIZE)
1560 nve_ifstart_locked(ifp);
1561
1562 fail:
1563
1564 return (1);
1565 }
1566
1567 /* This gets called by the Nvidia API when a new packet has been received */
1568 /* XXX What is newbuf used for? XXX */
1569 static NV_SINT32
1570 nve_ospacketrx(PNV_VOID ctx, PNV_VOID data, NV_UINT32 success, NV_UINT8 *newbuf,
1571 NV_UINT8 priority)
1572 {
1573 struct nve_softc *sc = ctx;
1574 struct ifnet *ifp;
1575 struct nve_rx_desc *desc;
1576 struct nve_map_buffer *buf;
1577 ADAPTER_READ_DATA *readdata;
1578 struct mbuf *m;
1579
1580 NVE_LOCK_ASSERT(sc);
1581
1582 DEBUGOUT(NVE_DEBUG_API, "nve: nve_ospacketrx\n");
1583
1584 ifp = sc->ifp;
1585
1586 readdata = (ADAPTER_READ_DATA *) data;
1587 desc = readdata->pvID;
1588 buf = &desc->buf;
1589 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1590
1591 if (success) {
1592 /* Sync DMA bounce buffer. */
1593 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1594
1595 /* First mbuf in packet holds the ethernet and packet headers */
1596 buf->mbuf->m_pkthdr.rcvif = ifp;
1597 buf->mbuf->m_pkthdr.len = buf->mbuf->m_len =
1598 readdata->ulTotalLength;
1599
1600 bus_dmamap_unload(sc->mtag, buf->map);
1601
1602 /* Blat the mbuf pointer, kernel will free the mbuf cluster */
1603 m = buf->mbuf;
1604 buf->mbuf = NULL;
1605
1606 /* Give mbuf to OS. */
1607 NVE_UNLOCK(sc);
1608 (*ifp->if_input)(ifp, m);
1609 NVE_LOCK(sc);
1610 if (readdata->ulFilterMatch & ADREADFL_MULTICAST_MATCH)
1611 ifp->if_imcasts++;
1612
1613 } else {
1614 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1615 bus_dmamap_unload(sc->mtag, buf->map);
1616 m_freem(buf->mbuf);
1617 buf->mbuf = NULL;
1618 }
1619
1620 sc->cur_rx = desc - sc->rx_desc;
1621 sc->pending_rxs--;
1622
1623 return (1);
1624 }
1625
1626 /* This gets called by NVIDIA API when the PHY link state changes */
1627 static NV_SINT32
1628 nve_oslinkchg(PNV_VOID ctx, NV_SINT32 enabled)
1629 {
1630
1631 DEBUGOUT(NVE_DEBUG_API, "nve: nve_oslinkchg\n");
1632
1633 return (1);
1634 }
1635
1636 /* Setup a watchdog timer */
1637 static NV_SINT32
1638 nve_osalloctimer(PNV_VOID ctx, PNV_VOID *timer)
1639 {
1640 struct nve_softc *sc = (struct nve_softc *)ctx;
1641
1642 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osalloctimer\n");
1643
1644 callout_init(&sc->ostimer, CALLOUT_MPSAFE);
1645 *timer = &sc->ostimer;
1646
1647 return (1);
1648 }
1649
1650 /* Free the timer */
1651 static NV_SINT32
1652 nve_osfreetimer(PNV_VOID ctx, PNV_VOID timer)
1653 {
1654
1655 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osfreetimer\n");
1656
1657 callout_drain((struct callout *)timer);
1658
1659 return (1);
1660 }
1661
1662 /* Setup timer parameters */
1663 static NV_SINT32
1664 nve_osinittimer(PNV_VOID ctx, PNV_VOID timer, PTIMER_FUNC func, PNV_VOID parameters)
1665 {
1666 struct nve_softc *sc = (struct nve_softc *)ctx;
1667
1668 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osinittimer\n");
1669
1670 sc->ostimer_func = func;
1671 sc->ostimer_params = parameters;
1672
1673 return (1);
1674 }
1675
1676 /* Set the timer to go off */
1677 static NV_SINT32
1678 nve_ossettimer(PNV_VOID ctx, PNV_VOID timer, NV_UINT32 delay)
1679 {
1680 struct nve_softc *sc = ctx;
1681
1682 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ossettimer\n");
1683
1684 callout_reset((struct callout *)timer, delay, sc->ostimer_func,
1685 sc->ostimer_params);
1686
1687 return (1);
1688 }
1689
1690 /* Cancel the timer */
1691 static NV_SINT32
1692 nve_oscanceltimer(PNV_VOID ctx, PNV_VOID timer)
1693 {
1694
1695 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_oscanceltimer\n");
1696
1697 callout_stop((struct callout *)timer);
1698
1699 return (1);
1700 }
1701
1702 static NV_SINT32
1703 nve_ospreprocpkt(PNV_VOID ctx, PNV_VOID readdata, PNV_VOID *id,
1704 NV_UINT8 *newbuffer, NV_UINT8 priority)
1705 {
1706
1707 /* Not implemented */
1708 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ospreprocpkt\n");
1709
1710 return (1);
1711 }
1712
1713 static PNV_VOID
1714 nve_ospreprocpktnopq(PNV_VOID ctx, PNV_VOID readdata)
1715 {
1716
1717 /* Not implemented */
1718 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ospreprocpkt\n");
1719
1720 return (NULL);
1721 }
1722
1723 static NV_SINT32
1724 nve_osindicatepkt(PNV_VOID ctx, PNV_VOID *id, NV_UINT32 pktno)
1725 {
1726
1727 /* Not implemented */
1728 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osindicatepkt\n");
1729
1730 return (1);
1731 }
1732
1733 /* Allocate mutex context (already done in nve_attach) */
1734 static NV_SINT32
1735 nve_oslockalloc(PNV_VOID ctx, NV_SINT32 type, PNV_VOID *pLock)
1736 {
1737 struct nve_softc *sc = (struct nve_softc *)ctx;
1738
1739 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockalloc\n");
1740
1741 *pLock = (void **)sc;
1742
1743 return (1);
1744 }
1745
1746 /* Obtain a spin lock */
1747 static NV_SINT32
1748 nve_oslockacquire(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
1749 {
1750
1751 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockacquire\n");
1752
1753 return (1);
1754 }
1755
1756 /* Release lock */
1757 static NV_SINT32
1758 nve_oslockrelease(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
1759 {
1760
1761 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockrelease\n");
1762
1763 return (1);
1764 }
1765
1766 /* I have no idea what this is for */
1767 static PNV_VOID
1768 nve_osreturnbufvirt(PNV_VOID ctx, PNV_VOID readdata)
1769 {
1770
1771 /* Not implemented */
1772 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_osreturnbufvirt\n");
1773 panic("nve: nve_osreturnbufvirtual not implemented\n");
1774
1775 return (NULL);
1776 }
1777
1778 /* --- End on NVOSAPI interface --- */
Cache object: df3384f3821f934d3d415b07a723e101
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