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sys/dev/nvme/nvme.h
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1 /*- 2 * Copyright (C) 2012-2013 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __NVME_H__ 30 #define __NVME_H__ 31 32 #ifdef _KERNEL 33 #include <sys/types.h> 34 #endif 35 36 #include <sys/param.h> 37 38 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 39 #define NVME_RESET_CONTROLLER _IO('n', 1) 40 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid) 41 42 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 43 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 44 45 /* 46 * Macros to deal with NVME revisions, as defined VS register 47 */ 48 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 49 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 50 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 51 52 /* 53 * Use to mark a command to apply to all namespaces, or to retrieve global 54 * log pages. 55 */ 56 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 57 58 /* Cap nvme to 1MB transfers driver explodes with larger sizes */ 59 #define NVME_MAX_XFER_SIZE (MAXPHYS < (1<<20) ? MAXPHYS : (1<<20)) 60 61 union cap_lo_register { 62 uint32_t raw; 63 struct { 64 /** maximum queue entries supported */ 65 uint32_t mqes : 16; 66 67 /** contiguous queues required */ 68 uint32_t cqr : 1; 69 70 /** arbitration mechanism supported */ 71 uint32_t ams : 2; 72 73 uint32_t reserved1 : 5; 74 75 /** timeout */ 76 uint32_t to : 8; 77 } bits __packed; 78 } __packed; 79 80 _Static_assert(sizeof(union cap_lo_register) == 4, "bad size for cap_lo_register"); 81 82 union cap_hi_register { 83 uint32_t raw; 84 struct { 85 /** doorbell stride */ 86 uint32_t dstrd : 4; 87 88 uint32_t reserved3 : 1; 89 90 /** command sets supported */ 91 uint32_t css_nvm : 1; 92 93 uint32_t css_reserved : 3; 94 uint32_t reserved2 : 7; 95 96 /** memory page size minimum */ 97 uint32_t mpsmin : 4; 98 99 /** memory page size maximum */ 100 uint32_t mpsmax : 4; 101 102 uint32_t reserved1 : 8; 103 } bits __packed; 104 } __packed; 105 106 _Static_assert(sizeof(union cap_hi_register) == 4, "bad size of cap_hi_register"); 107 108 union cc_register { 109 uint32_t raw; 110 struct { 111 /** enable */ 112 uint32_t en : 1; 113 114 uint32_t reserved1 : 3; 115 116 /** i/o command set selected */ 117 uint32_t css : 3; 118 119 /** memory page size */ 120 uint32_t mps : 4; 121 122 /** arbitration mechanism selected */ 123 uint32_t ams : 3; 124 125 /** shutdown notification */ 126 uint32_t shn : 2; 127 128 /** i/o submission queue entry size */ 129 uint32_t iosqes : 4; 130 131 /** i/o completion queue entry size */ 132 uint32_t iocqes : 4; 133 134 uint32_t reserved2 : 8; 135 } bits __packed; 136 } __packed; 137 138 _Static_assert(sizeof(union cc_register) == 4, "bad size for cc_register"); 139 140 enum shn_value { 141 NVME_SHN_NORMAL = 0x1, 142 NVME_SHN_ABRUPT = 0x2, 143 }; 144 145 union csts_register { 146 uint32_t raw; 147 struct { 148 /** ready */ 149 uint32_t rdy : 1; 150 151 /** controller fatal status */ 152 uint32_t cfs : 1; 153 154 /** shutdown status */ 155 uint32_t shst : 2; 156 157 uint32_t reserved1 : 28; 158 } bits __packed; 159 } __packed; 160 161 _Static_assert(sizeof(union csts_register) == 4, "bad size for csts_register"); 162 163 enum shst_value { 164 NVME_SHST_NORMAL = 0x0, 165 NVME_SHST_OCCURRING = 0x1, 166 NVME_SHST_COMPLETE = 0x2, 167 }; 168 169 union aqa_register { 170 uint32_t raw; 171 struct { 172 /** admin submission queue size */ 173 uint32_t asqs : 12; 174 175 uint32_t reserved1 : 4; 176 177 /** admin completion queue size */ 178 uint32_t acqs : 12; 179 180 uint32_t reserved2 : 4; 181 } bits __packed; 182 } __packed; 183 184 _Static_assert(sizeof(union aqa_register) == 4, "bad size for aqa_resgister"); 185 186 struct nvme_registers 187 { 188 /** controller capabilities */ 189 union cap_lo_register cap_lo; 190 union cap_hi_register cap_hi; 191 192 uint32_t vs; /* version */ 193 uint32_t intms; /* interrupt mask set */ 194 uint32_t intmc; /* interrupt mask clear */ 195 196 /** controller configuration */ 197 union cc_register cc; 198 199 uint32_t reserved1; 200 201 /** controller status */ 202 union csts_register csts; 203 204 uint32_t reserved2; 205 206 /** admin queue attributes */ 207 union aqa_register aqa; 208 209 uint64_t asq; /* admin submission queue base addr */ 210 uint64_t acq; /* admin completion queue base addr */ 211 uint32_t reserved3[0x3f2]; 212 213 struct { 214 uint32_t sq_tdbl; /* submission queue tail doorbell */ 215 uint32_t cq_hdbl; /* completion queue head doorbell */ 216 } doorbell[1] __packed; 217 } __packed; 218 219 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 220 221 struct nvme_command 222 { 223 /* dword 0 */ 224 uint16_t opc : 8; /* opcode */ 225 uint16_t fuse : 2; /* fused operation */ 226 uint16_t rsvd1 : 6; 227 uint16_t cid; /* command identifier */ 228 229 /* dword 1 */ 230 uint32_t nsid; /* namespace identifier */ 231 232 /* dword 2-3 */ 233 uint32_t rsvd2; 234 uint32_t rsvd3; 235 236 /* dword 4-5 */ 237 uint64_t mptr; /* metadata pointer */ 238 239 /* dword 6-7 */ 240 uint64_t prp1; /* prp entry 1 */ 241 242 /* dword 8-9 */ 243 uint64_t prp2; /* prp entry 2 */ 244 245 /* dword 10-15 */ 246 uint32_t cdw10; /* command-specific */ 247 uint32_t cdw11; /* command-specific */ 248 uint32_t cdw12; /* command-specific */ 249 uint32_t cdw13; /* command-specific */ 250 uint32_t cdw14; /* command-specific */ 251 uint32_t cdw15; /* command-specific */ 252 } __packed; 253 254 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 255 256 struct nvme_status { 257 258 uint16_t p : 1; /* phase tag */ 259 uint16_t sc : 8; /* status code */ 260 uint16_t sct : 3; /* status code type */ 261 uint16_t rsvd2 : 2; 262 uint16_t m : 1; /* more */ 263 uint16_t dnr : 1; /* do not retry */ 264 } __packed; 265 266 _Static_assert(sizeof(struct nvme_status) == 2, "bad size for nvme_status"); 267 268 struct nvme_completion { 269 270 /* dword 0 */ 271 uint32_t cdw0; /* command-specific */ 272 273 /* dword 1 */ 274 uint32_t rsvd1; 275 276 /* dword 2 */ 277 uint16_t sqhd; /* submission queue head pointer */ 278 uint16_t sqid; /* submission queue identifier */ 279 280 /* dword 3 */ 281 uint16_t cid; /* command identifier */ 282 struct nvme_status status; 283 } __packed; 284 285 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 286 287 struct nvme_dsm_range { 288 289 uint32_t attributes; 290 uint32_t length; 291 uint64_t starting_lba; 292 } __packed; 293 294 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 295 296 /* status code types */ 297 enum nvme_status_code_type { 298 NVME_SCT_GENERIC = 0x0, 299 NVME_SCT_COMMAND_SPECIFIC = 0x1, 300 NVME_SCT_MEDIA_ERROR = 0x2, 301 /* 0x3-0x6 - reserved */ 302 NVME_SCT_VENDOR_SPECIFIC = 0x7, 303 }; 304 305 /* generic command status codes */ 306 enum nvme_generic_command_status_code { 307 NVME_SC_SUCCESS = 0x00, 308 NVME_SC_INVALID_OPCODE = 0x01, 309 NVME_SC_INVALID_FIELD = 0x02, 310 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 311 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 312 NVME_SC_ABORTED_POWER_LOSS = 0x05, 313 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 314 NVME_SC_ABORTED_BY_REQUEST = 0x07, 315 NVME_SC_ABORTED_SQ_DELETION = 0x08, 316 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 317 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 318 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 319 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 320 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 321 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 322 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 323 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 324 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 325 NVME_SC_INVALID_USE_OF_CMB = 0x12, 326 NVME_SC_PRP_OFFET_INVALID = 0x13, 327 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 328 NVME_SC_OPERATION_DENIED = 0x15, 329 NVME_SC_SGL_OFFSET_INVALID = 0x16, 330 /* 0x17 - reserved */ 331 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 332 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 333 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 334 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 335 NVME_SC_SANITIZE_FAILED = 0x1c, 336 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 337 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 338 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 339 340 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 341 NVME_SC_CAPACITY_EXCEEDED = 0x81, 342 NVME_SC_NAMESPACE_NOT_READY = 0x82, 343 NVME_SC_RESERVATION_CONFLICT = 0x83, 344 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 345 }; 346 347 /* command specific status codes */ 348 enum nvme_command_specific_status_code { 349 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 350 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 351 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 352 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 353 /* 0x04 - reserved */ 354 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 355 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 356 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 357 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 358 NVME_SC_INVALID_LOG_PAGE = 0x09, 359 NVME_SC_INVALID_FORMAT = 0x0a, 360 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 361 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 362 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 363 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 364 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 365 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 366 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 367 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 368 NVME_SC_FW_ACT_PROHIBITED = 0x13, 369 NVME_SC_OVERLAPPING_RANGE = 0x14, 370 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 371 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 372 /* 0x17 - reserved */ 373 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 374 NVME_SC_NS_IS_PRIVATE = 0x19, 375 NVME_SC_NS_NOT_ATTACHED = 0x1a, 376 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 377 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 378 NVME_SC_SELT_TEST_IN_PROGRESS = 0x1d, 379 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 380 NVME_SC_INVALID_CTRLR_ID = 0x1f, 381 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 382 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 383 NVME_SC_INVALID_RESOURCE_ID = 0x22, 384 385 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 386 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 387 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 388 }; 389 390 /* media error status codes */ 391 enum nvme_media_error_status_code { 392 NVME_SC_WRITE_FAULTS = 0x80, 393 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 394 NVME_SC_GUARD_CHECK_ERROR = 0x82, 395 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 396 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 397 NVME_SC_COMPARE_FAILURE = 0x85, 398 NVME_SC_ACCESS_DENIED = 0x86, 399 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 400 }; 401 402 /* admin opcodes */ 403 enum nvme_admin_opcode { 404 NVME_OPC_DELETE_IO_SQ = 0x00, 405 NVME_OPC_CREATE_IO_SQ = 0x01, 406 NVME_OPC_GET_LOG_PAGE = 0x02, 407 /* 0x03 - reserved */ 408 NVME_OPC_DELETE_IO_CQ = 0x04, 409 NVME_OPC_CREATE_IO_CQ = 0x05, 410 NVME_OPC_IDENTIFY = 0x06, 411 /* 0x07 - reserved */ 412 NVME_OPC_ABORT = 0x08, 413 NVME_OPC_SET_FEATURES = 0x09, 414 NVME_OPC_GET_FEATURES = 0x0a, 415 /* 0x0b - reserved */ 416 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 417 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 418 /* 0x0e-0x0f - reserved */ 419 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 420 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 421 NVME_OPC_DEVICE_SELF_TEST = 0x14, 422 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 423 NVME_OPC_KEEP_ALIVE = 0x18, 424 NVME_OPC_DIRECTIVE_SEND = 0x19, 425 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 426 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 427 NVME_OPC_NVME_MI_SEND = 0x1d, 428 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 429 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 430 431 NVME_OPC_FORMAT_NVM = 0x80, 432 NVME_OPC_SECURITY_SEND = 0x81, 433 NVME_OPC_SECURITY_RECEIVE = 0x82, 434 NVME_OPC_SANITIZE = 0x84, 435 }; 436 437 /* nvme nvm opcodes */ 438 enum nvme_nvm_opcode { 439 NVME_OPC_FLUSH = 0x00, 440 NVME_OPC_WRITE = 0x01, 441 NVME_OPC_READ = 0x02, 442 /* 0x03 - reserved */ 443 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 444 NVME_OPC_COMPARE = 0x05, 445 /* 0x06 - reserved */ 446 NVME_OPC_WRITE_ZEROES = 0x08, 447 /* 0x07 - reserved */ 448 NVME_OPC_DATASET_MANAGEMENT = 0x09, 449 /* 0x0a-0x0c - reserved */ 450 NVME_OPC_RESERVATION_REGISTER = 0x0d, 451 NVME_OPC_RESERVATION_REPORT = 0x0e, 452 /* 0x0f-0x10 - reserved */ 453 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 454 /* 0x12-0x14 - reserved */ 455 NVME_OPC_RESERVATION_RELEASE = 0x15, 456 }; 457 458 enum nvme_feature { 459 /* 0x00 - reserved */ 460 NVME_FEAT_ARBITRATION = 0x01, 461 NVME_FEAT_POWER_MANAGEMENT = 0x02, 462 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 463 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 464 NVME_FEAT_ERROR_RECOVERY = 0x05, 465 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 466 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 467 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 468 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 469 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 470 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 471 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 472 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 473 NVME_FEAT_TIMESTAMP = 0x0E, 474 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 475 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 476 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 477 /* 0x12-0x77 - reserved */ 478 /* 0x78-0x7f - NVMe Management Interface */ 479 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 480 /* 0x81-0xBF - command set specific (reserved) */ 481 /* 0xC0-0xFF - vendor specific */ 482 }; 483 484 enum nvme_dsm_attribute { 485 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 486 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 487 NVME_DSM_ATTR_DEALLOCATE = 0x4, 488 }; 489 490 enum nvme_activate_action { 491 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 492 NVME_AA_REPLACE_ACTIVATE = 0x1, 493 NVME_AA_ACTIVATE = 0x2, 494 }; 495 496 struct nvme_power_state { 497 /** Maximum Power */ 498 uint16_t mp; /* Maximum Power */ 499 uint8_t ps_rsvd1; 500 uint8_t mps : 1; /* Max Power Scale */ 501 uint8_t nops : 1; /* Non-Operational State */ 502 uint8_t ps_rsvd2 : 6; 503 uint32_t enlat; /* Entry Latency */ 504 uint32_t exlat; /* Exit Latency */ 505 uint8_t rrt : 5; /* Relative Read Throughput */ 506 uint8_t ps_rsvd3 : 3; 507 uint8_t rrl : 5; /* Relative Read Latency */ 508 uint8_t ps_rsvd4 : 3; 509 uint8_t rwt : 5; /* Relative Write Throughput */ 510 uint8_t ps_rsvd5 : 3; 511 uint8_t rwl : 5; /* Relative Write Latency */ 512 uint8_t ps_rsvd6 : 3; 513 uint16_t idlp; /* Idle Power */ 514 uint8_t ps_rsvd7 : 6; 515 uint8_t ips : 2; /* Idle Power Scale */ 516 uint8_t ps_rsvd8; 517 uint16_t actp; /* Active Power */ 518 uint8_t apw : 3; /* Active Power Workload */ 519 uint8_t ps_rsvd9 : 3; 520 uint8_t aps : 2; /* Active Power Scale */ 521 uint8_t ps_rsvd10[9]; 522 } __packed; 523 524 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 525 526 #define NVME_SERIAL_NUMBER_LENGTH 20 527 #define NVME_MODEL_NUMBER_LENGTH 40 528 #define NVME_FIRMWARE_REVISION_LENGTH 8 529 530 struct nvme_controller_data { 531 532 /* bytes 0-255: controller capabilities and features */ 533 534 /** pci vendor id */ 535 uint16_t vid; 536 537 /** pci subsystem vendor id */ 538 uint16_t ssvid; 539 540 /** serial number */ 541 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 542 543 /** model number */ 544 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 545 546 /** firmware revision */ 547 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 548 549 /** recommended arbitration burst */ 550 uint8_t rab; 551 552 /** ieee oui identifier */ 553 uint8_t ieee[3]; 554 555 /** multi-interface capabilities */ 556 uint8_t mic; 557 558 /** maximum data transfer size */ 559 uint8_t mdts; 560 561 /** Controller ID */ 562 uint16_t ctrlr_id; 563 564 /** Version */ 565 uint32_t ver; 566 567 /** RTD3 Resume Latency */ 568 uint32_t rtd3r; 569 570 /** RTD3 Enter Latency */ 571 uint32_t rtd3e; 572 573 /** Optional Asynchronous Events Supported */ 574 uint32_t oaes; /* bitfield really */ 575 576 /** Controller Attributes */ 577 uint32_t ctratt; /* bitfield really */ 578 579 uint8_t reserved1[12]; 580 581 /** FRU Globally Unique Identifier */ 582 uint8_t fguid[16]; 583 584 uint8_t reserved2[128]; 585 586 /* bytes 256-511: admin command set attributes */ 587 588 /** optional admin command support */ 589 struct { 590 /* supports security send/receive commands */ 591 uint16_t security : 1; 592 593 /* supports format nvm command */ 594 uint16_t format : 1; 595 596 /* supports firmware activate/download commands */ 597 uint16_t firmware : 1; 598 599 /* supports namespace management commands */ 600 uint16_t nsmgmt : 1; 601 602 uint16_t oacs_rsvd : 12; 603 } __packed oacs; 604 605 /** abort command limit */ 606 uint8_t acl; 607 608 /** asynchronous event request limit */ 609 uint8_t aerl; 610 611 /** firmware updates */ 612 struct { 613 /* first slot is read-only */ 614 uint8_t slot1_ro : 1; 615 616 /* number of firmware slots */ 617 uint8_t num_slots : 3; 618 619 uint8_t frmw_rsvd : 4; 620 } __packed frmw; 621 622 /** log page attributes */ 623 struct { 624 /* per namespace smart/health log page */ 625 uint8_t ns_smart : 1; 626 627 uint8_t lpa_rsvd : 7; 628 } __packed lpa; 629 630 /** error log page entries */ 631 uint8_t elpe; 632 633 /** number of power states supported */ 634 uint8_t npss; 635 636 /** admin vendor specific command configuration */ 637 struct { 638 /* admin vendor specific commands use spec format */ 639 uint8_t spec_format : 1; 640 641 uint8_t avscc_rsvd : 7; 642 } __packed avscc; 643 644 /** Autonomous Power State Transition Attributes */ 645 struct { 646 /* Autonmous Power State Transitions supported */ 647 uint8_t apst_supp : 1; 648 649 uint8_t apsta_rsvd : 7; 650 } __packed apsta; 651 652 /** Warning Composite Temperature Threshold */ 653 uint16_t wctemp; 654 655 /** Critical Composite Temperature Threshold */ 656 uint16_t cctemp; 657 658 /** Maximum Time for Firmware Activation */ 659 uint16_t mtfa; 660 661 /** Host Memory Buffer Preferred Size */ 662 uint32_t hmpre; 663 664 /** Host Memory Buffer Minimum Size */ 665 uint32_t hmmin; 666 667 /** Name space capabilities */ 668 struct { 669 /* if nsmgmt, report tnvmcap and unvmcap */ 670 uint8_t tnvmcap[16]; 671 uint8_t unvmcap[16]; 672 } __packed untncap; 673 674 /** Replay Protected Memory Block Support */ 675 uint32_t rpmbs; /* Really a bitfield */ 676 677 /** Extended Device Self-test Time */ 678 uint16_t edstt; 679 680 /** Device Self-test Options */ 681 uint8_t dsto; /* Really a bitfield */ 682 683 /** Firmware Update Granularity */ 684 uint8_t fwug; 685 686 /** Keep Alive Support */ 687 uint16_t kas; 688 689 /** Host Controlled Thermal Management Attributes */ 690 uint16_t hctma; /* Really a bitfield */ 691 692 /** Minimum Thermal Management Temperature */ 693 uint16_t mntmt; 694 695 /** Maximum Thermal Management Temperature */ 696 uint16_t mxtmt; 697 698 /** Sanitize Capabilities */ 699 uint32_t sanicap; /* Really a bitfield */ 700 701 uint8_t reserved3[180]; 702 /* bytes 512-703: nvm command set attributes */ 703 704 /** submission queue entry size */ 705 struct { 706 uint8_t min : 4; 707 uint8_t max : 4; 708 } __packed sqes; 709 710 /** completion queue entry size */ 711 struct { 712 uint8_t min : 4; 713 uint8_t max : 4; 714 } __packed cqes; 715 716 /** Maximum Outstanding Commands */ 717 uint16_t maxcmd; 718 719 /** number of namespaces */ 720 uint32_t nn; 721 722 /** optional nvm command support */ 723 struct { 724 uint16_t compare : 1; 725 uint16_t write_unc : 1; 726 uint16_t dsm: 1; 727 uint16_t reserved: 13; 728 } __packed oncs; 729 730 /** fused operation support */ 731 uint16_t fuses; 732 733 /** format nvm attributes */ 734 uint8_t fna; 735 736 /** volatile write cache */ 737 struct { 738 uint8_t present : 1; 739 uint8_t reserved : 7; 740 } __packed vwc; 741 742 /* TODO: flesh out remaining nvm command set attributes */ 743 uint8_t reserved5[178]; 744 745 /* bytes 704-2047: i/o command set attributes */ 746 uint8_t reserved6[1344]; 747 748 /* bytes 2048-3071: power state descriptors */ 749 struct nvme_power_state power_state[32]; 750 751 /* bytes 3072-4095: vendor specific */ 752 uint8_t vs[1024]; 753 } __packed __aligned(4); 754 755 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 756 757 struct nvme_namespace_data { 758 759 /** namespace size */ 760 uint64_t nsze; 761 762 /** namespace capacity */ 763 uint64_t ncap; 764 765 /** namespace utilization */ 766 uint64_t nuse; 767 768 /** namespace features */ 769 struct { 770 /** thin provisioning */ 771 uint8_t thin_prov : 1; 772 uint8_t reserved1 : 7; 773 } __packed nsfeat; 774 775 /** number of lba formats */ 776 uint8_t nlbaf; 777 778 /** formatted lba size */ 779 struct { 780 uint8_t format : 4; 781 uint8_t extended : 1; 782 uint8_t reserved2 : 3; 783 } __packed flbas; 784 785 /** metadata capabilities */ 786 struct { 787 /* metadata can be transferred as part of data prp list */ 788 uint8_t extended : 1; 789 790 /* metadata can be transferred with separate metadata pointer */ 791 uint8_t pointer : 1; 792 793 uint8_t reserved3 : 6; 794 } __packed mc; 795 796 /** end-to-end data protection capabilities */ 797 struct { 798 /* protection information type 1 */ 799 uint8_t pit1 : 1; 800 801 /* protection information type 2 */ 802 uint8_t pit2 : 1; 803 804 /* protection information type 3 */ 805 uint8_t pit3 : 1; 806 807 /* first eight bytes of metadata */ 808 uint8_t md_start : 1; 809 810 /* last eight bytes of metadata */ 811 uint8_t md_end : 1; 812 } __packed dpc; 813 814 /** end-to-end data protection type settings */ 815 struct { 816 /* protection information type */ 817 uint8_t pit : 3; 818 819 /* 1 == protection info transferred at start of metadata */ 820 /* 0 == protection info transferred at end of metadata */ 821 uint8_t md_start : 1; 822 823 uint8_t reserved4 : 4; 824 } __packed dps; 825 826 uint8_t reserved5[98]; 827 828 /** lba format support */ 829 struct { 830 /** metadata size */ 831 uint32_t ms : 16; 832 833 /** lba data size */ 834 uint32_t lbads : 8; 835 836 /** relative performance */ 837 uint32_t rp : 2; 838 839 uint32_t reserved6 : 6; 840 } __packed lbaf[16]; 841 842 uint8_t reserved6[192]; 843 844 uint8_t vendor_specific[3712]; 845 } __packed __aligned(4); 846 847 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 848 849 enum nvme_log_page { 850 851 /* 0x00 - reserved */ 852 NVME_LOG_ERROR = 0x01, 853 NVME_LOG_HEALTH_INFORMATION = 0x02, 854 NVME_LOG_FIRMWARE_SLOT = 0x03, 855 NVME_LOG_CHANGED_NAMESPACE = 0x04, 856 NVME_LOG_COMMAND_EFFECT = 0x05, 857 /* 0x06-0x7F - reserved */ 858 /* 0x80-0xBF - I/O command set specific */ 859 NVME_LOG_RES_NOTIFICATION = 0x80, 860 /* 0xC0-0xFF - vendor specific */ 861 862 /* 863 * The following are Intel Specific log pages, but they seem 864 * to be widely implemented. 865 */ 866 INTEL_LOG_READ_LAT_LOG = 0xc1, 867 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 868 INTEL_LOG_TEMP_STATS = 0xc5, 869 INTEL_LOG_ADD_SMART = 0xca, 870 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 871 872 /* 873 * HGST log page, with lots ofs sub pages. 874 */ 875 HGST_INFO_LOG = 0xc1, 876 }; 877 878 struct nvme_error_information_entry { 879 880 uint64_t error_count; 881 uint16_t sqid; 882 uint16_t cid; 883 struct nvme_status status; 884 uint16_t error_location; 885 uint64_t lba; 886 uint32_t nsid; 887 uint8_t vendor_specific; 888 uint8_t reserved[35]; 889 } __packed __aligned(4); 890 891 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 892 893 union nvme_critical_warning_state { 894 895 uint8_t raw; 896 897 struct { 898 uint8_t available_spare : 1; 899 uint8_t temperature : 1; 900 uint8_t device_reliability : 1; 901 uint8_t read_only : 1; 902 uint8_t volatile_memory_backup : 1; 903 uint8_t reserved : 3; 904 } __packed bits; 905 } __packed; 906 907 _Static_assert(sizeof(union nvme_critical_warning_state) == 1, "bad size for nvme_critical_warning_state"); 908 909 struct nvme_health_information_page { 910 911 union nvme_critical_warning_state critical_warning; 912 913 uint16_t temperature; 914 uint8_t available_spare; 915 uint8_t available_spare_threshold; 916 uint8_t percentage_used; 917 918 uint8_t reserved[26]; 919 920 /* 921 * Note that the following are 128-bit values, but are 922 * defined as an array of 2 64-bit values. 923 */ 924 /* Data Units Read is always in 512-byte units. */ 925 uint64_t data_units_read[2]; 926 /* Data Units Written is always in 512-byte units. */ 927 uint64_t data_units_written[2]; 928 /* For NVM command set, this includes Compare commands. */ 929 uint64_t host_read_commands[2]; 930 uint64_t host_write_commands[2]; 931 /* Controller Busy Time is reported in minutes. */ 932 uint64_t controller_busy_time[2]; 933 uint64_t power_cycles[2]; 934 uint64_t power_on_hours[2]; 935 uint64_t unsafe_shutdowns[2]; 936 uint64_t media_errors[2]; 937 uint64_t num_error_info_log_entries[2]; 938 uint32_t warning_temp_time; 939 uint32_t error_temp_time; 940 uint16_t temp_sensor[8]; 941 942 uint8_t reserved2[296]; 943 } __packed __aligned(4); 944 945 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 946 947 struct nvme_firmware_page { 948 949 struct { 950 uint8_t slot : 3; /* slot for current FW */ 951 uint8_t reserved : 5; 952 } __packed afi; 953 954 uint8_t reserved[7]; 955 uint64_t revision[7]; /* revisions for 7 slots */ 956 uint8_t reserved2[448]; 957 } __packed __aligned(4); 958 959 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 960 961 struct intel_log_temp_stats 962 { 963 uint64_t current; 964 uint64_t overtemp_flag_last; 965 uint64_t overtemp_flag_life; 966 uint64_t max_temp; 967 uint64_t min_temp; 968 uint64_t _rsvd[5]; 969 uint64_t max_oper_temp; 970 uint64_t min_oper_temp; 971 uint64_t est_offset; 972 } __packed __aligned(4); 973 974 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 975 976 #define NVME_TEST_MAX_THREADS 128 977 978 struct nvme_io_test { 979 980 enum nvme_nvm_opcode opc; 981 uint32_t size; 982 uint32_t time; /* in seconds */ 983 uint32_t num_threads; 984 uint32_t flags; 985 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 986 }; 987 988 enum nvme_io_test_flags { 989 990 /* 991 * Specifies whether dev_refthread/dev_relthread should be 992 * called during NVME_BIO_TEST. Ignored for other test 993 * types. 994 */ 995 NVME_TEST_FLAG_REFTHREAD = 0x1, 996 }; 997 998 struct nvme_pt_command { 999 1000 /* 1001 * cmd is used to specify a passthrough command to a controller or 1002 * namespace. 1003 * 1004 * The following fields from cmd may be specified by the caller: 1005 * * opc (opcode) 1006 * * nsid (namespace id) - for admin commands only 1007 * * cdw10-cdw15 1008 * 1009 * Remaining fields must be set to 0 by the caller. 1010 */ 1011 struct nvme_command cmd; 1012 1013 /* 1014 * cpl returns completion status for the passthrough command 1015 * specified by cmd. 1016 * 1017 * The following fields will be filled out by the driver, for 1018 * consumption by the caller: 1019 * * cdw0 1020 * * status (except for phase) 1021 * 1022 * Remaining fields will be set to 0 by the driver. 1023 */ 1024 struct nvme_completion cpl; 1025 1026 /* buf is the data buffer associated with this passthrough command. */ 1027 void * buf; 1028 1029 /* 1030 * len is the length of the data buffer associated with this 1031 * passthrough command. 1032 */ 1033 uint32_t len; 1034 1035 /* 1036 * is_read = 1 if the passthrough command will read data into the 1037 * supplied buffer from the controller. 1038 * 1039 * is_read = 0 if the passthrough command will write data from the 1040 * supplied buffer to the controller. 1041 */ 1042 uint32_t is_read; 1043 1044 /* 1045 * driver_lock is used by the driver only. It must be set to 0 1046 * by the caller. 1047 */ 1048 struct mtx * driver_lock; 1049 }; 1050 1051 struct nvme_get_nsid { 1052 char cdev[SPECNAMELEN + 1]; 1053 uint32_t nsid; 1054 }; 1055 1056 #define nvme_completion_is_error(cpl) \ 1057 ((cpl)->status.sc != 0 || (cpl)->status.sct != 0) 1058 1059 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1060 1061 #ifdef _KERNEL 1062 1063 struct bio; 1064 struct thread; 1065 1066 struct nvme_namespace; 1067 struct nvme_controller; 1068 struct nvme_consumer; 1069 1070 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1071 1072 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1073 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1074 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1075 uint32_t, void *, uint32_t); 1076 typedef void (*nvme_cons_fail_fn_t)(void *); 1077 1078 enum nvme_namespace_flags { 1079 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1080 NVME_NS_FLUSH_SUPPORTED = 0x2, 1081 }; 1082 1083 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1084 struct nvme_pt_command *pt, 1085 uint32_t nsid, int is_user_buffer, 1086 int is_admin_cmd); 1087 1088 /* Admin functions */ 1089 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1090 uint8_t feature, uint32_t cdw11, 1091 void *payload, uint32_t payload_size, 1092 nvme_cb_fn_t cb_fn, void *cb_arg); 1093 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1094 uint8_t feature, uint32_t cdw11, 1095 void *payload, uint32_t payload_size, 1096 nvme_cb_fn_t cb_fn, void *cb_arg); 1097 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1098 uint8_t log_page, uint32_t nsid, 1099 void *payload, uint32_t payload_size, 1100 nvme_cb_fn_t cb_fn, void *cb_arg); 1101 1102 /* NVM I/O functions */ 1103 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1104 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1105 void *cb_arg); 1106 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1107 nvme_cb_fn_t cb_fn, void *cb_arg); 1108 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1109 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1110 void *cb_arg); 1111 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1112 nvme_cb_fn_t cb_fn, void *cb_arg); 1113 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1114 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1115 void *cb_arg); 1116 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1117 void *cb_arg); 1118 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1119 size_t len); 1120 1121 /* Registration functions */ 1122 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1123 nvme_cons_ctrlr_fn_t ctrlr_fn, 1124 nvme_cons_async_fn_t async_fn, 1125 nvme_cons_fail_fn_t fail_fn); 1126 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1127 1128 /* Controller helper functions */ 1129 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1130 const struct nvme_controller_data * 1131 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1132 1133 /* Namespace helper functions */ 1134 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1135 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1136 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1137 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1138 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1139 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1140 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1141 const struct nvme_namespace_data * 1142 nvme_ns_get_data(struct nvme_namespace *ns); 1143 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1144 1145 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1146 nvme_cb_fn_t cb_fn); 1147 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd, 1148 caddr_t arg, int flag, struct thread *td); 1149 1150 /* 1151 * Command building helper functions -- shared with CAM 1152 * These functions assume allocator zeros out cmd structure 1153 * CAM's xpt_get_ccb and the request allocator for nvme both 1154 * do zero'd allocations. 1155 */ 1156 static inline 1157 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1158 { 1159 1160 cmd->opc = NVME_OPC_FLUSH; 1161 cmd->nsid = nsid; 1162 } 1163 1164 static inline 1165 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1166 uint64_t lba, uint32_t count) 1167 { 1168 cmd->opc = rwcmd; 1169 cmd->nsid = nsid; 1170 cmd->cdw10 = lba & 0xffffffffu; 1171 cmd->cdw11 = lba >> 32; 1172 cmd->cdw12 = count-1; 1173 } 1174 1175 static inline 1176 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1177 uint64_t lba, uint32_t count) 1178 { 1179 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1180 } 1181 1182 static inline 1183 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1184 uint64_t lba, uint32_t count) 1185 { 1186 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1187 } 1188 1189 static inline 1190 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1191 uint32_t num_ranges) 1192 { 1193 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1194 cmd->nsid = nsid; 1195 cmd->cdw10 = num_ranges - 1; 1196 cmd->cdw11 = NVME_DSM_ATTR_DEALLOCATE; 1197 } 1198 1199 extern int nvme_use_nvd; 1200 1201 #endif /* _KERNEL */ 1202 1203 #endif /* __NVME_H__ */
Cache object: c2228170d361e41fe4ed9f4b544d0f29
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