Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/nvme/nvme_pci.c
Version:
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1 /*- 2 * Copyright (C) 2012-2016 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 #include <vm/vm.h> 38 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 42 #include "nvme_private.h" 43 44 static int nvme_pci_probe(device_t); 45 static int nvme_pci_attach(device_t); 46 static int nvme_pci_detach(device_t); 47 static int nvme_pci_suspend(device_t); 48 static int nvme_pci_resume(device_t); 49 50 static int nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); 51 52 static device_method_t nvme_pci_methods[] = { 53 /* Device interface */ 54 DEVMETHOD(device_probe, nvme_pci_probe), 55 DEVMETHOD(device_attach, nvme_pci_attach), 56 DEVMETHOD(device_detach, nvme_pci_detach), 57 DEVMETHOD(device_suspend, nvme_pci_suspend), 58 DEVMETHOD(device_resume, nvme_pci_resume), 59 DEVMETHOD(device_shutdown, nvme_shutdown), 60 { 0, 0 } 61 }; 62 63 static driver_t nvme_pci_driver = { 64 "nvme", 65 nvme_pci_methods, 66 sizeof(struct nvme_controller), 67 }; 68 69 DRIVER_MODULE(nvme, pci, nvme_pci_driver, nvme_devclass, NULL, 0); 70 71 static struct _pcsid 72 { 73 uint32_t devid; 74 int match_subdevice; 75 uint16_t subdevice; 76 const char *desc; 77 uint32_t quirks; 78 } pci_ids[] = { 79 { 0x01118086, 0, 0, "NVMe Controller" }, 80 { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, 81 { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, 82 { 0x09538086, 1, 0x3702, "DC P3700 SSD" }, 83 { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, 84 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, 85 { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, 86 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, 87 { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, 88 { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY }, 89 { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY }, 90 { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY }, 91 { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY }, 92 { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY }, 93 { 0x00000000, 0, 0, NULL } 94 }; 95 96 static int 97 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) 98 { 99 if (devid != ep->devid) 100 return 0; 101 102 if (!ep->match_subdevice) 103 return 1; 104 105 if (subdevice == ep->subdevice) 106 return 1; 107 else 108 return 0; 109 } 110 111 static int 112 nvme_pci_probe (device_t device) 113 { 114 struct nvme_controller *ctrlr = DEVICE2SOFTC(device); 115 struct _pcsid *ep; 116 uint32_t devid; 117 uint16_t subdevice; 118 119 devid = pci_get_devid(device); 120 subdevice = pci_get_subdevice(device); 121 ep = pci_ids; 122 123 while (ep->devid) { 124 if (nvme_match(devid, subdevice, ep)) 125 break; 126 ++ep; 127 } 128 if (ep->devid) 129 ctrlr->quirks = ep->quirks; 130 131 if (ep->desc) { 132 device_set_desc(device, ep->desc); 133 return (BUS_PROBE_DEFAULT); 134 } 135 136 #if defined(PCIS_STORAGE_NVM) 137 if (pci_get_class(device) == PCIC_STORAGE && 138 pci_get_subclass(device) == PCIS_STORAGE_NVM && 139 pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) { 140 device_set_desc(device, "Generic NVMe Device"); 141 return (BUS_PROBE_GENERIC); 142 } 143 #endif 144 145 return (ENXIO); 146 } 147 148 static int 149 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 150 { 151 152 ctrlr->resource_id = PCIR_BAR(0); 153 154 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 155 &ctrlr->resource_id, RF_ACTIVE); 156 157 if(ctrlr->resource == NULL) { 158 nvme_printf(ctrlr, "unable to allocate pci resource\n"); 159 return (ENOMEM); 160 } 161 162 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 163 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 164 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 165 166 /* 167 * The NVMe spec allows for the MSI-X table to be placed behind 168 * BAR 4/5, separate from the control/doorbell registers. Always 169 * try to map this bar, because it must be mapped prior to calling 170 * pci_alloc_msix(). If the table isn't behind BAR 4/5, 171 * bus_alloc_resource() will just return NULL which is OK. 172 */ 173 ctrlr->bar4_resource_id = PCIR_BAR(4); 174 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 175 &ctrlr->bar4_resource_id, RF_ACTIVE); 176 177 return (0); 178 } 179 180 static int 181 nvme_pci_attach(device_t dev) 182 { 183 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 184 int status; 185 186 ctrlr->dev = dev; 187 status = nvme_ctrlr_allocate_bar(ctrlr); 188 if (status != 0) 189 goto bad; 190 pci_enable_busmaster(dev); 191 status = nvme_ctrlr_setup_interrupts(ctrlr); 192 if (status != 0) 193 goto bad; 194 return nvme_attach(dev); 195 bad: 196 if (ctrlr->resource != NULL) { 197 bus_release_resource(dev, SYS_RES_MEMORY, 198 ctrlr->resource_id, ctrlr->resource); 199 } 200 201 if (ctrlr->bar4_resource != NULL) { 202 bus_release_resource(dev, SYS_RES_MEMORY, 203 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 204 } 205 206 if (ctrlr->tag) 207 bus_teardown_intr(dev, ctrlr->res, ctrlr->tag); 208 209 if (ctrlr->res) 210 bus_release_resource(dev, SYS_RES_IRQ, 211 rman_get_rid(ctrlr->res), ctrlr->res); 212 213 if (ctrlr->msi_count > 0) 214 pci_release_msi(dev); 215 216 return status; 217 } 218 219 static int 220 nvme_pci_detach(device_t dev) 221 { 222 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 223 int rv; 224 225 rv = nvme_detach(dev); 226 if (ctrlr->msi_count > 0) 227 pci_release_msi(dev); 228 pci_disable_busmaster(dev); 229 return (rv); 230 } 231 232 static int 233 nvme_ctrlr_setup_shared(struct nvme_controller *ctrlr, int rid) 234 { 235 int error; 236 237 ctrlr->num_io_queues = 1; 238 ctrlr->rid = rid; 239 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 240 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 241 if (ctrlr->res == NULL) { 242 nvme_printf(ctrlr, "unable to allocate shared interrupt\n"); 243 return (ENOMEM); 244 } 245 246 error = bus_setup_intr(ctrlr->dev, ctrlr->res, 247 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_shared_handler, 248 ctrlr, &ctrlr->tag); 249 if (error) { 250 nvme_printf(ctrlr, "unable to setup shared interrupt\n"); 251 return (error); 252 } 253 254 return (0); 255 } 256 257 static int 258 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) 259 { 260 device_t dev; 261 int force_intx, num_io_queues, per_cpu_io_queues; 262 int min_cpus_per_ioq; 263 int num_vectors_requested; 264 265 dev = ctrlr->dev; 266 267 force_intx = 0; 268 TUNABLE_INT_FETCH("hw.nvme.force_intx", &force_intx); 269 if (force_intx) 270 return (nvme_ctrlr_setup_shared(ctrlr, 0)); 271 272 if (pci_msix_count(dev) == 0) 273 goto msi; 274 275 /* 276 * Try to allocate one MSI-X per core for I/O queues, plus one 277 * for admin queue, but accept single shared MSI-X if have to. 278 * Fall back to MSI if can't get any MSI-X. 279 */ 280 num_io_queues = mp_ncpus; 281 TUNABLE_INT_FETCH("hw.nvme.num_io_queues", &num_io_queues); 282 if (num_io_queues < 1 || num_io_queues > mp_ncpus) 283 num_io_queues = mp_ncpus; 284 285 per_cpu_io_queues = 1; 286 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 287 if (per_cpu_io_queues == 0) 288 num_io_queues = 1; 289 290 min_cpus_per_ioq = smp_threads_per_core; 291 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); 292 if (min_cpus_per_ioq > 1) { 293 num_io_queues = min(num_io_queues, 294 max(1, mp_ncpus / min_cpus_per_ioq)); 295 } 296 297 num_io_queues = min(num_io_queues, max(1, pci_msix_count(dev) - 1)); 298 299 again: 300 if (num_io_queues > vm_ndomains) 301 num_io_queues -= num_io_queues % vm_ndomains; 302 num_vectors_requested = min(num_io_queues + 1, pci_msix_count(dev)); 303 ctrlr->msi_count = num_vectors_requested; 304 if (pci_alloc_msix(dev, &ctrlr->msi_count) != 0) { 305 nvme_printf(ctrlr, "unable to allocate MSI-X\n"); 306 ctrlr->msi_count = 0; 307 goto msi; 308 } 309 if (ctrlr->msi_count == 1) 310 return (nvme_ctrlr_setup_shared(ctrlr, 1)); 311 if (ctrlr->msi_count != num_vectors_requested) { 312 pci_release_msi(dev); 313 num_io_queues = ctrlr->msi_count - 1; 314 goto again; 315 } 316 317 ctrlr->num_io_queues = num_io_queues; 318 return (0); 319 320 msi: 321 /* 322 * Try to allocate 2 MSIs (admin and I/O queues), but accept single 323 * shared if have to. Fall back to INTx if can't get any MSI. 324 */ 325 ctrlr->msi_count = min(pci_msi_count(dev), 2); 326 if (ctrlr->msi_count > 0) { 327 if (pci_alloc_msi(dev, &ctrlr->msi_count) != 0) { 328 nvme_printf(ctrlr, "unable to allocate MSI\n"); 329 ctrlr->msi_count = 0; 330 } else if (ctrlr->msi_count == 2) { 331 ctrlr->num_io_queues = 1; 332 return (0); 333 } 334 } 335 return (nvme_ctrlr_setup_shared(ctrlr, ctrlr->msi_count > 0 ? 1 : 0)); 336 } 337 338 static int 339 nvme_pci_suspend(device_t dev) 340 { 341 struct nvme_controller *ctrlr; 342 343 ctrlr = DEVICE2SOFTC(dev); 344 return (nvme_ctrlr_suspend(ctrlr)); 345 } 346 347 static int 348 nvme_pci_resume(device_t dev) 349 { 350 struct nvme_controller *ctrlr; 351 352 ctrlr = DEVICE2SOFTC(dev); 353 return (nvme_ctrlr_resume(ctrlr)); 354 }
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