1 /*-
2 * Copyright (c) 2002-2007 Neterion, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #ifndef XGE_HAL_CONFIG_H
30 #define XGE_HAL_CONFIG_H
31
32 #include <dev/nxge/include/xge-os-pal.h>
33 #include <dev/nxge/include/xgehal-types.h>
34 #include <dev/nxge/include/xge-queue.h>
35
36 __EXTERN_BEGIN_DECLS
37
38 #define XGE_HAL_DEFAULT_USE_HARDCODE -1
39
40 #define XGE_HAL_MAX_VIRTUAL_PATHS 8
41 #define XGE_HAL_MAX_INTR_PER_VP 4
42
43
44 /**
45 * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration.
46 * @enabled: Set to 1, if TTI feature is enabled.
47 * @urange_a: Link utilization range A. The value from 0 to 100%.
48 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated
49 * each time when (and only when) the line is utilized no more
50 * than @urange_a percent in the transmit direction,
51 * and number of transmitted frames is greater or equal @ufc_a.
52 * @urange_b: Link utilization range B.
53 * @ufc_b: Frame count for the utilization range B.
54 * @urange_c: Link utilization range C.
55 * @ufc_c: Frame count for the utilization range C.
56 * @urange_d: Link utilization range D.
57 * @ufc_d: Frame count for the utilization range D.
58 * @timer_val_us: Interval of time, in microseconds, at which transmit timer
59 * interrupt is to be generated. Note that unless @timer_ci_en
60 * is set, the timer interrupt is generated only in presence
61 * of the transmit traffic. Note also that timer interrupt
62 * and utilization interrupt are two separate interrupt
63 * sources.
64 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization
65 * interrupt was generated during the interval.
66 * @timer_ci_en: Enable/disable continuous interrupt. Set this value
67 * to 1 in order to generate continuous interrupt
68 * at fixed @timer_val intervals of time, independently
69 * of whether there is transmit traffic or not.
70 * @enabled: Set to 1, if TTI feature is enabled.
71 *
72 * Xframe transmit interrupt configuration.
73 * See Xframe User Guide, Section 3.5 "Device Interrupts"
74 * for more details. Note also (min, max)
75 * ranges in the body of the xge_hal_tx_intr_config_t structure.
76 * Note: Valid (min, max) range for each attribute is specified in the body of
77 * the xge_hal_tti_config_t{} structure. Please refer to the
78 * corresponding header file.
79 */
80 typedef struct xge_hal_tti_config_t {
81
82 int enabled;
83 #define XGE_HAL_TTI_ENABLE 1
84 #define XGE_HAL_TTI_DISABLE 0
85
86 /* Line utilization interrupts */
87
88 int urange_a;
89 #define XGE_HAL_MIN_TX_URANGE_A 0
90 #define XGE_HAL_MAX_TX_URANGE_A 100
91
92 int ufc_a;
93 #define XGE_HAL_MIN_TX_UFC_A 0
94 #define XGE_HAL_MAX_TX_UFC_A 65535
95
96 int urange_b;
97 #define XGE_HAL_MIN_TX_URANGE_B 0
98 #define XGE_HAL_MAX_TX_URANGE_B 100
99
100 int ufc_b;
101 #define XGE_HAL_MIN_TX_UFC_B 0
102 #define XGE_HAL_MAX_TX_UFC_B 65535
103
104 int urange_c;
105 #define XGE_HAL_MIN_TX_URANGE_C 0
106 #define XGE_HAL_MAX_TX_URANGE_C 100
107
108 int ufc_c;
109 #define XGE_HAL_MIN_TX_UFC_C 0
110 #define XGE_HAL_MAX_TX_UFC_C 65535
111
112 int ufc_d;
113 #define XGE_HAL_MIN_TX_UFC_D 0
114 #define XGE_HAL_MAX_TX_UFC_D 65535
115
116 int timer_val_us;
117 #define XGE_HAL_MIN_TX_TIMER_VAL 0
118 #define XGE_HAL_MAX_TX_TIMER_VAL 65535
119
120 int timer_ac_en;
121 #define XGE_HAL_MIN_TX_TIMER_AC_EN 0
122 #define XGE_HAL_MAX_TX_TIMER_AC_EN 1
123
124 int timer_ci_en;
125 #define XGE_HAL_MIN_TX_TIMER_CI_EN 0
126 #define XGE_HAL_MAX_TX_TIMER_CI_EN 1
127
128
129 } xge_hal_tti_config_t;
130
131 /**
132 * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration.
133 * @urange_a: Link utilization range A. The value from 0 to 100%.
134 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated
135 * each time when (and only when) the line is utilized no more
136 * than @urange_a percent inbound,
137 * and number of received frames is greater or equal @ufc_a.
138 * @urange_b: Link utilization range B.
139 * @ufc_b: Frame count for the utilization range B.
140 * @urange_c: Link utilization range C.
141 * @ufc_c: Frame count for the utilization range C.
142 * @urange_d: Link utilization range D.
143 * @ufc_d: Frame count for the utilization range D.
144 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization
145 * interrupt was generated during the interval.
146 * @timer_val_us: Interval of time, in microseconds, at which receive timer
147 * interrupt is to be generated. The timer interrupt is generated
148 * only in presence of the inbound traffic. Note also that timer
149 * interrupt and utilization interrupt are two separate interrupt
150 * sources.
151 *
152 * Xframe receive interrupt configuration.
153 * See Xframe User Guide, Section 3.5 "Device Interrupts"
154 * for more details. Note also (min, max)
155 * ranges in the body of the xge_hal_intr_config_t structure.
156 * Note: Valid (min, max) range for each attribute is specified in the body of
157 * the xge_hal_rti_config_t{} structure. Please refer to the
158 * corresponding header file.
159 */
160 typedef struct xge_hal_rti_config_t {
161
162 int urange_a;
163 #define XGE_HAL_MIN_RX_URANGE_A 0
164 #define XGE_HAL_MAX_RX_URANGE_A 127
165
166 int ufc_a;
167 #define XGE_HAL_MIN_RX_UFC_A 0
168 #define XGE_HAL_MAX_RX_UFC_A 65535
169
170 int urange_b;
171 #define XGE_HAL_MIN_RX_URANGE_B 0
172 #define XGE_HAL_MAX_RX_URANGE_B 127
173
174 int ufc_b;
175 #define XGE_HAL_MIN_RX_UFC_B 0
176 #define XGE_HAL_MAX_RX_UFC_B 65535
177
178 int urange_c;
179 #define XGE_HAL_MIN_RX_URANGE_C 0
180 #define XGE_HAL_MAX_RX_URANGE_C 127
181
182 int ufc_c;
183 #define XGE_HAL_MIN_RX_UFC_C 0
184 #define XGE_HAL_MAX_RX_UFC_C 65535
185
186 int ufc_d;
187 #define XGE_HAL_MIN_RX_UFC_D 0
188 #define XGE_HAL_MAX_RX_UFC_D 65535
189
190 int timer_ac_en;
191 #define XGE_HAL_MIN_RX_TIMER_AC_EN 0
192 #define XGE_HAL_MAX_RX_TIMER_AC_EN 1
193
194 int timer_val_us;
195 #define XGE_HAL_MIN_RX_TIMER_VAL 0
196 #define XGE_HAL_MAX_RX_TIMER_VAL 65535
197
198 } xge_hal_rti_config_t;
199
200 /**
201 * struct xge_hal_fifo_queue_t - Single fifo configuration.
202 * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue.
203 * @initial: Initial numbers of TxDLs per queue (can grow up to @max).
204 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL.
205 * Use 0 otherwise.
206 * @intr_vector: TBD
207 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
208 * which generally improves latency of the host bridge operation
209 * (see PCI specification). For valid values please refer
210 * to xge_hal_fifo_queue_t{} in the driver sources.
211 * @priority: TBD
212 * @configured: Boolean. Use 1 to specify that the fifo is configured.
213 * Only "configured" fifos can be activated and used to post
214 * Tx descriptors. Any subset of 8 available fifos can be
215 * "configured".
216 * @tti: TBD
217 *
218 * Single fifo configuration.
219 * Note: Valid (min, max) range for each attribute is specified in the body of
220 * the xge_hal_fifo_queue_t{} structure. Please refer to the
221 * corresponding header file.
222 * See also: xge_hal_fifo_config_t{}
223 */
224 typedef struct xge_hal_fifo_queue_t {
225 int max;
226 int initial;
227 #define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2
228 #define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192
229
230 int intr;
231 #define XGE_HAL_MIN_FIFO_QUEUE_INTR 0
232 #define XGE_HAL_MAX_FIFO_QUEUE_INTR 1
233
234 int intr_vector;
235 #define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0
236 #define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64
237
238 int no_snoop_bits;
239 #define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0
240 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1
241 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2
242 #define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3
243
244 int priority;
245 #define XGE_HAL_MIN_FIFO_PRIORITY 0
246 #define XGE_HAL_MAX_FIFO_PRIORITY 63
247
248 int configured;
249 #define XGE_HAL_MIN_FIFO_CONFIGURED 0
250 #define XGE_HAL_MAX_FIFO_CONFIGURED 1
251
252 #define XGE_HAL_MAX_FIFO_TTI_NUM 7
253 #define XGE_HAL_MAX_FIFO_TTI_RING_0 56
254 xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM];
255
256 } xge_hal_fifo_queue_t;
257
258 /**
259 * struct xge_hal_fifo_config_t - Configuration of all 8 fifos.
260 * @max_frags: Max number of Tx buffers per TxDL (that is, per single
261 * transmit operation).
262 * No more than 256 transmit buffers can be specified.
263 * @max_aligned_frags: Number of fragments to be aligned out of
264 * maximum fragments (see @max_frags).
265 * @reserve_threshold: Descriptor reservation threshold.
266 * At least @reserve_threshold descriptors will remain
267 * unallocated at all times.
268 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
269 * bytes. Setting @memblock_size to page size ensures
270 * by-page allocation of descriptors. 128K bytes is the
271 * maximum supported block size.
272 * @queue: Array of per-fifo configurations.
273 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data
274 * (e.g., to align on a cache line).
275 *
276 * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t
277 * structures.
278 * Note: Valid (min, max) range for each attribute is specified in the body of
279 * the xge_hal_fifo_config_t{} structure. Please refer to the
280 * corresponding header file.
281 * See also: xge_hal_ring_queue_t{}.
282 */
283 typedef struct xge_hal_fifo_config_t {
284 int max_frags;
285 #define XGE_HAL_MIN_FIFO_FRAGS 1
286 #define XGE_HAL_MAX_FIFO_FRAGS 256
287
288 int reserve_threshold;
289 #define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0
290 #define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192
291
292 int memblock_size;
293 #define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096
294 #define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072
295
296 int alignment_size;
297 #define XGE_HAL_MIN_ALIGNMENT_SIZE 0
298 #define XGE_HAL_MAX_ALIGNMENT_SIZE 65536
299
300 int max_aligned_frags;
301 /* range: (1, @max_frags) */
302
303 #define XGE_HAL_MIN_FIFO_NUM 1
304 #define XGE_HAL_MAX_FIFO_NUM_HERC 8
305 #define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1)
306 #define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS)
307 xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM];
308 } xge_hal_fifo_config_t;
309
310 /**
311 * struct xge_hal_rts_port_t - RTS port entry
312 * @num: Port number
313 * @udp: Port is UDP (default TCP)
314 * @src: Port is Source (default Destination)
315 */
316 typedef struct xge_hal_rts_port_t {
317 int num;
318 int udp;
319 int src;
320 } xge_hal_rts_port_t;
321
322 /**
323 * struct xge_hal_ring_queue_t - Single ring configuration.
324 * @max: Max numbers of RxD blocks per queue
325 * @initial: Initial numbers of RxD blocks per queue
326 * (can grow up to @max)
327 * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer
328 * to Xframe User Guide.
329 * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring.
330 * Note that 64MB of available
331 * on-board DRAM is shared between receive rings.
332 * If a single ring is used, @dram_size_mb can be set to 64.
333 * Sum of all rings' @dram_size_mb cannot exceed 64.
334 * @intr_vector: TBD
335 * @backoff_interval_us: Time (in microseconds), after which Xframe
336 * tries to download RxDs posted by the host.
337 * Note that the "backoff" does not happen if host posts receive
338 * descriptors in the timely fashion.
339 * @max_frm_len: Maximum frame length that can be received on _that_ ring.
340 * Setting this field to -1 ensures that the ring will
341 * "accept" MTU-size frames (note that MTU can be changed at
342 * runtime).
343 * Any value other than (-1) specifies a certain "hard"
344 * limit on the receive frame sizes.
345 * The field can be used to activate receive frame-length based
346 * steering.
347 * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used
348 * to give prioritized access to PCI-X. See Xframe documentation
349 * for details.
350 * @rth_en: Enable Receive Traffic Hashing (RTH).
351 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
352 * which generally improves latency of the host bridge operation
353 * (see PCI specification). For valid values please refer
354 * to xge_hal_ring_queue_t{} in the driver sources.
355 * @indicate_max_pkts: Sets maximum number of received frames to be processed
356 * within single interrupt.
357 * @configured: Boolean. Use 1 to specify that the ring is configured.
358 * Only "configured" rings can be activated and used to post
359 * Rx descriptors. Any subset of 8 available rings can be
360 * "configured".
361 * @rts_mac_en: 1 - To enable Receive MAC address steering.
362 * 0 - To disable Receive MAC address steering.
363 * @rth_en: TBD
364 * @rts_port_en: TBD
365 * @rts_ports: TBD
366 * @rti: Xframe receive interrupt configuration.
367 *
368 * Single ring configuration.
369 * Note: Valid (min, max) range for each attribute is specified in the body of
370 * the xge_hal_ring_queue_t{} structure. Please refer to the
371 * corresponding header file.
372 * See also: xge_hal_fifo_config_t{}.
373 */
374 typedef struct xge_hal_ring_queue_t {
375 int max;
376 int initial;
377 #define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1
378 #define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64
379
380 int buffer_mode;
381 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1
382 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2
383 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3
384 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5
385
386 int dram_size_mb;
387 #define XGE_HAL_MIN_RING_QUEUE_SIZE 0
388 #define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64
389 #define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32
390
391 int intr_vector;
392 #define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0
393 #define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64
394
395 int backoff_interval_us;
396 #define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1
397 #define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000
398
399 int max_frm_len;
400 #define XGE_HAL_MIN_MAX_FRM_LEN -1
401 #define XGE_HAL_MAX_MAX_FRM_LEN 9622
402
403 int priority;
404 #define XGE_HAL_MIN_RING_PRIORITY 0
405 #define XGE_HAL_MAX_RING_PRIORITY 7
406
407 int no_snoop_bits;
408 #define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0
409 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1
410 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2
411 #define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3
412
413 int indicate_max_pkts;
414 #define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1
415 #define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536
416
417 int configured;
418 #define XGE_HAL_MIN_RING_CONFIGURED 0
419 #define XGE_HAL_MAX_RING_CONFIGURED 1
420
421 int rts_mac_en;
422 #define XGE_HAL_MIN_RING_RTS_MAC_EN 0
423 #define XGE_HAL_MAX_RING_RTS_MAC_EN 1
424
425 int rth_en;
426 #define XGE_HAL_MIN_RING_RTH_EN 0
427 #define XGE_HAL_MAX_RING_RTH_EN 1
428
429 int rts_port_en;
430 #define XGE_HAL_MIN_RING_RTS_PORT_EN 0
431 #define XGE_HAL_MAX_RING_RTS_PORT_EN 1
432
433 #define XGE_HAL_MAX_STEERABLE_PORTS 32
434 xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS];
435
436 xge_hal_rti_config_t rti;
437
438 } xge_hal_ring_queue_t;
439
440 /**
441 * struct xge_hal_ring_config_t - Array of ring configurations.
442 * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size
443 * bytes. Setting @memblock_size to page size ensures
444 * by-page allocation of descriptors. 128K bytes is the
445 * upper limit.
446 * @scatter_mode: Xframe supports two receive scatter modes: A and B.
447 * For details please refer to Xframe User Guide.
448 * @strip_vlan_tag: TBD
449 * @queue: Array of all Xframe ring configurations.
450 *
451 * Array of ring configurations.
452 * See also: xge_hal_ring_queue_t{}.
453 */
454 typedef struct xge_hal_ring_config_t {
455
456 int memblock_size;
457 #define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096
458 #define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072
459
460 int scatter_mode;
461 #define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0
462 #define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1
463
464 int strip_vlan_tag;
465 #define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0
466 #define XGE_HAL_RING_STRIP_VLAN_TAG 1
467
468 #define XGE_HAL_MIN_RING_NUM 1
469 #define XGE_HAL_MAX_RING_NUM_HERC 8
470 #define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1)
471 #define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS)
472 xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM];
473
474 } xge_hal_ring_config_t;
475
476 /**
477 * struct xge_hal_mac_config_t - MAC configuration.
478 * @media: Transponder type.
479 * @tmac_util_period: The sampling period over which the transmit utilization
480 * is calculated.
481 * @rmac_util_period: The sampling period over which the receive utilization
482 * is calculated.
483 * @rmac_strip_pad: Determines whether padding of received frames is removed by
484 * the MAC or sent to the host.
485 * @rmac_bcast_en: Enable frames containing broadcast address to be
486 * passed to the host.
487 * @rmac_pause_gen_en: Received pause generation enable.
488 * @rmac_pause_rcv_en: Receive pause enable.
489 * @rmac_pause_time: The value to be inserted in outgoing pause frames.
490 * Has units of pause quanta (one pause quanta = 512 bit times).
491 * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation
492 * for queues 0 through 3. The threshold value indicates portion of the
493 * individual receive buffer queue size. Thresholds have a range of 0 to
494 * 255, allowing 256 possible watermarks in a queue.
495 * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation
496 * for queues 4 through 7. The threshold value indicates portion of the
497 * individual receive buffer queue size. Thresholds have a range of 0 to
498 * 255, allowing 256 possible watermarks in a queue.
499 *
500 * MAC configuration. This includes various aspects of configuration, including:
501 * - Pause frame threshold;
502 * - sampling rate to calculate link utilization;
503 * - enabling/disabling broadcasts.
504 *
505 * See Xframe User Guide for more details.
506 * Note: Valid (min, max) range for each attribute is specified in the body of
507 * the xge_hal_mac_config_t{} structure. Please refer to the
508 * corresponding include file.
509 */
510 typedef struct xge_hal_mac_config_t {
511 int media;
512 #define XGE_HAL_MIN_MEDIA 0
513 #define XGE_HAL_MEDIA_SR 0
514 #define XGE_HAL_MEDIA_SW 1
515 #define XGE_HAL_MEDIA_LR 2
516 #define XGE_HAL_MEDIA_LW 3
517 #define XGE_HAL_MEDIA_ER 4
518 #define XGE_HAL_MEDIA_EW 5
519 #define XGE_HAL_MAX_MEDIA 5
520
521 int tmac_util_period;
522 #define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0
523 #define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15
524
525 int rmac_util_period;
526 #define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0
527 #define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15
528
529 int rmac_bcast_en;
530 #define XGE_HAL_MIN_RMAC_BCAST_EN 0
531 #define XGE_HAL_MAX_RMAC_BCAST_EN 1
532
533 int rmac_pause_gen_en;
534 #define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0
535 #define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1
536
537 int rmac_pause_rcv_en;
538 #define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0
539 #define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1
540
541 int rmac_pause_time;
542 #define XGE_HAL_MIN_RMAC_HIGH_PTIME 16
543 #define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535
544
545 int mc_pause_threshold_q0q3;
546 #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0
547 #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254
548
549 int mc_pause_threshold_q4q7;
550 #define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0
551 #define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254
552
553 } xge_hal_mac_config_t;
554
555 /**
556 * struct xge_hal_device_config_t - Device configuration.
557 * @mtu: Current mtu size.
558 * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx
559 * completions. Used in xge_hal_device_handle_irq().
560 * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance
561 * with the PCI Specification, the value of the Latency Timer
562 * for this PCI bus master.
563 * Specify either zero or -1 to use BIOS default.
564 * @napi_weight: (TODO)
565 * @max_splits_trans: Maximum number of PCI-X split transactions.
566 * Specify (-1) to use BIOS default.
567 * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default
568 * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B;
569 * 1 - 1KB, 2 - 2KB, and 3 - 4KB.
570 * @shared_splits: The number of Outstanding Split Transactions that is
571 * shared by Tx and Rx requests. The device stops issuing Tx
572 * requests once the number of Outstanding Split Transactions is
573 * equal to the value of Shared_Splits.
574 * A value of zero indicates that the Tx and Rx share all allocated
575 * Split Requests, i.e. the device can issue both types (Tx and Rx)
576 * of read requests until the number of Maximum Outstanding Split
577 * Transactions is reached.
578 * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer
579 * to the host. This includes MAC stats as well as PCI stats.
580 * See xge_hal_stats_hw_info_t{}.
581 * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz.
582 * @intr_mode: Line, MSI, or MSI-X interrupt.
583 * @sched_timer_us: If greater than zero, specifies time interval
584 * (in microseconds) for the device to generate
585 * interrupt. Note that unlike tti and rti interrupts,
586 * the scheduled interrupt is generated independently of
587 * whether there is transmit or receive traffic, respectively.
588 * @sched_timer_one_shot: 1 - generate scheduled interrupt only once.
589 * 0 - generate scheduled interrupt periodically at the specified
590 * @sched_timer_us interval.
591 *
592 * @ring: See xge_hal_ring_config_t{}.
593 * @mac: See xge_hal_mac_config_t{}.
594 * @tti: See xge_hal_tti_config_t{}.
595 * @fifo: See xge_hal_fifo_config_t{}.
596 *
597 * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#.
598 * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on
599 * ECC error.
600 * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on
601 * parity error.
602 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table).
603 * @rth_bucket_size: RTH bucket width (in bits). For valid range please see
604 * xge_hal_device_config_t{} in the driver sources.
605 * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair
606 * Direct Match).
607 * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of
608 * hash value in the RTH SPDM based steering.
609 * @rxufca_intr_thres: (TODO)
610 * @rxufca_lo_lim: (TODO)
611 * @rxufca_hi_lim: (TODO)
612 * @rxufca_lbolt_period: (TODO)
613 * @link_valid_cnt: link-valid counting is done only at device-open time,
614 * to determine with the specified certainty that the link is up. See also
615 * @link_retry_cnt.
616 * @link_retry_cnt: Max number of polls for link-up. Done only at device
617 * open time. Reducing this value as well as the previous @link_valid_cnt,
618 * speeds up device startup, which may be important if the driver
619 * is compiled into OS.
620 * @link_stability_period: Specify the period for which the link must be
621 * stable in order for the adapter to declare "LINK UP".
622 * The enumerated settings (see Xframe-II UG) are:
623 * 0 ........... instantaneous
624 * 1 ........... 500 ³s
625 * 2 ........... 1 ms
626 * 3 ........... 64 ms
627 * 4 ........... 256 ms
628 * 5 ........... 512 ms
629 * 6 ........... 1 s
630 * 7 ........... 2 s
631 * @device_poll_millis: Specify the interval (in mulliseconds) between
632 * successive xge_hal_device_poll() runs.
633 * stable in order for the adapter to declare "LINK UP".
634 * @no_isr_events: TBD
635 * @lro_sg_size: TBD
636 * @lro_frm_len: TBD
637 * @bimodal_interrupts: Enable bimodal interrupts in device
638 * @bimodal_timer_lo_us: TBD
639 * @bimodal_timer_hi_us: TBD
640 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address
641 * @rts_qos_en: TBD
642 * @rts_port_en: TBD
643 * @vp_config: Configuration for virtual paths
644 * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ
645 * can own at any one time.
646 * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that
647 * this S-RQ can own at any one time.
648 * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for
649 * WQEs before generating a message or interrupt.
650 * @refill_threshold_high:This field provides a hysteresis upper bound for
651 * automatic adapter refill operations.
652 * @refill_threshold_low:This field provides a hysteresis lower bound for
653 * automatic adapter refill operations.
654 * @eol_policy:This field sets the policy for handling the end of list condition.
655 * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0.
656 * 2'b01 - Send UMQ message when EOL is reached.
657 * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message
658 * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for
659 * a non-zero block wrapper before giving up and sending a UMQ message
660 * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held
661 * by a session at any one time.
662 * @poll_or_doorbell: TBD
663 *
664 * Xframe configuration.
665 * Contains per-device configuration parameters, including:
666 * - latency timer (settable via PCI configuration space);
667 * - maximum number of split transactions;
668 * - maximum number of shared splits;
669 * - stats sampling interval, etc.
670 *
671 * In addition, xge_hal_device_config_t{} includes "subordinate"
672 * configurations, including:
673 * - fifos and rings;
674 * - MAC (see xge_hal_mac_config_t{}).
675 *
676 * See Xframe User Guide for more details.
677 * Note: Valid (min, max) range for each attribute is specified in the body of
678 * the xge_hal_device_config_t{} structure. Please refer to the
679 * corresponding include file.
680 * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{},
681 * xge_hal_mac_config_t{}.
682 */
683 typedef struct xge_hal_device_config_t {
684 int mtu;
685 #define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU
686 #define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU
687
688 int isr_polling_cnt;
689 #define XGE_HAL_MIN_ISR_POLLING_CNT 0
690 #define XGE_HAL_MAX_ISR_POLLING_CNT 65536
691
692 int latency_timer;
693 #define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1
694 #define XGE_HAL_MIN_LATENCY_TIMER 8
695 #define XGE_HAL_MAX_LATENCY_TIMER 255
696
697 int napi_weight;
698 #define XGE_HAL_DEF_NAPI_WEIGHT 64
699
700 int max_splits_trans;
701 #define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1
702 #define XGE_HAL_ONE_SPLIT_TRANSACTION 0
703 #define XGE_HAL_TWO_SPLIT_TRANSACTION 1
704 #define XGE_HAL_THREE_SPLIT_TRANSACTION 2
705 #define XGE_HAL_FOUR_SPLIT_TRANSACTION 3
706 #define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4
707 #define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5
708 #define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6
709 #define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7
710
711 int mmrb_count;
712 #define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1
713 #define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */
714 #define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */
715
716 int shared_splits;
717 #define XGE_HAL_MIN_SHARED_SPLITS 0
718 #define XGE_HAL_MAX_SHARED_SPLITS 31
719
720 int stats_refresh_time_sec;
721 #define XGE_HAL_STATS_REFRESH_DISABLE 0
722 #define XGE_HAL_MIN_STATS_REFRESH_TIME 1
723 #define XGE_HAL_MAX_STATS_REFRESH_TIME 300
724
725 int pci_freq_mherz;
726 #define XGE_HAL_PCI_FREQ_MHERZ_33 33
727 #define XGE_HAL_PCI_FREQ_MHERZ_66 66
728 #define XGE_HAL_PCI_FREQ_MHERZ_100 100
729 #define XGE_HAL_PCI_FREQ_MHERZ_133 133
730 #define XGE_HAL_PCI_FREQ_MHERZ_266 266
731
732 int intr_mode;
733 #define XGE_HAL_INTR_MODE_IRQLINE 0
734 #define XGE_HAL_INTR_MODE_MSI 1
735 #define XGE_HAL_INTR_MODE_MSIX 2
736
737 int sched_timer_us;
738 #define XGE_HAL_SCHED_TIMER_DISABLED 0
739 #define XGE_HAL_SCHED_TIMER_MIN 0
740 #define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF
741
742 int sched_timer_one_shot;
743 #define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0
744 #define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1
745
746 xge_hal_ring_config_t ring;
747 xge_hal_mac_config_t mac;
748 xge_hal_fifo_config_t fifo;
749
750 int dump_on_serr;
751 #define XGE_HAL_DUMP_ON_SERR_DISABLE 0
752 #define XGE_HAL_DUMP_ON_SERR_ENABLE 1
753
754 int dump_on_eccerr;
755 #define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0
756 #define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1
757
758 int dump_on_parityerr;
759 #define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0
760 #define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1
761
762 int rth_en;
763 #define XGE_HAL_RTH_DISABLE 0
764 #define XGE_HAL_RTH_ENABLE 1
765
766 int rth_bucket_size;
767 #define XGE_HAL_MIN_RTH_BUCKET_SIZE 1
768 #define XGE_HAL_MAX_RTH_BUCKET_SIZE 8
769
770 int rth_spdm_en;
771 #define XGE_HAL_RTH_SPDM_DISABLE 0
772 #define XGE_HAL_RTH_SPDM_ENABLE 1
773
774 int rth_spdm_use_l4;
775 #define XGE_HAL_RTH_SPDM_USE_L4 1
776
777 int rxufca_intr_thres;
778 #define XGE_HAL_RXUFCA_INTR_THRES_MIN 1
779 #define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096
780
781 int rxufca_lo_lim;
782 #define XGE_HAL_RXUFCA_LO_LIM_MIN 1
783 #define XGE_HAL_RXUFCA_LO_LIM_MAX 16
784
785 int rxufca_hi_lim;
786 #define XGE_HAL_RXUFCA_HI_LIM_MIN 1
787 #define XGE_HAL_RXUFCA_HI_LIM_MAX 256
788
789 int rxufca_lbolt_period;
790 #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1
791 #define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024
792
793 int link_valid_cnt;
794 #define XGE_HAL_LINK_VALID_CNT_MIN 0
795 #define XGE_HAL_LINK_VALID_CNT_MAX 127
796
797 int link_retry_cnt;
798 #define XGE_HAL_LINK_RETRY_CNT_MIN 0
799 #define XGE_HAL_LINK_RETRY_CNT_MAX 127
800
801 int link_stability_period;
802 #define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */
803 #define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */
804 #define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */
805
806 int device_poll_millis;
807 #define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000
808 #define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1
809 #define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000
810
811 int no_isr_events;
812 #define XGE_HAL_NO_ISR_EVENTS_MIN 0
813 #define XGE_HAL_NO_ISR_EVENTS_MAX 1
814
815 int lro_sg_size;
816 #define XGE_HAL_LRO_DEFAULT_SG_SIZE 10
817 #define XGE_HAL_LRO_MIN_SG_SIZE 1
818 #define XGE_HAL_LRO_MAX_SG_SIZE 64
819
820 int lro_frm_len;
821 #define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536
822 #define XGE_HAL_LRO_MIN_FRM_LEN 4096
823 #define XGE_HAL_LRO_MAX_FRM_LEN 65536
824
825 int bimodal_interrupts;
826 #define XGE_HAL_BIMODAL_INTR_MIN -1
827 #define XGE_HAL_BIMODAL_INTR_MAX 1
828
829 int bimodal_timer_lo_us;
830 #define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1
831 #define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127
832
833 int bimodal_timer_hi_us;
834 #define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128
835 #define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535
836
837 int rts_mac_en;
838 #define XGE_HAL_RTS_MAC_DISABLE 0
839 #define XGE_HAL_RTS_MAC_ENABLE 1
840
841 int rts_qos_en;
842 #define XGE_HAL_RTS_QOS_DISABLE 0
843 #define XGE_HAL_RTS_QOS_ENABLE 1
844
845 int rts_port_en;
846 #define XGE_HAL_RTS_PORT_DISABLE 0
847 #define XGE_HAL_RTS_PORT_ENABLE 1
848
849 } xge_hal_device_config_t;
850
851 /**
852 * struct xge_hal_driver_config_t - HAL (layer) configuration.
853 * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to
854 * periodically poll HAL, i.e, invoke
855 * xge_hal_device_poll().
856 * Note that HAL does not maintain its own
857 * polling context. HAL relies on ULD to
858 * provide one.
859 * @queue_size_initial: Initial size of the HAL protected event queue.
860 * The queue is shared by HAL and upper-layer drivers.
861 * The queue is used to exchange and process slow-path
862 * events. See xge_hal_event_e.
863 * @queue_size_max: Maximum size of the HAL queue. Depending on the load,
864 * the queue may grow at run-time up to @queue_max_size.
865 * @tracebuf_size: Size of the trace buffer. Set it to '' to disable.
866 * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple)
867 * HAL devices.)
868 * Currently this structure contains just a few basic values.
869 * Note: Valid (min, max) range for each attribute is specified in the body of
870 * the structure. Please refer to the corresponding header file.
871 * See also: xge_hal_device_poll()
872 */
873 typedef struct xge_hal_driver_config_t {
874 int queue_size_initial;
875 #define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1
876 #define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16
877
878 int queue_size_max;
879 #define XGE_HAL_MIN_QUEUE_SIZE_MAX 1
880 #define XGE_HAL_MAX_QUEUE_SIZE_MAX 16
881
882 #ifdef XGE_TRACE_INTO_CIRCULAR_ARR
883 int tracebuf_size;
884 #define XGE_HAL_MIN_CIRCULAR_ARR 4096
885 #define XGE_HAL_MAX_CIRCULAR_ARR 1048576
886 #define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE
887
888 int tracebuf_timestamp_en;
889 #define XGE_HAL_MIN_TIMESTAMP_EN 0
890 #define XGE_HAL_MAX_TIMESTAMP_EN 1
891 #endif
892
893 } xge_hal_driver_config_t;
894
895
896 /* ========================== PRIVATE API ================================= */
897
898 xge_hal_status_e
899 __hal_device_config_check_common (xge_hal_device_config_t *new_config);
900
901 xge_hal_status_e
902 __hal_device_config_check_xena (xge_hal_device_config_t *new_config);
903
904 xge_hal_status_e
905 __hal_device_config_check_herc (xge_hal_device_config_t *new_config);
906
907 xge_hal_status_e
908 __hal_driver_config_check (xge_hal_driver_config_t *new_config);
909
910 __EXTERN_END_DECLS
911
912 #endif /* XGE_HAL_CONFIG_H */
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