1 /*-
2 * Copyright (c) 2002-2007 Neterion, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/nxge/include/xgehal-regs.h,v 1.2 2007/10/29 14:19:31 rwatson Exp $
27 */
28
29 #ifndef XGE_HAL_REGS_H
30 #define XGE_HAL_REGS_H
31
32 __EXTERN_BEGIN_DECLS
33
34 typedef struct {
35
36 /* General Control-Status Registers */
37 u64 general_int_status;
38 #define XGE_HAL_GEN_INTR_TXPIC BIT(0)
39 #define XGE_HAL_GEN_INTR_TXDMA BIT(1)
40 #define XGE_HAL_GEN_INTR_TXMAC BIT(2)
41 #define XGE_HAL_GEN_INTR_TXXGXS BIT(3)
42 #define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8)
43 #define XGE_HAL_GEN_INTR_RXPIC BIT(32)
44 #define XGE_HAL_GEN_INTR_RXDMA BIT(33)
45 #define XGE_HAL_GEN_INTR_RXMAC BIT(34)
46 #define XGE_HAL_GEN_INTR_MC BIT(35)
47 #define XGE_HAL_GEN_INTR_RXXGXS BIT(36)
48 #define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40)
49 #define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \
50 XGE_HAL_GEN_INTR_RXPIC | \
51 XGE_HAL_GEN_INTR_TXDMA | \
52 XGE_HAL_GEN_INTR_RXDMA | \
53 XGE_HAL_GEN_INTR_TXMAC | \
54 XGE_HAL_GEN_INTR_RXMAC | \
55 XGE_HAL_GEN_INTR_TXXGXS | \
56 XGE_HAL_GEN_INTR_RXXGXS | \
57 XGE_HAL_GEN_INTR_MC)
58
59 u64 general_int_mask;
60
61 u8 unused0[0x100 - 0x10];
62
63 u64 sw_reset;
64
65 /* XGXS must be removed from reset only once. */
66 #define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8)
67 #define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8)
68 #define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8)
69 #define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8)
70 #define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \
71 XGE_HAL_SW_RESET_FLASH | \
72 XGE_HAL_SW_RESET_EOI | \
73 XGE_HAL_SW_RESET_XGXS)
74
75 /* The SW_RESET register must read this value after a successful reset. */
76 #if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
77 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL
78 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL
79 #else
80 #define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL
81 #define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL
82 #endif
83
84
85 u64 adapter_status;
86 #define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0)
87 #define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1)
88 #define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2)
89 #define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
90 #define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
91 #define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
92 #define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
93 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
94 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8)
95 #define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8)
96
97 #define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
98 #define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24)
99 #define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
100 #define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30)
101 #define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31)
102
103 u64 adapter_control;
104 #define XGE_HAL_ADAPTER_CNTL_EN BIT(7)
105 #define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15)
106 #define XGE_HAL_ADAPTER_LED_ON BIT(23)
107 #define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4)
108 #define XGE_HAL_ADAPTER_WAIT_INT BIT(48)
109 #define XGE_HAL_ADAPTER_ECC_EN BIT(55)
110
111 u64 serr_source;
112 #define XGE_HAL_SERR_SOURCE_PIC BIT(0)
113 #define XGE_HAL_SERR_SOURCE_TXDMA BIT(1)
114 #define XGE_HAL_SERR_SOURCE_RXDMA BIT(2)
115 #define XGE_HAL_SERR_SOURCE_MAC BIT(3)
116 #define XGE_HAL_SERR_SOURCE_MC BIT(4)
117 #define XGE_HAL_SERR_SOURCE_XGXS BIT(5)
118 #define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \
119 XGE_HAL_SERR_SOURCE_TXDMA | \
120 XGE_HAL_SERR_SOURCE_RXDMA | \
121 XGE_HAL_SERR_SOURCE_MAC | \
122 XGE_HAL_SERR_SOURCE_MC | \
123 XGE_HAL_SERR_SOURCE_XGXS)
124
125 u64 pci_info;
126 #define XGE_HAL_PCI_INFO vBIT(0xF,0,4)
127 #define XGE_HAL_PCI_32_BIT BIT(8)
128
129 u8 unused0_1[0x160 - 0x128];
130
131 u64 ric_status;
132
133 u8 unused0_2[0x558 - 0x168];
134
135 u64 mbist_status;
136
137 u8 unused0_3[0x800 - 0x560];
138
139 /* PCI-X Controller registers */
140 u64 pic_int_status;
141 u64 pic_int_mask;
142 #define XGE_HAL_PIC_INT_TX BIT(0)
143 #define XGE_HAL_PIC_INT_FLSH BIT(1)
144 #define XGE_HAL_PIC_INT_MDIO BIT(2)
145 #define XGE_HAL_PIC_INT_IIC BIT(3)
146 #define XGE_HAL_PIC_INT_MISC BIT(4)
147 #define XGE_HAL_PIC_INT_RX BIT(32)
148
149 u64 txpic_int_reg;
150 #define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42)
151 u64 txpic_int_mask;
152 #define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0)
153 #define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1)
154 #define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
155 #define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
156 #define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
157 #define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
158 #define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13)
159 #define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14)
160 #define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
161 #define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
162 #define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
163 #define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
164 #define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
165 /*
166 #define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
167 #define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
168 #define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
169 */
170 u64 txpic_alarms;
171 u64 rxpic_int_reg;
172 #define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0)
173 #define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44)
174 #define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55)
175 u64 rxpic_int_mask;
176 u64 rxpic_alarms;
177
178 u64 flsh_int_reg;
179 u64 flsh_int_mask;
180 #define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
181 #define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62)
182 u64 flash_alarms;
183
184 u64 mdio_int_reg;
185 u64 mdio_int_mask;
186 #define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
187 #define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8)
188 #define XGE_HAL_MDIO_INT_REG_LASI BIT(39)
189 u64 mdio_alarms;
190
191 u64 iic_int_reg;
192 u64 iic_int_mask;
193 #define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4)
194 #define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5)
195 #define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
196 #define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7)
197 #define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8)
198 u64 iic_alarms;
199
200 u64 msi_pending_reg;
201
202 u64 misc_int_reg;
203 #define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0)
204 #define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1)
205 #define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2)
206 u64 misc_int_mask;
207 u64 misc_alarms;
208
209 u64 msi_triggered_reg;
210
211 u64 xfp_gpio_int_reg;
212 u64 xfp_gpio_int_mask;
213 u64 xfp_alarms;
214
215 u8 unused5[0x8E0 - 0x8C8];
216
217 u64 tx_traffic_int;
218 #define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n)
219 u64 tx_traffic_mask;
220
221 u64 rx_traffic_int;
222 #define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n)
223 u64 rx_traffic_mask;
224
225 /* PIC Control registers */
226 u64 pic_control;
227 #define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
228 #define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1)
229 #define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4)
230
231 u64 swapper_ctrl;
232 #define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0)
233 #define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1)
234 #define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8)
235 #define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9)
236 #define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10)
237 #define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11)
238 #define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16)
239 #define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17)
240 #define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18)
241 #define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19)
242 #define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20)
243 #define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21)
244 #define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22)
245 #define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23)
246 #define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32)
247 #define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33)
248 #define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34)
249 #define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35)
250 #define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36)
251 #define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37)
252 #define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40)
253 #define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41)
254 #define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48)
255 #define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49)
256
257 u64 pif_rd_swapper_fb;
258 #define XGE_HAL_IF_RD_SWAPPER_FB 0x0123456789ABCDEFULL
259
260 u64 scheduled_int_ctrl;
261 #define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0)
262 #define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1)
263 #define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
264 #define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32)
265 #define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL
266
267
268 u64 txreqtimeout;
269 #define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32)
270 #define XGE_HAL_TXREQTO_EN BIT(63)
271
272 u64 statsreqtimeout;
273 #define XGE_HAL_STATREQTO_VAL(n) TBD
274 #define XGE_HAL_STATREQTO_EN BIT(63)
275
276 u64 read_retry_delay;
277 u64 read_retry_acceleration;
278 u64 write_retry_delay;
279 u64 write_retry_acceleration;
280
281 u64 xmsi_control;
282 #define XGE_HAL_XMSI_EN BIT(0)
283 #define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1)
284 #define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3)
285
286 u64 xmsi_access;
287 #define XGE_HAL_XMSI_WR_RDN BIT(7)
288 #define XGE_HAL_XMSI_STROBE BIT(15)
289 #define XGE_HAL_XMSI_NO(val) vBIT(val,26,6)
290
291 u64 xmsi_address;
292 u64 xmsi_data;
293
294 u64 rx_mat;
295 #define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8)
296
297 u8 unused6[0x8];
298
299 u64 tx_mat[8];
300 #define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8)
301
302 u64 xmsi_mask_reg;
303
304 /* Automated statistics collection */
305 u64 stat_byte_cnt;
306 u64 stat_cfg;
307 #define XGE_HAL_STAT_CFG_STAT_EN BIT(0)
308 #define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1)
309 #define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8)
310 #define XGE_HAL_STAT_CFG_STAT_RO BIT(9)
311 #define XGE_HAL_XENA_PER_SEC 0x208d5
312 #define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32)
313
314 u64 stat_addr;
315
316 /* General Configuration */
317 u64 mdio_control;
318 #define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16)
319 #define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5)
320 #define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5)
321 #define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16)
322 #define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4)
323 #define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2)
324 #define XGE_HAL_MDIO_CONTROL_MMD_DATA_GET(n) ((n>>16)&0xFFFF)
325 #define XGE_HAL_MDIO_MMD_PMA_DEV_ADDR 0x01
326 #define XGE_HAL_MDIO_DOM_REG_ADDR 0xA100
327 #define XGE_HAL_MDIO_ALARM_FLAGS_ADDR 0xA070
328 #define XGE_HAL_MDIO_WARN_FLAGS_ADDR 0xA074
329 #define XGE_HAL_MDIO_CTRL_START 0xE
330 #define XGE_HAL_MDIO_OP_ADDRESS 0x0
331 #define XGE_HAL_MDIO_OP_WRITE 0x1
332 #define XGE_HAL_MDIO_OP_READ 0x3
333 #define XGE_HAL_MDIO_OP_READ_POST_INCREMENT 0x2
334 #define XGE_HAL_MDIO_ALARM_TEMPHIGH 0x0080
335 #define XGE_HAL_MDIO_ALARM_TEMPLOW 0x0040
336 #define XGE_HAL_MDIO_ALARM_BIASHIGH 0x0008
337 #define XGE_HAL_MDIO_ALARM_BIASLOW 0x0004
338 #define XGE_HAL_MDIO_ALARM_POUTPUTHIGH 0x0002
339 #define XGE_HAL_MDIO_ALARM_POUTPUTLOW 0x0001
340 #define XGE_HAL_MDIO_WARN_TEMPHIGH 0x0080
341 #define XGE_HAL_MDIO_WARN_TEMPLOW 0x0040
342 #define XGE_HAL_MDIO_WARN_BIASHIGH 0x0008
343 #define XGE_HAL_MDIO_WARN_BIASLOW 0x0004
344 #define XGE_HAL_MDIO_WARN_POUTPUTHIGH 0x0002
345 #define XGE_HAL_MDIO_WARN_POUTPUTLOW 0x0001
346
347 u64 dtx_control;
348
349 u64 i2c_control;
350 #define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
351 #define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
352 #define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
353 #define XGE_HAL_I2C_CONTROL_READ BIT(24)
354 #define XGE_HAL_I2C_CONTROL_NACK BIT(25)
355 #define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
356 #define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
357 #define XGE_HAL_I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
358 #define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
359
360 u64 beacon_control;
361 u64 misc_control;
362 #define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3)
363 #define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1)
364 #define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0)
365
366 u64 xfb_control;
367 u64 gpio_control;
368 #define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8)
369
370 u64 txfifo_dw_mask;
371 u64 split_table_line_no;
372 u64 sc_timeout;
373 u64 pic_control_2;
374 #define XGE_HAL_TXD_WRITE_BC(n) vBIT(n, 13, 3)
375 u64 ini_dperr_ctrl;
376 u64 wreq_split_mask;
377 u64 qw_per_rxd;
378 u8 unused7[0x300 - 0x250];
379
380 u64 pic_status;
381 u64 txp_status;
382 u64 txp_err_context;
383 u64 spdm_bir_offset;
384 #define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \
385 (u8)(spdm_bir_offset >> 61)
386 #define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \
387 (u32)((spdm_bir_offset >> 32) & 0x1FFFFFFF)
388 u64 spdm_overwrite;
389 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \
390 (u8)((spdm_overwrite >> 48) & 0xff)
391 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \
392 (u8)((spdm_overwrite >> 40) & 0x3)
393 #define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \
394 (u8)((spdm_overwrite >> 32) & 0x7)
395 u64 cfg_addr_on_dperr;
396 u64 pif_addr_on_dperr;
397 u64 tags_in_use;
398 u64 rd_req_types;
399 u64 split_table_line;
400 u64 unxp_split_add_ph;
401 u64 unexp_split_attr_ph;
402 u64 split_message;
403 u64 spdm_structure;
404 #define XGE_HAL_SPDM_MAX_ENTRIES(spdm_structure) (u16)(spdm_structure >> 48)
405 #define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \
406 (u8)((spdm_structure >> 40) & 0xff)
407 #define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \
408 (u8)((spdm_structure >> 32) & 0xff)
409
410 u64 txdw_ptr_cnt_0;
411 u64 txdw_ptr_cnt_1;
412 u64 txdw_ptr_cnt_2;
413 u64 txdw_ptr_cnt_3;
414 u64 txdw_ptr_cnt_4;
415 u64 txdw_ptr_cnt_5;
416 u64 txdw_ptr_cnt_6;
417 u64 txdw_ptr_cnt_7;
418 u64 rxdw_cnt_ring_0;
419 u64 rxdw_cnt_ring_1;
420 u64 rxdw_cnt_ring_2;
421 u64 rxdw_cnt_ring_3;
422 u64 rxdw_cnt_ring_4;
423 u64 rxdw_cnt_ring_5;
424 u64 rxdw_cnt_ring_6;
425 u64 rxdw_cnt_ring_7;
426
427 u8 unused8[0x410];
428
429 /* TxDMA registers */
430 u64 txdma_int_status;
431 u64 txdma_int_mask;
432 #define XGE_HAL_TXDMA_PFC_INT BIT(0)
433 #define XGE_HAL_TXDMA_TDA_INT BIT(1)
434 #define XGE_HAL_TXDMA_PCC_INT BIT(2)
435 #define XGE_HAL_TXDMA_TTI_INT BIT(3)
436 #define XGE_HAL_TXDMA_LSO_INT BIT(4)
437 #define XGE_HAL_TXDMA_TPA_INT BIT(5)
438 #define XGE_HAL_TXDMA_SM_INT BIT(6)
439 u64 pfc_err_reg;
440 #define XGE_HAL_PFC_ECC_SG_ERR BIT(7)
441 #define XGE_HAL_PFC_ECC_DB_ERR BIT(15)
442 #define XGE_HAL_PFC_SM_ERR_ALARM BIT(23)
443 #define XGE_HAL_PFC_MISC_0_ERR BIT(31)
444 #define XGE_HAL_PFC_MISC_1_ERR BIT(32)
445 #define XGE_HAL_PFC_PCIX_ERR BIT(39)
446 u64 pfc_err_mask;
447 u64 pfc_err_alarm;
448
449 u64 tda_err_reg;
450 #define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
451 #define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
452 #define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22)
453 #define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23)
454 #define XGE_HAL_TDA_PCIX_ERR BIT(39)
455 u64 tda_err_mask;
456 u64 tda_err_alarm;
457
458 u64 pcc_err_reg;
459 #define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
460 #define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
461 #define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
462 #define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
463 #define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8)
464 #define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8)
465 #define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8)
466 #define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8)
467 #define XGE_HAL_PCC_6_COF_OV_ERR BIT(56)
468 #define XGE_HAL_PCC_7_COF_OV_ERR BIT(57)
469 #define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58)
470 #define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59)
471 u64 pcc_err_mask;
472 u64 pcc_err_alarm;
473
474 u64 tti_err_reg;
475 #define XGE_HAL_TTI_ECC_SG_ERR BIT(7)
476 #define XGE_HAL_TTI_ECC_DB_ERR BIT(15)
477 #define XGE_HAL_TTI_SM_ERR_ALARM BIT(23)
478 u64 tti_err_mask;
479 u64 tti_err_alarm;
480
481 u64 lso_err_reg;
482 #define XGE_HAL_LSO6_SEND_OFLOW BIT(12)
483 #define XGE_HAL_LSO7_SEND_OFLOW BIT(13)
484 #define XGE_HAL_LSO6_ABORT BIT(14)
485 #define XGE_HAL_LSO7_ABORT BIT(15)
486 #define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22)
487 #define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23)
488 u64 lso_err_mask;
489 u64 lso_err_alarm;
490
491 u64 tpa_err_reg;
492 #define XGE_HAL_TPA_TX_FRM_DROP BIT(7)
493 #define XGE_HAL_TPA_SM_ERR_ALARM BIT(23)
494 u64 tpa_err_mask;
495 u64 tpa_err_alarm;
496
497 u64 sm_err_reg;
498 #define XGE_HAL_SM_SM_ERR_ALARM BIT(15)
499 u64 sm_err_mask;
500 u64 sm_err_alarm;
501
502 u8 unused9[0x100 - 0xB8];
503
504 /* TxDMA arbiter */
505 u64 tx_dma_wrap_stat;
506
507 /* Tx FIFO controller */
508 #define XGE_HAL_X_MAX_FIFOS 8
509 #define XGE_HAL_X_FIFO_MAX_LEN 0x1FFF /*8191 */
510 u64 tx_fifo_partition_0;
511 #define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0)
512 #define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
513 #define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
514 #define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
515 #define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
516
517 u64 tx_fifo_partition_1;
518 #define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
519 #define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
520 #define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
521 #define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
522
523 u64 tx_fifo_partition_2;
524 #define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
525 #define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
526 #define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
527 #define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
528
529 u64 tx_fifo_partition_3;
530 #define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
531 #define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
532 #define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
533 #define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
534
535 #define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */
536 #define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1
537 #define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2
538 #define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3
539 #define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4
540 #define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5
541 #define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6
542 #define XGE_HAL_TX_FIFO_PARTITION_PRI_7 7 /* lowest */
543
544 u64 tx_w_round_robin_0;
545 u64 tx_w_round_robin_1;
546 u64 tx_w_round_robin_2;
547 u64 tx_w_round_robin_3;
548 u64 tx_w_round_robin_4;
549
550 u64 tti_command_mem;
551 #define XGE_HAL_TTI_CMD_MEM_WE BIT(7)
552 #define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
553 #define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
554 #define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
555
556 u64 tti_data1_mem;
557 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
558 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
559 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
560 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
561 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
562 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
563 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
564
565 u64 tti_data2_mem;
566 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
567 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
568 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
569 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
570
571 /* Tx Protocol assist */
572 u64 tx_pa_cfg;
573 #define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
574 #define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
575 #define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
576 #define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6)
577
578 /* Recent add, used only debug purposes. */
579 u64 pcc_enable;
580
581 u64 pfc_monitor_0;
582 u64 pfc_monitor_1;
583 u64 pfc_monitor_2;
584 u64 pfc_monitor_3;
585 u64 txd_ownership_ctrl;
586 u64 pfc_read_cntrl;
587 u64 pfc_read_data;
588
589 u8 unused10[0x1700 - 0x11B0];
590
591 u64 txdma_debug_ctrl;
592
593 u8 unused11[0x1800 - 0x1708];
594
595 /* RxDMA Registers */
596 u64 rxdma_int_status;
597 #define XGE_HAL_RXDMA_RC_INT BIT(0)
598 #define XGE_HAL_RXDMA_RPA_INT BIT(1)
599 #define XGE_HAL_RXDMA_RDA_INT BIT(2)
600 #define XGE_HAL_RXDMA_RTI_INT BIT(3)
601
602 u64 rxdma_int_mask;
603 #define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0)
604 #define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1)
605 #define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2)
606 #define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3)
607
608 u64 rda_err_reg;
609 #define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
610 #define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
611 #define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23)
612 #define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31)
613 #define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38)
614 #define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39)
615 #define XGE_HAL_RDA_MISC_ERR BIT(47)
616 #define XGE_HAL_RDA_PCIX_ERR BIT(55)
617 #define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63)
618 u64 rda_err_mask;
619 u64 rda_err_alarm;
620
621 u64 rc_err_reg;
622 #define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
623 #define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
624 #define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23)
625 #define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31)
626 #define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
627 #define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47)
628 #define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
629 u64 rc_err_mask;
630 u64 rc_err_alarm;
631
632 u64 prc_pcix_err_reg;
633 #define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
634 #define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
635 #define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
636 #define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
637 #define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
638 #define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
639 u64 prc_pcix_err_mask;
640 u64 prc_pcix_err_alarm;
641
642 u64 rpa_err_reg;
643 #define XGE_HAL_RPA_ECC_SG_ERR BIT(7)
644 #define XGE_HAL_RPA_ECC_DB_ERR BIT(15)
645 #define XGE_HAL_RPA_FLUSH_REQUEST BIT(22)
646 #define XGE_HAL_RPA_SM_ERR_ALARM BIT(23)
647 #define XGE_HAL_RPA_CREDIT_ERR BIT(31)
648 u64 rpa_err_mask;
649 u64 rpa_err_alarm;
650
651 u64 rti_err_reg;
652 #define XGE_HAL_RTI_ECC_SG_ERR BIT(7)
653 #define XGE_HAL_RTI_ECC_DB_ERR BIT(15)
654 #define XGE_HAL_RTI_SM_ERR_ALARM BIT(23)
655 u64 rti_err_mask;
656 u64 rti_err_alarm;
657
658 u8 unused12[0x100 - 0x88];
659
660 /* DMA arbiter */
661 u64 rx_queue_priority;
662 #define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
663 #define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
664 #define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
665 #define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
666 #define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
667 #define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
668 #define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
669 #define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
670
671 #define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */
672 #define XGE_HAL_RX_QUEUE_PRI_1 1
673 #define XGE_HAL_RX_QUEUE_PRI_2 2
674 #define XGE_HAL_RX_QUEUE_PRI_3 3
675 #define XGE_HAL_RX_QUEUE_PRI_4 4
676 #define XGE_HAL_RX_QUEUE_PRI_5 5
677 #define XGE_HAL_RX_QUEUE_PRI_6 6
678 #define XGE_HAL_RX_QUEUE_PRI_7 7 /* lowest */
679
680 u64 rx_w_round_robin_0;
681 u64 rx_w_round_robin_1;
682 u64 rx_w_round_robin_2;
683 u64 rx_w_round_robin_3;
684 u64 rx_w_round_robin_4;
685
686 /* Per-ring controller regs */
687 #define XGE_HAL_RX_MAX_RINGS 8
688 u64 prc_rxd0_n[XGE_HAL_RX_MAX_RINGS];
689 u64 prc_ctrl_n[XGE_HAL_RX_MAX_RINGS];
690 #define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7)
691 #define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
692 #define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
693 #define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
694 #define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
695 #define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2)
696 #define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2)
697 #define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31)
698 #define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT BIT(37)
699 #define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38)
700 #define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
701
702 u64 prc_alarm_action;
703 #define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
704 #define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
705 #define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
706 #define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
707 #define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
708 #define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
709 #define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
710 #define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
711 #define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
712 #define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
713 #define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
714 #define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
715 #define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
716 #define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
717 #define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
718 #define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
719
720 /* Receive traffic interrupts */
721 u64 rti_command_mem;
722 #define XGE_HAL_RTI_CMD_MEM_WE BIT(7)
723 #define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15)
724 #define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
725 #define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
726 #define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
727
728 u64 rti_data1_mem;
729 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
730 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
731 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
732 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
733 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
734 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
735
736 u64 rti_data2_mem;
737 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
738 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
739 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
740 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
741
742 u64 rx_pa_cfg;
743 #define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
744 #define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
745 #define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
746 #define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1)
747 #define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1)
748
749 u8 unused13_0[0x8];
750
751 u64 ring_bump_counter1;
752 u64 ring_bump_counter2;
753 #define XGE_HAL_RING_BUMP_CNT(i, val) (u16)(val >> (48 - (16 * (i % 4))))
754
755 u8 unused13[0x700 - 0x1f0];
756
757 u64 rxdma_debug_ctrl;
758
759 u8 unused14[0x2000 - 0x1f08];
760
761 /* Media Access Controller Register */
762 u64 mac_int_status;
763 u64 mac_int_mask;
764 #define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0)
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