oce_hw.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (C) 2013 Emulex
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions are met:
    9  *
   10  * 1. Redistributions of source code must retain the above copyright notice,
   11  *    this list of conditions and the following disclaimer.
   12  *
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * 3. Neither the name of the Emulex Corporation nor the names of its
   18  *    contributors may be used to endorse or promote products derived from
   19  *    this software without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   31  * POSSIBILITY OF SUCH DAMAGE.
   32  *
   33  * Contact Information:
   34  * freebsd-drivers@emulex.com
   35  *
   36  * Emulex
   37  * 3333 Susan Street
   38  * Costa Mesa, CA 92626
   39  */
   40 
   41 /* $FreeBSD$ */
   42 
   43 #include <sys/types.h>
   44 
   45 #undef _BIG_ENDIAN /* TODO */
   46 #pragma pack(1)
   47 
   48 #define OC_CNA_GEN2                     0x2
   49 #define OC_CNA_GEN3                     0x3
   50 #define DEVID_TIGERSHARK                0x700
   51 #define DEVID_TOMCAT                    0x710
   52 
   53 /* PCI CSR offsets */
   54 #define PCICFG_F1_CSR                   0x0     /* F1 for NIC */
   55 #define PCICFG_SEMAPHORE                0xbc
   56 #define PCICFG_SOFT_RESET               0x5c
   57 #define PCICFG_UE_STATUS_HI_MASK        0xac
   58 #define PCICFG_UE_STATUS_LO_MASK        0xa8
   59 #define PCICFG_ONLINE0                  0xb0
   60 #define PCICFG_ONLINE1                  0xb4
   61 #define INTR_EN                         0x20000000
   62 #define IMAGE_TRANSFER_SIZE             (32 * 1024)     /* 32K at a time */
   63 
   64 /********* UE Status and Mask Registers ***/
   65 #define PCICFG_UE_STATUS_LOW                    0xA0
   66 #define PCICFG_UE_STATUS_HIGH                   0xA4
   67 #define PCICFG_UE_STATUS_LOW_MASK               0xA8
   68 
   69 /* Lancer SLIPORT registers */
   70 #define SLIPORT_STATUS_OFFSET           0x404
   71 #define SLIPORT_CONTROL_OFFSET          0x408
   72 #define SLIPORT_ERROR1_OFFSET           0x40C
   73 #define SLIPORT_ERROR2_OFFSET           0x410
   74 #define PHYSDEV_CONTROL_OFFSET          0x414
   75 
   76 #define SLIPORT_STATUS_ERR_MASK         0x80000000
   77 #define SLIPORT_STATUS_DIP_MASK         0x02000000
   78 #define SLIPORT_STATUS_RN_MASK          0x01000000
   79 #define SLIPORT_STATUS_RDY_MASK         0x00800000
   80 #define SLI_PORT_CONTROL_IP_MASK        0x08000000
   81 #define PHYSDEV_CONTROL_FW_RESET_MASK   0x00000002
   82 #define PHYSDEV_CONTROL_DD_MASK         0x00000004
   83 #define PHYSDEV_CONTROL_INP_MASK        0x40000000
   84 
   85 #define SLIPORT_ERROR_NO_RESOURCE1      0x2
   86 #define SLIPORT_ERROR_NO_RESOURCE2      0x9
   87 /* CSR register offsets */
   88 #define MPU_EP_CONTROL                  0
   89 #define MPU_EP_SEMAPHORE_BE3            0xac
   90 #define MPU_EP_SEMAPHORE_XE201          0x400
   91 #define MPU_EP_SEMAPHORE_SH             0x94
   92 #define PCICFG_INTR_CTRL                0xfc
   93 #define HOSTINTR_MASK                   (1 << 29)
   94 #define HOSTINTR_PFUNC_SHIFT            26
   95 #define HOSTINTR_PFUNC_MASK             7
   96 
   97 /* POST status reg struct */
   98 #define POST_STAGE_POWER_ON_RESET       0x00
   99 #define POST_STAGE_AWAITING_HOST_RDY    0x01
  100 #define POST_STAGE_HOST_RDY             0x02
  101 #define POST_STAGE_CHIP_RESET           0x03
  102 #define POST_STAGE_ARMFW_READY          0xc000
  103 #define POST_STAGE_ARMFW_UE             0xf000
  104 
  105 /* DOORBELL registers */
  106 #define PD_RXULP_DB                     0x0100
  107 #define PD_TXULP_DB                     0x0060
  108 #define DB_RQ_ID_MASK                   0x3FF
  109 
  110 #define PD_CQ_DB                        0x0120
  111 #define PD_EQ_DB                        PD_CQ_DB
  112 #define PD_MPU_MBOX_DB                  0x0160
  113 #define PD_MQ_DB                        0x0140
  114 
  115 #define DB_OFFSET                       0xc0
  116 #define DB_LRO_RQ_ID_MASK               0x7FF
  117 
  118 /* EQE completion types */
  119 #define EQ_MINOR_CODE_COMPLETION        0x00
  120 #define EQ_MINOR_CODE_OTHER             0x01
  121 #define EQ_MAJOR_CODE_COMPLETION        0x00
  122 
  123 /* Link Status field values */
  124 #define PHY_LINK_FAULT_NONE             0x0
  125 #define PHY_LINK_FAULT_LOCAL            0x01
  126 #define PHY_LINK_FAULT_REMOTE           0x02
  127 
  128 #define PHY_LINK_SPEED_ZERO             0x0     /* No link */
  129 #define PHY_LINK_SPEED_10MBPS           0x1     /* (10 Mbps) */
  130 #define PHY_LINK_SPEED_100MBPS          0x2     /* (100 Mbps) */
  131 #define PHY_LINK_SPEED_1GBPS            0x3     /* (1 Gbps) */
  132 #define PHY_LINK_SPEED_10GBPS           0x4     /* (10 Gbps) */
  133 
  134 #define PHY_LINK_DUPLEX_NONE            0x0
  135 #define PHY_LINK_DUPLEX_HALF            0x1
  136 #define PHY_LINK_DUPLEX_FULL            0x2
  137 
  138 #define NTWK_PORT_A                     0x0     /* (Port A) */
  139 #define NTWK_PORT_B                     0x1     /* (Port B) */
  140 
  141 #define PHY_LINK_SPEED_ZERO                     0x0     /* (No link.) */
  142 #define PHY_LINK_SPEED_10MBPS           0x1     /* (10 Mbps) */
  143 #define PHY_LINK_SPEED_100MBPS          0x2     /* (100 Mbps) */
  144 #define PHY_LINK_SPEED_1GBPS            0x3     /* (1 Gbps) */
  145 #define PHY_LINK_SPEED_10GBPS           0x4     /* (10 Gbps) */
  146 
  147 /* Hardware Address types */
  148 #define MAC_ADDRESS_TYPE_STORAGE        0x0     /* (Storage MAC Address) */
  149 #define MAC_ADDRESS_TYPE_NETWORK        0x1     /* (Network MAC Address) */
  150 #define MAC_ADDRESS_TYPE_PD             0x2     /* (Protection Domain MAC Addr) */
  151 #define MAC_ADDRESS_TYPE_MANAGEMENT     0x3     /* (Management MAC Address) */
  152 #define MAC_ADDRESS_TYPE_FCOE           0x4     /* (FCoE MAC Address) */
  153 
  154 /* CREATE_IFACE capability and cap_en flags */
  155 #define MBX_RX_IFACE_FLAGS_RSS          0x4
  156 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS  0x8
  157 #define MBX_RX_IFACE_FLAGS_BROADCAST    0x10
  158 #define MBX_RX_IFACE_FLAGS_UNTAGGED     0x20
  159 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS     0x80
  160 #define MBX_RX_IFACE_FLAGS_VLAN         0x100
  161 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS    0x200
  162 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR  0x400
  163 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR        0x800
  164 #define MBX_RX_IFACE_FLAGS_MULTICAST    0x1000
  165 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000
  166 #define MBX_RX_IFACE_FLAGS_HDS          0x4000
  167 #define MBX_RX_IFACE_FLAGS_DIRECTED     0x8000
  168 #define MBX_RX_IFACE_FLAGS_VMQ          0x10000
  169 #define MBX_RX_IFACE_FLAGS_NETQ         0x20000
  170 #define MBX_RX_IFACE_FLAGS_QGROUPS      0x40000
  171 #define MBX_RX_IFACE_FLAGS_LSO          0x80000
  172 #define MBX_RX_IFACE_FLAGS_LRO          0x100000
  173 
  174 #define MQ_RING_CONTEXT_SIZE_16         0x5     /* (16 entries) */
  175 #define MQ_RING_CONTEXT_SIZE_32         0x6     /* (32 entries) */
  176 #define MQ_RING_CONTEXT_SIZE_64         0x7     /* (64 entries) */
  177 #define MQ_RING_CONTEXT_SIZE_128        0x8     /* (128 entries) */
  178 
  179 #define MBX_DB_READY_BIT                0x1
  180 #define MBX_DB_HI_BIT                   0x2
  181 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  182 #define ASYNC_EVENT_LINK_UP             0x1
  183 #define ASYNC_EVENT_LINK_DOWN           0x0
  184 #define ASYNC_EVENT_GRP5                0x5
  185 #define ASYNC_EVENT_CODE_DEBUG          0x6
  186 #define ASYNC_EVENT_PVID_STATE          0x3
  187 #define ASYNC_EVENT_OS2BMC              0x5
  188 #define ASYNC_EVENT_DEBUG_QNQ           0x1
  189 #define ASYNC_EVENT_CODE_SLIPORT        0x11
  190 #define VLAN_VID_MASK                   0x0FFF
  191 
  192 /* port link_status */
  193 #define ASYNC_EVENT_LOGICAL             0x02
  194 
  195 /* Logical Link Status */
  196 #define NTWK_LOGICAL_LINK_DOWN          0
  197 #define NTWK_LOGICAL_LINK_UP            1
  198 
  199 /* Rx filter bits */
  200 #define NTWK_RX_FILTER_IP_CKSUM         0x1
  201 #define NTWK_RX_FILTER_TCP_CKSUM        0x2
  202 #define NTWK_RX_FILTER_UDP_CKSUM        0x4
  203 #define NTWK_RX_FILTER_STRIP_CRC        0x8
  204 
  205 /* max SGE per mbx */
  206 #define MAX_MBX_SGE                     19
  207 
  208 /* Max multicast filter size*/
  209 #define OCE_MAX_MC_FILTER_SIZE          64
  210 
  211 /* PCI SLI (Service Level Interface) capabilities register */ 
  212 #define OCE_INTF_REG_OFFSET             0x58
  213 #define OCE_INTF_VALID_SIG              6       /* register's signature */
  214 #define OCE_INTF_FUNC_RESET_REQD        1
  215 #define OCE_INTF_HINT1_NOHINT           0
  216 #define OCE_INTF_HINT1_SEMAINIT         1
  217 #define OCE_INTF_HINT1_STATCTRL         2
  218 #define OCE_INTF_IF_TYPE_0              0
  219 #define OCE_INTF_IF_TYPE_1              1
  220 #define OCE_INTF_IF_TYPE_2              2
  221 #define OCE_INTF_IF_TYPE_3              3
  222 #define OCE_INTF_SLI_REV3               3       /* not supported by driver */
  223 #define OCE_INTF_SLI_REV4               4       /* driver supports SLI-4 */
  224 #define OCE_INTF_PHYS_FUNC              0
  225 #define OCE_INTF_VIRT_FUNC              1
  226 #define OCE_INTF_FAMILY_BE2             0       /* not supported by driver */
  227 #define OCE_INTF_FAMILY_BE3             1       /* driver supports BE3 */
  228 #define OCE_INTF_FAMILY_A0_CHIP         0xA     /* Lancer A0 chip (supported) */
  229 #define OCE_INTF_FAMILY_B0_CHIP         0xB     /* Lancer B0 chip (future) */
  230 
  231 #define NIC_WQE_SIZE    16
  232 #define NIC_UNICAST     0x00
  233 #define NIC_MULTICAST   0x01
  234 #define NIC_BROADCAST   0x02
  235 
  236 #define NIC_HDS_NO_SPLIT        0x00
  237 #define NIC_HDS_SPLIT_L3PL      0x01
  238 #define NIC_HDS_SPLIT_L4PL      0x02
  239 
  240 #define NIC_WQ_TYPE_FORWARDING          0x01
  241 #define NIC_WQ_TYPE_STANDARD            0x02
  242 #define NIC_WQ_TYPE_LOW_LATENCY         0x04
  243 
  244 #define OCE_RESET_STATS         1
  245 #define OCE_RETAIN_STATS        0
  246 #define OCE_TXP_SW_SZ           48
  247 
  248 typedef union pci_sli_intf_u {
  249         uint32_t dw0;
  250         struct {
  251 #ifdef _BIG_ENDIAN
  252                 uint32_t sli_valid:3;
  253                 uint32_t sli_hint2:5;
  254                 uint32_t sli_hint1:8;
  255                 uint32_t sli_if_type:4;
  256                 uint32_t sli_family:4;
  257                 uint32_t sli_rev:4;
  258                 uint32_t rsv0:3;
  259                 uint32_t sli_func_type:1;
  260 #else
  261                 uint32_t sli_func_type:1;
  262                 uint32_t rsv0:3;
  263                 uint32_t sli_rev:4;
  264                 uint32_t sli_family:4;
  265                 uint32_t sli_if_type:4;
  266                 uint32_t sli_hint1:8;
  267                 uint32_t sli_hint2:5;
  268                 uint32_t sli_valid:3;
  269 #endif
  270         } bits;
  271 } pci_sli_intf_t;
  272 
  273 /* physical address structure to be used in MBX */
  274 struct phys_addr {
  275         /* dw0 */
  276         uint32_t lo;
  277         /* dw1 */
  278         uint32_t hi;
  279 };
  280 
  281 typedef union pcicfg_intr_ctl_u {
  282         uint32_t dw0;
  283         struct {
  284 #ifdef _BIG_ENDIAN
  285                 uint32_t winselect:2;
  286                 uint32_t hostintr:1;
  287                 uint32_t pfnum:3;
  288                 uint32_t vf_cev_int_line_en:1;
  289                 uint32_t winaddr:23;
  290                 uint32_t membarwinen:1;
  291 #else
  292                 uint32_t membarwinen:1;
  293                 uint32_t winaddr:23;
  294                 uint32_t vf_cev_int_line_en:1;
  295                 uint32_t pfnum:3;
  296                 uint32_t hostintr:1;
  297                 uint32_t winselect:2;
  298 #endif
  299         } bits;
  300 } pcicfg_intr_ctl_t;
  301 
  302 typedef union pcicfg_semaphore_u {
  303         uint32_t dw0;
  304         struct {
  305 #ifdef _BIG_ENDIAN
  306                 uint32_t rsvd:31;
  307                 uint32_t lock:1;
  308 #else
  309                 uint32_t lock:1;
  310                 uint32_t rsvd:31;
  311 #endif
  312         } bits;
  313 } pcicfg_semaphore_t;
  314 
  315 typedef union pcicfg_soft_reset_u {
  316         uint32_t dw0;
  317         struct {
  318 #ifdef _BIG_ENDIAN
  319                 uint32_t nec_ll_rcvdetect:8;
  320                 uint32_t dbg_all_reqs_62_49:14;
  321                 uint32_t scratchpad0:1;
  322                 uint32_t exception_oe:1;
  323                 uint32_t soft_reset:1;
  324                 uint32_t rsvd0:7;
  325 #else
  326                 uint32_t rsvd0:7;
  327                 uint32_t soft_reset:1;
  328                 uint32_t exception_oe:1;
  329                 uint32_t scratchpad0:1;
  330                 uint32_t dbg_all_reqs_62_49:14;
  331                 uint32_t nec_ll_rcvdetect:8;
  332 #endif
  333         } bits;
  334 } pcicfg_soft_reset_t;
  335 
  336 typedef union pcicfg_online1_u {
  337         uint32_t dw0;
  338         struct {
  339 #ifdef _BIG_ENDIAN
  340                 uint32_t host8_online:1;
  341                 uint32_t host7_online:1;
  342                 uint32_t host6_online:1;
  343                 uint32_t host5_online:1;
  344                 uint32_t host4_online:1;
  345                 uint32_t host3_online:1;
  346                 uint32_t host2_online:1;
  347                 uint32_t ipc_online:1;
  348                 uint32_t arm_online:1;
  349                 uint32_t txp_online:1;
  350                 uint32_t xaui_online:1;
  351                 uint32_t rxpp_online:1;
  352                 uint32_t txpb_online:1;
  353                 uint32_t rr_online:1;
  354                 uint32_t pmem_online:1;
  355                 uint32_t pctl1_online:1;
  356                 uint32_t pctl0_online:1;
  357                 uint32_t pcs1online_online:1;
  358                 uint32_t mpu_iram_online:1;
  359                 uint32_t pcs0online_online:1;
  360                 uint32_t mgmt_mac_online:1;
  361                 uint32_t lpcmemhost_online:1;
  362 #else
  363                 uint32_t lpcmemhost_online:1;
  364                 uint32_t mgmt_mac_online:1;
  365                 uint32_t pcs0online_online:1;
  366                 uint32_t mpu_iram_online:1;
  367                 uint32_t pcs1online_online:1;
  368                 uint32_t pctl0_online:1;
  369                 uint32_t pctl1_online:1;
  370                 uint32_t pmem_online:1;
  371                 uint32_t rr_online:1;
  372                 uint32_t txpb_online:1;
  373                 uint32_t rxpp_online:1;
  374                 uint32_t xaui_online:1;
  375                 uint32_t txp_online:1;
  376                 uint32_t arm_online:1;
  377                 uint32_t ipc_online:1;
  378                 uint32_t host2_online:1;
  379                 uint32_t host3_online:1;
  380                 uint32_t host4_online:1;
  381                 uint32_t host5_online:1;
  382                 uint32_t host6_online:1;
  383                 uint32_t host7_online:1;
  384                 uint32_t host8_online:1;
  385 #endif
  386         } bits;
  387 } pcicfg_online1_t;
  388 
  389 typedef union mpu_ep_semaphore_u {
  390         uint32_t dw0;
  391         struct {
  392 #ifdef _BIG_ENDIAN
  393                 uint32_t error:1;
  394                 uint32_t backup_fw:1;
  395                 uint32_t iscsi_no_ip:1;
  396                 uint32_t iscsi_ip_conflict:1;
  397                 uint32_t option_rom_installed:1;
  398                 uint32_t iscsi_drv_loaded:1;
  399                 uint32_t rsvd0:10;
  400                 uint32_t stage:16;
  401 #else
  402                 uint32_t stage:16;
  403                 uint32_t rsvd0:10;
  404                 uint32_t iscsi_drv_loaded:1;
  405                 uint32_t option_rom_installed:1;
  406                 uint32_t iscsi_ip_conflict:1;
  407                 uint32_t iscsi_no_ip:1;
  408                 uint32_t backup_fw:1;
  409                 uint32_t error:1;
  410 #endif
  411         } bits;
  412 } mpu_ep_semaphore_t;
  413 
  414 typedef union mpu_ep_control_u {
  415         uint32_t dw0;
  416         struct {
  417 #ifdef _BIG_ENDIAN
  418                 uint32_t cpu_reset:1;
  419                 uint32_t rsvd1:15;
  420                 uint32_t ep_ram_init_status:1;
  421                 uint32_t rsvd0:12;
  422                 uint32_t m2_rxpbuf:1;
  423                 uint32_t m1_rxpbuf:1;
  424                 uint32_t m0_rxpbuf:1;
  425 #else
  426                 uint32_t m0_rxpbuf:1;
  427                 uint32_t m1_rxpbuf:1;
  428                 uint32_t m2_rxpbuf:1;
  429                 uint32_t rsvd0:12;
  430                 uint32_t ep_ram_init_status:1;
  431                 uint32_t rsvd1:15;
  432                 uint32_t cpu_reset:1;
  433 #endif
  434         } bits;
  435 } mpu_ep_control_t;
  436 
  437 /* RX doorbell */
  438 typedef union pd_rxulp_db_u {
  439         uint32_t dw0;
  440         struct {
  441 #ifdef _BIG_ENDIAN
  442                 uint32_t num_posted:8;
  443                 uint32_t invalidate:1;
  444                 uint32_t rsvd1:13;
  445                 uint32_t qid:10;
  446 #else
  447                 uint32_t qid:10;
  448                 uint32_t rsvd1:13;
  449                 uint32_t invalidate:1;
  450                 uint32_t num_posted:8;
  451 #endif
  452         } bits;
  453 } pd_rxulp_db_t;
  454 
  455 /* TX doorbell */
  456 typedef union pd_txulp_db_u {
  457         uint32_t dw0;
  458         struct {
  459 #ifdef _BIG_ENDIAN
  460                 uint32_t rsvd1:2;
  461                 uint32_t num_posted:14;
  462                 uint32_t rsvd0:6;
  463                 uint32_t qid:10;
  464 #else
  465                 uint32_t qid:10;
  466                 uint32_t rsvd0:6;
  467                 uint32_t num_posted:14;
  468                 uint32_t rsvd1:2;
  469 #endif
  470         } bits;
  471 } pd_txulp_db_t;
  472 
  473 /* CQ doorbell */
  474 typedef union cq_db_u {
  475         uint32_t dw0;
  476         struct {
  477 #ifdef _BIG_ENDIAN
  478                 uint32_t rsvd1:2;
  479                 uint32_t rearm:1;
  480                 uint32_t num_popped:13;
  481                 uint32_t rsvd0:5;
  482                 uint32_t event:1;
  483                 uint32_t qid:10;
  484 #else
  485                 uint32_t qid:10;
  486                 uint32_t event:1;
  487                 uint32_t rsvd0:5;
  488                 uint32_t num_popped:13;
  489                 uint32_t rearm:1;
  490                 uint32_t rsvd1:2;
  491 #endif
  492         } bits;
  493 } cq_db_t;
  494 
  495 /* EQ doorbell */
  496 typedef union eq_db_u {
  497         uint32_t dw0;
  498         struct {
  499 #ifdef _BIG_ENDIAN
  500                 uint32_t rsvd1:2;
  501                 uint32_t rearm:1;
  502                 uint32_t num_popped:13;
  503                 uint32_t rsvd0:5;
  504                 uint32_t event:1;
  505                 uint32_t clrint:1;
  506                 uint32_t qid:9;
  507 #else
  508                 uint32_t qid:9;
  509                 uint32_t clrint:1;
  510                 uint32_t event:1;
  511                 uint32_t rsvd0:5;
  512                 uint32_t num_popped:13;
  513                 uint32_t rearm:1;
  514                 uint32_t rsvd1:2;
  515 #endif
  516         } bits;
  517 } eq_db_t;
  518 
  519 /* bootstrap mbox doorbell */
  520 typedef union pd_mpu_mbox_db_u {
  521         uint32_t dw0;
  522         struct {
  523 #ifdef _BIG_ENDIAN
  524                 uint32_t address:30;
  525                 uint32_t hi:1;
  526                 uint32_t ready:1;
  527 #else
  528                 uint32_t ready:1;
  529                 uint32_t hi:1;
  530                 uint32_t address:30;
  531 #endif
  532         } bits;
  533 } pd_mpu_mbox_db_t;
  534 
  535 /* MQ ring doorbell */
  536 typedef union pd_mq_db_u {
  537         uint32_t dw0;
  538         struct {
  539 #ifdef _BIG_ENDIAN
  540                 uint32_t rsvd1:2;
  541                 uint32_t num_posted:14;
  542                 uint32_t rsvd0:5;
  543                 uint32_t mq_id:11;
  544 #else
  545                 uint32_t mq_id:11;
  546                 uint32_t rsvd0:5;
  547                 uint32_t num_posted:14;
  548                 uint32_t rsvd1:2;
  549 #endif
  550         } bits;
  551 } pd_mq_db_t;
  552 
  553 /*
  554  * Event Queue Entry
  555  */
  556 struct oce_eqe {
  557         uint32_t evnt;
  558 };
  559 
  560 /* MQ scatter gather entry. Array of these make an SGL */
  561 struct oce_mq_sge {
  562         uint32_t pa_lo;
  563         uint32_t pa_hi;
  564         uint32_t length;
  565 };
  566 
  567 /*
  568  * payload can contain an SGL or an embedded array of upto 59 dwords
  569  */
  570 struct oce_mbx_payload {
  571         union {
  572                 union {
  573                         struct oce_mq_sge sgl[MAX_MBX_SGE];
  574                         uint32_t embedded[59];
  575                 } u1;
  576                 uint32_t dw[59];
  577         } u0;
  578 };
  579 
  580 /*
  581  * MQ MBX structure
  582  */
  583 struct oce_mbx {
  584         union {
  585                 struct {
  586 #ifdef _BIG_ENDIAN
  587                         uint32_t special:8;
  588                         uint32_t rsvd1:16;
  589                         uint32_t sge_count:5;
  590                         uint32_t rsvd0:2;
  591                         uint32_t embedded:1;
  592 #else
  593                         uint32_t embedded:1;
  594                         uint32_t rsvd0:2;
  595                         uint32_t sge_count:5;
  596                         uint32_t rsvd1:16;
  597                         uint32_t special:8;
  598 #endif
  599                 } s;
  600                 uint32_t dw0;
  601         } u0;
  602 
  603         uint32_t payload_length;
  604         uint32_t tag[2];
  605         uint32_t rsvd2[1];
  606         struct oce_mbx_payload payload;
  607 };
  608 
  609 /* completion queue entry for MQ */
  610 struct oce_mq_cqe {
  611         union {
  612                 struct {
  613 #ifdef _BIG_ENDIAN
  614                         /* dw0 */
  615                         uint32_t extended_status:16;
  616                         uint32_t completion_status:16;
  617                         /* dw1 dw2 */
  618                         uint32_t mq_tag[2];
  619                         /* dw3 */
  620                         uint32_t valid:1;
  621                         uint32_t async_event:1;
  622                         uint32_t hpi_buffer_cmpl:1;
  623                         uint32_t completed:1;
  624                         uint32_t consumed:1;
  625                         uint32_t rsvd0:3;
  626                         uint32_t async_type:8;
  627                         uint32_t event_type:8;
  628                         uint32_t rsvd1:8;
  629 #else
  630                         /* dw0 */
  631                         uint32_t completion_status:16;
  632                         uint32_t extended_status:16;
  633                         /* dw1 dw2 */
  634                         uint32_t mq_tag[2];
  635                         /* dw3 */
  636                         uint32_t rsvd1:8;
  637                         uint32_t event_type:8;
  638                         uint32_t async_type:8;
  639                         uint32_t rsvd0:3;
  640                         uint32_t consumed:1;
  641                         uint32_t completed:1;
  642                         uint32_t hpi_buffer_cmpl:1;
  643                         uint32_t async_event:1;
  644                         uint32_t valid:1;
  645 #endif
  646                 } s;
  647                 uint32_t dw[4];
  648         } u0;
  649 };
  650 
  651 /* Mailbox Completion Status Codes */
  652 enum MBX_COMPLETION_STATUS {
  653         MBX_CQE_STATUS_SUCCESS = 0x00,
  654         MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01,
  655         MBX_CQE_STATUS_INVALID_PARAMETER = 0x02,
  656         MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03,
  657         MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04,
  658         MBX_CQE_STATUS_DMA_FAILED = 0x05
  659 };
  660 
  661 struct oce_async_cqe_link_state {
  662         union {
  663                 struct {
  664 #ifdef _BIG_ENDIAN
  665                         /* dw0 */
  666                         uint8_t speed;
  667                         uint8_t duplex;
  668                         uint8_t link_status;
  669                         uint8_t phy_port;
  670                         /* dw1 */
  671                         uint16_t qos_link_speed;
  672                         uint8_t rsvd0;
  673                         uint8_t fault;
  674                         /* dw2 */
  675                         uint32_t event_tag;
  676                         /* dw3 */
  677                         uint32_t valid:1;
  678                         uint32_t async_event:1;
  679                         uint32_t rsvd2:6;
  680                         uint32_t event_type:8;
  681                         uint32_t event_code:8;
  682                         uint32_t rsvd1:8;
  683 #else
  684                         /* dw0 */
  685                         uint8_t phy_port;
  686                         uint8_t link_status;
  687                         uint8_t duplex;
  688                         uint8_t speed;
  689                         /* dw1 */
  690                         uint8_t fault;
  691                         uint8_t rsvd0;
  692                         uint16_t qos_link_speed;
  693                         /* dw2 */
  694                         uint32_t event_tag;
  695                         /* dw3 */
  696                         uint32_t rsvd1:8;
  697                         uint32_t event_code:8;
  698                         uint32_t event_type:8;
  699                         uint32_t rsvd2:6;
  700                         uint32_t async_event:1;
  701                         uint32_t valid:1;
  702 #endif
  703                 } s;
  704                 uint32_t dw[4];
  705         } u0;
  706 };
  707 
  708 /* OS2BMC async event */
  709 struct oce_async_evt_grp5_os2bmc {
  710         union {
  711                 struct {
  712                         uint32_t lrn_enable:1;
  713                         uint32_t lrn_disable:1;
  714                         uint32_t mgmt_enable:1;
  715                         uint32_t mgmt_disable:1;
  716                         uint32_t rsvd0:12;
  717                         uint32_t vlan_tag:16;
  718                         uint32_t arp_filter:1;
  719                         uint32_t dhcp_client_filt:1;
  720                         uint32_t dhcp_server_filt:1;
  721                         uint32_t net_bios_filt:1;
  722                         uint32_t rsvd1:3;
  723                         uint32_t bcast_filt:1;
  724                         uint32_t ipv6_nbr_filt:1;
  725                         uint32_t ipv6_ra_filt:1;
  726                         uint32_t ipv6_ras_filt:1;
  727                         uint32_t rsvd2[4];
  728                         uint32_t mcast_filt:1;
  729                         uint32_t rsvd3:16;
  730                         uint32_t evt_tag;
  731                         uint32_t dword3;
  732                 } s;
  733                 uint32_t dword[4];
  734         } u;
  735 };
  736 
  737 /* PVID aync event */
  738 struct oce_async_event_grp5_pvid_state {
  739         uint8_t enabled;
  740         uint8_t rsvd0;
  741         uint16_t tag;
  742         uint32_t event_tag;
  743         uint32_t rsvd1;
  744         uint32_t code;
  745 };
  746 
  747 /* async event indicating outer VLAN tag in QnQ */
  748 struct oce_async_event_qnq {
  749         uint8_t valid;       /* Indicates if outer VLAN is valid */
  750         uint8_t rsvd0;
  751         uint16_t vlan_tag;
  752         uint32_t event_tag;
  753         uint8_t rsvd1[4];
  754         uint32_t code;
  755 } ;
  756 
  757 typedef union oce_mq_ext_ctx_u {
  758         uint32_t dw[6];
  759         struct {
  760                 #ifdef _BIG_ENDIAN
  761                 /* dw0 */
  762                 uint32_t dw4rsvd1:16;
  763                 uint32_t num_pages:16;
  764                 /* dw1 */
  765                 uint32_t async_evt_bitmap;
  766                 /* dw2 */
  767                 uint32_t cq_id:10;
  768                 uint32_t dw5rsvd2:2;
  769                 uint32_t ring_size:4;
  770                 uint32_t dw5rsvd1:16;
  771                 /* dw3 */
  772                 uint32_t valid:1;
  773                 uint32_t dw6rsvd1:31;
  774                 /* dw4 */
  775                 uint32_t dw7rsvd1:21;
  776                 uint32_t async_cq_id:10;
  777                 uint32_t async_cq_valid:1;
  778         #else
  779                 /* dw0 */
  780                 uint32_t num_pages:16;
  781                 uint32_t dw4rsvd1:16;
  782                 /* dw1 */
  783                 uint32_t async_evt_bitmap;
  784                 /* dw2 */
  785                 uint32_t dw5rsvd1:16;
  786                 uint32_t ring_size:4;
  787                 uint32_t dw5rsvd2:2;
  788                 uint32_t cq_id:10;
  789                 /* dw3 */
  790                 uint32_t dw6rsvd1:31;
  791                 uint32_t valid:1;
  792                 /* dw4 */
  793                 uint32_t async_cq_valid:1;
  794                 uint32_t async_cq_id:10;
  795                 uint32_t dw7rsvd1:21;
  796         #endif
  797                 /* dw5 */
  798                 uint32_t dw8rsvd1;
  799         } v0;
  800                 struct {
  801         #ifdef _BIG_ENDIAN
  802                 /* dw0 */
  803                 uint32_t cq_id:16;
  804                 uint32_t num_pages:16;
  805                 /* dw1 */
  806                 uint32_t async_evt_bitmap;
  807                 /* dw2 */
  808                 uint32_t dw5rsvd2:12;
  809                 uint32_t ring_size:4;
  810                 uint32_t async_cq_id:16;
  811                 /* dw3 */
  812                 uint32_t valid:1;
  813                 uint32_t dw6rsvd1:31;
  814                 /* dw4 */
  815                 uint32_t dw7rsvd1:31;
  816                 uint32_t async_cq_valid:1;
  817         #else
  818                 /* dw0 */
  819                 uint32_t num_pages:16;
  820                 uint32_t cq_id:16;
  821                 /* dw1 */
  822                 uint32_t async_evt_bitmap;
  823                 /* dw2 */
  824                 uint32_t async_cq_id:16;
  825                 uint32_t ring_size:4;
  826                 uint32_t dw5rsvd2:12;
  827                 /* dw3 */
  828                 uint32_t dw6rsvd1:31;
  829                 uint32_t valid:1;
  830                 /* dw4 */
  831                 uint32_t async_cq_valid:1;
  832                 uint32_t dw7rsvd1:31;
  833         #endif
  834                 /* dw5 */
  835                 uint32_t dw8rsvd1;
  836         } v1;
  837 
  838 } oce_mq_ext_ctx_t;
  839 
  840 /* MQ mailbox structure */
  841 struct oce_bmbx {
  842         struct oce_mbx mbx;
  843         struct oce_mq_cqe cqe;
  844 };
  845 
  846 /* ---[ MBXs start here ]---------------------------------------------- */
  847 /* MBXs sub system codes */
  848 enum MBX_SUBSYSTEM_CODES {
  849         MBX_SUBSYSTEM_RSVD = 0,
  850         MBX_SUBSYSTEM_COMMON = 1,
  851         MBX_SUBSYSTEM_COMMON_ISCSI = 2,
  852         MBX_SUBSYSTEM_NIC = 3,
  853         MBX_SUBSYSTEM_TOE = 4,
  854         MBX_SUBSYSTEM_PXE_UNDI = 5,
  855         MBX_SUBSYSTEM_ISCSI_INI = 6,
  856         MBX_SUBSYSTEM_ISCSI_TGT = 7,
  857         MBX_SUBSYSTEM_MILI_PTL = 8,
  858         MBX_SUBSYSTEM_MILI_TMD = 9,
  859         MBX_SUBSYSTEM_RDMA = 10,
  860         MBX_SUBSYSTEM_LOWLEVEL = 11,
  861         MBX_SUBSYSTEM_LRO = 13,
  862         IOCBMBX_SUBSYSTEM_DCBX = 15,
  863         IOCBMBX_SUBSYSTEM_DIAG = 16,
  864         IOCBMBX_SUBSYSTEM_VENDOR = 17
  865 };
  866 
  867 /* common ioctl opcodes */
  868 enum COMMON_SUBSYSTEM_OPCODES {
  869 /* These opcodes are common to both networking and storage PCI functions
  870  * They are used to reserve resources and configure CNA. These opcodes
  871  * all use the MBX_SUBSYSTEM_COMMON subsystem code.
  872  */
  873         OPCODE_COMMON_QUERY_IFACE_MAC = 1,
  874         OPCODE_COMMON_SET_IFACE_MAC = 2,
  875         OPCODE_COMMON_SET_IFACE_MULTICAST = 3,
  876         OPCODE_COMMON_CONFIG_IFACE_VLAN = 4,
  877         OPCODE_COMMON_QUERY_LINK_CONFIG = 5,
  878         OPCODE_COMMON_READ_FLASHROM = 6,
  879         OPCODE_COMMON_WRITE_FLASHROM = 7,
  880         OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8,
  881         OPCODE_COMMON_CREATE_CQ = 12,
  882         OPCODE_COMMON_CREATE_EQ = 13,
  883         OPCODE_COMMON_CREATE_MQ = 21,
  884         OPCODE_COMMON_GET_QOS = 27,
  885         OPCODE_COMMON_SET_QOS = 28,
  886         OPCODE_COMMON_READ_EPROM = 30,
  887         OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32,
  888         OPCODE_COMMON_NOP = 33,
  889         OPCODE_COMMON_SET_IFACE_RX_FILTER = 34,
  890         OPCODE_COMMON_GET_FW_VERSION = 35,
  891         OPCODE_COMMON_SET_FLOW_CONTROL = 36,
  892         OPCODE_COMMON_GET_FLOW_CONTROL = 37,
  893         OPCODE_COMMON_SET_FRAME_SIZE = 39,
  894         OPCODE_COMMON_MODIFY_EQ_DELAY = 41,
  895         OPCODE_COMMON_CREATE_IFACE = 50,
  896         OPCODE_COMMON_DESTROY_IFACE = 51,
  897         OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52,
  898         OPCODE_COMMON_DESTROY_MQ = 53,
  899         OPCODE_COMMON_DESTROY_CQ = 54,
  900         OPCODE_COMMON_DESTROY_EQ = 55,
  901         OPCODE_COMMON_UPLOAD_TCP = 56,
  902         OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57,
  903         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58,
  904         OPCODE_COMMON_ADD_IFACE_MAC = 59,
  905         OPCODE_COMMON_DEL_IFACE_MAC = 60,
  906         OPCODE_COMMON_FUNCTION_RESET = 61,
  907         OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62,
  908         OPCODE_COMMON_GET_BOOT_CONFIG = 66,
  909         OPCPDE_COMMON_SET_BOOT_CONFIG = 67,
  910         OPCODE_COMMON_SET_BEACON_CONFIG = 69,
  911         OPCODE_COMMON_GET_BEACON_CONFIG = 70,
  912         OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71,
  913         OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73,
  914         OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76,
  915         OPCODE_COMMON_GET_PORT_NAME = 77,
  916         OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78,
  917         OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79,
  918         OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80,
  919         OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81,
  920         OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82,
  921         OPCODE_COMMON_GET_RESET_NEEDED = 84,
  922         OPCODE_COMMON_GET_SERIAL_NUMBER = 85,
  923         OPCODE_COMMON_GET_NCSI_CONFIG = 86,
  924         OPCODE_COMMON_SET_NCSI_CONFIG = 87,
  925         OPCODE_COMMON_CREATE_MQ_EXT = 90,
  926         OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100,
  927         OPCODE_COMMON_SET_VF_PORT_TYPE = 101,
  928         OPCODE_COMMON_GET_PHY_CONFIG = 102,
  929         OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103,
  930         OPCODE_COMMON_GET_ADAPTER_ID = 110,
  931         OPCODE_COMMON_GET_UPGRADE_FEATURES = 111,
  932         OPCODE_COMMON_GET_INSTALLED_FEATURES = 112,
  933         OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113,
  934         OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114,
  935         OPCODE_COMMON_SEND_ACTIVATION = 115,
  936         OPCODE_COMMON_RESET_LICENSES = 116,
  937         OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121,
  938         OPCODE_COMMON_QUERY_TCB = 144,
  939         OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145,
  940         OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146,
  941         OPCODE_COMMON_GET_IFACE_MAC_LIST = 147,
  942         OPCODE_COMMON_SET_IFACE_MAC_LIST = 148,
  943         OPCODE_COMMON_MODIFY_CQ = 149,
  944         OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150,
  945         OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151,
  946         OPCODE_COMMON_GET_HSW_CONFIG = 152,
  947         OPCODE_COMMON_SET_HSW_CONFIG = 153,
  948         OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154,
  949         OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155,
  950         OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156,
  951         OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157,
  952         OPCODE_COMMON_SET_DIAG_REGISTERS = 158,
  953         OPCODE_COMMON_GET_FUNCTION_CONFIG = 160,
  954         OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161,
  955         OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162,
  956         OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163,
  957         OPCODE_COMMON_GET_PROFILE_CONFIG = 164,
  958         OPCODE_COMMON_SET_PROFILE_CONFIG = 165,
  959         OPCODE_COMMON_GET_PROFILE_LIST = 166,
  960         OPCODE_COMMON_GET_ACTIVE_PROFILE = 167,
  961         OPCODE_COMMON_SET_ACTIVE_PROFILE = 168,
  962         OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170,
  963         OPCODE_COMMON_READ_OBJECT = 171,
  964         OPCODE_COMMON_WRITE_OBJECT = 172
  965 };
  966 
  967 /* common ioctl header */
  968 #define OCE_MBX_VER_V2  0x0002          /* Version V2 mailbox command */
  969 #define OCE_MBX_VER_V1  0x0001          /* Version V1 mailbox command */
  970 #define OCE_MBX_VER_V0  0x0000          /* Version V0 mailbox command */
  971 struct mbx_hdr {
  972         union {
  973                 uint32_t dw[4];
  974                 struct {
  975                 #ifdef _BIG_ENDIAN
  976                         /* dw 0 */
  977                         uint32_t domain:8;
  978                         uint32_t port_number:8;
  979                         uint32_t subsystem:8;
  980                         uint32_t opcode:8;
  981                         /* dw 1 */
  982                         uint32_t timeout;
  983                         /* dw 2 */
  984                         uint32_t request_length;
  985                         /* dw 3 */
  986                         uint32_t rsvd0:24;
  987                         uint32_t version:8;
  988                 #else
  989                         /* dw 0 */
  990                         uint32_t opcode:8;
  991                         uint32_t subsystem:8;
  992                         uint32_t port_number:8;
  993                         uint32_t domain:8;
  994                         /* dw 1 */
  995                         uint32_t timeout;
  996                         /* dw 2 */
  997                         uint32_t request_length;
  998                         /* dw 3 */
  999                         uint32_t version:8;
 1000                         uint32_t rsvd0:24;
 1001                 #endif
 1002                 } req;
 1003                 struct {
 1004                 #ifdef _BIG_ENDIAN
 1005                         /* dw 0 */
 1006                         uint32_t domain:8;
 1007                         uint32_t rsvd0:8;
 1008                         uint32_t subsystem:8;
 1009                         uint32_t opcode:8;
 1010                         /* dw 1 */
 1011                         uint32_t rsvd1:16;
 1012                         uint32_t additional_status:8;
 1013                         uint32_t status:8;
 1014                 #else
 1015                         /* dw 0 */
 1016                         uint32_t opcode:8;
 1017                         uint32_t subsystem:8;
 1018                         uint32_t rsvd0:8;
 1019                         uint32_t domain:8;
 1020                         /* dw 1 */
 1021                         uint32_t status:8;
 1022                         uint32_t additional_status:8;
 1023                         uint32_t rsvd1:16;
 1024                 #endif
 1025                         uint32_t rsp_length;
 1026                         uint32_t actual_rsp_length;
 1027                 } rsp;
 1028         } u0;
 1029 };
 1030 #define OCE_BMBX_RHDR_SZ 20
 1031 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
 1032 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
 1033 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
 1034 
 1035 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG_V1 */
 1036 struct mbx_query_common_link_config {
 1037         struct mbx_hdr hdr;
 1038         union {
 1039                 struct {
 1040                         uint32_t rsvd0;
 1041                 } req;
 1042 
 1043                 struct {
 1044                 #ifdef _BIG_ENDIAN
 1045                         uint32_t physical_port_fault:8;
 1046                         uint32_t physical_port_speed:8;
 1047                         uint32_t link_duplex:8;
 1048                         uint32_t pt:2;
 1049                         uint32_t port_number:6;
 1050 
 1051                         uint16_t qos_link_speed;
 1052                         uint16_t rsvd0;
 1053 
 1054                         uint32_t rsvd1:21;
 1055                         uint32_t phys_fcv:1;
 1056                         uint32_t phys_rxf:1;
 1057                         uint32_t phys_txf:1;
 1058                         uint32_t logical_link_status:8;
 1059                 #else
 1060                         uint32_t port_number:6;
 1061                         uint32_t pt:2;
 1062                         uint32_t link_duplex:8;
 1063                         uint32_t physical_port_speed:8;
 1064                         uint32_t physical_port_fault:8;
 1065 
 1066                         uint16_t rsvd0;
 1067                         uint16_t qos_link_speed;
 1068 
 1069                         uint32_t logical_link_status:8;
 1070                         uint32_t phys_txf:1;
 1071                         uint32_t phys_rxf:1;
 1072                         uint32_t phys_fcv:1;
 1073                         uint32_t rsvd1:21;
 1074                 #endif
 1075                 } rsp;
 1076         } params;
 1077 };
 1078 
 1079 /* [57] OPCODE_COMMON_SET_LINK_SPEED */
 1080 struct mbx_set_common_link_speed {
 1081         struct mbx_hdr hdr;
 1082         union {
 1083                 struct {
 1084 #ifdef _BIG_ENDIAN
 1085                         uint8_t rsvd0;
 1086                         uint8_t mac_speed;
 1087                         uint8_t virtual_port;
 1088                         uint8_t physical_port;
 1089 #else
 1090                         uint8_t physical_port;
 1091                         uint8_t virtual_port;
 1092                         uint8_t mac_speed;
 1093                         uint8_t rsvd0;
 1094 #endif
 1095                 } req;
 1096 
 1097                 struct {
 1098                         uint32_t rsvd0;
 1099                 } rsp;
 1100 
 1101                 uint32_t dw;
 1102         } params;
 1103 };
 1104 
 1105 struct mac_address_format {
 1106         uint16_t size_of_struct;
 1107         uint8_t mac_addr[6];
 1108 };
 1109 
 1110 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */
 1111 struct mbx_query_common_iface_mac {
 1112         struct mbx_hdr hdr;
 1113         union {
 1114                 struct {
 1115 #ifdef _BIG_ENDIAN
 1116                         uint16_t if_id;
 1117                         uint8_t permanent;
 1118                         uint8_t type;
 1119 #else
 1120                         uint8_t type;
 1121                         uint8_t permanent;
 1122                         uint16_t if_id;
 1123 #endif
 1124 
 1125                 } req;
 1126 
 1127                 struct {
 1128                         struct mac_address_format mac;
 1129                 } rsp;
 1130         } params;
 1131 };
 1132 
 1133 /* [02] OPCODE_COMMON_SET_IFACE_MAC */
 1134 struct mbx_set_common_iface_mac {
 1135         struct mbx_hdr hdr;
 1136         union {
 1137                 struct {
 1138 #ifdef _BIG_ENDIAN
 1139                         /* dw 0 */
 1140                         uint16_t if_id;
 1141                         uint8_t invalidate;
 1142                         uint8_t type;
 1143 #else
 1144                         /* dw 0 */
 1145                         uint8_t type;
 1146                         uint8_t invalidate;
 1147                         uint16_t if_id;
 1148 #endif
 1149                         /* dw 1 */
 1150                         struct mac_address_format mac;
 1151                 } req;
 1152 
 1153                 struct {
 1154                         uint32_t rsvd0;
 1155                 } rsp;
 1156 
 1157                 uint32_t dw[2];
 1158         } params;
 1159 };
 1160 
 1161 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */
 1162 struct mbx_set_common_iface_multicast {
 1163         struct mbx_hdr hdr;
 1164         union {
 1165                 struct {
 1166                         /* dw 0 */
 1167                         uint16_t num_mac;
 1168                         uint8_t promiscuous;
 1169                         uint8_t if_id;
 1170                         /* dw 1-48 */
 1171                         struct {
 1172                                 uint8_t byte[6];
 1173                         } mac[32];
 1174 
 1175                 } req;
 1176 
 1177                 struct {
 1178                         uint32_t rsvd0;
 1179                 } rsp;
 1180 
 1181                 uint32_t dw[49];
 1182         } params;
 1183 };
 1184 
 1185 struct qinq_vlan {
 1186 #ifdef _BIG_ENDIAN
 1187         uint16_t inner;
 1188         uint16_t outer;
 1189 #else
 1190         uint16_t outer;
 1191         uint16_t inner;
 1192 #endif
 1193 };
 1194 
 1195 struct normal_vlan {
 1196         uint16_t vtag;
 1197 };
 1198 
 1199 struct ntwk_if_vlan_tag {
 1200         union {
 1201                 struct normal_vlan normal;
 1202                 struct qinq_vlan qinq;
 1203         } u0;
 1204 };
 1205 
 1206 /* [50] OPCODE_COMMON_CREATE_IFACE */
 1207 struct mbx_create_common_iface {
 1208         struct mbx_hdr hdr;
 1209         union {
 1210                 struct {
 1211                         uint32_t version;
 1212                         uint32_t cap_flags;
 1213                         uint32_t enable_flags;
 1214                         uint8_t mac_addr[6];
 1215                         uint8_t rsvd0;
 1216                         uint8_t mac_invalid;
 1217                         struct ntwk_if_vlan_tag vlan_tag;
 1218                 } req;
 1219 
 1220                 struct {
 1221                         uint32_t if_id;
 1222                         uint32_t pmac_id;
 1223                 } rsp;
 1224                 uint32_t dw[4];
 1225         } params;
 1226 };
 1227 
 1228 /* [51] OPCODE_COMMON_DESTROY_IFACE */
 1229 struct mbx_destroy_common_iface {
 1230         struct mbx_hdr hdr;
 1231         union {
 1232                 struct {
 1233                         uint32_t if_id;
 1234                 } req;
 1235 
 1236                 struct {
 1237                         uint32_t rsvd0;
 1238                 } rsp;
 1239 
 1240                 uint32_t dw;
 1241         } params;
 1242 };
 1243 
 1244 /* event queue context structure */
 1245 struct oce_eq_ctx {
 1246 #ifdef _BIG_ENDIAN
 1247         uint32_t dw4rsvd1:16;
 1248         uint32_t num_pages:16;
 1249 
 1250         uint32_t size:1;
 1251         uint32_t dw5rsvd2:1;
 1252         uint32_t valid:1;
 1253         uint32_t dw5rsvd1:29;
 1254 
 1255         uint32_t armed:1;
 1256         uint32_t dw6rsvd2:2;
 1257         uint32_t count:3;
 1258         uint32_t dw6rsvd1:26;
 1259 
 1260         uint32_t dw7rsvd2:9;
 1261         uint32_t delay_mult:10;
 1262         uint32_t dw7rsvd1:13;
 1263 
 1264         uint32_t dw8rsvd1;
 1265 #else
 1266         uint32_t num_pages:16;
 1267         uint32_t dw4rsvd1:16;
 1268 
 1269         uint32_t dw5rsvd1:29;
 1270         uint32_t valid:1;
 1271         uint32_t dw5rsvd2:1;
 1272         uint32_t size:1;
 1273 
 1274         uint32_t dw6rsvd1:26;
 1275         uint32_t count:3;
 1276         uint32_t dw6rsvd2:2;
 1277         uint32_t armed:1;
 1278 
 1279         uint32_t dw7rsvd1:13;
 1280         uint32_t delay_mult:10;
 1281         uint32_t dw7rsvd2:9;
 1282 
 1283         uint32_t dw8rsvd1;
 1284 #endif
 1285 };
 1286 
 1287 /* [13] OPCODE_COMMON_CREATE_EQ */
 1288 struct mbx_create_common_eq {
 1289         struct mbx_hdr hdr;
 1290         union {
 1291                 struct {
 1292                         struct oce_eq_ctx ctx;
 1293                         struct phys_addr pages[8];
 1294                 } req;
 1295 
 1296                 struct {
 1297                         uint16_t eq_id;
 1298                         uint16_t rsvd0;
 1299                 } rsp;
 1300         } params;
 1301 };
 1302 
 1303 /* [55] OPCODE_COMMON_DESTROY_EQ */
 1304 struct mbx_destroy_common_eq {
 1305         struct mbx_hdr hdr;
 1306         union {
 1307                 struct {
 1308 #ifdef _BIG_ENDIAN
 1309                         uint16_t rsvd0;
 1310                         uint16_t id;
 1311 #else
 1312                         uint16_t id;
 1313                         uint16_t rsvd0;
 1314 #endif
 1315                 } req;
 1316 
 1317                 struct {
 1318                         uint32_t rsvd0;
 1319                 } rsp;
 1320         } params;
 1321 };
 1322 
 1323 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */
 1324 typedef union oce_cq_ctx_u {
 1325         uint32_t dw[5];
 1326         struct {
 1327         #ifdef _BIG_ENDIAN
 1328                 /* dw4 */
 1329                 uint32_t dw4rsvd1:16;
 1330                 uint32_t num_pages:16;
 1331                 /* dw5 */
 1332                 uint32_t eventable:1;
 1333                 uint32_t dw5rsvd3:1;
 1334                 uint32_t valid:1;
 1335                 uint32_t count:2;
 1336                 uint32_t dw5rsvd2:12;
 1337                 uint32_t nodelay:1;
 1338                 uint32_t coalesce_wm:2;
 1339                 uint32_t dw5rsvd1:12;
 1340                 /* dw6 */
 1341                 uint32_t armed:1;
 1342                 uint32_t dw6rsvd2:1;
 1343                 uint32_t eq_id:8;
 1344                 uint32_t dw6rsvd1:22;
 1345         #else
 1346                 /* dw4 */
 1347                 uint32_t num_pages:16;
 1348                 uint32_t dw4rsvd1:16;
 1349                 /* dw5 */
 1350                 uint32_t dw5rsvd1:12;
 1351                 uint32_t coalesce_wm:2;
 1352                 uint32_t nodelay:1;
 1353                 uint32_t dw5rsvd2:12;
 1354                 uint32_t count:2;
 1355                 uint32_t valid:1;
 1356                 uint32_t dw5rsvd3:1;
 1357                 uint32_t eventable:1;
 1358                 /* dw6 */
 1359                 uint32_t dw6rsvd1:22;
 1360                 uint32_t eq_id:8;
 1361                 uint32_t dw6rsvd2:1;
 1362                 uint32_t armed:1;
 1363         #endif
 1364                 /* dw7 */
 1365                 uint32_t dw7rsvd1;
 1366                 /* dw8 */
 1367                 uint32_t dw8rsvd1;
 1368         } v0;
 1369         struct {
 1370         #ifdef _BIG_ENDIAN
 1371                 /* dw4 */
 1372                 uint32_t dw4rsvd1:8;
 1373                 uint32_t page_size:8;
 1374                 uint32_t num_pages:16;
 1375                 /* dw5 */
 1376                 uint32_t eventable:1;
 1377                 uint32_t dw5rsvd3:1;
 1378                 uint32_t valid:1;
 1379                 uint32_t count:2;
 1380                 uint32_t dw5rsvd2:11;
 1381                 uint32_t autovalid:1;
 1382                 uint32_t nodelay:1;
 1383                 uint32_t coalesce_wm:2;
 1384                 uint32_t dw5rsvd1:12;
 1385                 /* dw6 */
 1386                 uint32_t armed:1;
 1387                 uint32_t dw6rsvd1:15;
 1388                 uint32_t eq_id:16;
 1389                 /* dw7 */
 1390                 uint32_t dw7rsvd1:16;
 1391                 uint32_t cqe_count:16;
 1392         #else
 1393                 /* dw4 */
 1394                 uint32_t num_pages:16;
 1395                 uint32_t page_size:8;
 1396                 uint32_t dw4rsvd1:8;
 1397                 /* dw5 */
 1398                 uint32_t dw5rsvd1:12;
 1399                 uint32_t coalesce_wm:2;
 1400                 uint32_t nodelay:1;
 1401                 uint32_t autovalid:1;
 1402                 uint32_t dw5rsvd2:11;
 1403                 uint32_t count:2;
 1404                 uint32_t valid:1;
 1405                 uint32_t dw5rsvd3:1;
 1406                 uint32_t eventable:1;
 1407                 /* dw6 */
 1408                 uint32_t eq_id:16;
 1409                 uint32_t dw6rsvd1:15;
 1410                 uint32_t armed:1;
 1411                 /* dw7 */
 1412                 uint32_t cqe_count:16;
 1413                 uint32_t dw7rsvd1:16;
 1414         #endif
 1415                 /* dw8 */
 1416                 uint32_t dw8rsvd1;
 1417         } v2;
 1418 } oce_cq_ctx_t;
 1419 
 1420 /* [12] OPCODE_COMMON_CREATE_CQ */
 1421 struct mbx_create_common_cq {
 1422         struct mbx_hdr hdr;
 1423         union {
 1424                 struct {
 1425                         oce_cq_ctx_t cq_ctx;
 1426                         struct phys_addr pages[4];
 1427                 } req;
 1428 
 1429                 struct {
 1430                         uint16_t cq_id;
 1431                         uint16_t rsvd0;
 1432                 } rsp;
 1433         } params;
 1434 };
 1435 
 1436 /* [54] OPCODE_COMMON_DESTROY_CQ */
 1437 struct mbx_destroy_common_cq {
 1438         struct mbx_hdr hdr;
 1439         union {
 1440                 struct {
 1441 #ifdef _BIG_ENDIAN
 1442                         uint16_t rsvd0;
 1443                         uint16_t id;
 1444 #else
 1445                         uint16_t id;
 1446                         uint16_t rsvd0;
 1447 #endif
 1448                 } req;
 1449 
 1450                 struct {
 1451                         uint32_t rsvd0;
 1452                 } rsp;
 1453         } params;
 1454 };
 1455 
 1456 typedef union oce_mq_ctx_u {
 1457         uint32_t dw[5];
 1458         struct {
 1459         #ifdef _BIG_ENDIAN
 1460                 /* dw4 */
 1461                 uint32_t dw4rsvd1:16;
 1462                 uint32_t num_pages:16;
 1463                 /* dw5 */
 1464                 uint32_t cq_id:10;
 1465                 uint32_t dw5rsvd2:2;
 1466                 uint32_t ring_size:4;
 1467                 uint32_t dw5rsvd1:16;
 1468                 /* dw6 */
 1469                 uint32_t valid:1;
 1470                 uint32_t dw6rsvd1:31;
 1471                 /* dw7 */
 1472                 uint32_t dw7rsvd1:21;
 1473                 uint32_t async_cq_id:10;
 1474                 uint32_t async_cq_valid:1;
 1475         #else
 1476                 /* dw4 */
 1477                 uint32_t num_pages:16;
 1478                 uint32_t dw4rsvd1:16;
 1479                 /* dw5 */
 1480                 uint32_t dw5rsvd1:16;
 1481                 uint32_t ring_size:4;
 1482                 uint32_t dw5rsvd2:2;
 1483                 uint32_t cq_id:10;
 1484                 /* dw6 */
 1485                 uint32_t dw6rsvd1:31;
 1486                 uint32_t valid:1;
 1487                 /* dw7 */
 1488                 uint32_t async_cq_valid:1;
 1489                 uint32_t async_cq_id:10;
 1490                 uint32_t dw7rsvd1:21;
 1491         #endif
 1492                 /* dw8 */
 1493                 uint32_t dw8rsvd1;
 1494         } v0;
 1495 } oce_mq_ctx_t;
 1496 
 1497 /**
 1498  * @brief [21] OPCODE_COMMON_CREATE_MQ
 1499  * A MQ must be at least 16 entries deep (corresponding to 1 page) and
 1500  * at most 128 entries deep (corresponding to 8 pages).
 1501  */
 1502 struct mbx_create_common_mq {
 1503         struct mbx_hdr hdr;
 1504         union {
 1505                 struct {
 1506                         oce_mq_ctx_t context;
 1507                         struct phys_addr pages[8];
 1508                 } req;
 1509 
 1510                 struct {
 1511                         uint32_t mq_id:16;
 1512                         uint32_t rsvd0:16;
 1513                 } rsp;
 1514         } params;
 1515 };
 1516 
 1517 struct mbx_create_common_mq_ex {
 1518         struct mbx_hdr hdr;
 1519         union {
 1520                 struct {
 1521                         oce_mq_ext_ctx_t context;
 1522                         struct phys_addr pages[8];
 1523                 } req;
 1524 
 1525                 struct {
 1526                         uint32_t mq_id:16;
 1527                         uint32_t rsvd0:16;
 1528                 } rsp;
 1529         } params;
 1530 };
 1531 
 1532 /* [53] OPCODE_COMMON_DESTROY_MQ */
 1533 struct mbx_destroy_common_mq {
 1534         struct mbx_hdr hdr;
 1535         union {
 1536                 struct {
 1537 #ifdef _BIG_ENDIAN
 1538                         uint16_t rsvd0;
 1539                         uint16_t id;
 1540 #else
 1541                         uint16_t id;
 1542                         uint16_t rsvd0;
 1543 #endif
 1544                 } req;
 1545 
 1546                 struct {
 1547                         uint32_t rsvd0;
 1548                 } rsp;
 1549         } params;
 1550 };
 1551 
 1552 /* [35] OPCODE_COMMON_GET_ FW_VERSION */
 1553 struct mbx_get_common_fw_version {
 1554         struct mbx_hdr hdr;
 1555         union {
 1556                 struct {
 1557                         uint32_t rsvd0;
 1558                 } req;
 1559 
 1560                 struct {
 1561                         uint8_t fw_ver_str[32];
 1562                         uint8_t fw_on_flash_ver_str[32];
 1563                 } rsp;
 1564         } params;
 1565 };
 1566 
 1567 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
 1568 struct mbx_common_cev_modify_msi_messages {
 1569         struct mbx_hdr hdr;
 1570         union {
 1571                 struct {
 1572                         uint32_t num_msi_msgs;
 1573                 } req;
 1574 
 1575                 struct {
 1576                         uint32_t rsvd0;
 1577                 } rsp;
 1578         } params;
 1579 };
 1580 
 1581 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */
 1582 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */
 1583 struct mbx_common_get_set_flow_control {
 1584         struct mbx_hdr hdr;
 1585 #ifdef _BIG_ENDIAN
 1586         uint16_t tx_flow_control;
 1587         uint16_t rx_flow_control;
 1588 #else
 1589         uint16_t rx_flow_control;
 1590         uint16_t tx_flow_control;
 1591 #endif
 1592 };
 1593 
 1594 enum e_flash_opcode {
 1595         MGMT_FLASHROM_OPCODE_FLASH = 1,
 1596         MGMT_FLASHROM_OPCODE_SAVE = 2
 1597 };
 1598 
 1599 /* [06] OPCODE_READ_COMMON_FLASHROM */
 1600 /* [07] OPCODE_WRITE_COMMON_FLASHROM */
 1601 
 1602 struct mbx_common_read_write_flashrom {
 1603         struct mbx_hdr hdr;
 1604         uint32_t flash_op_code;
 1605         uint32_t flash_op_type;
 1606         uint32_t data_buffer_size;
 1607         uint32_t data_offset;
 1608         uint8_t  data_buffer[32768];    /* + IMAGE_TRANSFER_SIZE */
 1609         uint8_t  rsvd[4];
 1610 };
 1611 
 1612 struct oce_phy_info {
 1613         uint16_t phy_type;
 1614         uint16_t interface_type;
 1615         uint32_t misc_params;
 1616         uint16_t ext_phy_details;
 1617         uint16_t rsvd;
 1618         uint16_t auto_speeds_supported;
 1619         uint16_t fixed_speeds_supported;
 1620         uint32_t future_use[2];
 1621 };
 1622 
 1623 struct mbx_common_phy_info {
 1624         struct mbx_hdr hdr;
 1625         union {
 1626                 struct {
 1627                         uint32_t rsvd0[4];
 1628                 } req;
 1629                 struct {
 1630                         struct oce_phy_info phy_info;
 1631                 } rsp;
 1632         } params;
 1633 };
 1634 
 1635 /*Lancer firmware*/
 1636 
 1637 struct mbx_lancer_common_write_object {
 1638         union {
 1639                 struct {
 1640                         struct   mbx_hdr hdr;
 1641                         uint32_t write_length: 24;
 1642                         uint32_t rsvd: 7;
 1643                         uint32_t eof: 1;
 1644                         uint32_t write_offset;
 1645                         uint8_t  object_name[104];
 1646                         uint32_t descriptor_count;
 1647                         uint32_t buffer_length;
 1648                         uint32_t address_lower;
 1649                         uint32_t address_upper;
 1650                 } req;
 1651                 struct {
 1652                         uint8_t  opcode;
 1653                         uint8_t  subsystem;
 1654                         uint8_t  rsvd1[2];
 1655                         uint8_t  status;
 1656                         uint8_t  additional_status;
 1657                         uint8_t  rsvd2[2];
 1658                         uint32_t response_length;
 1659                         uint32_t actual_response_length;
 1660                         uint32_t actual_write_length;
 1661                 } rsp;
 1662         } params;
 1663 };
 1664 
 1665 /**
 1666  * @brief MBX Common Quiery Firmaware Config
 1667  * This command retrieves firmware configuration parameters and adapter
 1668  * resources available to the driver originating the request. The firmware
 1669  * configuration defines supported protocols by the installed adapter firmware.
 1670  * This includes which ULP processors support the specified protocols and
 1671  * the number of TCP connections allowed for that protocol.
 1672  */
 1673 struct mbx_common_query_fw_config {
 1674         struct mbx_hdr hdr;
 1675         union {
 1676                 struct {
 1677                         uint32_t rsvd0[30];
 1678                 } req;
 1679 
 1680                 struct {
 1681                         uint32_t config_number;
 1682                         uint32_t asic_revision;
 1683                         uint32_t port_id;       /* used for stats retrieval */
 1684                         uint32_t function_mode;
 1685                         struct {
 1686                                 uint32_t ulp_mode;
 1687                                 uint32_t nic_wqid_base;
 1688                                 uint32_t nic_wq_tot;
 1689                                 uint32_t toe_wqid_base;
 1690                                 uint32_t toe_wq_tot;
 1691                                 uint32_t toe_rqid_base;
 1692                                 uint32_t toe_rqid_tot;
 1693                                 uint32_t toe_defrqid_base;
 1694                                 uint32_t toe_defrqid_count;
 1695                                 uint32_t lro_rqid_base;
 1696                                 uint32_t lro_rqid_tot;
 1697                                 uint32_t iscsi_icd_base;
 1698                                 uint32_t iscsi_icd_count;
 1699                         } ulp[2];
 1700                         uint32_t function_caps;
 1701                         uint32_t cqid_base;
 1702                         uint32_t cqid_tot;
 1703                         uint32_t eqid_base;
 1704                         uint32_t eqid_tot;
 1705                 } rsp;
 1706         } params;
 1707 };
 1708 
 1709 enum CQFW_CONFIG_NUMBER {
 1710         FCN_NIC_ISCSI_Initiator = 0x0,
 1711         FCN_ISCSI_Target = 0x3,
 1712         FCN_FCoE = 0x7, 
 1713         FCN_ISCSI_Initiator_Target = 0x9,
 1714         FCN_NIC_RDMA_TOE = 0xA,
 1715         FCN_NIC_RDMA_FCoE = 0xB,
 1716         FCN_NIC_RDMA_iSCSI = 0xC,
 1717         FCN_NIC_iSCSI_FCoE = 0xD 
 1718 };
 1719 
 1720 /**
 1721  * @brief Function Capabilites
 1722  * This field contains the flags indicating the capabilities of
 1723  * the SLI Host’s PCI function.
 1724  */
 1725 enum CQFW_FUNCTION_CAPABILITIES {
 1726         FNC_UNCLASSIFIED_STATS = 0x1,
 1727         FNC_RSS = 0x2,
 1728         FNC_PROMISCUOUS = 0x4,
 1729         FNC_LEGACY_MODE = 0x8,
 1730         FNC_HDS = 0x4000,
 1731         FNC_VMQ = 0x10000,
 1732         FNC_NETQ = 0x20000,
 1733         FNC_QGROUPS = 0x40000,
 1734         FNC_LRO = 0x100000,
 1735         FNC_VLAN_OFFLOAD = 0x800000
 1736 };
 1737 
 1738 enum CQFW_ULP_MODES_SUPPORTED {
 1739         ULP_TOE_MODE = 0x1,
 1740         ULP_NIC_MODE = 0x2,
 1741         ULP_RDMA_MODE = 0x4,
 1742         ULP_ISCSI_INI_MODE = 0x10,
 1743         ULP_ISCSI_TGT_MODE = 0x20,
 1744         ULP_FCOE_INI_MODE = 0x40,
 1745         ULP_FCOE_TGT_MODE = 0x80,
 1746         ULP_DAL_MODE = 0x100,
 1747         ULP_LRO_MODE = 0x200
 1748 };
 1749 
 1750 /**
 1751  * @brief Function Modes Supported
 1752  * Valid function modes (or protocol-types) supported on the SLI-Host’s
 1753  * PCIe function.  This field is a logical OR of the following values:
 1754  */
 1755 enum CQFW_FUNCTION_MODES_SUPPORTED {
 1756         FNM_TOE_MODE = 0x1,             /* TCP offload supported */
 1757         FNM_NIC_MODE = 0x2,             /* Raw Ethernet supported */
 1758         FNM_RDMA_MODE = 0x4,            /* RDMA protocol supported */
 1759         FNM_VM_MODE = 0x8,              /* Virtual Machines supported  */
 1760         FNM_ISCSI_INI_MODE = 0x10,      /* iSCSI initiator supported */
 1761         FNM_ISCSI_TGT_MODE = 0x20,      /* iSCSI target plus initiator */
 1762         FNM_FCOE_INI_MODE = 0x40,       /* FCoE Initiator supported */
 1763         FNM_FCOE_TGT_MODE = 0x80,       /* FCoE target supported */
 1764         FNM_DAL_MODE = 0x100,           /* DAL supported */
 1765         FNM_LRO_MODE = 0x200,           /* LRO supported */
 1766         FNM_FLEX10_MODE = 0x400,        /* QinQ, FLEX-10 or VNIC */
 1767         FNM_NCSI_MODE = 0x800,          /* NCSI supported */
 1768         FNM_IPV6_MODE = 0x1000,         /* IPV6 stack enabled */
 1769         FNM_BE2_COMPAT_MODE = 0x2000,   /* BE2 compatibility (BE3 disable)*/
 1770         FNM_INVALID_MODE = 0x8000,      /* Invalid */
 1771         FNM_BE3_COMPAT_MODE = 0x10000,  /* BE3 features */
 1772         FNM_VNIC_MODE = 0x20000,        /* Set when IBM vNIC mode is set */
 1773         FNM_VNTAG_MODE = 0x40000,       /* Set when VNTAG mode is set */
 1774         FNM_UMC_MODE = 0x1000000,       /* Set when UMC mode is set */
 1775         FNM_UMC_DEF_EN = 0x100000,      /* Set when UMC Default is set */
 1776         FNM_ONE_GB_EN = 0x200000,       /* Set when 1GB Default is set */
 1777         FNM_VNIC_DEF_VALID = 0x400000,  /* Set when VNIC_DEF_EN is valid */
 1778         FNM_VNIC_DEF_EN = 0x800000      /* Set when VNIC Default enabled */
 1779 };
 1780 
 1781 struct mbx_common_config_vlan {
 1782         struct mbx_hdr hdr;
 1783         union {
 1784                 struct {
 1785 #ifdef _BIG_ENDIAN
 1786                         uint8_t num_vlans;
 1787                         uint8_t untagged;
 1788                         uint8_t promisc;
 1789                         uint8_t if_id;
 1790 #else
 1791                         uint8_t if_id;
 1792                         uint8_t promisc;
 1793                         uint8_t untagged;
 1794                         uint8_t num_vlans;
 1795 #endif
 1796                         union {
 1797                                 struct normal_vlan normal_vlans[64];
 1798                                 struct qinq_vlan qinq_vlans[32];
 1799                         } tags;
 1800                 } req;
 1801 
 1802                 struct {
 1803                         uint32_t rsvd;
 1804                 } rsp;
 1805         } params;
 1806 };
 1807 
 1808 typedef struct iface_rx_filter_ctx {
 1809         uint32_t global_flags_mask;
 1810         uint32_t global_flags;
 1811         uint32_t iface_flags_mask;
 1812         uint32_t iface_flags;
 1813         uint32_t if_id;
 1814         #define IFACE_RX_NUM_MCAST_MAX          64
 1815         uint32_t num_mcast;
 1816         struct mbx_mcast_addr {
 1817                 uint8_t byte[6];
 1818         } mac[IFACE_RX_NUM_MCAST_MAX];
 1819 } iface_rx_filter_ctx_t;
 1820 
 1821 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */
 1822 struct mbx_set_common_iface_rx_filter {
 1823         struct mbx_hdr hdr;
 1824         union {
 1825                 iface_rx_filter_ctx_t req;
 1826                 iface_rx_filter_ctx_t rsp;
 1827         } params;
 1828 };
 1829 
 1830 struct be_set_eqd {
 1831         uint32_t eq_id;
 1832         uint32_t phase;
 1833         uint32_t dm;
 1834 };
 1835 
 1836 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */
 1837 struct mbx_modify_common_eq_delay {
 1838         struct mbx_hdr hdr;
 1839         union {
 1840                 struct {
 1841                         uint32_t num_eq;
 1842                         struct {
 1843                                 uint32_t eq_id;
 1844                                 uint32_t phase;
 1845                                 uint32_t dm;
 1846                         } delay[8];
 1847                 } req;
 1848 
 1849                 struct {
 1850                         uint32_t rsvd0;
 1851                 } rsp;
 1852         } params;
 1853 };
 1854 
 1855 /* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */
 1856 
 1857 struct mgmt_hba_attr {
 1858         int8_t   flashrom_ver_str[32];
 1859         int8_t   manufac_name[32];
 1860         uint32_t supp_modes;
 1861         int8_t   seeprom_ver_lo;
 1862         int8_t   seeprom_ver_hi;
 1863         int8_t   rsvd0[2];
 1864         uint32_t ioctl_data_struct_ver;
 1865         uint32_t ep_fw_data_struct_ver;
 1866         uint8_t  ncsi_ver_str[12];
 1867         uint32_t def_ext_to;
 1868         int8_t   cntl_mod_num[32];
 1869         int8_t   cntl_desc[64];
 1870         int8_t   cntl_ser_num[32];
 1871         int8_t   ip_ver_str[32];
 1872         int8_t   fw_ver_str[32];
 1873         int8_t   bios_ver_str[32];
 1874         int8_t   redboot_ver_str[32];
 1875         int8_t   drv_ver_str[32];
 1876         int8_t   fw_on_flash_ver_str[32];
 1877         uint32_t funcs_supp;
 1878         uint16_t max_cdblen;
 1879         uint8_t  asic_rev;
 1880         uint8_t  gen_guid[16];
 1881         uint8_t  hba_port_count;
 1882         uint16_t default_link_down_timeout;
 1883         uint8_t  iscsi_ver_min_max;
 1884         uint8_t  multifunc_dev;
 1885         uint8_t  cache_valid;
 1886         uint8_t  hba_status;
 1887         uint8_t  max_domains_supp;
 1888         uint8_t  phy_port;
 1889         uint32_t fw_post_status;
 1890         uint32_t hba_mtu[8];
 1891         uint8_t  iSCSI_feat;
 1892         uint8_t  asic_gen;
 1893         uint8_t  future_u8[2];
 1894         uint32_t future_u32[3];
 1895 };
 1896 
 1897 struct mgmt_cntl_attr {
 1898         struct    mgmt_hba_attr hba_attr;
 1899         uint16_t  pci_vendor_id;
 1900         uint16_t  pci_device_id;
 1901         uint16_t  pci_sub_vendor_id;
 1902         uint16_t  pci_sub_system_id;
 1903         uint8_t   pci_bus_num;
 1904         uint8_t   pci_dev_num;
 1905         uint8_t   pci_func_num;
 1906         uint8_t   interface_type;
 1907         uint64_t  unique_id;
 1908         uint8_t   netfilters;
 1909         uint8_t   rsvd0[3];
 1910         uint32_t  future_u32[4];
 1911 };
 1912 
 1913 struct mbx_common_get_cntl_attr {
 1914         struct mbx_hdr hdr;
 1915         union {
 1916                 struct {
 1917                         uint32_t rsvd0;
 1918                 } req;
 1919                 struct {
 1920                         struct mgmt_cntl_attr cntl_attr_info;
 1921                 } rsp;
 1922         } params;
 1923 };
 1924 
 1925 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */
 1926 struct mbx_add_common_iface_mac {
 1927         struct mbx_hdr hdr;
 1928         union {
 1929                 struct {
 1930                         uint32_t if_id;
 1931                         uint8_t mac_address[6];
 1932                         uint8_t rsvd0[2];
 1933                 } req;
 1934                 struct {
 1935                         uint32_t pmac_id;
 1936                 } rsp;
 1937         } params;
 1938 };
 1939 
 1940 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */
 1941 struct mbx_del_common_iface_mac {
 1942         struct mbx_hdr hdr;
 1943         union {
 1944                 struct {
 1945                         uint32_t if_id;
 1946                         uint32_t pmac_id;
 1947                 } req;
 1948                 struct {
 1949                         uint32_t rsvd0;
 1950                 } rsp;
 1951         } params;
 1952 };
 1953 
 1954 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
 1955 struct mbx_query_common_max_mbx_buffer_size {
 1956         struct mbx_hdr hdr;
 1957         struct {
 1958                 uint32_t max_ioctl_bufsz;
 1959         } rsp;
 1960 };
 1961 
 1962 /* [61] OPCODE_COMMON_FUNCTION_RESET */
 1963 struct ioctl_common_function_reset {
 1964         struct mbx_hdr hdr;
 1965 };
 1966 
 1967 /* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */
 1968 struct mbx_read_common_transrecv_data {
 1969         struct mbx_hdr hdr;
 1970         union {
 1971                 struct {
 1972                         uint32_t    page_num;
 1973                         uint32_t    port;
 1974                 } req;
 1975                 struct {
 1976                         uint32_t    page_num;
 1977                         uint32_t    port;
 1978                         uint32_t    page_data[32];
 1979                 } rsp;
 1980         } params;
 1981 
 1982 };
 1983 
 1984 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
 1985 struct mbx_common_func_link_cfg {
 1986         struct mbx_hdr hdr;
 1987         union {
 1988                 struct {
 1989                         uint32_t enable;
 1990                 } req;
 1991                 struct {
 1992                         uint32_t rsvd0;
 1993                 } rsp;
 1994         } params;
 1995 };
 1996 
 1997 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */
 1998 #define CAP_SW_TIMESTAMPS       2
 1999 #define CAP_BE3_NATIVE_ERX_API  4
 2000 
 2001 struct mbx_common_set_function_cap {
 2002         struct mbx_hdr hdr;
 2003         union {
 2004                 struct {
 2005                         uint32_t valid_capability_flags;
 2006                         uint32_t capability_flags;
 2007                         uint8_t  sbz[212];
 2008                 } req;
 2009                 struct {
 2010                         uint32_t valid_capability_flags;
 2011                         uint32_t capability_flags;
 2012                         uint8_t  sbz[212];
 2013                 } rsp;
 2014         } params;
 2015 };
 2016 struct mbx_lowlevel_test_loopback_mode {
 2017         struct mbx_hdr hdr;
 2018         union {
 2019                 struct {
 2020                         uint32_t loopback_type;
 2021                         uint32_t num_pkts;
 2022                         uint64_t pattern;
 2023                         uint32_t src_port;
 2024                         uint32_t dest_port;
 2025                         uint32_t pkt_size;
 2026                 }req;
 2027                 struct {
 2028                         uint32_t    status;
 2029                         uint32_t    num_txfer;
 2030                         uint32_t    num_rx;
 2031                         uint32_t    miscomp_off;
 2032                         uint32_t    ticks_compl;
 2033                 }rsp;
 2034         } params;
 2035 };
 2036 
 2037 struct mbx_lowlevel_set_loopback_mode {
 2038         struct mbx_hdr hdr;
 2039         union {
 2040                 struct {
 2041                         uint8_t src_port;
 2042                         uint8_t dest_port;
 2043                         uint8_t loopback_type;
 2044                         uint8_t loopback_state;
 2045                 } req;
 2046                 struct {
 2047                         uint8_t rsvd0[4];
 2048                 } rsp;
 2049         } params;
 2050 };
 2051 #define MAX_RESC_DESC                           256
 2052 #define RESC_DESC_SIZE                          88
 2053 #define ACTIVE_PROFILE                          2
 2054 #define NIC_RESC_DESC_TYPE_V0                   0x41
 2055 #define NIC_RESC_DESC_TYPE_V1                   0x51
 2056 /* OPCODE_COMMON_GET_FUNCTION_CONFIG */
 2057 struct mbx_common_get_func_config {
 2058         struct mbx_hdr hdr;
 2059         union {
 2060                 struct {
 2061                         uint8_t rsvd;
 2062                         uint8_t type;
 2063                         uint16_t rsvd1;
 2064                 } req;
 2065                 struct {
 2066                         uint32_t desc_count;
 2067                         uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE];
 2068                 } rsp;
 2069         } params;
 2070 };
 2071 
 2072 /* OPCODE_COMMON_GET_PROFILE_CONFIG */
 2073 
 2074 struct mbx_common_get_profile_config {
 2075         struct mbx_hdr hdr;
 2076         union {
 2077                 struct {
 2078                         uint8_t rsvd;
 2079                         uint8_t type;
 2080                         uint16_t rsvd1;
 2081                 } req;
 2082                 struct {
 2083                         uint32_t desc_count;
 2084                         uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE];
 2085                 } rsp;
 2086         } params;
 2087 };
 2088 
 2089 struct oce_nic_resc_desc {
 2090         uint8_t desc_type;
 2091         uint8_t desc_len;
 2092         uint8_t rsvd1;
 2093         uint8_t flags;
 2094         uint8_t vf_num;
 2095         uint8_t rsvd2;
 2096         uint8_t pf_num;
 2097         uint8_t rsvd3;
 2098         uint16_t unicast_mac_count;
 2099         uint8_t rsvd4[6];
 2100         uint16_t mcc_count;
 2101         uint16_t vlan_count;
 2102         uint16_t mcast_mac_count;
 2103         uint16_t txq_count;
 2104         uint16_t rq_count;
 2105         uint16_t rssq_count;
 2106         uint16_t lro_count;
 2107         uint16_t cq_count;
 2108         uint16_t toe_conn_count;
 2109         uint16_t eq_count;
 2110         uint32_t rsvd5;
 2111         uint32_t cap_flags;
 2112         uint8_t link_param;
 2113         uint8_t rsvd6[3];
 2114         uint32_t bw_min;
 2115         uint32_t bw_max;
 2116         uint8_t acpi_params;
 2117         uint8_t wol_param;
 2118         uint16_t rsvd7;
 2119         uint32_t rsvd8[7];
 2120 
 2121 };
 2122 
 2123 struct flash_file_hdr {
 2124         uint8_t  sign[52];
 2125         uint8_t  ufi_version[4];
 2126         uint32_t file_len;
 2127         uint32_t cksum;
 2128         uint32_t antidote;
 2129         uint32_t num_imgs;
 2130         uint8_t  build[24];
 2131         uint8_t  asic_type_rev;
 2132         uint8_t  rsvd[31];
 2133 };
 2134 
 2135 struct image_hdr {
 2136         uint32_t imageid;
 2137         uint32_t imageoffset;
 2138         uint32_t imagelength;
 2139         uint32_t image_checksum;
 2140         uint8_t  image_version[32];
 2141 };
 2142 
 2143 struct flash_section_hdr {
 2144         uint32_t format_rev;
 2145         uint32_t cksum;
 2146         uint32_t antidote;
 2147         uint32_t num_images;
 2148         uint8_t  id_string[128];
 2149         uint32_t rsvd[4];
 2150 };
 2151 
 2152 struct flash_section_entry {
 2153         uint32_t type;
 2154         uint32_t offset;
 2155         uint32_t pad_size;
 2156         uint32_t image_size;
 2157         uint32_t cksum;
 2158         uint32_t entry_point;
 2159         uint32_t rsvd0;
 2160         uint32_t rsvd1;
 2161         uint8_t  ver_data[32];
 2162 };
 2163 
 2164 struct flash_sec_info {
 2165         uint8_t cookie[32];
 2166         struct  flash_section_hdr fsec_hdr;
 2167         struct  flash_section_entry fsec_entry[32];
 2168 };
 2169 
 2170 enum LOWLEVEL_SUBSYSTEM_OPCODES {
 2171 /* Opcodes used for lowlevel functions common to many subystems.
 2172  * Some of these opcodes are used for diagnostic functions only.
 2173  * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code.
 2174  */
 2175         OPCODE_LOWLEVEL_TEST_LOOPBACK = 18,
 2176         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19,
 2177         OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20
 2178 };
 2179 
 2180 enum LLDP_SUBSYSTEM_OPCODES {
 2181 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */
 2182         OPCODE_LLDP_GET_CFG = 1,
 2183         OPCODE_LLDP_SET_CFG = 2,
 2184         OPCODE_LLDP_GET_STATS = 3
 2185 };
 2186 
 2187 enum DCBX_SUBSYSTEM_OPCODES {
 2188 /* Opcodes used for DCBX. */
 2189         OPCODE_DCBX_GET_CFG = 1,
 2190         OPCODE_DCBX_SET_CFG = 2,
 2191         OPCODE_DCBX_GET_MIB_INFO = 3,
 2192         OPCODE_DCBX_GET_DCBX_MODE = 4,
 2193         OPCODE_DCBX_SET_MODE = 5
 2194 };
 2195 
 2196 enum DMTF_SUBSYSTEM_OPCODES {
 2197 /* Opcodes used for DCBX subsystem. */
 2198         OPCODE_DMTF_EXEC_CLP_CMD = 1
 2199 };
 2200 
 2201 enum DIAG_SUBSYSTEM_OPCODES {
 2202 /* Opcodes used for diag functions common to many subsystems. */
 2203         OPCODE_DIAG_RUN_DMA_TEST = 1,
 2204         OPCODE_DIAG_RUN_MDIO_TEST = 2,
 2205         OPCODE_DIAG_RUN_NLB_TEST = 3,
 2206         OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4,
 2207         OPCODE_DIAG_GET_MAC = 5
 2208 };
 2209 
 2210 enum VENDOR_SUBSYSTEM_OPCODES {
 2211 /* Opcodes used for Vendor subsystem. */
 2212         OPCODE_VENDOR_SLI = 1
 2213 };
 2214 
 2215 /* Management Status Codes */
 2216 enum MGMT_STATUS_SUCCESS {
 2217         MGMT_SUCCESS = 0,
 2218         MGMT_FAILED = 1,
 2219         MGMT_ILLEGAL_REQUEST = 2,
 2220         MGMT_ILLEGAL_FIELD = 3,
 2221         MGMT_INSUFFICIENT_BUFFER = 4,
 2222         MGMT_UNAUTHORIZED_REQUEST = 5,
 2223         MGMT_INVALID_ISNS_ADDRESS = 10,
 2224         MGMT_INVALID_IPADDR = 11,
 2225         MGMT_INVALID_GATEWAY = 12,
 2226         MGMT_INVALID_SUBNETMASK = 13,
 2227         MGMT_INVALID_TARGET_IPADDR = 16,
 2228         MGMT_TGTTBL_FULL = 20,
 2229         MGMT_FLASHROM_SAVE_FAILED = 23,
 2230         MGMT_IOCTLHANDLE_ALLOC_FAILED = 27,
 2231         MGMT_INVALID_SESSION = 31,
 2232         MGMT_INVALID_CONNECTION = 32,
 2233         MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33,
 2234         MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34,
 2235         MGMT_BTL_PATH_TGTID_OCCUPIED = 35,
 2236         MGMT_BTL_NO_FREE_SLOT_PATH = 36,
 2237         MGMT_BTL_NO_FREE_SLOT_TGTID = 37,
 2238         MGMT_POLL_IOCTL_TIMEOUT = 40,
 2239         MGMT_ERROR_ACITISCSI = 41,
 2240         MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43,
 2241         MGMT_REBOOT_REQUIRED = 44,
 2242         MGMT_INSUFFICIENT_TIMEOUT = 45,
 2243         MGMT_IPADDR_NOT_SET = 46,
 2244         MGMT_IPADDR_DUP_DETECTED = 47,
 2245         MGMT_CANT_REMOVE_LAST_CONNECTION = 48,
 2246         MGMT_TARGET_BUSY = 49,
 2247         MGMT_TGT_ERR_LISTEN_SOCKET = 50,
 2248         MGMT_TGT_ERR_BIND_SOCKET = 51,
 2249         MGMT_TGT_ERR_NO_SOCKET = 52,
 2250         MGMT_TGT_ERR_ISNS_COMM_FAILED = 55,
 2251         MGMT_CANNOT_DELETE_BOOT_TARGET = 56,
 2252         MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57,
 2253         MGMT_FCF_IN_USE = 58 ,
 2254         MGMT_NO_CQE = 59,
 2255         MGMT_TARGET_NOT_FOUND = 65,
 2256         MGMT_NOT_SUPPORTED = 66,
 2257         MGMT_NO_FCF_RECORDS = 67,
 2258         MGMT_FEATURE_NOT_SUPPORTED = 68,
 2259         MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69,
 2260         MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70,
 2261         MGMT_INVALID_NON_EMBEDDED_WRB = 71,
 2262         MGMT_OOR = 100,
 2263         MGMT_INVALID_PD = 101,
 2264         MGMT_STATUS_PD_INUSE = 102,
 2265         MGMT_INVALID_CQ = 103,
 2266         MGMT_INVALID_QP = 104,
 2267         MGMT_INVALID_STAG = 105,
 2268         MGMT_ORD_EXCEEDS = 106,
 2269         MGMT_IRD_EXCEEDS = 107,
 2270         MGMT_SENDQ_WQE_EXCEEDS = 108,
 2271         MGMT_RECVQ_RQE_EXCEEDS = 109,
 2272         MGMT_SGE_SEND_EXCEEDS = 110,
 2273         MGMT_SGE_WRITE_EXCEEDS = 111,
 2274         MGMT_SGE_RECV_EXCEEDS = 112,
 2275         MGMT_INVALID_STATE_CHANGE = 113,
 2276         MGMT_MW_BOUND = 114,
 2277         MGMT_INVALID_VA = 115,
 2278         MGMT_INVALID_LENGTH = 116,
 2279         MGMT_INVALID_FBO = 117,
 2280         MGMT_INVALID_ACC_RIGHTS = 118,
 2281         MGMT_INVALID_PBE_SIZE = 119,
 2282         MGMT_INVALID_PBL_ENTRY = 120,
 2283         MGMT_INVALID_PBL_OFFSET = 121,
 2284         MGMT_ADDR_NON_EXIST = 122,
 2285         MGMT_INVALID_VLANID = 123,
 2286         MGMT_INVALID_MTU = 124,
 2287         MGMT_INVALID_BACKLOG = 125,
 2288         MGMT_CONNECTION_INPROGRESS = 126,
 2289         MGMT_INVALID_RQE_SIZE = 127,
 2290         MGMT_INVALID_RQE_ENTRY = 128
 2291 };
 2292 
 2293 /* Additional Management Status Codes */
 2294 enum MGMT_ADDI_STATUS {
 2295         MGMT_ADDI_NO_STATUS = 0,
 2296         MGMT_ADDI_INVALID_IPTYPE = 1,
 2297         MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9,
 2298         MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10,
 2299         MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11,
 2300         MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16,
 2301         MGMT_ADDI_SESSION_ALREADY_OPENED = 17,
 2302         MGMT_ADDI_SESSION_ALREADY_CLOSED = 18,
 2303         MGMT_ADDI_DEST_HOST_UNREACHABLE = 19,
 2304         MGMT_ADDI_LOGIN_IN_PROGRESS = 20,
 2305         MGMT_ADDI_TCP_CONNECT_FAILED = 21,
 2306         MGMT_ADDI_INSUFFICIENT_RESOURCES = 22,
 2307         MGMT_ADDI_LINK_DOWN = 23,
 2308         MGMT_ADDI_DHCP_ERROR = 24,
 2309         MGMT_ADDI_CONNECTION_OFFLOADED = 25,
 2310         MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26,
 2311         MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27,
 2312         MGMT_ADDI_REQUEST_REJECTED = 28,
 2313         MGMT_ADDI_INVALID_SUBSYSTEM = 29,
 2314         MGMT_ADDI_INVALID_OPCODE = 30,
 2315         MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31,
 2316         MGMT_ADDI_INVALID_KEY = 32,
 2317         MGMT_ADDI_INVALID_DOMAIN = 35,
 2318         MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43,
 2319         MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44,
 2320         MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45,
 2321         MGMT_ADDI_LOGIN_NOT_FOUND = 46,
 2322         MGMT_ADDI_LOGIN_TARGET_REMOVED = 47,
 2323         MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48,
 2324         MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49,
 2325         MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50,
 2326         MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51,
 2327         MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52,
 2328         MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53,
 2329         MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54,
 2330         MGMT_ADDI_LOGIN_TARGET_ERROR = 55,
 2331         MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56,
 2332         MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57,
 2333         MGMT_ADDI_SAME_CHAP_SECRET = 58,
 2334         MGMT_ADDI_INVALID_SECRET_LENGTH = 59,
 2335         MGMT_ADDI_DUPLICATE_ENTRY = 60,
 2336         MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63,
 2337         MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64,
 2338         MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65,
 2339         MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66,
 2340         MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67,
 2341         MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68,
 2342         MGMT_ADDI_INVALID_VLAN_RANGE = 69,
 2343         MGMT_ADDI_ERR_SET_VLAN = 70,
 2344         MGMT_ADDI_ERR_DEL_VLAN = 71,
 2345         MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72,
 2346         MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73,
 2347         MGMT_ADDI_TOO_MANY_INTERFACES = 74,
 2348         MGMT_ADDI_INVALID_REQUEST = 75
 2349 };
 2350 
 2351 enum NIC_SUBSYSTEM_OPCODES {
 2352 /**
 2353  * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2)
 2354  * These opcodes are used for configuring the Ethernet interfaces.
 2355  * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code.
 2356  */
 2357         NIC_CONFIG_RSS = 1,
 2358         NIC_CONFIG_ACPI = 2,
 2359         NIC_CONFIG_PROMISCUOUS = 3,
 2360         NIC_GET_STATS = 4,
 2361         NIC_CREATE_WQ = 7,
 2362         NIC_CREATE_RQ = 8,
 2363         NIC_DELETE_WQ = 9,
 2364         NIC_DELETE_RQ = 10,
 2365         NIC_CONFIG_ACPI_WOL_MAGIC = 12,
 2366         NIC_GET_NETWORK_STATS = 13,
 2367         NIC_CREATE_HDS_RQ = 16,
 2368         NIC_DELETE_HDS_RQ = 17,
 2369         NIC_GET_PPORT_STATS = 18,
 2370         NIC_GET_VPORT_STATS = 19,
 2371         NIC_GET_QUEUE_STATS = 20
 2372 };
 2373 
 2374 /* Hash option flags for RSS enable */
 2375 enum RSS_ENABLE_FLAGS {
 2376         RSS_ENABLE_NONE         = 0x0,  /* (No RSS) */
 2377         RSS_ENABLE_IPV4         = 0x1,  /* (IPV4 HASH enabled ) */
 2378         RSS_ENABLE_TCP_IPV4     = 0x2,  /* (TCP IPV4 Hash enabled) */
 2379         RSS_ENABLE_IPV6         = 0x4,  /* (IPV6 HASH enabled) */
 2380         RSS_ENABLE_TCP_IPV6     = 0x8,  /* (TCP IPV6 HASH */
 2381         RSS_ENABLE_UDP_IPV4     = 0x10, /* UDP IPV4 HASH */
 2382         RSS_ENABLE_UDP_IPV6     = 0x20  /* UDP IPV6 HASH */
 2383 };
 2384 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4)
 2385 #define RSS_DISABLE RSS_ENABLE_NONE
 2386 
 2387 /* NIC header WQE */
 2388 struct oce_nic_hdr_wqe {
 2389         union {
 2390                 struct {
 2391 #ifdef _BIG_ENDIAN
 2392                         /* dw0 */
 2393                         uint32_t rsvd0;
 2394 
 2395                         /* dw1 */
 2396                         uint32_t last_seg_udp_len:14;
 2397                         uint32_t rsvd1:18;
 2398 
 2399                         /* dw2 */
 2400                         uint32_t lso_mss:14;
 2401                         uint32_t num_wqe:5;
 2402                         uint32_t rsvd4:2;
 2403                         uint32_t vlan:1;
 2404                         uint32_t lso:1;
 2405                         uint32_t tcpcs:1;
 2406                         uint32_t udpcs:1;
 2407                         uint32_t ipcs:1;
 2408                         uint32_t mgmt:1;
 2409                         uint32_t lso6:1;
 2410                         uint32_t forward:1;
 2411                         uint32_t crc:1;
 2412                         uint32_t event:1;
 2413                         uint32_t complete:1;
 2414 
 2415                         /* dw3 */
 2416                         uint32_t vlan_tag:16;
 2417                         uint32_t total_length:16;
 2418 #else
 2419                         /* dw0 */
 2420                         uint32_t rsvd0;
 2421 
 2422                         /* dw1 */
 2423                         uint32_t rsvd1:18;
 2424                         uint32_t last_seg_udp_len:14;
 2425 
 2426                         /* dw2 */
 2427                         uint32_t complete:1;
 2428                         uint32_t event:1;
 2429                         uint32_t crc:1;
 2430                         uint32_t forward:1;
 2431                         uint32_t lso6:1;
 2432                         uint32_t mgmt:1;
 2433                         uint32_t ipcs:1;
 2434                         uint32_t udpcs:1;
 2435                         uint32_t tcpcs:1;
 2436                         uint32_t lso:1;
 2437                         uint32_t vlan:1;
 2438                         uint32_t rsvd4:2;
 2439                         uint32_t num_wqe:5;
 2440                         uint32_t lso_mss:14;
 2441 
 2442                         /* dw3 */
 2443                         uint32_t total_length:16;
 2444                         uint32_t vlan_tag:16;
 2445 #endif
 2446                 } s;
 2447                 uint32_t dw[4];
 2448         } u0;
 2449 };
 2450 
 2451 /* NIC fragment WQE */
 2452 struct oce_nic_frag_wqe {
 2453         union {
 2454                 struct {
 2455                         /* dw0 */
 2456                         uint32_t frag_pa_hi;
 2457                         /* dw1 */
 2458                         uint32_t frag_pa_lo;
 2459                         /* dw2 */
 2460                         uint32_t rsvd0;
 2461                         uint32_t frag_len;
 2462                 } s;
 2463                 uint32_t dw[4];
 2464         } u0;
 2465 };
 2466 
 2467 /* Ethernet Tx Completion Descriptor */
 2468 struct oce_nic_tx_cqe {
 2469         union {
 2470                 struct {
 2471 #ifdef _BIG_ENDIAN
 2472                         /* dw 0 */
 2473                         uint32_t status:4;
 2474                         uint32_t rsvd0:8;
 2475                         uint32_t port:2;
 2476                         uint32_t ct:2;
 2477                         uint32_t wqe_index:16;
 2478 
 2479                         /* dw 1 */
 2480                         uint32_t rsvd1:5;
 2481                         uint32_t cast_enc:2;
 2482                         uint32_t lso:1;
 2483                         uint32_t nwh_bytes:8;
 2484                         uint32_t user_bytes:16;
 2485 
 2486                         /* dw 2 */
 2487                         uint32_t rsvd2;
 2488 
 2489                         /* dw 3 */
 2490                         uint32_t valid:1;
 2491                         uint32_t rsvd3:4;
 2492                         uint32_t wq_id:11;
 2493                         uint32_t num_pkts:16;
 2494 #else
 2495                         /* dw 0 */
 2496                         uint32_t wqe_index:16;
 2497                         uint32_t ct:2;
 2498                         uint32_t port:2;
 2499                         uint32_t rsvd0:8;
 2500                         uint32_t status:4;
 2501 
 2502                         /* dw 1 */
 2503                         uint32_t user_bytes:16;
 2504                         uint32_t nwh_bytes:8;
 2505                         uint32_t lso:1;
 2506                         uint32_t cast_enc:2;
 2507                         uint32_t rsvd1:5;
 2508                         /* dw 2 */
 2509                         uint32_t rsvd2;
 2510 
 2511                         /* dw 3 */
 2512                         uint32_t num_pkts:16;
 2513                         uint32_t wq_id:11;
 2514                         uint32_t rsvd3:4;
 2515                         uint32_t valid:1;
 2516 #endif
 2517                 } s;
 2518                 uint32_t dw[4];
 2519         } u0;
 2520 };
 2521 #define WQ_CQE_VALID(_cqe)  (_cqe->u0.dw[3])
 2522 #define WQ_CQE_INVALIDATE(_cqe)  (_cqe->u0.dw[3] = 0)
 2523 
 2524 /* Receive Queue Entry (RQE) */
 2525 struct oce_nic_rqe {
 2526         union {
 2527                 struct {
 2528                         uint32_t frag_pa_hi;
 2529                         uint32_t frag_pa_lo;
 2530                 } s;
 2531                 uint32_t dw[2];
 2532         } u0;
 2533 };
 2534 
 2535 /* NIC Receive CQE */
 2536 struct oce_nic_rx_cqe {
 2537         union {
 2538                 struct {
 2539 #ifdef _BIG_ENDIAN
 2540                         /* dw 0 */
 2541                         uint32_t ip_options:1;
 2542                         uint32_t port:1;
 2543                         uint32_t pkt_size:14;
 2544                         uint32_t vlan_tag:16;
 2545 
 2546                         /* dw 1 */
 2547                         uint32_t num_fragments:3;
 2548                         uint32_t switched:1;
 2549                         uint32_t ct:2;
 2550                         uint32_t frag_index:10;
 2551                         uint32_t rsvd0:1;
 2552                         uint32_t vlan_tag_present:1;
 2553                         uint32_t mac_dst:6;
 2554                         uint32_t ip_ver:1;
 2555                         uint32_t l4_cksum_pass:1;
 2556                         uint32_t ip_cksum_pass:1;
 2557                         uint32_t udpframe:1;
 2558                         uint32_t tcpframe:1;
 2559                         uint32_t ipframe:1;
 2560                         uint32_t rss_hp:1;
 2561                         uint32_t error:1;
 2562 
 2563                         /* dw 2 */
 2564                         uint32_t valid:1;
 2565                         uint32_t hds_type:2;
 2566                         uint32_t lro_pkt:1;
 2567                         uint32_t rsvd4:1;
 2568                         uint32_t hds_hdr_size:12;
 2569                         uint32_t hds_hdr_frag_index:10;
 2570                         uint32_t rss_bank:1;
 2571                         uint32_t qnq:1;
 2572                         uint32_t pkt_type:2;
 2573                         uint32_t rss_flush:1;
 2574 
 2575                         /* dw 3 */
 2576                         uint32_t rss_hash_value;
 2577 #else
 2578                         /* dw 0 */
 2579                         uint32_t vlan_tag:16;
 2580                         uint32_t pkt_size:14;
 2581                         uint32_t port:1;
 2582                         uint32_t ip_options:1;
 2583                         /* dw 1 */
 2584                         uint32_t error:1;
 2585                         uint32_t rss_hp:1;
 2586                         uint32_t ipframe:1;
 2587                         uint32_t tcpframe:1;
 2588                         uint32_t udpframe:1;
 2589                         uint32_t ip_cksum_pass:1;
 2590                         uint32_t l4_cksum_pass:1;
 2591                         uint32_t ip_ver:1;
 2592                         uint32_t mac_dst:6;
 2593                         uint32_t vlan_tag_present:1;
 2594                         uint32_t rsvd0:1;
 2595                         uint32_t frag_index:10;
 2596                         uint32_t ct:2;
 2597                         uint32_t switched:1;
 2598                         uint32_t num_fragments:3;
 2599 
 2600                         /* dw 2 */
 2601                         uint32_t rss_flush:1;
 2602                         uint32_t pkt_type:2;
 2603                         uint32_t qnq:1;
 2604                         uint32_t rss_bank:1;
 2605                         uint32_t hds_hdr_frag_index:10;
 2606                         uint32_t hds_hdr_size:12;
 2607                         uint32_t rsvd4:1;
 2608                         uint32_t lro_pkt:1;
 2609                         uint32_t hds_type:2;
 2610                         uint32_t valid:1;
 2611                         /* dw 3 */
 2612                         uint32_t rss_hash_value;
 2613 #endif
 2614                 } s;
 2615                 uint32_t dw[4];
 2616         } u0;
 2617 };
 2618 /* NIC Receive CQE_v1 */
 2619 struct oce_nic_rx_cqe_v1 {
 2620         union {
 2621                 struct {
 2622 #ifdef _BIG_ENDIAN
 2623                         /* dw 0 */
 2624                         uint32_t ip_options:1;
 2625                         uint32_t vlan_tag_present:1;
 2626                         uint32_t pkt_size:14;
 2627                         uint32_t vlan_tag:16;
 2628 
 2629                         /* dw 1 */
 2630                         uint32_t num_fragments:3;
 2631                         uint32_t switched:1;
 2632                         uint32_t ct:2;
 2633                         uint32_t frag_index:10;
 2634                         uint32_t rsvd0:1;
 2635                         uint32_t mac_dst:7;
 2636                         uint32_t ip_ver:1;
 2637                         uint32_t l4_cksum_pass:1;
 2638                         uint32_t ip_cksum_pass:1;
 2639                         uint32_t udpframe:1;
 2640                         uint32_t tcpframe:1;
 2641                         uint32_t ipframe:1;
 2642                         uint32_t rss_hp:1;
 2643                         uint32_t error:1;
 2644 
 2645                         /* dw 2 */
 2646                         uint32_t valid:1;
 2647                         uint32_t rsvd4:13;
 2648                         uint32_t hds_hdr_size:
 2649                         uint32_t hds_hdr_frag_index:8;
 2650                         uint32_t vlantag:1;
 2651                         uint32_t port:2;
 2652                         uint32_t rss_bank:1;
 2653                         uint32_t qnq:1;
 2654                         uint32_t pkt_type:2;
 2655                         uint32_t rss_flush:1;
 2656 
 2657                         /* dw 3 */
 2658                         uint32_t rss_hash_value;
 2659         #else
 2660                         /* dw 0 */
 2661                         uint32_t vlan_tag:16;
 2662                         uint32_t pkt_size:14;
 2663                         uint32_t vlan_tag_present:1;
 2664                         uint32_t ip_options:1;
 2665                         /* dw 1 */
 2666                         uint32_t error:1;
 2667                         uint32_t rss_hp:1;
 2668                         uint32_t ipframe:1;
 2669                         uint32_t tcpframe:1;
 2670                         uint32_t udpframe:1;
 2671                         uint32_t ip_cksum_pass:1;
 2672                         uint32_t l4_cksum_pass:1;
 2673                         uint32_t ip_ver:1;
 2674                         uint32_t mac_dst:7;
 2675                         uint32_t rsvd0:1;
 2676                         uint32_t frag_index:10;
 2677                         uint32_t ct:2;
 2678                         uint32_t switched:1;
 2679                         uint32_t num_fragments:3;
 2680 
 2681                         /* dw 2 */
 2682                         uint32_t rss_flush:1;
 2683                         uint32_t pkt_type:2;
 2684                         uint32_t qnq:1;
 2685                         uint32_t rss_bank:1;
 2686                         uint32_t port:2;
 2687                         uint32_t vlantag:1;
 2688                         uint32_t hds_hdr_frag_index:8;
 2689                         uint32_t hds_hdr_size:2;
 2690                         uint32_t rsvd4:13;
 2691                         uint32_t valid:1;
 2692                         /* dw 3 */
 2693                         uint32_t rss_hash_value;
 2694 #endif
 2695                 } s;
 2696                 uint32_t dw[4];
 2697         } u0;
 2698 };
 2699 
 2700 #define RQ_CQE_VALID_MASK  0x80
 2701 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2])
 2702 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0)
 2703 
 2704 struct mbx_config_nic_promiscuous {
 2705         struct mbx_hdr hdr;
 2706         union {
 2707                 struct {
 2708 #ifdef _BIG_ENDIAN
 2709                         uint16_t rsvd0;
 2710                         uint8_t port1_promisc;
 2711                         uint8_t port0_promisc;
 2712 #else
 2713                         uint8_t port0_promisc;
 2714                         uint8_t port1_promisc;
 2715                         uint16_t rsvd0;
 2716 #endif
 2717                 } req;
 2718 
 2719                 struct {
 2720                         uint32_t rsvd0;
 2721                 } rsp;
 2722         } params;
 2723 };
 2724 
 2725 typedef union oce_wq_ctx_u {
 2726                 uint32_t dw[17];
 2727                 struct {
 2728 #ifdef _BIG_ENDIAN
 2729                         /* dw4 */
 2730                         uint32_t dw4rsvd2:8;
 2731                         uint32_t nic_wq_type:8;
 2732                         uint32_t dw4rsvd1:8;
 2733                         uint32_t num_pages:8;
 2734                         /* dw5 */
 2735                         uint32_t dw5rsvd2:12;
 2736                         uint32_t wq_size:4;
 2737                         uint32_t dw5rsvd1:16;
 2738                         /* dw6 */
 2739                         uint32_t valid:1;
 2740                         uint32_t dw6rsvd1:31;
 2741                         /* dw7 */
 2742                         uint32_t dw7rsvd1:16;
 2743                         uint32_t cq_id:16;
 2744 #else
 2745                         /* dw4 */
 2746                         uint32_t num_pages:8;
 2747 #if 0
 2748                         uint32_t dw4rsvd1:8;
 2749 #else
 2750 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */ 
 2751                         uint32_t ulp_mask:8;
 2752 #endif
 2753                         uint32_t nic_wq_type:8;
 2754                         uint32_t dw4rsvd2:8;
 2755                         /* dw5 */
 2756                         uint32_t dw5rsvd1:16;
 2757                         uint32_t wq_size:4;
 2758                         uint32_t dw5rsvd2:12;
 2759                         /* dw6 */
 2760                         uint32_t dw6rsvd1:31;
 2761                         uint32_t valid:1;
 2762                         /* dw7 */
 2763                         uint32_t cq_id:16;
 2764                         uint32_t dw7rsvd1:16;
 2765 #endif
 2766                         /* dw8 - dw20 */
 2767                         uint32_t dw8_20rsvd1[13];
 2768                 } v0;
 2769                 struct {
 2770 #ifdef _BIG_ENDIAN
 2771                         /* dw4 */
 2772                         uint32_t dw4rsvd2:8;
 2773                         uint32_t nic_wq_type:8;
 2774                         uint32_t dw4rsvd1:8;
 2775                         uint32_t num_pages:8;
 2776                         /* dw5 */
 2777                         uint32_t dw5rsvd2:12;
 2778                         uint32_t wq_size:4;
 2779                         uint32_t iface_id:16;
 2780                         /* dw6 */
 2781                         uint32_t valid:1;
 2782                         uint32_t dw6rsvd1:31;
 2783                         /* dw7 */
 2784                         uint32_t dw7rsvd1:16;
 2785                         uint32_t cq_id:16;
 2786 #else
 2787                         /* dw4 */
 2788                         uint32_t num_pages:8;
 2789                         uint32_t dw4rsvd1:8;
 2790                         uint32_t nic_wq_type:8;
 2791                         uint32_t dw4rsvd2:8;
 2792                         /* dw5 */
 2793                         uint32_t iface_id:16;
 2794                         uint32_t wq_size:4;
 2795                         uint32_t dw5rsvd2:12;
 2796                         /* dw6 */
 2797                         uint32_t dw6rsvd1:31;
 2798                         uint32_t valid:1;
 2799                         /* dw7 */
 2800                         uint32_t cq_id:16;
 2801                         uint32_t dw7rsvd1:16;
 2802 #endif
 2803                         /* dw8 - dw20 */
 2804                         uint32_t dw8_20rsvd1[13];
 2805                 } v1;
 2806 } oce_wq_ctx_t;
 2807 
 2808 /**
 2809  * @brief [07] NIC_CREATE_WQ
 2810  * @note
 2811  * Lancer requires an InterfaceID to be specified with every WQ. This
 2812  * is the basis for NIC IOV where the Interface maps to a vPort and maps
 2813  * to both Tx and Rx sides.
 2814  */
 2815 #define OCE_WQ_TYPE_FORWARDING  0x1     /* wq forwards pkts to TOE */
 2816 #define OCE_WQ_TYPE_STANDARD    0x2     /* wq sends network pkts */
 2817 struct mbx_create_nic_wq {
 2818         struct mbx_hdr hdr;
 2819         union {
 2820                 struct {
 2821                         uint8_t num_pages;
 2822                         uint8_t ulp_num;
 2823                         uint16_t nic_wq_type;
 2824                         uint16_t if_id;
 2825                         uint8_t wq_size;
 2826                         uint8_t rsvd1;
 2827                         uint32_t rsvd2;
 2828                         uint16_t cq_id;
 2829                         uint16_t rsvd3;
 2830                         uint32_t rsvd4[13];
 2831                         struct phys_addr pages[8];
 2832 
 2833                 } req;
 2834 
 2835                 struct {
 2836                         uint16_t wq_id;
 2837                         uint16_t rid;
 2838                         uint32_t db_offset;
 2839                         uint8_t tc_id;
 2840                         uint8_t rsvd0[3];
 2841                 } rsp;
 2842         } params;
 2843 };
 2844 
 2845 /* [09] NIC_DELETE_WQ */
 2846 struct mbx_delete_nic_wq {
 2847         /* dw0 - dw3 */
 2848         struct mbx_hdr hdr;
 2849         union {
 2850                 struct {
 2851 #ifdef _BIG_ENDIAN
 2852                         /* dw4 */
 2853                         uint16_t rsvd0;
 2854                         uint16_t wq_id;
 2855 #else
 2856                         /* dw4 */
 2857                         uint16_t wq_id;
 2858                         uint16_t rsvd0;
 2859 #endif
 2860                 } req;
 2861                 struct {
 2862                         uint32_t rsvd0;
 2863                 } rsp;
 2864         } params;
 2865 };
 2866 
 2867 struct mbx_create_nic_rq {
 2868         struct mbx_hdr hdr;
 2869         union {
 2870                 struct {
 2871                         uint16_t cq_id;
 2872                         uint8_t frag_size;
 2873                         uint8_t num_pages;
 2874                         struct phys_addr pages[2];
 2875                         uint32_t if_id;
 2876                         uint16_t max_frame_size;
 2877                         uint16_t page_size;
 2878                         uint32_t is_rss_queue;
 2879                 } req;
 2880 
 2881                 struct {
 2882                         uint16_t rq_id;
 2883                         uint8_t rss_cpuid;
 2884                         uint8_t rsvd0;
 2885                 } rsp;
 2886 
 2887         } params;
 2888 };
 2889 
 2890 /* [10] NIC_DELETE_RQ */
 2891 struct mbx_delete_nic_rq {
 2892         /* dw0 - dw3 */
 2893         struct mbx_hdr hdr;
 2894         union {
 2895                 struct {
 2896 #ifdef _BIG_ENDIAN
 2897                         /* dw4 */
 2898                         uint16_t bypass_flush;
 2899                         uint16_t rq_id;
 2900 #else
 2901                         /* dw4 */
 2902                         uint16_t rq_id;
 2903                         uint16_t bypass_flush;
 2904 #endif
 2905                 } req;
 2906 
 2907                 struct {
 2908                         /* dw4 */
 2909                         uint32_t rsvd0;
 2910                 } rsp;
 2911         } params;
 2912 };
 2913 
 2914 struct oce_port_rxf_stats_v0 {
 2915         uint32_t rx_bytes_lsd;                  /* dword 0*/
 2916         uint32_t rx_bytes_msd;                  /* dword 1*/
 2917         uint32_t rx_total_frames;               /* dword 2*/
 2918         uint32_t rx_unicast_frames;             /* dword 3*/
 2919         uint32_t rx_multicast_frames;           /* dword 4*/
 2920         uint32_t rx_broadcast_frames;           /* dword 5*/
 2921         uint32_t rx_crc_errors;                 /* dword 6*/
 2922         uint32_t rx_alignment_symbol_errors;    /* dword 7*/
 2923         uint32_t rx_pause_frames;               /* dword 8*/
 2924         uint32_t rx_control_frames;             /* dword 9*/
 2925         uint32_t rx_in_range_errors;            /* dword 10*/
 2926         uint32_t rx_out_range_errors;           /* dword 11*/
 2927         uint32_t rx_frame_too_long;             /* dword 12*/
 2928         uint32_t rx_address_match_errors;       /* dword 13*/
 2929         uint32_t rx_vlan_mismatch;              /* dword 14*/
 2930         uint32_t rx_dropped_too_small;          /* dword 15*/
 2931         uint32_t rx_dropped_too_short;          /* dword 16*/
 2932         uint32_t rx_dropped_header_too_small;   /* dword 17*/
 2933         uint32_t rx_dropped_tcp_length;         /* dword 18*/
 2934         uint32_t rx_dropped_runt;               /* dword 19*/
 2935         uint32_t rx_64_byte_packets;            /* dword 20*/
 2936         uint32_t rx_65_127_byte_packets;        /* dword 21*/
 2937         uint32_t rx_128_256_byte_packets;       /* dword 22*/
 2938         uint32_t rx_256_511_byte_packets;       /* dword 23*/
 2939         uint32_t rx_512_1023_byte_packets;      /* dword 24*/
 2940         uint32_t rx_1024_1518_byte_packets;     /* dword 25*/
 2941         uint32_t rx_1519_2047_byte_packets;     /* dword 26*/
 2942         uint32_t rx_2048_4095_byte_packets;     /* dword 27*/
 2943         uint32_t rx_4096_8191_byte_packets;     /* dword 28*/
 2944         uint32_t rx_8192_9216_byte_packets;     /* dword 29*/
 2945         uint32_t rx_ip_checksum_errs;           /* dword 30*/
 2946         uint32_t rx_tcp_checksum_errs;          /* dword 31*/
 2947         uint32_t rx_udp_checksum_errs;          /* dword 32*/
 2948         uint32_t rx_non_rss_packets;            /* dword 33*/
 2949         uint32_t rx_ipv4_packets;               /* dword 34*/
 2950         uint32_t rx_ipv6_packets;               /* dword 35*/
 2951         uint32_t rx_ipv4_bytes_lsd;             /* dword 36*/
 2952         uint32_t rx_ipv4_bytes_msd;             /* dword 37*/
 2953         uint32_t rx_ipv6_bytes_lsd;             /* dword 38*/
 2954         uint32_t rx_ipv6_bytes_msd;             /* dword 39*/
 2955         uint32_t rx_chute1_packets;             /* dword 40*/
 2956         uint32_t rx_chute2_packets;             /* dword 41*/
 2957         uint32_t rx_chute3_packets;             /* dword 42*/
 2958         uint32_t rx_management_packets;         /* dword 43*/
 2959         uint32_t rx_switched_unicast_packets;   /* dword 44*/
 2960         uint32_t rx_switched_multicast_packets; /* dword 45*/
 2961         uint32_t rx_switched_broadcast_packets; /* dword 46*/
 2962         uint32_t tx_bytes_lsd;                  /* dword 47*/
 2963         uint32_t tx_bytes_msd;                  /* dword 48*/
 2964         uint32_t tx_unicastframes;              /* dword 49*/
 2965         uint32_t tx_multicastframes;            /* dword 50*/
 2966         uint32_t tx_broadcastframes;            /* dword 51*/
 2967         uint32_t tx_pauseframes;                /* dword 52*/
 2968         uint32_t tx_controlframes;              /* dword 53*/
 2969         uint32_t tx_64_byte_packets;            /* dword 54*/
 2970         uint32_t tx_65_127_byte_packets;        /* dword 55*/
 2971         uint32_t tx_128_256_byte_packets;       /* dword 56*/
 2972         uint32_t tx_256_511_byte_packets;       /* dword 57*/
 2973         uint32_t tx_512_1023_byte_packets;      /* dword 58*/
 2974         uint32_t tx_1024_1518_byte_packets;     /* dword 59*/
 2975         uint32_t tx_1519_2047_byte_packets;     /* dword 60*/
 2976         uint32_t tx_2048_4095_byte_packets;     /* dword 61*/
 2977         uint32_t tx_4096_8191_byte_packets;     /* dword 62*/
 2978         uint32_t tx_8192_9216_byte_packets;     /* dword 63*/
 2979         uint32_t rxpp_fifo_overflow_drop;       /* dword 64*/
 2980         uint32_t rx_input_fifo_overflow_drop;   /* dword 65*/
 2981 };
 2982 
 2983 struct oce_rxf_stats_v0 {
 2984         struct oce_port_rxf_stats_v0 port[2];
 2985         uint32_t rx_drops_no_pbuf;              /* dword 132*/
 2986         uint32_t rx_drops_no_txpb;              /* dword 133*/
 2987         uint32_t rx_drops_no_erx_descr;         /* dword 134*/
 2988         uint32_t rx_drops_no_tpre_descr;        /* dword 135*/
 2989         uint32_t management_rx_port_packets;    /* dword 136*/
 2990         uint32_t management_rx_port_bytes;      /* dword 137*/
 2991         uint32_t management_rx_port_pause_frames;/* dword 138*/
 2992         uint32_t management_rx_port_errors;     /* dword 139*/
 2993         uint32_t management_tx_port_packets;    /* dword 140*/
 2994         uint32_t management_tx_port_bytes;      /* dword 141*/
 2995         uint32_t management_tx_port_pause;      /* dword 142*/
 2996         uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/
 2997         uint32_t rx_drops_too_many_frags;       /* dword 144*/
 2998         uint32_t rx_drops_invalid_ring;         /* dword 145*/
 2999         uint32_t forwarded_packets;             /* dword 146*/
 3000         uint32_t rx_drops_mtu;                  /* dword 147*/
 3001         uint32_t rsvd0[7];
 3002         uint32_t port0_jabber_events;
 3003         uint32_t port1_jabber_events;
 3004         uint32_t rsvd1[6];
 3005 };
 3006 
 3007 struct oce_port_rxf_stats_v2 {
 3008         uint32_t rsvd0[10];
 3009         uint32_t roce_bytes_received_lsd;
 3010         uint32_t roce_bytes_received_msd;
 3011         uint32_t rsvd1[5];
 3012         uint32_t roce_frames_received;
 3013         uint32_t rx_crc_errors;
 3014         uint32_t rx_alignment_symbol_errors;
 3015         uint32_t rx_pause_frames;
 3016         uint32_t rx_priority_pause_frames;
 3017         uint32_t rx_control_frames;
 3018         uint32_t rx_in_range_errors;
 3019         uint32_t rx_out_range_errors;
 3020         uint32_t rx_frame_too_long;
 3021         uint32_t rx_address_match_errors;
 3022         uint32_t rx_dropped_too_small;
 3023         uint32_t rx_dropped_too_short;
 3024         uint32_t rx_dropped_header_too_small;
 3025         uint32_t rx_dropped_tcp_length;
 3026         uint32_t rx_dropped_runt;
 3027         uint32_t rsvd2[10];
 3028         uint32_t rx_ip_checksum_errs;
 3029         uint32_t rx_tcp_checksum_errs;
 3030         uint32_t rx_udp_checksum_errs;
 3031         uint32_t rsvd3[7];
 3032         uint32_t rx_switched_unicast_packets;
 3033         uint32_t rx_switched_multicast_packets;
 3034         uint32_t rx_switched_broadcast_packets;
 3035         uint32_t rsvd4[3];
 3036         uint32_t tx_pauseframes;
 3037         uint32_t tx_priority_pauseframes;
 3038         uint32_t tx_controlframes;
 3039         uint32_t rsvd5[10];
 3040         uint32_t rxpp_fifo_overflow_drop;
 3041         uint32_t rx_input_fifo_overflow_drop;
 3042         uint32_t pmem_fifo_overflow_drop;
 3043         uint32_t jabber_events;
 3044         uint32_t rsvd6[3];
 3045         uint32_t rx_drops_payload_size;
 3046         uint32_t rx_drops_clipped_header;
 3047         uint32_t rx_drops_crc;
 3048         uint32_t roce_drops_payload_len;
 3049         uint32_t roce_drops_crc;
 3050         uint32_t rsvd7[19];
 3051 };
 3052 
 3053 struct oce_port_rxf_stats_v1 {
 3054         uint32_t rsvd0[12];
 3055         uint32_t rx_crc_errors;
 3056         uint32_t rx_alignment_symbol_errors;
 3057         uint32_t rx_pause_frames;
 3058         uint32_t rx_priority_pause_frames;
 3059         uint32_t rx_control_frames;
 3060         uint32_t rx_in_range_errors;
 3061         uint32_t rx_out_range_errors;
 3062         uint32_t rx_frame_too_long;
 3063         uint32_t rx_address_match_errors;
 3064         uint32_t rx_dropped_too_small;
 3065         uint32_t rx_dropped_too_short;
 3066         uint32_t rx_dropped_header_too_small;
 3067         uint32_t rx_dropped_tcp_length;
 3068         uint32_t rx_dropped_runt;
 3069         uint32_t rsvd1[10];
 3070         uint32_t rx_ip_checksum_errs;
 3071         uint32_t rx_tcp_checksum_errs;
 3072         uint32_t rx_udp_checksum_errs;
 3073         uint32_t rsvd2[7];
 3074         uint32_t rx_switched_unicast_packets;
 3075         uint32_t rx_switched_multicast_packets;
 3076         uint32_t rx_switched_broadcast_packets;
 3077         uint32_t rsvd3[3];
 3078         uint32_t tx_pauseframes;
 3079         uint32_t tx_priority_pauseframes;
 3080         uint32_t tx_controlframes;
 3081         uint32_t rsvd4[10];
 3082         uint32_t rxpp_fifo_overflow_drop;
 3083         uint32_t rx_input_fifo_overflow_drop;
 3084         uint32_t pmem_fifo_overflow_drop;
 3085         uint32_t jabber_events;
 3086         uint32_t rsvd5[3];
 3087 };
 3088 
 3089 struct oce_rxf_stats_v2 {
 3090         struct oce_port_rxf_stats_v2 port[4];
 3091         uint32_t rsvd0[2];
 3092         uint32_t rx_drops_no_pbuf;
 3093         uint32_t rx_drops_no_txpb;
 3094         uint32_t rx_drops_no_erx_descr;
 3095         uint32_t rx_drops_no_tpre_descr;
 3096         uint32_t rsvd1[6];
 3097         uint32_t rx_drops_too_many_frags;
 3098         uint32_t rx_drops_invalid_ring;
 3099         uint32_t forwarded_packets;
 3100         uint32_t rx_drops_mtu;
 3101         uint32_t rsvd2[35];
 3102 };
 3103 
 3104 struct oce_rxf_stats_v1 {
 3105         struct oce_port_rxf_stats_v1 port[4];
 3106         uint32_t rsvd0[2];
 3107         uint32_t rx_drops_no_pbuf;
 3108         uint32_t rx_drops_no_txpb;
 3109         uint32_t rx_drops_no_erx_descr;
 3110         uint32_t rx_drops_no_tpre_descr;
 3111         uint32_t rsvd1[6];
 3112         uint32_t rx_drops_too_many_frags;
 3113         uint32_t rx_drops_invalid_ring;
 3114         uint32_t forwarded_packets;
 3115         uint32_t rx_drops_mtu;
 3116         uint32_t rsvd2[14];
 3117 };
 3118 
 3119 struct oce_erx_stats_v2 {
 3120         uint32_t rx_drops_no_fragments[136];
 3121         uint32_t rsvd[3];
 3122 };
 3123 
 3124 struct oce_erx_stats_v1 {
 3125         uint32_t rx_drops_no_fragments[68];
 3126         uint32_t rsvd[4];
 3127 };
 3128 
 3129 struct oce_erx_stats_v0 {
 3130         uint32_t rx_drops_no_fragments[44];
 3131         uint32_t rsvd[4];
 3132 };
 3133 
 3134 struct oce_pmem_stats {
 3135         uint32_t eth_red_drops;
 3136         uint32_t rsvd[5];
 3137 };
 3138 
 3139 struct oce_hw_stats_v2 {
 3140         struct oce_rxf_stats_v2 rxf;
 3141         uint32_t rsvd0[OCE_TXP_SW_SZ];
 3142         struct oce_erx_stats_v2 erx;
 3143         struct oce_pmem_stats pmem;
 3144         uint32_t rsvd1[18];
 3145 };
 3146 
 3147 struct oce_hw_stats_v1 {
 3148         struct oce_rxf_stats_v1 rxf;
 3149         uint32_t rsvd0[OCE_TXP_SW_SZ];
 3150         struct oce_erx_stats_v1 erx;
 3151         struct oce_pmem_stats pmem;
 3152         uint32_t rsvd1[18];
 3153 };
 3154 
 3155 struct oce_hw_stats_v0 {
 3156         struct oce_rxf_stats_v0 rxf;
 3157         uint32_t rsvd[48];
 3158         struct oce_erx_stats_v0 erx;
 3159         struct oce_pmem_stats pmem;
 3160 };
 3161 
 3162 #define MBX_GET_NIC_STATS(version)                              \
 3163         struct mbx_get_nic_stats_v##version {                   \
 3164         struct mbx_hdr hdr;                                     \
 3165         union {                                                 \
 3166                 struct {                                        \
 3167                         uint32_t rsvd0;                         \
 3168                 } req;                                          \
 3169                 union {                                         \
 3170                         struct oce_hw_stats_v##version stats;   \
 3171                 } rsp;                                          \
 3172         } params;                                               \
 3173 }  
 3174 
 3175 MBX_GET_NIC_STATS(0);
 3176 MBX_GET_NIC_STATS(1);
 3177 MBX_GET_NIC_STATS(2);
 3178 
 3179 /* [18(0x12)] NIC_GET_PPORT_STATS */
 3180 struct pport_stats {
 3181         uint64_t tx_pkts;
 3182         uint64_t tx_unicast_pkts;
 3183         uint64_t tx_multicast_pkts;
 3184         uint64_t tx_broadcast_pkts;
 3185         uint64_t tx_bytes;
 3186         uint64_t tx_unicast_bytes;
 3187         uint64_t tx_multicast_bytes;
 3188         uint64_t tx_broadcast_bytes;
 3189         uint64_t tx_discards;
 3190         uint64_t tx_errors;
 3191         uint64_t tx_pause_frames;
 3192         uint64_t tx_pause_on_frames;
 3193         uint64_t tx_pause_off_frames;
 3194         uint64_t tx_internal_mac_errors;
 3195         uint64_t tx_control_frames;
 3196         uint64_t tx_pkts_64_bytes;
 3197         uint64_t tx_pkts_65_to_127_bytes;
 3198         uint64_t tx_pkts_128_to_255_bytes;
 3199         uint64_t tx_pkts_256_to_511_bytes;
 3200         uint64_t tx_pkts_512_to_1023_bytes;
 3201         uint64_t tx_pkts_1024_to_1518_bytes;
 3202         uint64_t tx_pkts_1519_to_2047_bytes;
 3203         uint64_t tx_pkts_2048_to_4095_bytes;
 3204         uint64_t tx_pkts_4096_to_8191_bytes;
 3205         uint64_t tx_pkts_8192_to_9216_bytes;
 3206         uint64_t tx_lso_pkts;
 3207         uint64_t rx_pkts;
 3208         uint64_t rx_unicast_pkts;
 3209         uint64_t rx_multicast_pkts;
 3210         uint64_t rx_broadcast_pkts;
 3211         uint64_t rx_bytes;
 3212         uint64_t rx_unicast_bytes;
 3213         uint64_t rx_multicast_bytes;
 3214         uint64_t rx_broadcast_bytes;
 3215         uint32_t rx_unknown_protos;
 3216         uint32_t reserved_word69;
 3217         uint64_t rx_discards;
 3218         uint64_t rx_errors;
 3219         uint64_t rx_crc_errors;
 3220         uint64_t rx_alignment_errors;
 3221         uint64_t rx_symbol_errors;
 3222         uint64_t rx_pause_frames;
 3223         uint64_t rx_pause_on_frames;
 3224         uint64_t rx_pause_off_frames;
 3225         uint64_t rx_frames_too_long;
 3226         uint64_t rx_internal_mac_errors;
 3227         uint32_t rx_undersize_pkts;
 3228         uint32_t rx_oversize_pkts;
 3229         uint32_t rx_fragment_pkts;
 3230         uint32_t rx_jabbers;
 3231         uint64_t rx_control_frames;
 3232         uint64_t rx_control_frames_unknown_opcode;
 3233         uint32_t rx_in_range_errors;
 3234         uint32_t rx_out_of_range_errors;
 3235         uint32_t rx_address_match_errors;
 3236         uint32_t rx_vlan_mismatch_errors;
 3237         uint32_t rx_dropped_too_small;
 3238         uint32_t rx_dropped_too_short;
 3239         uint32_t rx_dropped_header_too_small;
 3240         uint32_t rx_dropped_invalid_tcp_length;
 3241         uint32_t rx_dropped_runt;
 3242         uint32_t rx_ip_checksum_errors;
 3243         uint32_t rx_tcp_checksum_errors;
 3244         uint32_t rx_udp_checksum_errors;
 3245         uint32_t rx_non_rss_pkts;
 3246         uint64_t reserved_word111;
 3247         uint64_t rx_ipv4_pkts;
 3248         uint64_t rx_ipv6_pkts;
 3249         uint64_t rx_ipv4_bytes;
 3250         uint64_t rx_ipv6_bytes;
 3251         uint64_t rx_nic_pkts;
 3252         uint64_t rx_tcp_pkts;
 3253         uint64_t rx_iscsi_pkts;
 3254         uint64_t rx_management_pkts;
 3255         uint64_t rx_switched_unicast_pkts;
 3256         uint64_t rx_switched_multicast_pkts;
 3257         uint64_t rx_switched_broadcast_pkts;
 3258         uint64_t num_forwards;
 3259         uint32_t rx_fifo_overflow;
 3260         uint32_t rx_input_fifo_overflow;
 3261         uint64_t rx_drops_too_many_frags;
 3262         uint32_t rx_drops_invalid_queue;
 3263         uint32_t reserved_word141;
 3264         uint64_t rx_drops_mtu;
 3265         uint64_t rx_pkts_64_bytes;
 3266         uint64_t rx_pkts_65_to_127_bytes;
 3267         uint64_t rx_pkts_128_to_255_bytes;
 3268         uint64_t rx_pkts_256_to_511_bytes;
 3269         uint64_t rx_pkts_512_to_1023_bytes;
 3270         uint64_t rx_pkts_1024_to_1518_bytes;
 3271         uint64_t rx_pkts_1519_to_2047_bytes;
 3272         uint64_t rx_pkts_2048_to_4095_bytes;
 3273         uint64_t rx_pkts_4096_to_8191_bytes;
 3274         uint64_t rx_pkts_8192_to_9216_bytes;
 3275 };
 3276 
 3277 struct mbx_get_pport_stats {
 3278         /* dw0 - dw3 */
 3279         struct mbx_hdr hdr;
 3280         union {
 3281                 struct {
 3282                         /* dw4 */
 3283 #ifdef _BIG_ENDIAN
 3284                         uint32_t reset_stats:8;
 3285                         uint32_t rsvd0:8;
 3286                         uint32_t port_number:16;
 3287 #else
 3288                         uint32_t port_number:16;
 3289                         uint32_t rsvd0:8;
 3290                         uint32_t reset_stats:8;
 3291 #endif
 3292                 } req;
 3293 
 3294                 union {
 3295                         struct pport_stats pps;
 3296                         uint32_t pport_stats[164 - 4 + 1];
 3297                 } rsp;
 3298         } params;
 3299 };
 3300 
 3301 /* [19(0x13)] NIC_GET_VPORT_STATS */
 3302 struct vport_stats {
 3303         uint64_t tx_pkts;
 3304         uint64_t tx_unicast_pkts;
 3305         uint64_t tx_multicast_pkts;
 3306         uint64_t tx_broadcast_pkts;
 3307         uint64_t tx_bytes;
 3308         uint64_t tx_unicast_bytes;
 3309         uint64_t tx_multicast_bytes;
 3310         uint64_t tx_broadcast_bytes;
 3311         uint64_t tx_discards;
 3312         uint64_t tx_errors;
 3313         uint64_t tx_pkts_64_bytes;
 3314         uint64_t tx_pkts_65_to_127_bytes;
 3315         uint64_t tx_pkts_128_to_255_bytes;
 3316         uint64_t tx_pkts_256_to_511_bytes;
 3317         uint64_t tx_pkts_512_to_1023_bytes;
 3318         uint64_t tx_pkts_1024_to_1518_bytes;
 3319         uint64_t tx_pkts_1519_to_9699_bytes;
 3320         uint64_t tx_pkts_over_9699_bytes;
 3321         uint64_t rx_pkts;
 3322         uint64_t rx_unicast_pkts;
 3323         uint64_t rx_multicast_pkts;
 3324         uint64_t rx_broadcast_pkts;
 3325         uint64_t rx_bytes;
 3326         uint64_t rx_unicast_bytes;
 3327         uint64_t rx_multicast_bytes;
 3328         uint64_t rx_broadcast_bytes;
 3329         uint64_t rx_discards;
 3330         uint64_t rx_errors;
 3331         uint64_t rx_pkts_64_bytes;
 3332         uint64_t rx_pkts_65_to_127_bytes;
 3333         uint64_t rx_pkts_128_to_255_bytes;
 3334         uint64_t rx_pkts_256_to_511_bytes;
 3335         uint64_t rx_pkts_512_to_1023_bytes;
 3336         uint64_t rx_pkts_1024_to_1518_bytes;
 3337         uint64_t rx_pkts_1519_to_9699_bytes;
 3338         uint64_t rx_pkts_gt_9699_bytes;
 3339 };
 3340 struct mbx_get_vport_stats {
 3341         /* dw0 - dw3 */
 3342         struct mbx_hdr hdr;
 3343         union {
 3344                 struct {
 3345                         /* dw4 */
 3346 #ifdef _BIG_ENDIAN
 3347                         uint32_t reset_stats:8;
 3348                         uint32_t rsvd0:8;
 3349                         uint32_t vport_number:16;
 3350 #else
 3351                         uint32_t vport_number:16;
 3352                         uint32_t rsvd0:8;
 3353                         uint32_t reset_stats:8;
 3354 #endif
 3355                 } req;
 3356 
 3357                 union {
 3358                         struct vport_stats vps;
 3359                         uint32_t vport_stats[75 - 4 + 1];
 3360                 } rsp;
 3361         } params;
 3362 };
 3363 
 3364 /**
 3365  * @brief       [20(0x14)] NIC_GET_QUEUE_STATS
 3366  * The significant difference between vPort and Queue statistics is
 3367  * the packet byte counters.
 3368  */
 3369 struct queue_stats {
 3370         uint64_t packets;
 3371         uint64_t bytes;
 3372         uint64_t errors;
 3373         uint64_t drops;
 3374         uint64_t buffer_errors;         /* rsvd when tx */
 3375 };
 3376 
 3377 #define QUEUE_TYPE_WQ           0
 3378 #define QUEUE_TYPE_RQ           1
 3379 #define QUEUE_TYPE_HDS_RQ       1       /* same as RQ */
 3380 
 3381 struct mbx_get_queue_stats {
 3382         /* dw0 - dw3 */
 3383         struct mbx_hdr hdr;
 3384         union {
 3385                 struct {
 3386                         /* dw4 */
 3387 #ifdef _BIG_ENDIAN
 3388                         uint32_t reset_stats:8;
 3389                         uint32_t queue_type:8;
 3390                         uint32_t queue_id:16;
 3391 #else
 3392                         uint32_t queue_id:16;
 3393                         uint32_t queue_type:8;
 3394                         uint32_t reset_stats:8;
 3395 #endif
 3396                 } req;
 3397 
 3398                 union {
 3399                         struct queue_stats qs;
 3400                         uint32_t queue_stats[13 - 4 + 1];
 3401                 } rsp;
 3402         } params;
 3403 };
 3404 
 3405 /* [01] NIC_CONFIG_RSS */
 3406 #define OCE_HASH_TBL_SZ 10
 3407 #define OCE_CPU_TBL_SZ  128
 3408 #define OCE_FLUSH       1       /* RSS flush completion per CQ port */
 3409 struct mbx_config_nic_rss {
 3410         struct mbx_hdr hdr;
 3411         union {
 3412                 struct {
 3413 #ifdef _BIG_ENDIAN
 3414                         uint32_t if_id;
 3415                         uint16_t cpu_tbl_sz_log2;
 3416                         uint16_t enable_rss;
 3417                         uint32_t hash[OCE_HASH_TBL_SZ];
 3418                         uint8_t cputable[OCE_CPU_TBL_SZ];
 3419                         uint8_t rsvd[3];
 3420                         uint8_t flush;
 3421 #else
 3422                         uint32_t if_id;
 3423                         uint16_t enable_rss;
 3424                         uint16_t cpu_tbl_sz_log2;
 3425                         uint32_t hash[OCE_HASH_TBL_SZ];
 3426                         uint8_t cputable[OCE_CPU_TBL_SZ];
 3427                         uint8_t flush;
 3428                         uint8_t rsvd[3];
 3429 #endif
 3430                 } req;
 3431                 struct {
 3432                         uint8_t rsvd[3];
 3433                         uint8_t rss_bank;
 3434                 } rsp;
 3435         } params;
 3436 };
 3437 
 3438 #pragma pack()
 3439 
 3440 typedef uint32_t oce_stat_t;            /* statistic counter */
 3441 
 3442 enum OCE_RXF_PORT_STATS {
 3443         RXF_RX_BYTES_LSD,
 3444         RXF_RX_BYTES_MSD,
 3445         RXF_RX_TOTAL_FRAMES,
 3446         RXF_RX_UNICAST_FRAMES,
 3447         RXF_RX_MULTICAST_FRAMES,
 3448         RXF_RX_BROADCAST_FRAMES,
 3449         RXF_RX_CRC_ERRORS,
 3450         RXF_RX_ALIGNMENT_SYMBOL_ERRORS,
 3451         RXF_RX_PAUSE_FRAMES,
 3452         RXF_RX_CONTROL_FRAMES,
 3453         RXF_RX_IN_RANGE_ERRORS,
 3454         RXF_RX_OUT_RANGE_ERRORS,
 3455         RXF_RX_FRAME_TOO_LONG,
 3456         RXF_RX_ADDRESS_MATCH_ERRORS,
 3457         RXF_RX_VLAN_MISMATCH,
 3458         RXF_RX_DROPPED_TOO_SMALL,
 3459         RXF_RX_DROPPED_TOO_SHORT,
 3460         RXF_RX_DROPPED_HEADER_TOO_SMALL,
 3461         RXF_RX_DROPPED_TCP_LENGTH,
 3462         RXF_RX_DROPPED_RUNT,
 3463         RXF_RX_64_BYTE_PACKETS,
 3464         RXF_RX_65_127_BYTE_PACKETS,
 3465         RXF_RX_128_256_BYTE_PACKETS,
 3466         RXF_RX_256_511_BYTE_PACKETS,
 3467         RXF_RX_512_1023_BYTE_PACKETS,
 3468         RXF_RX_1024_1518_BYTE_PACKETS,
 3469         RXF_RX_1519_2047_BYTE_PACKETS,
 3470         RXF_RX_2048_4095_BYTE_PACKETS,
 3471         RXF_RX_4096_8191_BYTE_PACKETS,
 3472         RXF_RX_8192_9216_BYTE_PACKETS,
 3473         RXF_RX_IP_CHECKSUM_ERRS,
 3474         RXF_RX_TCP_CHECKSUM_ERRS,
 3475         RXF_RX_UDP_CHECKSUM_ERRS,
 3476         RXF_RX_NON_RSS_PACKETS,
 3477         RXF_RX_IPV4_PACKETS,
 3478         RXF_RX_IPV6_PACKETS,
 3479         RXF_RX_IPV4_BYTES_LSD,
 3480         RXF_RX_IPV4_BYTES_MSD,
 3481         RXF_RX_IPV6_BYTES_LSD,
 3482         RXF_RX_IPV6_BYTES_MSD,
 3483         RXF_RX_CHUTE1_PACKETS,
 3484         RXF_RX_CHUTE2_PACKETS,
 3485         RXF_RX_CHUTE3_PACKETS,
 3486         RXF_RX_MANAGEMENT_PACKETS,
 3487         RXF_RX_SWITCHED_UNICAST_PACKETS,
 3488         RXF_RX_SWITCHED_MULTICAST_PACKETS,
 3489         RXF_RX_SWITCHED_BROADCAST_PACKETS,
 3490         RXF_TX_BYTES_LSD,
 3491         RXF_TX_BYTES_MSD,
 3492         RXF_TX_UNICAST_FRAMES,
 3493         RXF_TX_MULTICAST_FRAMES,
 3494         RXF_TX_BROADCAST_FRAMES,
 3495         RXF_TX_PAUSE_FRAMES,
 3496         RXF_TX_CONTROL_FRAMES,
 3497         RXF_TX_64_BYTE_PACKETS,
 3498         RXF_TX_65_127_BYTE_PACKETS,
 3499         RXF_TX_128_256_BYTE_PACKETS,
 3500         RXF_TX_256_511_BYTE_PACKETS,
 3501         RXF_TX_512_1023_BYTE_PACKETS,
 3502         RXF_TX_1024_1518_BYTE_PACKETS,
 3503         RXF_TX_1519_2047_BYTE_PACKETS,
 3504         RXF_TX_2048_4095_BYTE_PACKETS,
 3505         RXF_TX_4096_8191_BYTE_PACKETS,
 3506         RXF_TX_8192_9216_BYTE_PACKETS,
 3507         RXF_RX_FIFO_OVERFLOW,
 3508         RXF_RX_INPUT_FIFO_OVERFLOW,
 3509         RXF_PORT_STATS_N_WORDS
 3510 };
 3511 
 3512 enum OCE_RXF_ADDL_STATS {
 3513         RXF_RX_DROPS_NO_PBUF,
 3514         RXF_RX_DROPS_NO_TXPB,
 3515         RXF_RX_DROPS_NO_ERX_DESCR,
 3516         RXF_RX_DROPS_NO_TPRE_DESCR,
 3517         RXF_MANAGEMENT_RX_PORT_PACKETS,
 3518         RXF_MANAGEMENT_RX_PORT_BYTES,
 3519         RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES,
 3520         RXF_MANAGEMENT_RX_PORT_ERRORS,
 3521         RXF_MANAGEMENT_TX_PORT_PACKETS,
 3522         RXF_MANAGEMENT_TX_PORT_BYTES,
 3523         RXF_MANAGEMENT_TX_PORT_PAUSE,
 3524         RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW,
 3525         RXF_RX_DROPS_TOO_MANY_FRAGS,
 3526         RXF_RX_DROPS_INVALID_RING,
 3527         RXF_FORWARDED_PACKETS,
 3528         RXF_RX_DROPS_MTU,
 3529         RXF_ADDL_STATS_N_WORDS
 3530 };
 3531 
 3532 enum OCE_TX_CHUTE_PORT_STATS {
 3533         CTPT_XMT_IPV4_PKTS,
 3534         CTPT_XMT_IPV4_LSD,
 3535         CTPT_XMT_IPV4_MSD,
 3536         CTPT_XMT_IPV6_PKTS,
 3537         CTPT_XMT_IPV6_LSD,
 3538         CTPT_XMT_IPV6_MSD,
 3539         CTPT_REXMT_IPV4_PKTs,
 3540         CTPT_REXMT_IPV4_LSD,
 3541         CTPT_REXMT_IPV4_MSD,
 3542         CTPT_REXMT_IPV6_PKTs,
 3543         CTPT_REXMT_IPV6_LSD,
 3544         CTPT_REXMT_IPV6_MSD,
 3545         CTPT_N_WORDS,
 3546 };
 3547 
 3548 enum OCE_RX_ERR_STATS {
 3549         RX_DROPS_NO_FRAGMENTS_0,
 3550         RX_DROPS_NO_FRAGMENTS_1,
 3551         RX_DROPS_NO_FRAGMENTS_2,
 3552         RX_DROPS_NO_FRAGMENTS_3,
 3553         RX_DROPS_NO_FRAGMENTS_4,
 3554         RX_DROPS_NO_FRAGMENTS_5,
 3555         RX_DROPS_NO_FRAGMENTS_6,
 3556         RX_DROPS_NO_FRAGMENTS_7,
 3557         RX_DROPS_NO_FRAGMENTS_8,
 3558         RX_DROPS_NO_FRAGMENTS_9,
 3559         RX_DROPS_NO_FRAGMENTS_10,
 3560         RX_DROPS_NO_FRAGMENTS_11,
 3561         RX_DROPS_NO_FRAGMENTS_12,
 3562         RX_DROPS_NO_FRAGMENTS_13,
 3563         RX_DROPS_NO_FRAGMENTS_14,
 3564         RX_DROPS_NO_FRAGMENTS_15,
 3565         RX_DROPS_NO_FRAGMENTS_16,
 3566         RX_DROPS_NO_FRAGMENTS_17,
 3567         RX_DROPS_NO_FRAGMENTS_18,
 3568         RX_DROPS_NO_FRAGMENTS_19,
 3569         RX_DROPS_NO_FRAGMENTS_20,
 3570         RX_DROPS_NO_FRAGMENTS_21,
 3571         RX_DROPS_NO_FRAGMENTS_22,
 3572         RX_DROPS_NO_FRAGMENTS_23,
 3573         RX_DROPS_NO_FRAGMENTS_24,
 3574         RX_DROPS_NO_FRAGMENTS_25,
 3575         RX_DROPS_NO_FRAGMENTS_26,
 3576         RX_DROPS_NO_FRAGMENTS_27,
 3577         RX_DROPS_NO_FRAGMENTS_28,
 3578         RX_DROPS_NO_FRAGMENTS_29,
 3579         RX_DROPS_NO_FRAGMENTS_30,
 3580         RX_DROPS_NO_FRAGMENTS_31,
 3581         RX_DROPS_NO_FRAGMENTS_32,
 3582         RX_DROPS_NO_FRAGMENTS_33,
 3583         RX_DROPS_NO_FRAGMENTS_34,
 3584         RX_DROPS_NO_FRAGMENTS_35,
 3585         RX_DROPS_NO_FRAGMENTS_36,
 3586         RX_DROPS_NO_FRAGMENTS_37,
 3587         RX_DROPS_NO_FRAGMENTS_38,
 3588         RX_DROPS_NO_FRAGMENTS_39,
 3589         RX_DROPS_NO_FRAGMENTS_40,
 3590         RX_DROPS_NO_FRAGMENTS_41,
 3591         RX_DROPS_NO_FRAGMENTS_42,
 3592         RX_DROPS_NO_FRAGMENTS_43,
 3593         RX_DEBUG_WDMA_SENT_HOLD,
 3594         RX_DEBUG_WDMA_PBFREE_SENT_HOLD,
 3595         RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD,
 3596         RX_DEBUG_PMEM_PBUF_DEALLOC,
 3597         RX_ERRORS_N_WORDS
 3598 };
 3599 
 3600 enum OCE_PMEM_ERR_STATS {
 3601         PMEM_ETH_RED_DROPS,
 3602         PMEM_LRO_RED_DROPS,
 3603         PMEM_ULP0_RED_DROPS,
 3604         PMEM_ULP1_RED_DROPS,
 3605         PMEM_GLOBAL_RED_DROPS,
 3606         PMEM_ERRORS_N_WORDS
 3607 };
 3608 
 3609 /**
 3610  * @brief Statistics for a given Physical Port
 3611  * These satisfy all the required BE2 statistics and also the
 3612  * following MIB objects:
 3613  * 
 3614  * RFC 2863 - The Interfaces Group MIB
 3615  * RFC 2819 - Remote Network Monitoring Management Information Base (RMON)
 3616  * RFC 3635 - Managed Objects for the Ethernet-like Interface Types
 3617  * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2)
 3618  * 
 3619  */
 3620 enum OCE_PPORT_STATS {
 3621         PPORT_TX_PKTS = 0,
 3622         PPORT_TX_UNICAST_PKTS = 2,
 3623         PPORT_TX_MULTICAST_PKTS = 4,
 3624         PPORT_TX_BROADCAST_PKTS = 6,
 3625         PPORT_TX_BYTES = 8,
 3626         PPORT_TX_UNICAST_BYTES = 10,
 3627         PPORT_TX_MULTICAST_BYTES = 12,
 3628         PPORT_TX_BROADCAST_BYTES = 14,
 3629         PPORT_TX_DISCARDS = 16,
 3630         PPORT_TX_ERRORS = 18,
 3631         PPORT_TX_PAUSE_FRAMES = 20,
 3632         PPORT_TX_PAUSE_ON_FRAMES = 22,
 3633         PPORT_TX_PAUSE_OFF_FRAMES = 24,
 3634         PPORT_TX_INTERNAL_MAC_ERRORS = 26,
 3635         PPORT_TX_CONTROL_FRAMES = 28,
 3636         PPORT_TX_PKTS_64_BYTES = 30,
 3637         PPORT_TX_PKTS_65_TO_127_BYTES = 32,
 3638         PPORT_TX_PKTS_128_TO_255_BYTES = 34,
 3639         PPORT_TX_PKTS_256_TO_511_BYTES = 36,
 3640         PPORT_TX_PKTS_512_TO_1023_BYTES = 38,
 3641         PPORT_TX_PKTS_1024_TO_1518_BYTES = 40,
 3642         PPORT_TX_PKTS_1519_TO_2047_BYTES = 42,
 3643         PPORT_TX_PKTS_2048_TO_4095_BYTES = 44,
 3644         PPORT_TX_PKTS_4096_TO_8191_BYTES = 46,
 3645         PPORT_TX_PKTS_8192_TO_9216_BYTES = 48,
 3646         PPORT_TX_LSO_PKTS = 50,
 3647         PPORT_RX_PKTS = 52,
 3648         PPORT_RX_UNICAST_PKTS = 54,
 3649         PPORT_RX_MULTICAST_PKTS = 56,
 3650         PPORT_RX_BROADCAST_PKTS = 58,
 3651         PPORT_RX_BYTES = 60,
 3652         PPORT_RX_UNICAST_BYTES = 62,
 3653         PPORT_RX_MULTICAST_BYTES = 64,
 3654         PPORT_RX_BROADCAST_BYTES = 66,
 3655         PPORT_RX_UNKNOWN_PROTOS = 68,
 3656         PPORT_RESERVED_WORD69 = 69,
 3657         PPORT_RX_DISCARDS = 70,
 3658         PPORT_RX_ERRORS = 72,
 3659         PPORT_RX_CRC_ERRORS = 74,
 3660         PPORT_RX_ALIGNMENT_ERRORS = 76,
 3661         PPORT_RX_SYMBOL_ERRORS = 78,
 3662         PPORT_RX_PAUSE_FRAMES = 80,
 3663         PPORT_RX_PAUSE_ON_FRAMES = 82,
 3664         PPORT_RX_PAUSE_OFF_FRAMES = 84,
 3665         PPORT_RX_FRAMES_TOO_LONG = 86,
 3666         PPORT_RX_INTERNAL_MAC_ERRORS = 88,
 3667         PPORT_RX_UNDERSIZE_PKTS = 90,
 3668         PPORT_RX_OVERSIZE_PKTS = 91,
 3669         PPORT_RX_FRAGMENT_PKTS = 92,
 3670         PPORT_RX_JABBERS = 93,
 3671         PPORT_RX_CONTROL_FRAMES = 94,
 3672         PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96,
 3673         PPORT_RX_IN_RANGE_ERRORS = 98,
 3674         PPORT_RX_OUT_OF_RANGE_ERRORS = 99,
 3675         PPORT_RX_ADDRESS_MATCH_ERRORS = 100,
 3676         PPORT_RX_VLAN_MISMATCH_ERRORS = 101,
 3677         PPORT_RX_DROPPED_TOO_SMALL = 102,
 3678         PPORT_RX_DROPPED_TOO_SHORT = 103,
 3679         PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104,
 3680         PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105,
 3681         PPORT_RX_DROPPED_RUNT = 106,
 3682         PPORT_RX_IP_CHECKSUM_ERRORS = 107,
 3683         PPORT_RX_TCP_CHECKSUM_ERRORS = 108,
 3684         PPORT_RX_UDP_CHECKSUM_ERRORS = 109,
 3685         PPORT_RX_NON_RSS_PKTS = 110,
 3686         PPORT_RESERVED_WORD111 = 111,
 3687         PPORT_RX_IPV4_PKTS = 112,
 3688         PPORT_RX_IPV6_PKTS = 114,
 3689         PPORT_RX_IPV4_BYTES = 116,
 3690         PPORT_RX_IPV6_BYTES = 118,
 3691         PPORT_RX_NIC_PKTS = 120,
 3692         PPORT_RX_TCP_PKTS = 122,
 3693         PPORT_RX_ISCSI_PKTS = 124,
 3694         PPORT_RX_MANAGEMENT_PKTS = 126,
 3695         PPORT_RX_SWITCHED_UNICAST_PKTS = 128,
 3696         PPORT_RX_SWITCHED_MULTICAST_PKTS = 130,
 3697         PPORT_RX_SWITCHED_BROADCAST_PKTS = 132,
 3698         PPORT_NUM_FORWARDS = 134,
 3699         PPORT_RX_FIFO_OVERFLOW = 136,
 3700         PPORT_RX_INPUT_FIFO_OVERFLOW = 137,
 3701         PPORT_RX_DROPS_TOO_MANY_FRAGS = 138,
 3702         PPORT_RX_DROPS_INVALID_QUEUE = 140,
 3703         PPORT_RESERVED_WORD141 = 141,
 3704         PPORT_RX_DROPS_MTU = 142,
 3705         PPORT_RX_PKTS_64_BYTES = 144,
 3706         PPORT_RX_PKTS_65_TO_127_BYTES = 146,
 3707         PPORT_RX_PKTS_128_TO_255_BYTES = 148,
 3708         PPORT_RX_PKTS_256_TO_511_BYTES = 150,
 3709         PPORT_RX_PKTS_512_TO_1023_BYTES = 152,
 3710         PPORT_RX_PKTS_1024_TO_1518_BYTES = 154,
 3711         PPORT_RX_PKTS_1519_TO_2047_BYTES = 156,
 3712         PPORT_RX_PKTS_2048_TO_4095_BYTES = 158,
 3713         PPORT_RX_PKTS_4096_TO_8191_BYTES = 160,
 3714         PPORT_RX_PKTS_8192_TO_9216_BYTES = 162,
 3715         PPORT_N_WORDS = 164
 3716 };
 3717 
 3718 /**
 3719  * @brief Statistics for a given Virtual Port (vPort)
 3720  * The following describes the vPort statistics satisfying
 3721  * requirements of Linux/VMWare netdev statistics and
 3722  * Microsoft Windows Statistics along with other Operating Systems.
 3723  */
 3724 enum OCE_VPORT_STATS {
 3725         VPORT_TX_PKTS = 0,
 3726         VPORT_TX_UNICAST_PKTS = 2,
 3727         VPORT_TX_MULTICAST_PKTS = 4,
 3728         VPORT_TX_BROADCAST_PKTS = 6,
 3729         VPORT_TX_BYTES = 8,
 3730         VPORT_TX_UNICAST_BYTES = 10,
 3731         VPORT_TX_MULTICAST_BYTES = 12,
 3732         VPORT_TX_BROADCAST_BYTES = 14,
 3733         VPORT_TX_DISCARDS = 16,
 3734         VPORT_TX_ERRORS = 18,
 3735         VPORT_TX_PKTS_64_BYTES = 20,
 3736         VPORT_TX_PKTS_65_TO_127_BYTES = 22,
 3737         VPORT_TX_PKTS_128_TO_255_BYTES = 24,
 3738         VPORT_TX_PKTS_256_TO_511_BYTES = 26,
 3739         VPORT_TX_PKTS_512_TO_1023_BYTEs = 28,
 3740         VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30,
 3741         VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32,
 3742         VPORT_TX_PKTS_OVER_9699_BYTES = 34,
 3743         VPORT_RX_PKTS = 36,
 3744         VPORT_RX_UNICAST_PKTS = 38,
 3745         VPORT_RX_MULTICAST_PKTS = 40,
 3746         VPORT_RX_BROADCAST_PKTS = 42,
 3747         VPORT_RX_BYTES = 44,
 3748         VPORT_RX_UNICAST_BYTES = 46,
 3749         VPORT_RX_MULTICAST_BYTES = 48,
 3750         VPORT_RX_BROADCAST_BYTES = 50,
 3751         VPORT_RX_DISCARDS = 52,
 3752         VPORT_RX_ERRORS = 54,
 3753         VPORT_RX_PKTS_64_BYTES = 56,
 3754         VPORT_RX_PKTS_65_TO_127_BYTES = 58,
 3755         VPORT_RX_PKTS_128_TO_255_BYTES = 60,
 3756         VPORT_RX_PKTS_256_TO_511_BYTES = 62,
 3757         VPORT_RX_PKTS_512_TO_1023_BYTEs = 64,
 3758         VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66,
 3759         VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68,
 3760         VPORT_RX_PKTS_OVER_9699_BYTES = 70,
 3761         VPORT_N_WORDS = 72
 3762 };
 3763 
 3764 /**
 3765  * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ)
 3766  * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ
 3767  */
 3768 enum OCE_QUEUE_TX_STATS {
 3769         QUEUE_TX_PKTS = 0,
 3770         QUEUE_TX_BYTES = 2,
 3771         QUEUE_TX_ERRORS = 4,
 3772         QUEUE_TX_DROPS = 6,
 3773         QUEUE_TX_N_WORDS = 8
 3774 };
 3775 
 3776 enum OCE_QUEUE_RX_STATS {
 3777         QUEUE_RX_PKTS = 0,
 3778         QUEUE_RX_BYTES = 2,
 3779         QUEUE_RX_ERRORS = 4,
 3780         QUEUE_RX_DROPS = 6,
 3781         QUEUE_RX_BUFFER_ERRORS = 8,
 3782         QUEUE_RX_N_WORDS = 10
 3783 };
 3784 
 3785 /* HW LRO structures */
 3786 struct mbx_nic_query_lro_capabilities {
 3787         struct mbx_hdr hdr;
 3788         union {
 3789                 struct {
 3790                         uint32_t rsvd[6];
 3791                 } req;
 3792                 struct {
 3793 #ifdef _BIG_ENDIAN
 3794                         uint32_t lro_flags;
 3795                         uint16_t lro_rq_cnt;
 3796                         uint16_t plro_max_offload;
 3797                         uint32_t rsvd[4];
 3798 #else
 3799                         uint32_t lro_flags;
 3800                         uint16_t plro_max_offload;
 3801                         uint16_t lro_rq_cnt;
 3802                         uint32_t rsvd[4];
 3803 #endif
 3804                 } rsp;
 3805         } params;
 3806 };
 3807 
 3808 struct mbx_nic_set_iface_lro_config {
 3809         struct mbx_hdr hdr;
 3810         union {
 3811                 struct {
 3812 #ifdef _BIG_ENDIAN
 3813                         uint32_t lro_flags;
 3814                         uint32_t iface_id;
 3815                         uint32_t max_clsc_byte_cnt;
 3816                         uint32_t max_clsc_seg_cnt;
 3817                         uint32_t max_clsc_usec_delay;
 3818                         uint32_t min_clsc_frame_byte_cnt;
 3819                         uint32_t rsvd[2];
 3820 #else
 3821                         uint32_t lro_flags;
 3822                         uint32_t iface_id;
 3823                         uint32_t max_clsc_byte_cnt;
 3824                         uint32_t max_clsc_seg_cnt;
 3825                         uint32_t max_clsc_usec_delay;
 3826                         uint32_t min_clsc_frame_byte_cnt;
 3827                         uint32_t rsvd[2];
 3828 #endif
 3829                 } req;
 3830                 struct {
 3831 #ifdef _BIG_ENDIAN
 3832                         uint32_t lro_flags;
 3833                         uint32_t rsvd[7];
 3834 #else
 3835                         uint32_t lro_flags;
 3836                         uint32_t rsvd[7];
 3837 #endif
 3838                 } rsp;
 3839         } params;
 3840 };
 3841 
 3842 struct mbx_create_nic_rq_v2 {
 3843         struct mbx_hdr hdr;
 3844         union {
 3845                 struct {
 3846 #ifdef _BIG_ENDIAN
 3847                         uint8_t  num_pages;
 3848                         uint8_t  frag_size;
 3849                         uint16_t cq_id;
 3850 
 3851                         uint32_t if_id;
 3852 
 3853                         uint16_t page_size;
 3854                         uint16_t max_frame_size;
 3855 
 3856                         uint16_t rsvd;
 3857                         uint16_t pd_id;
 3858 
 3859                         uint16_t rsvd1;
 3860                         uint16_t rq_flags;
 3861 
 3862                         uint16_t hds_fixed_offset;
 3863                         uint8_t hds_start;
 3864                         uint8_t hds_frag;
 3865 
 3866                         uint16_t hds_backfill_size;
 3867                         uint16_t hds_frag_size;
 3868 
 3869                         uint32_t rbq_id;
 3870 
 3871                         uint32_t rsvd2[8];
 3872 
 3873                         struct phys_addr pages[2];
 3874 #else
 3875                         uint16_t cq_id;
 3876                         uint8_t  frag_size;
 3877                         uint8_t  num_pages;
 3878 
 3879                         uint32_t if_id;
 3880 
 3881                         uint16_t max_frame_size;
 3882                         uint16_t page_size;
 3883 
 3884                         uint16_t pd_id;
 3885                         uint16_t rsvd;
 3886 
 3887                         uint16_t rq_flags;
 3888                         uint16_t rsvd1;
 3889 
 3890                         uint8_t hds_frag;
 3891                         uint8_t hds_start;
 3892                         uint16_t hds_fixed_offset;
 3893 
 3894                         uint16_t hds_frag_size;
 3895                         uint16_t hds_backfill_size;
 3896 
 3897                         uint32_t rbq_id;
 3898 
 3899                         uint32_t rsvd2[8];
 3900 
 3901                         struct phys_addr pages[2];
 3902 #endif
 3903                 } req;
 3904                 struct {
 3905 #ifdef _BIG_ENDIAN
 3906                         uint8_t rsvd0;
 3907                         uint8_t rss_cpuid;
 3908                         uint16_t rq_id;
 3909 
 3910                         uint8_t db_format;
 3911                         uint8_t db_reg_set;
 3912                         uint16_t rsvd1;
 3913 
 3914                         uint32_t db_offset;
 3915 
 3916                         uint32_t rsvd2;
 3917 
 3918                         uint16_t rsvd3;
 3919                         uint16_t rq_flags;
 3920 
 3921 #else
 3922                         uint16_t rq_id;
 3923                         uint8_t rss_cpuid;
 3924                         uint8_t rsvd0;
 3925 
 3926                         uint16_t rsvd1;
 3927                         uint8_t db_reg_set;
 3928                         uint8_t db_format;
 3929 
 3930                         uint32_t db_offset;
 3931 
 3932                         uint32_t rsvd2;
 3933 
 3934                         uint16_t rq_flags;
 3935                         uint16_t rsvd3;
 3936 #endif
 3937                 } rsp;
 3938 
 3939         } params;
 3940 };
 3941 
 3942 struct mbx_delete_nic_rq_v1 {
 3943         struct mbx_hdr hdr;
 3944         union {
 3945                 struct {
 3946 #ifdef _BIG_ENDIAN
 3947                         uint16_t bypass_flush;
 3948                         uint16_t rq_id;
 3949                         uint16_t rsvd;
 3950                         uint16_t rq_flags;
 3951 #else
 3952                         uint16_t rq_id;
 3953                         uint16_t bypass_flush;
 3954                         uint16_t rq_flags;
 3955                         uint16_t rsvd;
 3956 #endif
 3957                 } req;
 3958                 struct {
 3959                         uint32_t rsvd[2];
 3960                 } rsp;
 3961         } params;
 3962 };
 3963 
 3964 struct nic_hwlro_singleton_cqe {
 3965 #ifdef _BIG_ENDIAN
 3966         /* dw 0 */
 3967         uint32_t ip_opt:1;
 3968         uint32_t vtp:1;
 3969         uint32_t pkt_size:14;
 3970         uint32_t vlan_tag:16;
 3971 
 3972         /* dw 1 */
 3973         uint32_t num_frags:3;
 3974         uint32_t rsvd1:3;
 3975         uint32_t frag_index:10;
 3976         uint32_t rsvd:8;
 3977         uint32_t ipv6_frame:1;
 3978         uint32_t l4_cksum_pass:1;
 3979         uint32_t ip_cksum_pass:1;
 3980         uint32_t udpframe:1;
 3981         uint32_t tcpframe:1;
 3982         uint32_t ipframe:1;
 3983         uint32_t rss_hp:1;
 3984         uint32_t error:1;
 3985 
 3986         /* dw 2 */
 3987         uint32_t valid:1;
 3988         uint32_t cqe_type:2;
 3989         uint32_t debug:7;
 3990         uint32_t rsvd4:6;
 3991         uint32_t data_offset:8;
 3992         uint32_t rsvd3:3;
 3993         uint32_t rss_bank:1;
 3994         uint32_t qnq:1;
 3995         uint32_t rsvd2:3;
 3996         
 3997         /* dw 3 */
 3998         uint32_t rss_hash_value;
 3999 #else
 4000         /* dw 0 */
 4001         uint32_t vlan_tag:16;
 4002         uint32_t pkt_size:14;
 4003         uint32_t vtp:1;
 4004         uint32_t ip_opt:1;
 4005 
 4006         /* dw 1 */
 4007         uint32_t error:1;
 4008         uint32_t rss_hp:1;
 4009         uint32_t ipframe:1;
 4010         uint32_t tcpframe:1;
 4011         uint32_t udpframe:1;
 4012         uint32_t ip_cksum_pass:1;
 4013         uint32_t l4_cksum_pass:1;
 4014         uint32_t ipv6_frame:1;
 4015         uint32_t rsvd:8;
 4016         uint32_t frag_index:10;
 4017         uint32_t rsvd1:3;
 4018         uint32_t num_frags:3;
 4019 
 4020         /* dw 2 */
 4021         uint32_t rsvd2:3;
 4022         uint32_t qnq:1;
 4023         uint32_t rss_bank:1;
 4024         uint32_t rsvd3:3;
 4025         uint32_t data_offset:8;
 4026         uint32_t rsvd4:6;
 4027         uint32_t debug:7;
 4028         uint32_t cqe_type:2;
 4029         uint32_t valid:1;
 4030 
 4031        /* dw 3 */
 4032         uint32_t rss_hash_value;
 4033 #endif
 4034 };
 4035 
 4036 struct nic_hwlro_cqe_part1 {
 4037 #ifdef _BIG_ENDIAN
 4038         /* dw 0 */
 4039         uint32_t tcp_timestamp_val;
 4040 
 4041         /* dw 1 */
 4042         uint32_t tcp_timestamp_ecr;
 4043 
 4044         /* dw 2 */
 4045         uint32_t valid:1;
 4046         uint32_t cqe_type:2;
 4047         uint32_t rsvd3:7;
 4048         uint32_t rss_policy:4;
 4049         uint32_t rsvd2:2;
 4050         uint32_t data_offset:8;
 4051         uint32_t rsvd1:1;
 4052         uint32_t lro_desc:1;
 4053         uint32_t lro_timer_pop:1;
 4054         uint32_t rss_bank:1;
 4055         uint32_t qnq:1;
 4056         uint32_t rsvd:2;
 4057         uint32_t rss_flush:1;
 4058 
 4059         /* dw 3 */
 4060         uint32_t rss_hash_value;
 4061 #else
 4062         /* dw 0 */
 4063         uint32_t tcp_timestamp_val;
 4064 
 4065         /* dw 1 */
 4066         uint32_t tcp_timestamp_ecr;
 4067 
 4068         /* dw 2 */
 4069         uint32_t rss_flush:1;
 4070         uint32_t rsvd:2;
 4071         uint32_t qnq:1;
 4072         uint32_t rss_bank:1;
 4073         uint32_t lro_timer_pop:1;
 4074         uint32_t lro_desc:1;
 4075         uint32_t rsvd1:1;
 4076         uint32_t data_offset:8;
 4077         uint32_t rsvd2:2;
 4078         uint32_t rss_policy:4;
 4079         uint32_t rsvd3:7;
 4080         uint32_t cqe_type:2;
 4081         uint32_t valid:1;
 4082 
 4083         /* dw 3 */
 4084         uint32_t rss_hash_value;
 4085 #endif
 4086 };
 4087 
 4088 struct nic_hwlro_cqe_part2 {
 4089 #ifdef _BIG_ENDIAN
 4090         /* dw 0 */
 4091         uint32_t ip_opt:1;
 4092         uint32_t vtp:1;
 4093         uint32_t pkt_size:14;
 4094         uint32_t vlan_tag:16;
 4095 
 4096         /* dw 1 */
 4097         uint32_t tcp_window:16;
 4098         uint32_t coalesced_size:16;
 4099         
 4100         /* dw 2 */
 4101         uint32_t valid:1;
 4102         uint32_t cqe_type:2;
 4103         uint32_t rsvd:2;
 4104         uint32_t push:1;
 4105         uint32_t ts_opt:1;
 4106         uint32_t threshold:1;
 4107         uint32_t seg_cnt:8;
 4108         uint32_t frame_lifespan:8;
 4109         uint32_t ipv6_frame:1;
 4110         uint32_t l4_cksum_pass:1;
 4111         uint32_t ip_cksum_pass:1;
 4112         uint32_t udpframe:1;
 4113         uint32_t tcpframe:1;
 4114         uint32_t ipframe:1;
 4115         uint32_t rss_hp:1;
 4116         uint32_t error:1;
 4117         
 4118         /* dw 3 */
 4119         uint32_t tcp_ack_num;
 4120 #else
 4121         /* dw 0 */
 4122         uint32_t vlan_tag:16;
 4123         uint32_t pkt_size:14;
 4124         uint32_t vtp:1;
 4125         uint32_t ip_opt:1;
 4126 
 4127         /* dw 1 */
 4128         uint32_t coalesced_size:16;
 4129         uint32_t tcp_window:16;
 4130 
 4131         /* dw 2 */
 4132         uint32_t error:1;
 4133         uint32_t rss_hp:1;
 4134         uint32_t ipframe:1;
 4135         uint32_t tcpframe:1;
 4136         uint32_t udpframe:1;
 4137         uint32_t ip_cksum_pass:1;
 4138         uint32_t l4_cksum_pass:1;
 4139         uint32_t ipv6_frame:1;
 4140         uint32_t frame_lifespan:8;
 4141         uint32_t seg_cnt:8;
 4142         uint32_t threshold:1;
 4143         uint32_t ts_opt:1;
 4144         uint32_t push:1;
 4145         uint32_t rsvd:2;
 4146         uint32_t cqe_type:2;
 4147         uint32_t valid:1;
 4148 
 4149         /* dw 3 */
 4150         uint32_t tcp_ack_num;
 4151 #endif
 4152 };
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FreeBSD/Linux Kernel Cross Reference sys/dev/oce/oce_hw.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/oce/oce_hw.h
