Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/oce/oce_if.h
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2013 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 /* $FreeBSD$ */ 42 43 #include <sys/param.h> 44 #include <sys/endian.h> 45 #include <sys/eventhandler.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/mbuf.h> 51 #include <sys/priv.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sockopt.h> 56 #include <sys/queue.h> 57 #include <sys/taskqueue.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/sysctl.h> 61 #include <sys/random.h> 62 #include <sys/firmware.h> 63 #include <sys/systm.h> 64 #include <sys/proc.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <net/bpf.h> 70 #include <net/ethernet.h> 71 #include <net/if.h> 72 #include <net/if_var.h> 73 #include <net/if_types.h> 74 #include <net/if_media.h> 75 #include <net/if_vlan_var.h> 76 #include <net/if_dl.h> 77 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/if_ether.h> 82 #include <netinet/ip.h> 83 #include <netinet/ip6.h> 84 #include <netinet6/in6_var.h> 85 #include <netinet6/ip6_mroute.h> 86 87 #include <netinet/udp.h> 88 #include <netinet/tcp.h> 89 #include <netinet/sctp.h> 90 #include <netinet/tcp_lro.h> 91 #include <netinet/icmp6.h> 92 93 #include <machine/bus.h> 94 95 #include "oce_hw.h" 96 97 /* OCE device driver module component revision informaiton */ 98 #define COMPONENT_REVISION "11.0.50.0" 99 100 /* OCE devices supported by this driver */ 101 #define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 102 #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 103 #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 104 #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 105 #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 106 #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ 107 #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */ 108 109 #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 110 (sc->flags & OCE_FLAGS_BE2))? 1:0) 111 #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3) 112 #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2) 113 #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 114 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) 115 #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0) 116 117 #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \ 118 (sc->function_mode & FNM_UMC_MODE) || \ 119 (sc->function_mode & FNM_VNIC_MODE)) 120 #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40 121 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC) 122 123 124 /* proportion Service Level Interface queues */ 125 #define OCE_MAX_UNITS 2 126 #define OCE_MAX_PPORT OCE_MAX_UNITS 127 #define OCE_MAX_VPORT OCE_MAX_UNITS 128 129 extern int mp_ncpus; /* system's total active cpu cores */ 130 #define OCE_NCPUS mp_ncpus 131 132 /* This should be powers of 2. Like 2,4,8 & 16 */ 133 #define OCE_MAX_RSS 8 134 #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ 135 #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc)) 136 137 #define OCE_MIN_RQ 1 138 #define OCE_MIN_WQ 1 139 140 #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 141 #define OCE_MAX_WQ 8 142 143 #define OCE_MAX_EQ 32 144 #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */ 145 #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */ 146 147 #define OCE_DEFAULT_WQ_EQD 16 148 #define OCE_MAX_PACKET_Q 16 149 #define OCE_LSO_MAX_SIZE (64 * 1024) 150 #define LONG_TIMEOUT 30 151 #define OCE_MAX_JUMBO_FRAME_SIZE 9018 152 #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \ 153 ETHER_VLAN_ENCAP_LEN - \ 154 ETHER_HDR_LEN) 155 156 #define OCE_RDMA_VECTORS 2 157 158 #define OCE_MAX_TX_ELEMENTS 29 159 #define OCE_MAX_TX_DESC 1024 160 #define OCE_MAX_TX_SIZE 65535 161 #define OCE_MAX_TSO_SIZE (65535 - ETHER_HDR_LEN) 162 #define OCE_MAX_RX_SIZE 4096 163 #define OCE_MAX_RQ_POSTS 255 164 #define OCE_HWLRO_MAX_RQ_POSTS 64 165 #define OCE_DEFAULT_PROMISCUOUS 0 166 167 168 #define RSS_ENABLE_IPV4 0x1 169 #define RSS_ENABLE_TCP_IPV4 0x2 170 #define RSS_ENABLE_IPV6 0x4 171 #define RSS_ENABLE_TCP_IPV6 0x8 172 173 #define INDIRECTION_TABLE_ENTRIES 128 174 175 /* flow control definitions */ 176 #define OCE_FC_NONE 0x00000000 177 #define OCE_FC_TX 0x00000001 178 #define OCE_FC_RX 0x00000002 179 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 180 181 182 /* Interface capabilities to give device when creating interface */ 183 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 184 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 185 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 186 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \ 187 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 188 MBX_RX_IFACE_FLAGS_RSS | \ 189 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 190 191 /* Interface capabilities to enable by default (others set dynamically) */ 192 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 193 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 194 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 195 196 #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 197 #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 198 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \ 199 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU) 200 #define OCE_IF_HWASSIST_NONE 0 201 #define OCE_IF_CAPABILITIES_NONE 0 202 203 204 #define ETH_ADDR_LEN 6 205 #define MAX_VLANFILTER_SIZE 64 206 #define MAX_VLANS 4096 207 208 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 209 #define BSWAP_8(x) ((x) & 0xff) 210 #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8)) 211 #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \ 212 BSWAP_16((x) >> 16)) 213 #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 214 BSWAP_32((x) >> 32)) 215 216 #define for_all_wq_queues(sc, wq, i) \ 217 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 218 #define for_all_rq_queues(sc, rq, i) \ 219 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) 220 #define for_all_rss_queues(sc, rq, i) \ 221 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \ 222 i++, rq = sc->rq[i + 1]) 223 #define for_all_evnt_queues(sc, eq, i) \ 224 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 225 #define for_all_cq_queues(sc, cq, i) \ 226 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 227 228 229 /* Flash specific */ 230 #define IOCTL_COOKIE "SERVERENGINES CORP" 231 #define MAX_FLASH_COMP 32 232 233 #define IMG_ISCSI 160 234 #define IMG_REDBOOT 224 235 #define IMG_BIOS 34 236 #define IMG_PXEBIOS 32 237 #define IMG_FCOEBIOS 33 238 #define IMG_ISCSI_BAK 176 239 #define IMG_FCOE 162 240 #define IMG_FCOE_BAK 178 241 #define IMG_NCSI 16 242 #define IMG_PHY 192 243 #define FLASHROM_OPER_FLASH 1 244 #define FLASHROM_OPER_SAVE 2 245 #define FLASHROM_OPER_REPORT 4 246 #define FLASHROM_OPER_FLASH_PHY 9 247 #define FLASHROM_OPER_SAVE_PHY 10 248 #define TN_8022 13 249 250 enum { 251 PHY_TYPE_CX4_10GB = 0, 252 PHY_TYPE_XFP_10GB, 253 PHY_TYPE_SFP_1GB, 254 PHY_TYPE_SFP_PLUS_10GB, 255 PHY_TYPE_KR_10GB, 256 PHY_TYPE_KX4_10GB, 257 PHY_TYPE_BASET_10GB, 258 PHY_TYPE_BASET_1GB, 259 PHY_TYPE_BASEX_1GB, 260 PHY_TYPE_SGMII, 261 PHY_TYPE_DISABLED = 255 262 }; 263 264 /** 265 * @brief Define and hold all necessary info for a single interrupt 266 */ 267 #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */ 268 #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */ 269 270 typedef struct oce_intr_info { 271 void *tag; /* cookie returned by bus_setup_intr */ 272 struct resource *intr_res; /* PCI resource container */ 273 int irq_rr; /* resource id for the interrupt */ 274 struct oce_softc *sc; /* pointer to the parent soft c */ 275 struct oce_eq *eq; /* pointer to the connected EQ */ 276 struct taskqueue *tq; /* Associated task queue */ 277 struct task task; /* task queue task */ 278 char task_name[32]; /* task name */ 279 int vector; /* interrupt vector number */ 280 } OCE_INTR_INFO, *POCE_INTR_INFO; 281 282 283 /* Ring related */ 284 #define GET_Q_NEXT(_START, _STEP, _END) \ 285 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ 286 : (((_START) + (_STEP)) - (_END))) 287 288 #define DBUF_PA(obj) ((obj)->addr) 289 #define DBUF_VA(obj) ((obj)->ptr) 290 #define DBUF_TAG(obj) ((obj)->tag) 291 #define DBUF_MAP(obj) ((obj)->map) 292 #define DBUF_SYNC(obj, flags) \ 293 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags)) 294 295 #define RING_NUM_PENDING(ring) ring->num_used 296 #define RING_FULL(ring) (ring->num_used == ring->num_items) 297 #define RING_EMPTY(ring) (ring->num_used == 0) 298 #define RING_NUM_FREE(ring) \ 299 (uint32_t)(ring->num_items - ring->num_used) 300 #define RING_GET(ring, n) \ 301 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items) 302 #define RING_PUT(ring, n) \ 303 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items) 304 305 #define RING_GET_CONSUMER_ITEM_VA(ring, type) \ 306 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx) 307 #define RING_GET_CONSUMER_ITEM_PA(ring, type) \ 308 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx) 309 #define RING_GET_PRODUCER_ITEM_VA(ring, type) \ 310 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx) 311 #define RING_GET_PRODUCER_ITEM_PA(ring, type) \ 312 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx) 313 314 #define OCE_DMAPTR(o, c) ((c *)(o)->ptr) 315 316 struct oce_packet_desc { 317 struct mbuf *mbuf; 318 bus_dmamap_t map; 319 int nsegs; 320 uint32_t wqe_idx; 321 }; 322 323 typedef struct oce_dma_mem { 324 bus_dma_tag_t tag; 325 bus_dmamap_t map; 326 void *ptr; 327 bus_addr_t paddr; 328 } OCE_DMA_MEM, *POCE_DMA_MEM; 329 330 typedef struct oce_ring_buffer_s { 331 uint16_t cidx; /* Get ptr */ 332 uint16_t pidx; /* Put Ptr */ 333 size_t item_size; 334 size_t num_items; 335 uint32_t num_used; 336 OCE_DMA_MEM dma; 337 } oce_ring_buffer_t; 338 339 /* Stats */ 340 #define OCE_UNICAST_PACKET 0 341 #define OCE_MULTICAST_PACKET 1 342 #define OCE_BROADCAST_PACKET 2 343 #define OCE_RSVD_PACKET 3 344 345 struct oce_rx_stats { 346 /* Total Receive Stats*/ 347 uint64_t t_rx_pkts; 348 uint64_t t_rx_bytes; 349 uint32_t t_rx_frags; 350 uint32_t t_rx_mcast_pkts; 351 uint32_t t_rx_ucast_pkts; 352 uint32_t t_rxcp_errs; 353 }; 354 struct oce_tx_stats { 355 /*Total Transmit Stats */ 356 uint64_t t_tx_pkts; 357 uint64_t t_tx_bytes; 358 uint32_t t_tx_reqs; 359 uint32_t t_tx_stops; 360 uint32_t t_tx_wrbs; 361 uint32_t t_tx_compl; 362 uint32_t t_ipv6_ext_hdr_tx_drop; 363 }; 364 365 struct oce_be_stats { 366 uint8_t be_on_die_temperature; 367 uint32_t be_tx_events; 368 uint32_t eth_red_drops; 369 uint32_t rx_drops_no_pbuf; 370 uint32_t rx_drops_no_txpb; 371 uint32_t rx_drops_no_erx_descr; 372 uint32_t rx_drops_no_tpre_descr; 373 uint32_t rx_drops_too_many_frags; 374 uint32_t rx_drops_invalid_ring; 375 uint32_t forwarded_packets; 376 uint32_t rx_drops_mtu; 377 uint32_t rx_crc_errors; 378 uint32_t rx_alignment_symbol_errors; 379 uint32_t rx_pause_frames; 380 uint32_t rx_priority_pause_frames; 381 uint32_t rx_control_frames; 382 uint32_t rx_in_range_errors; 383 uint32_t rx_out_range_errors; 384 uint32_t rx_frame_too_long; 385 uint32_t rx_address_match_errors; 386 uint32_t rx_dropped_too_small; 387 uint32_t rx_dropped_too_short; 388 uint32_t rx_dropped_header_too_small; 389 uint32_t rx_dropped_tcp_length; 390 uint32_t rx_dropped_runt; 391 uint32_t rx_ip_checksum_errs; 392 uint32_t rx_tcp_checksum_errs; 393 uint32_t rx_udp_checksum_errs; 394 uint32_t rx_switched_unicast_packets; 395 uint32_t rx_switched_multicast_packets; 396 uint32_t rx_switched_broadcast_packets; 397 uint32_t tx_pauseframes; 398 uint32_t tx_priority_pauseframes; 399 uint32_t tx_controlframes; 400 uint32_t rxpp_fifo_overflow_drop; 401 uint32_t rx_input_fifo_overflow_drop; 402 uint32_t pmem_fifo_overflow_drop; 403 uint32_t jabber_events; 404 }; 405 406 struct oce_xe201_stats { 407 uint64_t tx_pkts; 408 uint64_t tx_unicast_pkts; 409 uint64_t tx_multicast_pkts; 410 uint64_t tx_broadcast_pkts; 411 uint64_t tx_bytes; 412 uint64_t tx_unicast_bytes; 413 uint64_t tx_multicast_bytes; 414 uint64_t tx_broadcast_bytes; 415 uint64_t tx_discards; 416 uint64_t tx_errors; 417 uint64_t tx_pause_frames; 418 uint64_t tx_pause_on_frames; 419 uint64_t tx_pause_off_frames; 420 uint64_t tx_internal_mac_errors; 421 uint64_t tx_control_frames; 422 uint64_t tx_pkts_64_bytes; 423 uint64_t tx_pkts_65_to_127_bytes; 424 uint64_t tx_pkts_128_to_255_bytes; 425 uint64_t tx_pkts_256_to_511_bytes; 426 uint64_t tx_pkts_512_to_1023_bytes; 427 uint64_t tx_pkts_1024_to_1518_bytes; 428 uint64_t tx_pkts_1519_to_2047_bytes; 429 uint64_t tx_pkts_2048_to_4095_bytes; 430 uint64_t tx_pkts_4096_to_8191_bytes; 431 uint64_t tx_pkts_8192_to_9216_bytes; 432 uint64_t tx_lso_pkts; 433 uint64_t rx_pkts; 434 uint64_t rx_unicast_pkts; 435 uint64_t rx_multicast_pkts; 436 uint64_t rx_broadcast_pkts; 437 uint64_t rx_bytes; 438 uint64_t rx_unicast_bytes; 439 uint64_t rx_multicast_bytes; 440 uint64_t rx_broadcast_bytes; 441 uint32_t rx_unknown_protos; 442 uint64_t rx_discards; 443 uint64_t rx_errors; 444 uint64_t rx_crc_errors; 445 uint64_t rx_alignment_errors; 446 uint64_t rx_symbol_errors; 447 uint64_t rx_pause_frames; 448 uint64_t rx_pause_on_frames; 449 uint64_t rx_pause_off_frames; 450 uint64_t rx_frames_too_long; 451 uint64_t rx_internal_mac_errors; 452 uint32_t rx_undersize_pkts; 453 uint32_t rx_oversize_pkts; 454 uint32_t rx_fragment_pkts; 455 uint32_t rx_jabbers; 456 uint64_t rx_control_frames; 457 uint64_t rx_control_frames_unknown_opcode; 458 uint32_t rx_in_range_errors; 459 uint32_t rx_out_of_range_errors; 460 uint32_t rx_address_match_errors; 461 uint32_t rx_vlan_mismatch_errors; 462 uint32_t rx_dropped_too_small; 463 uint32_t rx_dropped_too_short; 464 uint32_t rx_dropped_header_too_small; 465 uint32_t rx_dropped_invalid_tcp_length; 466 uint32_t rx_dropped_runt; 467 uint32_t rx_ip_checksum_errors; 468 uint32_t rx_tcp_checksum_errors; 469 uint32_t rx_udp_checksum_errors; 470 uint32_t rx_non_rss_pkts; 471 uint64_t rx_ipv4_pkts; 472 uint64_t rx_ipv6_pkts; 473 uint64_t rx_ipv4_bytes; 474 uint64_t rx_ipv6_bytes; 475 uint64_t rx_nic_pkts; 476 uint64_t rx_tcp_pkts; 477 uint64_t rx_iscsi_pkts; 478 uint64_t rx_management_pkts; 479 uint64_t rx_switched_unicast_pkts; 480 uint64_t rx_switched_multicast_pkts; 481 uint64_t rx_switched_broadcast_pkts; 482 uint64_t num_forwards; 483 uint32_t rx_fifo_overflow; 484 uint32_t rx_input_fifo_overflow; 485 uint64_t rx_drops_too_many_frags; 486 uint32_t rx_drops_invalid_queue; 487 uint64_t rx_drops_mtu; 488 uint64_t rx_pkts_64_bytes; 489 uint64_t rx_pkts_65_to_127_bytes; 490 uint64_t rx_pkts_128_to_255_bytes; 491 uint64_t rx_pkts_256_to_511_bytes; 492 uint64_t rx_pkts_512_to_1023_bytes; 493 uint64_t rx_pkts_1024_to_1518_bytes; 494 uint64_t rx_pkts_1519_to_2047_bytes; 495 uint64_t rx_pkts_2048_to_4095_bytes; 496 uint64_t rx_pkts_4096_to_8191_bytes; 497 uint64_t rx_pkts_8192_to_9216_bytes; 498 }; 499 500 struct oce_drv_stats { 501 struct oce_rx_stats rx; 502 struct oce_tx_stats tx; 503 union { 504 struct oce_be_stats be; 505 struct oce_xe201_stats xe201; 506 } u0; 507 }; 508 509 #define INTR_RATE_HWM 15000 510 #define INTR_RATE_LWM 10000 511 512 #define OCE_MAX_EQD 128u 513 #define OCE_MIN_EQD 0u 514 515 struct oce_set_eqd { 516 uint32_t eq_id; 517 uint32_t phase; 518 uint32_t delay_multiplier; 519 }; 520 521 struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 522 boolean_t enable; 523 uint32_t min_eqd; /* in usecs */ 524 uint32_t max_eqd; /* in usecs */ 525 uint32_t cur_eqd; /* in usecs */ 526 uint32_t et_eqd; /* configured value when aic is off */ 527 uint64_t ticks; 528 uint64_t prev_rxpkts; 529 uint64_t prev_txreqs; 530 }; 531 532 #define MAX_LOCK_DESC_LEN 32 533 struct oce_lock { 534 struct mtx mutex; 535 char name[MAX_LOCK_DESC_LEN+1]; 536 }; 537 #define OCE_LOCK struct oce_lock 538 539 #define LOCK_CREATE(lock, desc) { \ 540 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \ 541 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \ 542 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \ 543 } 544 #define LOCK_DESTROY(lock) \ 545 if (mtx_initialized(&(lock)->mutex))\ 546 mtx_destroy(&(lock)->mutex) 547 #define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex) 548 #define LOCK(lock) mtx_lock(&(lock)->mutex) 549 #define LOCKED(lock) mtx_owned(&(lock)->mutex) 550 #define UNLOCK(lock) mtx_unlock(&(lock)->mutex) 551 552 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) 553 #define MBX_READY_TIMEOUT (1 * 1000 * 1000) 554 #define DEFAULT_DRAIN_TIME 200 555 #define MBX_TIMEOUT_SEC 5 556 #define STAT_TIMEOUT 2000000 557 558 /* size of the packet descriptor array in a transmit queue */ 559 #define OCE_TX_RING_SIZE 2048 560 #define OCE_RX_RING_SIZE 1024 561 #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2) 562 #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE) 563 564 struct oce_dev; 565 566 enum eq_len { 567 EQ_LEN_256 = 256, 568 EQ_LEN_512 = 512, 569 EQ_LEN_1024 = 1024, 570 EQ_LEN_2048 = 2048, 571 EQ_LEN_4096 = 4096 572 }; 573 574 enum eqe_size { 575 EQE_SIZE_4 = 4, 576 EQE_SIZE_16 = 16 577 }; 578 579 enum qtype { 580 QTYPE_EQ, 581 QTYPE_MQ, 582 QTYPE_WQ, 583 QTYPE_RQ, 584 QTYPE_CQ, 585 QTYPE_RSS 586 }; 587 588 typedef enum qstate_e { 589 QDELETED = 0x0, 590 QCREATED = 0x1 591 } qstate_t; 592 593 struct eq_config { 594 enum eq_len q_len; 595 enum eqe_size item_size; 596 uint32_t q_vector_num; 597 uint8_t min_eqd; 598 uint8_t max_eqd; 599 uint8_t cur_eqd; 600 uint8_t pad; 601 }; 602 603 struct oce_eq { 604 uint32_t eq_id; 605 void *parent; 606 void *cb_context; 607 oce_ring_buffer_t *ring; 608 uint32_t ref_count; 609 qstate_t qstate; 610 struct oce_cq *cq[OCE_MAX_CQ_EQ]; 611 int cq_valid; 612 struct eq_config eq_cfg; 613 int vector; 614 uint64_t intr; 615 }; 616 617 enum cq_len { 618 CQ_LEN_256 = 256, 619 CQ_LEN_512 = 512, 620 CQ_LEN_1024 = 1024, 621 CQ_LEN_2048 = 2048 622 }; 623 624 struct cq_config { 625 enum cq_len q_len; 626 uint32_t item_size; 627 boolean_t is_eventable; 628 boolean_t sol_eventable; 629 boolean_t nodelay; 630 uint16_t dma_coalescing; 631 }; 632 633 typedef uint16_t(*cq_handler_t) (void *arg1); 634 635 struct oce_cq { 636 uint32_t cq_id; 637 void *parent; 638 struct oce_eq *eq; 639 cq_handler_t cq_handler; 640 void *cb_arg; 641 oce_ring_buffer_t *ring; 642 qstate_t qstate; 643 struct cq_config cq_cfg; 644 uint32_t ref_count; 645 }; 646 647 648 struct mq_config { 649 uint32_t eqd; 650 uint8_t q_len; 651 uint8_t pad[3]; 652 }; 653 654 655 struct oce_mq { 656 void *parent; 657 oce_ring_buffer_t *ring; 658 uint32_t mq_id; 659 struct oce_cq *cq; 660 struct oce_cq *async_cq; 661 uint32_t mq_free; 662 qstate_t qstate; 663 struct mq_config cfg; 664 }; 665 666 struct oce_mbx_ctx { 667 struct oce_mbx *mbx; 668 void (*cb) (void *ctx); 669 void *cb_ctx; 670 }; 671 672 struct wq_config { 673 uint8_t wq_type; 674 uint16_t buf_size; 675 uint8_t pad[1]; 676 uint32_t q_len; 677 uint16_t pd_id; 678 uint16_t pci_fn_num; 679 uint32_t eqd; /* interrupt delay */ 680 uint32_t nbufs; 681 uint32_t nhdl; 682 }; 683 684 struct oce_tx_queue_stats { 685 uint64_t tx_pkts; 686 uint64_t tx_bytes; 687 uint32_t tx_reqs; 688 uint32_t tx_stops; /* number of times TX Q was stopped */ 689 uint32_t tx_wrbs; 690 uint32_t tx_compl; 691 uint32_t tx_rate; 692 uint32_t ipv6_ext_hdr_tx_drop; 693 }; 694 695 struct oce_wq { 696 OCE_LOCK tx_lock; 697 OCE_LOCK tx_compl_lock; 698 void *parent; 699 oce_ring_buffer_t *ring; 700 struct oce_cq *cq; 701 bus_dma_tag_t tag; 702 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; 703 uint32_t pkt_desc_tail; 704 uint32_t pkt_desc_head; 705 uint32_t wqm_used; 706 boolean_t resched; 707 uint32_t wq_free; 708 uint32_t tx_deferd; 709 uint32_t pkt_drops; 710 qstate_t qstate; 711 uint16_t wq_id; 712 struct wq_config cfg; 713 int queue_index; 714 struct oce_tx_queue_stats tx_stats; 715 struct buf_ring *br; 716 struct task txtask; 717 uint32_t db_offset; 718 }; 719 720 struct rq_config { 721 uint32_t q_len; 722 uint32_t frag_size; 723 uint32_t mtu; 724 uint32_t if_id; 725 uint32_t is_rss_queue; 726 uint32_t eqd; 727 uint32_t nbufs; 728 }; 729 730 struct oce_rx_queue_stats { 731 uint32_t rx_post_fail; 732 uint32_t rx_ucast_pkts; 733 uint32_t rx_compl; 734 uint64_t rx_bytes; 735 uint64_t rx_bytes_prev; 736 uint64_t rx_pkts; 737 uint32_t rx_rate; 738 uint32_t rx_mcast_pkts; 739 uint32_t rxcp_err; 740 uint32_t rx_frags; 741 uint32_t prev_rx_frags; 742 uint32_t rx_fps; 743 uint32_t rx_drops_no_frags; /* HW has no fetched frags */ 744 }; 745 746 747 struct oce_rq { 748 struct rq_config cfg; 749 uint32_t rq_id; 750 int queue_index; 751 uint32_t rss_cpuid; 752 void *parent; 753 oce_ring_buffer_t *ring; 754 struct oce_cq *cq; 755 void *pad1; 756 bus_dma_tag_t tag; 757 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE]; 758 uint32_t pending; 759 #ifdef notdef 760 struct mbuf *head; 761 struct mbuf *tail; 762 int fragsleft; 763 #endif 764 qstate_t qstate; 765 OCE_LOCK rx_lock; 766 struct oce_rx_queue_stats rx_stats; 767 struct lro_ctrl lro; 768 int lro_pkts_queued; 769 int islro; 770 struct nic_hwlro_cqe_part1 *cqe_firstpart; 771 772 }; 773 774 struct link_status { 775 uint8_t phys_port_speed; 776 uint8_t logical_link_status; 777 uint16_t qos_link_speed; 778 }; 779 780 781 782 #define OCE_FLAGS_PCIX 0x00000001 783 #define OCE_FLAGS_PCIE 0x00000002 784 #define OCE_FLAGS_MSI_CAPABLE 0x00000004 785 #define OCE_FLAGS_MSIX_CAPABLE 0x00000008 786 #define OCE_FLAGS_USING_MSI 0x00000010 787 #define OCE_FLAGS_USING_MSIX 0x00000020 788 #define OCE_FLAGS_FUNCRESET_RQD 0x00000040 789 #define OCE_FLAGS_VIRTUAL_PORT 0x00000080 790 #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 791 #define OCE_FLAGS_BE3 0x00000200 792 #define OCE_FLAGS_XE201 0x00000400 793 #define OCE_FLAGS_BE2 0x00000800 794 #define OCE_FLAGS_SH 0x00001000 795 #define OCE_FLAGS_OS2BMC 0x00002000 796 797 #define OCE_DEV_BE2_CFG_BAR 1 798 #define OCE_DEV_CFG_BAR 0 799 #define OCE_PCI_CSR_BAR 2 800 #define OCE_PCI_DB_BAR 4 801 802 typedef struct oce_softc { 803 device_t dev; 804 OCE_LOCK dev_lock; 805 806 uint32_t flags; 807 808 uint32_t pcie_link_speed; 809 uint32_t pcie_link_width; 810 811 uint8_t fn; /* PCI function number */ 812 813 struct resource *devcfg_res; 814 bus_space_tag_t devcfg_btag; 815 bus_space_handle_t devcfg_bhandle; 816 void *devcfg_vhandle; 817 818 struct resource *csr_res; 819 bus_space_tag_t csr_btag; 820 bus_space_handle_t csr_bhandle; 821 void *csr_vhandle; 822 823 struct resource *db_res; 824 bus_space_tag_t db_btag; 825 bus_space_handle_t db_bhandle; 826 void *db_vhandle; 827 828 OCE_INTR_INFO intrs[OCE_MAX_EQ]; 829 int intr_count; 830 int roce_intr_count; 831 832 struct ifnet *ifp; 833 834 struct ifmedia media; 835 uint8_t link_status; 836 uint8_t link_speed; 837 uint8_t duplex; 838 uint32_t qos_link_speed; 839 uint32_t speed; 840 uint32_t enable_hwlro; 841 842 char fw_version[32]; 843 struct mac_address_format macaddr; 844 845 OCE_DMA_MEM bsmbx; 846 OCE_LOCK bmbx_lock; 847 848 uint32_t config_number; 849 uint32_t asic_revision; 850 uint32_t port_id; 851 uint32_t function_mode; 852 uint32_t function_caps; 853 uint32_t max_tx_rings; 854 uint32_t max_rx_rings; 855 856 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */ 857 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */ 858 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 859 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 860 struct oce_mq *mq; /* Mailbox queue */ 861 862 uint32_t neqs; 863 uint32_t ncqs; 864 uint32_t nrqs; 865 uint32_t nwqs; 866 uint32_t nrssqs; 867 868 uint32_t tx_ring_size; 869 uint32_t rx_ring_size; 870 uint32_t rq_frag_size; 871 872 uint32_t if_id; /* interface ID */ 873 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 874 uint32_t pmac_id; /* PMAC id */ 875 876 uint32_t if_cap_flags; 877 878 uint32_t flow_control; 879 uint8_t promisc; 880 881 struct oce_aic_obj aic_obj[OCE_MAX_EQ]; 882 883 /*Vlan Filtering related */ 884 eventhandler_tag vlan_attach; 885 eventhandler_tag vlan_detach; 886 uint16_t vlans_added; 887 uint8_t vlan_tag[MAX_VLANS]; 888 /*stats */ 889 OCE_DMA_MEM stats_mem; 890 struct oce_drv_stats oce_stats_info; 891 struct callout timer; 892 int8_t be3_native; 893 uint8_t hw_error; 894 uint16_t qnq_debug_event; 895 uint16_t qnqid; 896 uint32_t pvid; 897 uint32_t max_vlans; 898 uint32_t bmc_filt_mask; 899 900 void *rdma_context; 901 uint32_t rdma_flags; 902 struct oce_softc *next; 903 904 } OCE_SOFTC, *POCE_SOFTC; 905 906 #define OCE_RDMA_FLAG_SUPPORTED 0x00000001 907 908 909 /************************************************** 910 * BUS memory read/write macros 911 * BE3: accesses three BAR spaces (CFG, CSR, DB) 912 * Lancer: accesses one BAR space (CFG) 913 **************************************************/ 914 #define OCE_READ_CSR_MPU(sc, space, o) \ 915 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 916 (sc)->space##_bhandle,o)) \ 917 : (bus_space_read_4((sc)->devcfg_btag, \ 918 (sc)->devcfg_bhandle,o))) 919 #define OCE_READ_REG32(sc, space, o) \ 920 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 921 (sc)->space##_bhandle,o)) \ 922 : (bus_space_read_4((sc)->devcfg_btag, \ 923 (sc)->devcfg_bhandle,o))) 924 #define OCE_READ_REG16(sc, space, o) \ 925 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 926 (sc)->space##_bhandle,o)) \ 927 : (bus_space_read_2((sc)->devcfg_btag, \ 928 (sc)->devcfg_bhandle,o))) 929 #define OCE_READ_REG8(sc, space, o) \ 930 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 931 (sc)->space##_bhandle,o)) \ 932 : (bus_space_read_1((sc)->devcfg_btag, \ 933 (sc)->devcfg_bhandle,o))) 934 935 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \ 936 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 937 (sc)->space##_bhandle,o,v)) \ 938 : (bus_space_write_4((sc)->devcfg_btag, \ 939 (sc)->devcfg_bhandle,o,v))) 940 #define OCE_WRITE_REG32(sc, space, o, v) \ 941 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 942 (sc)->space##_bhandle,o,v)) \ 943 : (bus_space_write_4((sc)->devcfg_btag, \ 944 (sc)->devcfg_bhandle,o,v))) 945 #define OCE_WRITE_REG16(sc, space, o, v) \ 946 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \ 947 (sc)->space##_bhandle,o,v)) \ 948 : (bus_space_write_2((sc)->devcfg_btag, \ 949 (sc)->devcfg_bhandle,o,v))) 950 #define OCE_WRITE_REG8(sc, space, o, v) \ 951 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \ 952 (sc)->space##_bhandle,o,v)) \ 953 : (bus_space_write_1((sc)->devcfg_btag, \ 954 (sc)->devcfg_bhandle,o,v))) 955 956 void oce_rx_flush_lro(struct oce_rq *rq); 957 /*********************************************************** 958 * DMA memory functions 959 ***********************************************************/ 960 #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 961 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 962 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); 963 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error); 964 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring); 965 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc, 966 uint32_t q_len, uint32_t num_entries); 967 /************************************************************ 968 * oce_hw_xxx functions 969 ************************************************************/ 970 int oce_clear_rx_buf(struct oce_rq *rq); 971 int oce_hw_pci_alloc(POCE_SOFTC sc); 972 int oce_hw_init(POCE_SOFTC sc); 973 int oce_hw_start(POCE_SOFTC sc); 974 int oce_create_nw_interface(POCE_SOFTC sc); 975 int oce_pci_soft_reset(POCE_SOFTC sc); 976 int oce_hw_update_multicast(POCE_SOFTC sc); 977 void oce_delete_nw_interface(POCE_SOFTC sc); 978 void oce_hw_shutdown(POCE_SOFTC sc); 979 void oce_hw_intr_enable(POCE_SOFTC sc); 980 void oce_hw_intr_disable(POCE_SOFTC sc); 981 void oce_hw_pci_free(POCE_SOFTC sc); 982 983 /*********************************************************** 984 * oce_queue_xxx functions 985 ***********************************************************/ 986 int oce_queue_init_all(POCE_SOFTC sc); 987 int oce_start_rq(struct oce_rq *rq); 988 int oce_start_wq(struct oce_wq *wq); 989 int oce_start_mq(struct oce_mq *mq); 990 int oce_start_rx(POCE_SOFTC sc); 991 void oce_arm_eq(POCE_SOFTC sc, 992 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint); 993 void oce_queue_release_all(POCE_SOFTC sc); 994 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm); 995 void oce_drain_eq(struct oce_eq *eq); 996 void oce_drain_mq_cq(void *arg); 997 void oce_drain_rq_cq(struct oce_rq *rq); 998 void oce_drain_wq_cq(struct oce_wq *wq); 999 1000 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list); 1001 1002 /*********************************************************** 1003 * cleanup functions 1004 ***********************************************************/ 1005 void oce_stop_rx(POCE_SOFTC sc); 1006 void oce_discard_rx_comp(struct oce_rq *rq, int num_frags); 1007 void oce_rx_cq_clean(struct oce_rq *rq); 1008 void oce_rx_cq_clean_hwlro(struct oce_rq *rq); 1009 void oce_intr_free(POCE_SOFTC sc); 1010 void oce_free_posted_rxbuf(struct oce_rq *rq); 1011 #if defined(INET6) || defined(INET) 1012 void oce_free_lro(POCE_SOFTC sc); 1013 #endif 1014 1015 1016 /************************************************************ 1017 * Mailbox functions 1018 ************************************************************/ 1019 int oce_fw_clean(POCE_SOFTC sc); 1020 int oce_wait_ready(POCE_SOFTC sc); 1021 int oce_reset_fun(POCE_SOFTC sc); 1022 int oce_mbox_init(POCE_SOFTC sc); 1023 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec); 1024 int oce_get_fw_version(POCE_SOFTC sc); 1025 int oce_first_mcc_cmd(POCE_SOFTC sc); 1026 1027 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm, 1028 uint8_t type, struct mac_address_format *mac); 1029 int oce_get_fw_config(POCE_SOFTC sc); 1030 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags, 1031 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 1032 int oce_if_del(POCE_SOFTC sc, uint32_t if_id); 1033 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id, 1034 struct normal_vlan *vtag_arr, uint8_t vtag_cnt, 1035 uint32_t untagged, uint32_t enable_promisc); 1036 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control); 1037 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss); 1038 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable); 1039 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl); 1040 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link); 1041 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1042 int oce_mbox_get_nic_stats_v1(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1043 int oce_mbox_get_nic_stats_v2(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1044 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1045 uint32_t reset_stats); 1046 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1047 uint32_t req_size, uint32_t reset_stats); 1048 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem); 1049 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size); 1050 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id); 1051 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1052 uint32_t if_id, uint32_t *pmac_id); 1053 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1054 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1055 uint64_t pattern); 1056 1057 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1058 uint8_t loopback_type, uint8_t enable); 1059 1060 int oce_mbox_check_native_mode(POCE_SOFTC sc); 1061 int oce_mbox_post(POCE_SOFTC sc, 1062 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx); 1063 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1064 POCE_DMA_MEM pdma_mem, uint32_t num_bytes); 1065 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1066 uint32_t data_offset,POCE_DMA_MEM pdma_mem, 1067 uint32_t *written_data, uint32_t *additional_status); 1068 1069 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1070 uint32_t offset, uint32_t optype); 1071 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info); 1072 int oce_mbox_create_rq(struct oce_rq *rq); 1073 int oce_mbox_create_wq(struct oce_wq *wq); 1074 int oce_mbox_create_eq(struct oce_eq *eq); 1075 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 1076 uint32_t is_eventable); 1077 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num); 1078 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1079 int num); 1080 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss); 1081 int oce_get_func_config(POCE_SOFTC sc); 1082 void mbx_common_req_hdr_init(struct mbx_hdr *hdr, 1083 uint8_t dom, 1084 uint8_t port, 1085 uint8_t subsys, 1086 uint8_t opcode, 1087 uint32_t timeout, uint32_t pyld_len, 1088 uint8_t version); 1089 1090 1091 uint16_t oce_mq_handler(void *arg); 1092 1093 /************************************************************ 1094 * Transmit functions 1095 ************************************************************/ 1096 uint16_t oce_wq_handler(void *arg); 1097 void oce_start(struct ifnet *ifp); 1098 void oce_tx_task(void *arg, int npending); 1099 1100 /************************************************************ 1101 * Receive functions 1102 ************************************************************/ 1103 int oce_alloc_rx_bufs(struct oce_rq *rq, int count); 1104 uint16_t oce_rq_handler(void *arg); 1105 1106 1107 /* Sysctl functions */ 1108 void oce_add_sysctls(POCE_SOFTC sc); 1109 void oce_refresh_queue_stats(POCE_SOFTC sc); 1110 int oce_refresh_nic_stats(POCE_SOFTC sc); 1111 int oce_stats_init(POCE_SOFTC sc); 1112 void oce_stats_free(POCE_SOFTC sc); 1113 1114 /* hw lro functions */ 1115 int oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags); 1116 int oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable); 1117 int oce_mbox_create_rq_v2(struct oce_rq *rq); 1118 1119 /* Capabilities */ 1120 #define OCE_MODCAP_RSS 1 1121 #define OCE_MAX_RSP_HANDLED 64 1122 extern uint32_t oce_max_rsp_handled; /* max responses */ 1123 extern uint32_t oce_rq_buf_size; 1124 1125 #define OCE_MAC_LOOPBACK 0x0 1126 #define OCE_PHY_LOOPBACK 0x1 1127 #define OCE_ONE_PORT_EXT_LOOPBACK 0x2 1128 #define OCE_NO_LOOPBACK 0xff 1129 1130 #undef IFM_40G_SR4 1131 #define IFM_40G_SR4 28 1132 1133 #define atomic_inc_32(x) atomic_add_32(x, 1) 1134 #define atomic_dec_32(x) atomic_subtract_32(x, 1) 1135 1136 #define LE_64(x) htole64(x) 1137 #define LE_32(x) htole32(x) 1138 #define LE_16(x) htole16(x) 1139 #define HOST_64(x) le64toh(x) 1140 #define HOST_32(x) le32toh(x) 1141 #define HOST_16(x) le16toh(x) 1142 #define DW_SWAP(x, l) 1143 #define IS_ALIGNED(x,a) ((x % a) == 0) 1144 #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 1145 #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 1146 1147 #define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 1148 #define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 1149 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) 1150 1151 #define OCE_LOG2(x) (oce_highbit(x)) 1152 static inline uint32_t oce_highbit(uint32_t x) 1153 { 1154 int i; 1155 int c; 1156 int b; 1157 1158 c = 0; 1159 b = 0; 1160 1161 for (i = 0; i < 32; i++) { 1162 if ((1 << i) & x) { 1163 c++; 1164 b = i; 1165 } 1166 } 1167 1168 if (c == 1) 1169 return b; 1170 1171 return 0; 1172 } 1173 1174 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc) 1175 { 1176 if (IS_BE(sc)) 1177 return MPU_EP_SEMAPHORE_BE3; 1178 else if (IS_SH(sc)) 1179 return MPU_EP_SEMAPHORE_SH; 1180 else 1181 return MPU_EP_SEMAPHORE_XE201; 1182 } 1183 1184 #define TRANSCEIVER_DATA_NUM_ELE 64 1185 #define TRANSCEIVER_DATA_SIZE 256 1186 #define TRANSCEIVER_A0_SIZE 128 1187 #define TRANSCEIVER_A2_SIZE 128 1188 #define PAGE_NUM_A0 0xa0 1189 #define PAGE_NUM_A2 0xa2 1190 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\ 1191 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE))) 1192 extern uint8_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_SIZE]; 1193 1194 struct oce_rdma_info; 1195 extern struct oce_rdma_if *oce_rdma_if; 1196 1197 1198 1199 /* OS2BMC related */ 1200 1201 #define DHCP_CLIENT_PORT 68 1202 #define DHCP_SERVER_PORT 67 1203 #define NET_BIOS_PORT1 137 1204 #define NET_BIOS_PORT2 138 1205 #define DHCPV6_RAS_PORT 547 1206 1207 #define BMC_FILT_BROADCAST_ARP ((uint32_t)(1)) 1208 #define BMC_FILT_BROADCAST_DHCP_CLIENT ((uint32_t)(1 << 1)) 1209 #define BMC_FILT_BROADCAST_DHCP_SERVER ((uint32_t)(1 << 2)) 1210 #define BMC_FILT_BROADCAST_NET_BIOS ((uint32_t)(1 << 3)) 1211 #define BMC_FILT_BROADCAST ((uint32_t)(1 << 4)) 1212 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER ((uint32_t)(1 << 5)) 1213 #define BMC_FILT_MULTICAST_IPV6_RA ((uint32_t)(1 << 6)) 1214 #define BMC_FILT_MULTICAST_IPV6_RAS ((uint32_t)(1 << 7)) 1215 #define BMC_FILT_MULTICAST ((uint32_t)(1 << 8)) 1216 1217 #define ND_ROUTER_ADVERT 134 1218 #define ND_NEIGHBOR_ADVERT 136 1219 1220 #define is_mc_allowed_on_bmc(sc, eh) \ 1221 (!is_multicast_filt_enabled(sc) && \ 1222 ETHER_IS_MULTICAST(eh->ether_dhost) && \ 1223 !ETHER_IS_BROADCAST(eh->ether_dhost)) 1224 1225 #define is_bc_allowed_on_bmc(sc, eh) \ 1226 (!is_broadcast_filt_enabled(sc) && \ 1227 ETHER_IS_BROADCAST(eh->ether_dhost)) 1228 1229 #define is_arp_allowed_on_bmc(sc, et) \ 1230 (is_arp(et) && is_arp_filt_enabled(sc)) 1231 1232 #define is_arp(et) (et == ETHERTYPE_ARP) 1233 1234 #define is_arp_filt_enabled(sc) \ 1235 (sc->bmc_filt_mask & (BMC_FILT_BROADCAST_ARP)) 1236 1237 #define is_dhcp_client_filt_enabled(sc) \ 1238 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_CLIENT) 1239 1240 #define is_dhcp_srvr_filt_enabled(sc) \ 1241 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_SERVER) 1242 1243 #define is_nbios_filt_enabled(sc) \ 1244 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_NET_BIOS) 1245 1246 #define is_ipv6_na_filt_enabled(sc) \ 1247 (sc->bmc_filt_mask & \ 1248 BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER) 1249 1250 #define is_ipv6_ra_filt_enabled(sc) \ 1251 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RA) 1252 1253 #define is_ipv6_ras_filt_enabled(sc) \ 1254 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RAS) 1255 1256 #define is_broadcast_filt_enabled(sc) \ 1257 (sc->bmc_filt_mask & BMC_FILT_BROADCAST) 1258 1259 #define is_multicast_filt_enabled(sc) \ 1260 (sc->bmc_filt_mask & BMC_FILT_MULTICAST) 1261 1262 #define is_os2bmc_enabled(sc) (sc->flags & OCE_FLAGS_OS2BMC) 1263 1264 #define LRO_FLAGS_HASH_MODE 0x00000001 1265 #define LRO_FLAGS_RSS_MODE 0x00000004 1266 #define LRO_FLAGS_CLSC_IPV4 0x00000010 1267 #define LRO_FLAGS_CLSC_IPV6 0x00000020 1268 #define NIC_RQ_FLAGS_RSS 0x0001 1269 #define NIC_RQ_FLAGS_LRO 0x0020 1270
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