Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/oce/oce_mbox.c
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2013 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 /* $FreeBSD$ */ 42 43 #include "oce_if.h" 44 45 int 46 oce_wait_ready(POCE_SOFTC sc) 47 { 48 #define SLIPORT_READY_TIMEOUT 30000 49 uint32_t sliport_status, i; 50 51 if (!IS_XE201(sc)) 52 return (-1); 53 54 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { 55 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET); 56 if (sliport_status & SLIPORT_STATUS_RDY_MASK) 57 return 0; 58 59 if (sliport_status & SLIPORT_STATUS_ERR_MASK && 60 !(sliport_status & SLIPORT_STATUS_RN_MASK)) { 61 device_printf(sc->dev, "Error detected in the card\n"); 62 return EIO; 63 } 64 65 DELAY(1000); 66 } 67 68 device_printf(sc->dev, "Firmware wait timed out\n"); 69 70 return (-1); 71 } 72 73 /** 74 * @brief Reset (firmware) common function 75 * @param sc software handle to the device 76 * @returns 0 on success, ETIMEDOUT on failure 77 */ 78 int 79 oce_reset_fun(POCE_SOFTC sc) 80 { 81 struct oce_mbx *mbx; 82 struct oce_bmbx *mb; 83 struct ioctl_common_function_reset *fwcmd; 84 int rc = 0; 85 86 if (IS_XE201(sc)) { 87 OCE_WRITE_REG32(sc, db, SLIPORT_CONTROL_OFFSET, 88 SLI_PORT_CONTROL_IP_MASK); 89 90 rc = oce_wait_ready(sc); 91 if (rc) { 92 device_printf(sc->dev, "Firmware reset Failed\n"); 93 } 94 95 return rc; 96 } 97 98 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 99 mbx = &mb->mbx; 100 bzero(mbx, sizeof(struct oce_mbx)); 101 102 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload; 103 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 104 MBX_SUBSYSTEM_COMMON, 105 OPCODE_COMMON_FUNCTION_RESET, 106 10, /* MBX_TIMEOUT_SEC */ 107 sizeof(struct 108 ioctl_common_function_reset), 109 OCE_MBX_VER_V0); 110 111 mbx->u0.s.embedded = 1; 112 mbx->payload_length = 113 sizeof(struct ioctl_common_function_reset); 114 115 rc = oce_mbox_dispatch(sc, 2); 116 117 return rc; 118 } 119 120 /** 121 * @brief This functions tells firmware we are 122 * done with commands. 123 * @param sc software handle to the device 124 * @returns 0 on success, ETIMEDOUT on failure 125 */ 126 int 127 oce_fw_clean(POCE_SOFTC sc) 128 { 129 struct oce_bmbx *mbx; 130 uint8_t *ptr; 131 int ret = 0; 132 133 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 134 ptr = (uint8_t *) &mbx->mbx; 135 136 /* Endian Signature */ 137 *ptr++ = 0xff; 138 *ptr++ = 0xaa; 139 *ptr++ = 0xbb; 140 *ptr++ = 0xff; 141 *ptr++ = 0xff; 142 *ptr++ = 0xcc; 143 *ptr++ = 0xdd; 144 *ptr = 0xff; 145 146 ret = oce_mbox_dispatch(sc, 2); 147 148 return ret; 149 } 150 151 /** 152 * @brief Mailbox wait 153 * @param sc software handle to the device 154 * @param tmo_sec timeout in seconds 155 */ 156 static int 157 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec) 158 { 159 tmo_sec *= 10000; 160 pd_mpu_mbox_db_t mbox_db; 161 162 for (;;) { 163 if (tmo_sec != 0) { 164 if (--tmo_sec == 0) 165 break; 166 } 167 168 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB); 169 170 if (mbox_db.bits.ready) 171 return 0; 172 173 DELAY(100); 174 } 175 176 device_printf(sc->dev, "Mailbox timed out\n"); 177 178 return ETIMEDOUT; 179 } 180 181 /** 182 * @brief Mailbox dispatch 183 * @param sc software handle to the device 184 * @param tmo_sec timeout in seconds 185 */ 186 int 187 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec) 188 { 189 pd_mpu_mbox_db_t mbox_db; 190 uint32_t pa; 191 int rc; 192 193 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE); 194 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34); 195 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t)); 196 mbox_db.bits.ready = 0; 197 mbox_db.bits.hi = 1; 198 mbox_db.bits.address = pa; 199 200 rc = oce_mbox_wait(sc, tmo_sec); 201 if (rc == 0) { 202 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0); 203 204 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff; 205 mbox_db.bits.ready = 0; 206 mbox_db.bits.hi = 0; 207 mbox_db.bits.address = pa; 208 209 rc = oce_mbox_wait(sc, tmo_sec); 210 211 if (rc == 0) { 212 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0); 213 214 rc = oce_mbox_wait(sc, tmo_sec); 215 216 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE); 217 } 218 } 219 220 return rc; 221 } 222 223 /** 224 * @brief Mailbox common request header initialization 225 * @param hdr mailbox header 226 * @param dom domain 227 * @param port port 228 * @param subsys subsystem 229 * @param opcode opcode 230 * @param timeout timeout 231 * @param pyld_len payload length 232 */ 233 void 234 mbx_common_req_hdr_init(struct mbx_hdr *hdr, 235 uint8_t dom, uint8_t port, 236 uint8_t subsys, uint8_t opcode, 237 uint32_t timeout, uint32_t pyld_len, 238 uint8_t version) 239 { 240 hdr->u0.req.opcode = opcode; 241 hdr->u0.req.subsystem = subsys; 242 hdr->u0.req.port_number = port; 243 hdr->u0.req.domain = dom; 244 245 hdr->u0.req.timeout = timeout; 246 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr); 247 hdr->u0.req.version = version; 248 } 249 250 /** 251 * @brief Function to initialize the hw with host endian information 252 * @param sc software handle to the device 253 * @returns 0 on success, ETIMEDOUT on failure 254 */ 255 int 256 oce_mbox_init(POCE_SOFTC sc) 257 { 258 struct oce_bmbx *mbx; 259 uint8_t *ptr; 260 int ret = 0; 261 262 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) { 263 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 264 ptr = (uint8_t *) &mbx->mbx; 265 266 /* Endian Signature */ 267 *ptr++ = 0xff; 268 *ptr++ = 0x12; 269 *ptr++ = 0x34; 270 *ptr++ = 0xff; 271 *ptr++ = 0xff; 272 *ptr++ = 0x56; 273 *ptr++ = 0x78; 274 *ptr = 0xff; 275 276 ret = oce_mbox_dispatch(sc, 0); 277 } 278 279 return ret; 280 } 281 282 /** 283 * @brief Function to get the firmware version 284 * @param sc software handle to the device 285 * @returns 0 on success, EIO on failure 286 */ 287 int 288 oce_get_fw_version(POCE_SOFTC sc) 289 { 290 struct oce_mbx mbx; 291 struct mbx_get_common_fw_version *fwcmd; 292 int ret = 0; 293 294 bzero(&mbx, sizeof(struct oce_mbx)); 295 296 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload; 297 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 298 MBX_SUBSYSTEM_COMMON, 299 OPCODE_COMMON_GET_FW_VERSION, 300 MBX_TIMEOUT_SEC, 301 sizeof(struct mbx_get_common_fw_version), 302 OCE_MBX_VER_V0); 303 304 mbx.u0.s.embedded = 1; 305 mbx.payload_length = sizeof(struct mbx_get_common_fw_version); 306 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 307 308 ret = oce_mbox_post(sc, &mbx, NULL); 309 if (!ret) 310 ret = fwcmd->hdr.u0.rsp.status; 311 if (ret) { 312 device_printf(sc->dev, 313 "%s failed - cmd status: %d addi status: %d\n", 314 __FUNCTION__, ret, 315 fwcmd->hdr.u0.rsp.additional_status); 316 goto error; 317 } 318 319 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32); 320 error: 321 return ret; 322 } 323 324 /** 325 * @brief Firmware will send gracious notifications during 326 * attach only after sending first mcc commnad. We 327 * use MCC queue only for getting async and mailbox 328 * for sending cmds. So to get gracious notifications 329 * atleast send one dummy command on mcc. 330 */ 331 int 332 oce_first_mcc_cmd(POCE_SOFTC sc) 333 { 334 struct oce_mbx *mbx; 335 struct oce_mq *mq = sc->mq; 336 struct mbx_get_common_fw_version *fwcmd; 337 uint32_t reg_value; 338 339 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx); 340 bzero(mbx, sizeof(struct oce_mbx)); 341 342 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload; 343 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 344 MBX_SUBSYSTEM_COMMON, 345 OPCODE_COMMON_GET_FW_VERSION, 346 MBX_TIMEOUT_SEC, 347 sizeof(struct mbx_get_common_fw_version), 348 OCE_MBX_VER_V0); 349 mbx->u0.s.embedded = 1; 350 mbx->payload_length = sizeof(struct mbx_get_common_fw_version); 351 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map, 352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 353 RING_PUT(mq->ring, 1); 354 reg_value = (1 << 16) | mq->mq_id; 355 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value); 356 357 return 0; 358 } 359 360 /** 361 * @brief Function to post a MBX to the mbox 362 * @param sc software handle to the device 363 * @param mbx pointer to the MBX to send 364 * @param mbxctx pointer to the mbx context structure 365 * @returns 0 on success, error on failure 366 */ 367 int 368 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx) 369 { 370 struct oce_mbx *mb_mbx = NULL; 371 struct oce_mq_cqe *mb_cqe = NULL; 372 struct oce_bmbx *mb = NULL; 373 int rc = 0; 374 uint32_t tmo = 0; 375 uint32_t cstatus = 0; 376 377 LOCK(&sc->bmbx_lock); 378 379 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 380 mb_mbx = &mb->mbx; 381 382 /* get the tmo */ 383 tmo = mbx->tag[0]; 384 mbx->tag[0] = 0; 385 386 /* copy mbx into mbox */ 387 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx)); 388 389 /* now dispatch */ 390 rc = oce_mbox_dispatch(sc, tmo); 391 if (rc == 0) { 392 /* 393 * the command completed successfully. Now get the 394 * completion queue entry 395 */ 396 mb_cqe = &mb->cqe; 397 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe)); 398 399 /* copy mbox mbx back */ 400 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx)); 401 402 /* pick up the mailbox status */ 403 cstatus = mb_cqe->u0.s.completion_status; 404 405 /* 406 * store the mbx context in the cqe tag section so that 407 * the upper layer handling the cqe can associate the mbx 408 * with the response 409 */ 410 if (cstatus == 0 && mbxctx) { 411 /* save context */ 412 mbxctx->mbx = mb_mbx; 413 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag, 414 sizeof(struct oce_mbx_ctx *)); 415 } 416 } 417 418 UNLOCK(&sc->bmbx_lock); 419 420 return rc; 421 } 422 423 /** 424 * @brief Function to read the mac address associated with an interface 425 * @param sc software handle to the device 426 * @param if_id interface id to read the address from 427 * @param perm set to 1 if reading the factory mac address. 428 * In this case if_id is ignored 429 * @param type type of the mac address, whether network or storage 430 * @param[out] mac [OUTPUT] pointer to a buffer containing the 431 * mac address when the command succeeds. 432 * @returns 0 on success, EIO on failure 433 */ 434 int 435 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, 436 uint8_t perm, uint8_t type, struct mac_address_format *mac) 437 { 438 struct oce_mbx mbx; 439 struct mbx_query_common_iface_mac *fwcmd; 440 int ret = 0; 441 442 bzero(&mbx, sizeof(struct oce_mbx)); 443 444 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload; 445 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 446 MBX_SUBSYSTEM_COMMON, 447 OPCODE_COMMON_QUERY_IFACE_MAC, 448 MBX_TIMEOUT_SEC, 449 sizeof(struct mbx_query_common_iface_mac), 450 OCE_MBX_VER_V0); 451 452 fwcmd->params.req.permanent = perm; 453 if (!perm) 454 fwcmd->params.req.if_id = (uint16_t) if_id; 455 else 456 fwcmd->params.req.if_id = 0; 457 458 fwcmd->params.req.type = type; 459 460 mbx.u0.s.embedded = 1; 461 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac); 462 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 463 464 ret = oce_mbox_post(sc, &mbx, NULL); 465 if (!ret) 466 ret = fwcmd->hdr.u0.rsp.status; 467 if (ret) { 468 device_printf(sc->dev, 469 "%s failed - cmd status: %d addi status: %d\n", 470 __FUNCTION__, ret, 471 fwcmd->hdr.u0.rsp.additional_status); 472 goto error; 473 } 474 475 /* copy the mac addres in the output parameter */ 476 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct; 477 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0], 478 mac->size_of_struct); 479 error: 480 return ret; 481 } 482 483 /** 484 * @brief Function to query the fw attributes from the hw 485 * @param sc software handle to the device 486 * @returns 0 on success, EIO on failure 487 */ 488 int 489 oce_get_fw_config(POCE_SOFTC sc) 490 { 491 struct oce_mbx mbx; 492 struct mbx_common_query_fw_config *fwcmd; 493 int ret = 0; 494 495 bzero(&mbx, sizeof(struct oce_mbx)); 496 497 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload; 498 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 499 MBX_SUBSYSTEM_COMMON, 500 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, 501 MBX_TIMEOUT_SEC, 502 sizeof(struct mbx_common_query_fw_config), 503 OCE_MBX_VER_V0); 504 505 mbx.u0.s.embedded = 1; 506 mbx.payload_length = sizeof(struct mbx_common_query_fw_config); 507 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 508 509 ret = oce_mbox_post(sc, &mbx, NULL); 510 if (!ret) 511 ret = fwcmd->hdr.u0.rsp.status; 512 if (ret) { 513 device_printf(sc->dev, 514 "%s failed - cmd status: %d addi status: %d\n", 515 __FUNCTION__, ret, 516 fwcmd->hdr.u0.rsp.additional_status); 517 goto error; 518 } 519 520 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config)); 521 522 sc->config_number = HOST_32(fwcmd->params.rsp.config_number); 523 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision); 524 sc->port_id = HOST_32(fwcmd->params.rsp.port_id); 525 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode); 526 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) == 527 (ULP_NIC_MODE | ULP_RDMA_MODE)) { 528 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED; 529 } 530 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps); 531 532 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) { 533 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot); 534 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot); 535 } else { 536 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot); 537 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot); 538 } 539 540 error: 541 return ret; 542 543 } 544 545 /** 546 * 547 * @brief function to create a device interface 548 * @param sc software handle to the device 549 * @param cap_flags capability flags 550 * @param en_flags enable capability flags 551 * @param vlan_tag optional vlan tag to associate with the if 552 * @param mac_addr pointer to a buffer containing the mac address 553 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the 554 interface created 555 * @returns 0 on success, EIO on failure 556 */ 557 int 558 oce_if_create(POCE_SOFTC sc, 559 uint32_t cap_flags, 560 uint32_t en_flags, 561 uint16_t vlan_tag, 562 uint8_t *mac_addr, 563 uint32_t *if_id) 564 { 565 struct oce_mbx mbx; 566 struct mbx_create_common_iface *fwcmd; 567 int rc = 0; 568 569 bzero(&mbx, sizeof(struct oce_mbx)); 570 571 fwcmd = (struct mbx_create_common_iface *)&mbx.payload; 572 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 573 MBX_SUBSYSTEM_COMMON, 574 OPCODE_COMMON_CREATE_IFACE, 575 MBX_TIMEOUT_SEC, 576 sizeof(struct mbx_create_common_iface), 577 OCE_MBX_VER_V0); 578 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr)); 579 580 fwcmd->params.req.version = 0; 581 fwcmd->params.req.cap_flags = LE_32(cap_flags); 582 fwcmd->params.req.enable_flags = LE_32(en_flags); 583 if (mac_addr != NULL) { 584 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6); 585 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag); 586 fwcmd->params.req.mac_invalid = 0; 587 } else { 588 fwcmd->params.req.mac_invalid = 1; 589 } 590 591 mbx.u0.s.embedded = 1; 592 mbx.payload_length = sizeof(struct mbx_create_common_iface); 593 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ); 594 595 rc = oce_mbox_post(sc, &mbx, NULL); 596 if (!rc) 597 rc = fwcmd->hdr.u0.rsp.status; 598 if (rc) { 599 device_printf(sc->dev, 600 "%s failed - cmd status: %d addi status: %d\n", 601 __FUNCTION__, rc, 602 fwcmd->hdr.u0.rsp.additional_status); 603 goto error; 604 } 605 606 *if_id = HOST_32(fwcmd->params.rsp.if_id); 607 608 if (mac_addr != NULL) 609 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id); 610 error: 611 return rc; 612 } 613 614 /** 615 * @brief Function to delete an interface 616 * @param sc software handle to the device 617 * @param if_id ID of the interface to delete 618 * @returns 0 on success, EIO on failure 619 */ 620 int 621 oce_if_del(POCE_SOFTC sc, uint32_t if_id) 622 { 623 struct oce_mbx mbx; 624 struct mbx_destroy_common_iface *fwcmd; 625 int rc = 0; 626 627 bzero(&mbx, sizeof(struct oce_mbx)); 628 629 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload; 630 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 631 MBX_SUBSYSTEM_COMMON, 632 OPCODE_COMMON_DESTROY_IFACE, 633 MBX_TIMEOUT_SEC, 634 sizeof(struct mbx_destroy_common_iface), 635 OCE_MBX_VER_V0); 636 637 fwcmd->params.req.if_id = if_id; 638 639 mbx.u0.s.embedded = 1; 640 mbx.payload_length = sizeof(struct mbx_destroy_common_iface); 641 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 642 643 rc = oce_mbox_post(sc, &mbx, NULL); 644 if (!rc) 645 rc = fwcmd->hdr.u0.rsp.status; 646 if (rc) 647 device_printf(sc->dev, 648 "%s failed - cmd status: %d addi status: %d\n", 649 __FUNCTION__, rc, 650 fwcmd->hdr.u0.rsp.additional_status); 651 return rc; 652 } 653 654 /** 655 * @brief Function to send the mbx command to configure vlan 656 * @param sc software handle to the device 657 * @param if_id interface identifier index 658 * @param vtag_arr array of vlan tags 659 * @param vtag_cnt number of elements in array 660 * @param untagged boolean TRUE/FLASE 661 * @param enable_promisc flag to enable/disable VLAN promiscuous mode 662 * @returns 0 on success, EIO on failure 663 */ 664 int 665 oce_config_vlan(POCE_SOFTC sc, 666 uint32_t if_id, 667 struct normal_vlan *vtag_arr, 668 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc) 669 { 670 struct oce_mbx mbx; 671 struct mbx_common_config_vlan *fwcmd; 672 int rc = 0; 673 674 if (sc->vlans_added > sc->max_vlans) 675 goto vlan_promisc; 676 677 bzero(&mbx, sizeof(struct oce_mbx)); 678 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload; 679 680 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 681 MBX_SUBSYSTEM_COMMON, 682 OPCODE_COMMON_CONFIG_IFACE_VLAN, 683 MBX_TIMEOUT_SEC, 684 sizeof(struct mbx_common_config_vlan), 685 OCE_MBX_VER_V0); 686 687 fwcmd->params.req.if_id = (uint8_t) if_id; 688 fwcmd->params.req.promisc = (uint8_t) enable_promisc; 689 fwcmd->params.req.untagged = (uint8_t) untagged; 690 fwcmd->params.req.num_vlans = vtag_cnt; 691 692 if (!enable_promisc) { 693 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans, 694 vtag_cnt * sizeof(struct normal_vlan)); 695 } 696 mbx.u0.s.embedded = 1; 697 mbx.payload_length = sizeof(struct mbx_common_config_vlan); 698 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length)); 699 700 rc = oce_mbox_post(sc, &mbx, NULL); 701 if (!rc) 702 rc = fwcmd->hdr.u0.rsp.status; 703 if (rc) 704 device_printf(sc->dev, 705 "%s failed - cmd status: %d addi status: %d\n", 706 __FUNCTION__, rc, 707 fwcmd->hdr.u0.rsp.additional_status); 708 709 goto done; 710 711 vlan_promisc: 712 /* Enable Vlan Promis */ 713 oce_rxf_set_promiscuous(sc, (1 << 1)); 714 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n"); 715 done: 716 return rc; 717 718 } 719 720 /** 721 * @brief Function to set flow control capability in the hardware 722 * @param sc software handle to the device 723 * @param flow_control flow control flags to set 724 * @returns 0 on success, EIO on failure 725 */ 726 int 727 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control) 728 { 729 struct oce_mbx mbx; 730 struct mbx_common_get_set_flow_control *fwcmd = 731 (struct mbx_common_get_set_flow_control *)&mbx.payload; 732 int rc; 733 734 bzero(&mbx, sizeof(struct oce_mbx)); 735 736 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 737 MBX_SUBSYSTEM_COMMON, 738 OPCODE_COMMON_SET_FLOW_CONTROL, 739 MBX_TIMEOUT_SEC, 740 sizeof(struct mbx_common_get_set_flow_control), 741 OCE_MBX_VER_V0); 742 743 if (flow_control & OCE_FC_TX) 744 fwcmd->tx_flow_control = 1; 745 746 if (flow_control & OCE_FC_RX) 747 fwcmd->rx_flow_control = 1; 748 749 mbx.u0.s.embedded = 1; 750 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control); 751 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 752 753 rc = oce_mbox_post(sc, &mbx, NULL); 754 if (!rc) 755 rc = fwcmd->hdr.u0.rsp.status; 756 if (rc) 757 device_printf(sc->dev, 758 "%s failed - cmd status: %d addi status: %d\n", 759 __FUNCTION__, rc, 760 fwcmd->hdr.u0.rsp.additional_status); 761 return rc; 762 } 763 764 /** 765 * @brief Initialize the RSS CPU indirection table 766 * 767 * The table is used to choose the queue to place the incomming packets. 768 * Incomming packets are hashed. The lowest bits in the hash result 769 * are used as the index into the CPU indirection table. 770 * Each entry in the table contains the RSS CPU-ID returned by the NIC 771 * create. Based on the CPU ID, the receive completion is routed to 772 * the corresponding RSS CQs. (Non-RSS packets are always completed 773 * on the default (0) CQ). 774 * 775 * @param sc software handle to the device 776 * @param *fwcmd pointer to the rss mbox command 777 * @returns none 778 */ 779 static int 780 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd) 781 { 782 int i = 0, j = 0, rc = 0; 783 uint8_t *tbl = fwcmd->params.req.cputable; 784 struct oce_rq *rq = NULL; 785 786 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) { 787 for_all_rss_queues(sc, rq, i) { 788 if ((j + i) >= INDIRECTION_TABLE_ENTRIES) 789 break; 790 tbl[j + i] = rq->rss_cpuid; 791 } 792 } 793 if (i == 0) { 794 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n"); 795 rc = ENXIO; 796 797 } 798 799 /* fill log2 value indicating the size of the CPU table */ 800 if (rc == 0) 801 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES)); 802 803 return rc; 804 } 805 806 /** 807 * @brief Function to set flow control capability in the hardware 808 * @param sc software handle to the device 809 * @param if_id interface id to read the address from 810 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise 811 * @returns 0 on success, EIO on failure 812 */ 813 int 814 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss) 815 { 816 int rc; 817 struct oce_mbx mbx; 818 struct mbx_config_nic_rss *fwcmd = 819 (struct mbx_config_nic_rss *)&mbx.payload; 820 int version; 821 822 bzero(&mbx, sizeof(struct oce_mbx)); 823 824 if (IS_XE201(sc) || IS_SH(sc)) { 825 version = OCE_MBX_VER_V1; 826 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 | 827 RSS_ENABLE_UDP_IPV6; 828 } else 829 version = OCE_MBX_VER_V0; 830 831 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 832 MBX_SUBSYSTEM_NIC, 833 NIC_CONFIG_RSS, 834 MBX_TIMEOUT_SEC, 835 sizeof(struct mbx_config_nic_rss), 836 version); 837 if (enable_rss) 838 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 | 839 RSS_ENABLE_TCP_IPV4 | 840 RSS_ENABLE_IPV6 | 841 RSS_ENABLE_TCP_IPV6); 842 843 if(!sc->enable_hwlro) 844 fwcmd->params.req.flush = OCE_FLUSH; 845 else 846 fwcmd->params.req.flush = 0; 847 848 fwcmd->params.req.if_id = LE_32(if_id); 849 850 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash)); 851 852 rc = oce_rss_itbl_init(sc, fwcmd); 853 if (rc == 0) { 854 mbx.u0.s.embedded = 1; 855 mbx.payload_length = sizeof(struct mbx_config_nic_rss); 856 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 857 858 rc = oce_mbox_post(sc, &mbx, NULL); 859 if (!rc) 860 rc = fwcmd->hdr.u0.rsp.status; 861 if (rc) 862 device_printf(sc->dev, 863 "%s failed - cmd status: %d addi status: %d\n", 864 __FUNCTION__, rc, 865 fwcmd->hdr.u0.rsp.additional_status); 866 } 867 return rc; 868 } 869 870 /** 871 * @brief RXF function to enable/disable device promiscuous mode 872 * @param sc software handle to the device 873 * @param enable enable/disable flag 874 * @returns 0 on success, EIO on failure 875 * @note 876 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer. 877 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead. 878 */ 879 int 880 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable) 881 { 882 struct mbx_set_common_iface_rx_filter *fwcmd; 883 int sz = sizeof(struct mbx_set_common_iface_rx_filter); 884 iface_rx_filter_ctx_t *req; 885 OCE_DMA_MEM sgl; 886 int rc; 887 888 /* allocate mbx payload's dma scatter/gather memory */ 889 rc = oce_dma_alloc(sc, sz, &sgl, 0); 890 if (rc) 891 return rc; 892 893 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter); 894 895 req = &fwcmd->params.req; 896 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS | 897 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS; 898 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */ 899 if (enable & 0x01) 900 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS; 901 902 if (enable & 0x02) 903 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS; 904 905 req->if_id = sc->if_id; 906 907 rc = oce_set_common_iface_rx_filter(sc, &sgl); 908 oce_dma_free(sc, &sgl); 909 910 return rc; 911 } 912 913 /** 914 * @brief Function modify and select rx filter options 915 * @param sc software handle to the device 916 * @param sgl scatter/gather request/response 917 * @returns 0 on success, error code on failure 918 */ 919 int 920 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl) 921 { 922 struct oce_mbx mbx; 923 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter); 924 struct mbx_set_common_iface_rx_filter *fwcmd; 925 int rc; 926 927 bzero(&mbx, sizeof(struct oce_mbx)); 928 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter); 929 930 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 931 MBX_SUBSYSTEM_COMMON, 932 OPCODE_COMMON_SET_IFACE_RX_FILTER, 933 MBX_TIMEOUT_SEC, 934 mbx_sz, 935 OCE_MBX_VER_V0); 936 937 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE); 938 mbx.u0.s.embedded = 0; 939 mbx.u0.s.sge_count = 1; 940 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr); 941 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr); 942 mbx.payload.u0.u1.sgl[0].length = mbx_sz; 943 mbx.payload_length = mbx_sz; 944 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 945 946 rc = oce_mbox_post(sc, &mbx, NULL); 947 if (!rc) 948 rc = fwcmd->hdr.u0.rsp.status; 949 if (rc) 950 device_printf(sc->dev, 951 "%s failed - cmd status: %d addi status: %d\n", 952 __FUNCTION__, rc, 953 fwcmd->hdr.u0.rsp.additional_status); 954 return rc; 955 } 956 957 /** 958 * @brief Function to query the link status from the hardware 959 * @param sc software handle to the device 960 * @param[out] link pointer to the structure returning link attributes 961 * @returns 0 on success, EIO on failure 962 */ 963 int 964 oce_get_link_status(POCE_SOFTC sc, struct link_status *link) 965 { 966 struct oce_mbx mbx; 967 struct mbx_query_common_link_config *fwcmd; 968 int rc = 0, version; 969 970 bzero(&mbx, sizeof(struct oce_mbx)); 971 972 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1); 973 974 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload; 975 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 976 MBX_SUBSYSTEM_COMMON, 977 OPCODE_COMMON_QUERY_LINK_CONFIG, 978 MBX_TIMEOUT_SEC, 979 sizeof(struct mbx_query_common_link_config), 980 version); 981 982 mbx.u0.s.embedded = 1; 983 mbx.payload_length = sizeof(struct mbx_query_common_link_config); 984 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 985 986 rc = oce_mbox_post(sc, &mbx, NULL); 987 988 if (!rc) 989 rc = fwcmd->hdr.u0.rsp.status; 990 if (rc) { 991 device_printf(sc->dev, 992 "%s failed - cmd status: %d addi status: %d\n", 993 __FUNCTION__, rc, 994 fwcmd->hdr.u0.rsp.additional_status); 995 goto error; 996 } 997 /* interpret response */ 998 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed); 999 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed; 1000 link->logical_link_status = fwcmd->params.rsp.logical_link_status; 1001 error: 1002 return rc; 1003 } 1004 1005 /** 1006 * @brief Function to get NIC statistics 1007 * @param sc software handle to the device 1008 * @param *stats pointer to where to store statistics 1009 * @param reset_stats resets statistics of set 1010 * @returns 0 on success, EIO on failure 1011 * @note command depricated in Lancer 1012 */ 1013 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \ 1014 int \ 1015 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \ 1016 { \ 1017 struct oce_mbx mbx; \ 1018 struct mbx_get_nic_stats_v##version *fwcmd; \ 1019 int rc = 0; \ 1020 \ 1021 bzero(&mbx, sizeof(struct oce_mbx)); \ 1022 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \ 1023 bzero(fwcmd, sizeof(*fwcmd)); \ 1024 \ 1025 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \ 1026 MBX_SUBSYSTEM_NIC, \ 1027 NIC_GET_STATS, \ 1028 MBX_TIMEOUT_SEC, \ 1029 sizeof(*fwcmd), \ 1030 OCE_MBX_VER_V##version); \ 1031 \ 1032 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \ 1033 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \ 1034 \ 1035 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \ 1036 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \ 1037 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \ 1038 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \ 1039 mbx.payload_length = sizeof(*fwcmd); \ 1040 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \ 1041 \ 1042 rc = oce_mbox_post(sc, &mbx, NULL); \ 1043 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \ 1044 if (!rc) \ 1045 rc = fwcmd->hdr.u0.rsp.status; \ 1046 if (rc) \ 1047 device_printf(sc->dev, \ 1048 "%s failed - cmd status: %d addi status: %d\n", \ 1049 __FUNCTION__, rc, \ 1050 fwcmd->hdr.u0.rsp.additional_status); \ 1051 return rc; \ 1052 } 1053 1054 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0); 1055 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1); 1056 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2); 1057 1058 /** 1059 * @brief Function to get pport (physical port) statistics 1060 * @param sc software handle to the device 1061 * @param *stats pointer to where to store statistics 1062 * @param reset_stats resets statistics of set 1063 * @returns 0 on success, EIO on failure 1064 */ 1065 int 1066 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1067 uint32_t reset_stats) 1068 { 1069 struct oce_mbx mbx; 1070 struct mbx_get_pport_stats *fwcmd; 1071 int rc = 0; 1072 1073 bzero(&mbx, sizeof(struct oce_mbx)); 1074 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats); 1075 bzero(fwcmd, sizeof(struct mbx_get_pport_stats)); 1076 1077 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1078 MBX_SUBSYSTEM_NIC, 1079 NIC_GET_PPORT_STATS, 1080 MBX_TIMEOUT_SEC, 1081 sizeof(struct mbx_get_pport_stats), 1082 OCE_MBX_VER_V0); 1083 1084 fwcmd->params.req.reset_stats = reset_stats; 1085 fwcmd->params.req.port_number = sc->port_id; 1086 1087 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ 1088 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 1089 1090 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 1091 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); 1092 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 1093 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats); 1094 1095 mbx.payload_length = sizeof(struct mbx_get_pport_stats); 1096 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1097 1098 rc = oce_mbox_post(sc, &mbx, NULL); 1099 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 1100 1101 if (!rc) 1102 rc = fwcmd->hdr.u0.rsp.status; 1103 if (rc) 1104 device_printf(sc->dev, 1105 "%s failed - cmd status: %d addi status: %d\n", 1106 __FUNCTION__, rc, 1107 fwcmd->hdr.u0.rsp.additional_status); 1108 return rc; 1109 } 1110 1111 /** 1112 * @brief Function to get vport (virtual port) statistics 1113 * @param sc software handle to the device 1114 * @param *stats pointer to where to store statistics 1115 * @param reset_stats resets statistics of set 1116 * @returns 0 on success, EIO on failure 1117 */ 1118 int 1119 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1120 uint32_t req_size, uint32_t reset_stats) 1121 { 1122 struct oce_mbx mbx; 1123 struct mbx_get_vport_stats *fwcmd; 1124 int rc = 0; 1125 1126 bzero(&mbx, sizeof(struct oce_mbx)); 1127 1128 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats); 1129 bzero(fwcmd, sizeof(struct mbx_get_vport_stats)); 1130 1131 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1132 MBX_SUBSYSTEM_NIC, 1133 NIC_GET_VPORT_STATS, 1134 MBX_TIMEOUT_SEC, 1135 sizeof(struct mbx_get_vport_stats), 1136 OCE_MBX_VER_V0); 1137 1138 fwcmd->params.req.reset_stats = reset_stats; 1139 fwcmd->params.req.vport_number = sc->if_id; 1140 1141 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ 1142 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 1143 1144 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 1145 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); 1146 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 1147 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats); 1148 1149 mbx.payload_length = sizeof(struct mbx_get_vport_stats); 1150 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1151 1152 rc = oce_mbox_post(sc, &mbx, NULL); 1153 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 1154 1155 if (!rc) 1156 rc = fwcmd->hdr.u0.rsp.status; 1157 if (rc) 1158 device_printf(sc->dev, 1159 "%s failed - cmd status: %d addi status: %d\n", 1160 __FUNCTION__, rc, 1161 fwcmd->hdr.u0.rsp.additional_status); 1162 return rc; 1163 } 1164 1165 /** 1166 * @brief Function to update the muticast filter with 1167 * values in dma_mem 1168 * @param sc software handle to the device 1169 * @param dma_mem pointer to dma memory region 1170 * @returns 0 on success, EIO on failure 1171 */ 1172 int 1173 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem) 1174 { 1175 struct oce_mbx mbx; 1176 struct oce_mq_sge *sgl; 1177 struct mbx_set_common_iface_multicast *req = NULL; 1178 int rc = 0; 1179 1180 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast); 1181 mbx_common_req_hdr_init(&req->hdr, 0, 0, 1182 MBX_SUBSYSTEM_COMMON, 1183 OPCODE_COMMON_SET_IFACE_MULTICAST, 1184 MBX_TIMEOUT_SEC, 1185 sizeof(struct mbx_set_common_iface_multicast), 1186 OCE_MBX_VER_V0); 1187 1188 bzero(&mbx, sizeof(struct oce_mbx)); 1189 1190 mbx.u0.s.embedded = 0; /*Non embeded*/ 1191 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast); 1192 mbx.u0.s.sge_count = 1; 1193 sgl = &mbx.payload.u0.u1.sgl[0]; 1194 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr)); 1195 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF); 1196 sgl->length = htole32(mbx.payload_length); 1197 1198 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1199 1200 rc = oce_mbox_post(sc, &mbx, NULL); 1201 if (!rc) 1202 rc = req->hdr.u0.rsp.status; 1203 if (rc) 1204 device_printf(sc->dev, 1205 "%s failed - cmd status: %d addi status: %d\n", 1206 __FUNCTION__, rc, 1207 req->hdr.u0.rsp.additional_status); 1208 return rc; 1209 } 1210 1211 /** 1212 * @brief Function to send passthrough Ioctls 1213 * @param sc software handle to the device 1214 * @param dma_mem pointer to dma memory region 1215 * @param req_size size of dma_mem 1216 * @returns 0 on success, EIO on failure 1217 */ 1218 int 1219 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size) 1220 { 1221 struct oce_mbx mbx; 1222 struct oce_mq_sge *sgl; 1223 int rc = 0; 1224 1225 bzero(&mbx, sizeof(struct oce_mbx)); 1226 1227 mbx.u0.s.embedded = 0; /*Non embeded*/ 1228 mbx.payload_length = req_size; 1229 mbx.u0.s.sge_count = 1; 1230 sgl = &mbx.payload.u0.u1.sgl[0]; 1231 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr)); 1232 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF); 1233 sgl->length = htole32(req_size); 1234 1235 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1236 1237 rc = oce_mbox_post(sc, &mbx, NULL); 1238 return rc; 1239 } 1240 1241 int 1242 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1243 uint32_t if_id, uint32_t *pmac_id) 1244 { 1245 struct oce_mbx mbx; 1246 struct mbx_add_common_iface_mac *fwcmd; 1247 int rc = 0; 1248 1249 bzero(&mbx, sizeof(struct oce_mbx)); 1250 1251 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload; 1252 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1253 MBX_SUBSYSTEM_COMMON, 1254 OPCODE_COMMON_ADD_IFACE_MAC, 1255 MBX_TIMEOUT_SEC, 1256 sizeof(struct mbx_add_common_iface_mac), 1257 OCE_MBX_VER_V0); 1258 1259 fwcmd->params.req.if_id = (uint16_t) if_id; 1260 bcopy(mac_addr, fwcmd->params.req.mac_address, 6); 1261 1262 mbx.u0.s.embedded = 1; 1263 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac); 1264 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1265 rc = oce_mbox_post(sc, &mbx, NULL); 1266 if (!rc) 1267 rc = fwcmd->hdr.u0.rsp.status; 1268 if (rc) { 1269 device_printf(sc->dev, 1270 "%s failed - cmd status: %d addi status: %d\n", 1271 __FUNCTION__, rc, 1272 fwcmd->hdr.u0.rsp.additional_status); 1273 goto error; 1274 } 1275 *pmac_id = fwcmd->params.rsp.pmac_id; 1276 error: 1277 return rc; 1278 } 1279 1280 int 1281 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id) 1282 { 1283 struct oce_mbx mbx; 1284 struct mbx_del_common_iface_mac *fwcmd; 1285 int rc = 0; 1286 1287 bzero(&mbx, sizeof(struct oce_mbx)); 1288 1289 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload; 1290 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1291 MBX_SUBSYSTEM_COMMON, 1292 OPCODE_COMMON_DEL_IFACE_MAC, 1293 MBX_TIMEOUT_SEC, 1294 sizeof(struct mbx_del_common_iface_mac), 1295 OCE_MBX_VER_V0); 1296 1297 fwcmd->params.req.if_id = (uint16_t)if_id; 1298 fwcmd->params.req.pmac_id = pmac_id; 1299 1300 mbx.u0.s.embedded = 1; 1301 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac); 1302 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1303 1304 rc = oce_mbox_post(sc, &mbx, NULL); 1305 if (!rc) 1306 rc = fwcmd->hdr.u0.rsp.status; 1307 if (rc) 1308 device_printf(sc->dev, 1309 "%s failed - cmd status: %d addi status: %d\n", 1310 __FUNCTION__, rc, 1311 fwcmd->hdr.u0.rsp.additional_status); 1312 return rc; 1313 } 1314 1315 int 1316 oce_mbox_check_native_mode(POCE_SOFTC sc) 1317 { 1318 struct oce_mbx mbx; 1319 struct mbx_common_set_function_cap *fwcmd; 1320 int rc = 0; 1321 1322 bzero(&mbx, sizeof(struct oce_mbx)); 1323 1324 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload; 1325 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1326 MBX_SUBSYSTEM_COMMON, 1327 OPCODE_COMMON_SET_FUNCTIONAL_CAPS, 1328 MBX_TIMEOUT_SEC, 1329 sizeof(struct mbx_common_set_function_cap), 1330 OCE_MBX_VER_V0); 1331 1332 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS | 1333 CAP_BE3_NATIVE_ERX_API; 1334 1335 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API; 1336 1337 mbx.u0.s.embedded = 1; 1338 mbx.payload_length = sizeof(struct mbx_common_set_function_cap); 1339 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1340 1341 rc = oce_mbox_post(sc, &mbx, NULL); 1342 if (!rc) 1343 rc = fwcmd->hdr.u0.rsp.status; 1344 if (rc) { 1345 device_printf(sc->dev, 1346 "%s failed - cmd status: %d addi status: %d\n", 1347 __FUNCTION__, rc, 1348 fwcmd->hdr.u0.rsp.additional_status); 1349 goto error; 1350 } 1351 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags) 1352 & CAP_BE3_NATIVE_ERX_API; 1353 1354 error: 1355 return 0; 1356 } 1357 1358 int 1359 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1360 uint8_t loopback_type, uint8_t enable) 1361 { 1362 struct oce_mbx mbx; 1363 struct mbx_lowlevel_set_loopback_mode *fwcmd; 1364 int rc = 0; 1365 1366 bzero(&mbx, sizeof(struct oce_mbx)); 1367 1368 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload; 1369 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1370 MBX_SUBSYSTEM_LOWLEVEL, 1371 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, 1372 MBX_TIMEOUT_SEC, 1373 sizeof(struct mbx_lowlevel_set_loopback_mode), 1374 OCE_MBX_VER_V0); 1375 1376 fwcmd->params.req.src_port = port_num; 1377 fwcmd->params.req.dest_port = port_num; 1378 fwcmd->params.req.loopback_type = loopback_type; 1379 fwcmd->params.req.loopback_state = enable; 1380 1381 mbx.u0.s.embedded = 1; 1382 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode); 1383 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1384 1385 rc = oce_mbox_post(sc, &mbx, NULL); 1386 if (!rc) 1387 rc = fwcmd->hdr.u0.rsp.status; 1388 if (rc) 1389 device_printf(sc->dev, 1390 "%s failed - cmd status: %d addi status: %d\n", 1391 __FUNCTION__, rc, 1392 fwcmd->hdr.u0.rsp.additional_status); 1393 1394 return rc; 1395 1396 } 1397 1398 int 1399 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1400 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1401 uint64_t pattern) 1402 { 1403 1404 struct oce_mbx mbx; 1405 struct mbx_lowlevel_test_loopback_mode *fwcmd; 1406 int rc = 0; 1407 1408 bzero(&mbx, sizeof(struct oce_mbx)); 1409 1410 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload; 1411 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1412 MBX_SUBSYSTEM_LOWLEVEL, 1413 OPCODE_LOWLEVEL_TEST_LOOPBACK, 1414 MBX_TIMEOUT_SEC, 1415 sizeof(struct mbx_lowlevel_test_loopback_mode), 1416 OCE_MBX_VER_V0); 1417 1418 fwcmd->params.req.pattern = pattern; 1419 fwcmd->params.req.src_port = port_num; 1420 fwcmd->params.req.dest_port = port_num; 1421 fwcmd->params.req.pkt_size = pkt_size; 1422 fwcmd->params.req.num_pkts = num_pkts; 1423 fwcmd->params.req.loopback_type = loopback_type; 1424 1425 mbx.u0.s.embedded = 1; 1426 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode); 1427 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1428 1429 rc = oce_mbox_post(sc, &mbx, NULL); 1430 if (!rc) 1431 rc = fwcmd->hdr.u0.rsp.status; 1432 if (rc) 1433 device_printf(sc->dev, 1434 "%s failed - cmd status: %d addi status: %d\n", 1435 __FUNCTION__, rc, 1436 fwcmd->hdr.u0.rsp.additional_status); 1437 1438 return rc; 1439 } 1440 1441 int 1442 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1443 POCE_DMA_MEM pdma_mem, uint32_t num_bytes) 1444 { 1445 1446 struct oce_mbx mbx; 1447 struct oce_mq_sge *sgl = NULL; 1448 struct mbx_common_read_write_flashrom *fwcmd = NULL; 1449 int rc = 0, payload_len = 0; 1450 1451 bzero(&mbx, sizeof(struct oce_mbx)); 1452 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom); 1453 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024; 1454 1455 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1456 MBX_SUBSYSTEM_COMMON, 1457 OPCODE_COMMON_WRITE_FLASHROM, 1458 LONG_TIMEOUT, 1459 payload_len, 1460 OCE_MBX_VER_V0); 1461 1462 fwcmd->flash_op_type = LE_32(optype); 1463 fwcmd->flash_op_code = LE_32(opcode); 1464 fwcmd->data_buffer_size = LE_32(num_bytes); 1465 1466 mbx.u0.s.embedded = 0; /*Non embeded*/ 1467 mbx.payload_length = payload_len; 1468 mbx.u0.s.sge_count = 1; 1469 1470 sgl = &mbx.payload.u0.u1.sgl[0]; 1471 sgl->pa_hi = upper_32_bits(pdma_mem->paddr); 1472 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF; 1473 sgl->length = payload_len; 1474 1475 /* post the command */ 1476 rc = oce_mbox_post(sc, &mbx, NULL); 1477 if (!rc) 1478 rc = fwcmd->hdr.u0.rsp.status; 1479 if (rc) 1480 device_printf(sc->dev, 1481 "%s failed - cmd status: %d addi status: %d\n", 1482 __FUNCTION__, rc, 1483 fwcmd->hdr.u0.rsp.additional_status); 1484 1485 return rc; 1486 1487 } 1488 1489 int 1490 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1491 uint32_t offset, uint32_t optype) 1492 { 1493 1494 int rc = 0, payload_len = 0; 1495 struct oce_mbx mbx; 1496 struct mbx_common_read_write_flashrom *fwcmd; 1497 1498 bzero(&mbx, sizeof(struct oce_mbx)); 1499 1500 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload; 1501 1502 /* Firmware requires extra 4 bytes with this ioctl. Since there 1503 is enough room in the mbx payload it should be good enough 1504 Reference: Bug 14853 1505 */ 1506 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4; 1507 1508 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1509 MBX_SUBSYSTEM_COMMON, 1510 OPCODE_COMMON_READ_FLASHROM, 1511 MBX_TIMEOUT_SEC, 1512 payload_len, 1513 OCE_MBX_VER_V0); 1514 1515 fwcmd->flash_op_type = optype; 1516 fwcmd->flash_op_code = FLASHROM_OPER_REPORT; 1517 fwcmd->data_offset = offset; 1518 fwcmd->data_buffer_size = 0x4; 1519 1520 mbx.u0.s.embedded = 1; 1521 mbx.payload_length = payload_len; 1522 1523 /* post the command */ 1524 rc = oce_mbox_post(sc, &mbx, NULL); 1525 if (!rc) 1526 rc = fwcmd->hdr.u0.rsp.status; 1527 if (rc) { 1528 device_printf(sc->dev, 1529 "%s failed - cmd status: %d addi status: %d\n", 1530 __FUNCTION__, rc, 1531 fwcmd->hdr.u0.rsp.additional_status); 1532 goto error; 1533 } 1534 bcopy(fwcmd->data_buffer, flash_crc, 4); 1535 error: 1536 return rc; 1537 } 1538 1539 int 1540 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info) 1541 { 1542 1543 struct oce_mbx mbx; 1544 struct mbx_common_phy_info *fwcmd; 1545 int rc = 0; 1546 1547 bzero(&mbx, sizeof(struct oce_mbx)); 1548 1549 fwcmd = (struct mbx_common_phy_info *)&mbx.payload; 1550 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1551 MBX_SUBSYSTEM_COMMON, 1552 OPCODE_COMMON_GET_PHY_CONFIG, 1553 MBX_TIMEOUT_SEC, 1554 sizeof(struct mbx_common_phy_info), 1555 OCE_MBX_VER_V0); 1556 1557 mbx.u0.s.embedded = 1; 1558 mbx.payload_length = sizeof(struct mbx_common_phy_info); 1559 1560 /* now post the command */ 1561 rc = oce_mbox_post(sc, &mbx, NULL); 1562 if (!rc) 1563 rc = fwcmd->hdr.u0.rsp.status; 1564 if (rc) { 1565 device_printf(sc->dev, 1566 "%s failed - cmd status: %d addi status: %d\n", 1567 __FUNCTION__, rc, 1568 fwcmd->hdr.u0.rsp.additional_status); 1569 goto error; 1570 } 1571 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type); 1572 phy_info->interface_type = 1573 HOST_16(fwcmd->params.rsp.phy_info.interface_type); 1574 phy_info->auto_speeds_supported = 1575 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported); 1576 phy_info->fixed_speeds_supported = 1577 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported); 1578 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params); 1579 error: 1580 return rc; 1581 1582 } 1583 1584 int 1585 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1586 uint32_t data_offset, POCE_DMA_MEM pdma_mem, 1587 uint32_t *written_data, uint32_t *additional_status) 1588 { 1589 1590 struct oce_mbx mbx; 1591 struct mbx_lancer_common_write_object *fwcmd = NULL; 1592 int rc = 0, payload_len = 0; 1593 1594 bzero(&mbx, sizeof(struct oce_mbx)); 1595 payload_len = sizeof(struct mbx_lancer_common_write_object); 1596 1597 mbx.u0.s.embedded = 1;/* Embedded */ 1598 mbx.payload_length = payload_len; 1599 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload; 1600 1601 /* initialize the ioctl header */ 1602 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0, 1603 MBX_SUBSYSTEM_COMMON, 1604 OPCODE_COMMON_WRITE_OBJECT, 1605 LONG_TIMEOUT, 1606 payload_len, 1607 OCE_MBX_VER_V0); 1608 1609 fwcmd->params.req.write_length = data_size; 1610 if (data_size == 0) 1611 fwcmd->params.req.eof = 1; 1612 else 1613 fwcmd->params.req.eof = 0; 1614 1615 strcpy(fwcmd->params.req.object_name, "/prg"); 1616 fwcmd->params.req.descriptor_count = 1; 1617 fwcmd->params.req.write_offset = data_offset; 1618 fwcmd->params.req.buffer_length = data_size; 1619 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF; 1620 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr); 1621 1622 /* post the command */ 1623 rc = oce_mbox_post(sc, &mbx, NULL); 1624 if (!rc) 1625 rc = fwcmd->params.rsp.status; 1626 if (rc) { 1627 device_printf(sc->dev, 1628 "%s failed - cmd status: %d addi status: %d\n", 1629 __FUNCTION__, rc, 1630 fwcmd->params.rsp.additional_status); 1631 goto error; 1632 } 1633 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length); 1634 *additional_status = fwcmd->params.rsp.additional_status; 1635 error: 1636 return rc; 1637 1638 } 1639 1640 int 1641 oce_mbox_create_rq(struct oce_rq *rq) 1642 { 1643 1644 struct oce_mbx mbx; 1645 struct mbx_create_nic_rq *fwcmd; 1646 POCE_SOFTC sc = rq->parent; 1647 int rc, num_pages = 0; 1648 1649 if (rq->qstate == QCREATED) 1650 return 0; 1651 1652 bzero(&mbx, sizeof(struct oce_mbx)); 1653 1654 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload; 1655 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1656 MBX_SUBSYSTEM_NIC, 1657 NIC_CREATE_RQ, MBX_TIMEOUT_SEC, 1658 sizeof(struct mbx_create_nic_rq), 1659 OCE_MBX_VER_V0); 1660 1661 /* oce_page_list will also prepare pages */ 1662 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); 1663 1664 if (IS_XE201(sc)) { 1665 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; 1666 fwcmd->params.req.page_size = 1; 1667 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1; 1668 } else 1669 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size); 1670 fwcmd->params.req.num_pages = num_pages; 1671 fwcmd->params.req.cq_id = rq->cq->cq_id; 1672 fwcmd->params.req.if_id = sc->if_id; 1673 fwcmd->params.req.max_frame_size = rq->cfg.mtu; 1674 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue; 1675 1676 mbx.u0.s.embedded = 1; 1677 mbx.payload_length = sizeof(struct mbx_create_nic_rq); 1678 1679 rc = oce_mbox_post(sc, &mbx, NULL); 1680 if (!rc) 1681 rc = fwcmd->hdr.u0.rsp.status; 1682 if (rc) { 1683 device_printf(sc->dev, 1684 "%s failed - cmd status: %d addi status: %d\n", 1685 __FUNCTION__, rc, 1686 fwcmd->hdr.u0.rsp.additional_status); 1687 goto error; 1688 } 1689 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id); 1690 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid; 1691 error: 1692 return rc; 1693 1694 } 1695 1696 int 1697 oce_mbox_create_wq(struct oce_wq *wq) 1698 { 1699 struct oce_mbx mbx; 1700 struct mbx_create_nic_wq *fwcmd; 1701 POCE_SOFTC sc = wq->parent; 1702 int rc = 0, version, num_pages; 1703 1704 bzero(&mbx, sizeof(struct oce_mbx)); 1705 1706 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload; 1707 if (IS_XE201(sc)) 1708 version = OCE_MBX_VER_V1; 1709 else if(IS_BE(sc)) 1710 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2) 1711 : (version = OCE_MBX_VER_V0); 1712 else 1713 version = OCE_MBX_VER_V2; 1714 1715 if (version > OCE_MBX_VER_V0) 1716 fwcmd->params.req.if_id = sc->if_id; 1717 1718 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1719 MBX_SUBSYSTEM_NIC, 1720 NIC_CREATE_WQ, MBX_TIMEOUT_SEC, 1721 sizeof(struct mbx_create_nic_wq), 1722 version); 1723 1724 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]); 1725 1726 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type; 1727 fwcmd->params.req.num_pages = num_pages; 1728 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1; 1729 fwcmd->params.req.cq_id = wq->cq->cq_id; 1730 fwcmd->params.req.ulp_num = 1; 1731 1732 mbx.u0.s.embedded = 1; 1733 mbx.payload_length = sizeof(struct mbx_create_nic_wq); 1734 1735 rc = oce_mbox_post(sc, &mbx, NULL); 1736 if (!rc) 1737 rc = fwcmd->hdr.u0.rsp.status; 1738 if (rc) { 1739 device_printf(sc->dev, 1740 "%s failed - cmd status: %d addi status: %d\n", 1741 __FUNCTION__, rc, 1742 fwcmd->hdr.u0.rsp.additional_status); 1743 goto error; 1744 } 1745 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id); 1746 if (version == OCE_MBX_VER_V2) 1747 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset); 1748 else 1749 wq->db_offset = PD_TXULP_DB; 1750 error: 1751 return rc; 1752 1753 } 1754 1755 int 1756 oce_mbox_create_eq(struct oce_eq *eq) 1757 { 1758 struct oce_mbx mbx; 1759 struct mbx_create_common_eq *fwcmd; 1760 POCE_SOFTC sc = eq->parent; 1761 int rc = 0; 1762 uint32_t num_pages; 1763 1764 bzero(&mbx, sizeof(struct oce_mbx)); 1765 1766 fwcmd = (struct mbx_create_common_eq *)&mbx.payload; 1767 1768 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1769 MBX_SUBSYSTEM_COMMON, 1770 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC, 1771 sizeof(struct mbx_create_common_eq), 1772 OCE_MBX_VER_V0); 1773 1774 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]); 1775 fwcmd->params.req.ctx.num_pages = num_pages; 1776 fwcmd->params.req.ctx.valid = 1; 1777 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1; 1778 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256); 1779 fwcmd->params.req.ctx.armed = 0; 1780 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd; 1781 1782 mbx.u0.s.embedded = 1; 1783 mbx.payload_length = sizeof(struct mbx_create_common_eq); 1784 1785 rc = oce_mbox_post(sc, &mbx, NULL); 1786 if (!rc) 1787 rc = fwcmd->hdr.u0.rsp.status; 1788 if (rc) { 1789 device_printf(sc->dev, 1790 "%s failed - cmd status: %d addi status: %d\n", 1791 __FUNCTION__, rc, 1792 fwcmd->hdr.u0.rsp.additional_status); 1793 goto error; 1794 } 1795 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id); 1796 error: 1797 return rc; 1798 } 1799 1800 int 1801 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable) 1802 { 1803 struct oce_mbx mbx; 1804 struct mbx_create_common_cq *fwcmd; 1805 POCE_SOFTC sc = cq->parent; 1806 uint8_t version; 1807 oce_cq_ctx_t *ctx; 1808 uint32_t num_pages, page_size; 1809 int rc = 0; 1810 1811 bzero(&mbx, sizeof(struct oce_mbx)); 1812 1813 fwcmd = (struct mbx_create_common_cq *)&mbx.payload; 1814 1815 if (IS_XE201(sc)) 1816 version = OCE_MBX_VER_V2; 1817 else 1818 version = OCE_MBX_VER_V0; 1819 1820 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1821 MBX_SUBSYSTEM_COMMON, 1822 OPCODE_COMMON_CREATE_CQ, 1823 MBX_TIMEOUT_SEC, 1824 sizeof(struct mbx_create_common_cq), 1825 version); 1826 1827 ctx = &fwcmd->params.req.cq_ctx; 1828 1829 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]); 1830 page_size = 1; /* 1 for 4K */ 1831 1832 if (version == OCE_MBX_VER_V2) { 1833 ctx->v2.num_pages = LE_16(num_pages); 1834 ctx->v2.page_size = page_size; 1835 ctx->v2.eventable = is_eventable; 1836 ctx->v2.valid = 1; 1837 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256); 1838 ctx->v2.nodelay = cq->cq_cfg.nodelay; 1839 ctx->v2.coalesce_wm = ncoalesce; 1840 ctx->v2.armed = 0; 1841 ctx->v2.eq_id = cq->eq->eq_id; 1842 if (ctx->v2.count == 3) { 1843 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1) 1844 ctx->v2.cqe_count = (4*1024)-1; 1845 else 1846 ctx->v2.cqe_count = cq->cq_cfg.q_len; 1847 } 1848 } else { 1849 ctx->v0.num_pages = LE_16(num_pages); 1850 ctx->v0.eventable = is_eventable; 1851 ctx->v0.valid = 1; 1852 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256); 1853 ctx->v0.nodelay = cq->cq_cfg.nodelay; 1854 ctx->v0.coalesce_wm = ncoalesce; 1855 ctx->v0.armed = 0; 1856 ctx->v0.eq_id = cq->eq->eq_id; 1857 } 1858 1859 mbx.u0.s.embedded = 1; 1860 mbx.payload_length = sizeof(struct mbx_create_common_cq); 1861 1862 rc = oce_mbox_post(sc, &mbx, NULL); 1863 if (!rc) 1864 rc = fwcmd->hdr.u0.rsp.status; 1865 if (rc) { 1866 device_printf(sc->dev, 1867 "%s failed - cmd status: %d addi status: %d\n", 1868 __FUNCTION__, rc, 1869 fwcmd->hdr.u0.rsp.additional_status); 1870 goto error; 1871 } 1872 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id); 1873 error: 1874 return rc; 1875 1876 } 1877 1878 int 1879 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num) 1880 { 1881 int rc = 0; 1882 struct oce_mbx mbx; 1883 struct mbx_read_common_transrecv_data *fwcmd; 1884 struct oce_mq_sge *sgl; 1885 OCE_DMA_MEM dma; 1886 1887 /* Allocate DMA mem*/ 1888 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data), 1889 &dma, 0)) 1890 return ENOMEM; 1891 1892 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data); 1893 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data)); 1894 1895 bzero(&mbx, sizeof(struct oce_mbx)); 1896 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1897 MBX_SUBSYSTEM_COMMON, 1898 OPCODE_COMMON_READ_TRANSRECEIVER_DATA, 1899 MBX_TIMEOUT_SEC, 1900 sizeof(struct mbx_read_common_transrecv_data), 1901 OCE_MBX_VER_V0); 1902 1903 /* fill rest of mbx */ 1904 mbx.u0.s.embedded = 0; 1905 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data); 1906 mbx.u0.s.sge_count = 1; 1907 sgl = &mbx.payload.u0.u1.sgl[0]; 1908 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 1909 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 1910 sgl->length = htole32(mbx.payload_length); 1911 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1912 1913 fwcmd->params.req.port = LE_32(sc->port_id); 1914 fwcmd->params.req.page_num = LE_32(page_num); 1915 1916 /* command post */ 1917 rc = oce_mbox_post(sc, &mbx, NULL); 1918 if (!rc) 1919 rc = fwcmd->hdr.u0.rsp.status; 1920 if (rc) { 1921 device_printf(sc->dev, 1922 "%s failed - cmd status: %d addi status: %d\n", 1923 __FUNCTION__, rc, 1924 fwcmd->hdr.u0.rsp.additional_status); 1925 goto error; 1926 } 1927 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0) 1928 { 1929 bcopy((char *)fwcmd->params.rsp.page_data, 1930 &sfp_vpd_dump_buffer[0], 1931 TRANSCEIVER_A0_SIZE); 1932 } 1933 1934 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2) 1935 { 1936 bcopy((char *)fwcmd->params.rsp.page_data, 1937 &sfp_vpd_dump_buffer[TRANSCEIVER_A0_SIZE], 1938 TRANSCEIVER_A2_SIZE); 1939 } 1940 error: 1941 oce_dma_free(sc, &dma); 1942 return rc; 1943 } 1944 1945 void 1946 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1947 int num) 1948 { 1949 struct oce_mbx mbx; 1950 struct mbx_modify_common_eq_delay *fwcmd; 1951 int rc = 0; 1952 int i = 0; 1953 1954 bzero(&mbx, sizeof(struct oce_mbx)); 1955 1956 /* Initialize MODIFY_EQ_DELAY ioctl header */ 1957 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload; 1958 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1959 MBX_SUBSYSTEM_COMMON, 1960 OPCODE_COMMON_MODIFY_EQ_DELAY, 1961 MBX_TIMEOUT_SEC, 1962 sizeof(struct mbx_modify_common_eq_delay), 1963 OCE_MBX_VER_V0); 1964 /* fill rest of mbx */ 1965 mbx.u0.s.embedded = 1; 1966 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay); 1967 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1968 1969 fwcmd->params.req.num_eq = num; 1970 for (i = 0; i < num; i++) { 1971 fwcmd->params.req.delay[i].eq_id = 1972 htole32(set_eqd[i].eq_id); 1973 fwcmd->params.req.delay[i].phase = 0; 1974 fwcmd->params.req.delay[i].dm = 1975 htole32(set_eqd[i].delay_multiplier); 1976 } 1977 1978 /* command post */ 1979 rc = oce_mbox_post(sc, &mbx, NULL); 1980 1981 if (!rc) 1982 rc = fwcmd->hdr.u0.rsp.status; 1983 if (rc) 1984 device_printf(sc->dev, 1985 "%s failed - cmd status: %d addi status: %d\n", 1986 __FUNCTION__, rc, 1987 fwcmd->hdr.u0.rsp.additional_status); 1988 } 1989 1990 int 1991 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss) 1992 { 1993 struct oce_mbx mbx; 1994 struct mbx_common_get_profile_config *fwcmd; 1995 int rc = 0; 1996 int version = 0; 1997 struct oce_mq_sge *sgl; 1998 OCE_DMA_MEM dma; 1999 uint32_t desc_count = 0; 2000 struct oce_nic_resc_desc *nic_desc = NULL; 2001 int i; 2002 boolean_t nic_desc_valid = FALSE; 2003 2004 if (IS_BE2(sc)) 2005 return -1; 2006 2007 /* Allocate DMA mem*/ 2008 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config), 2009 &dma, 0)) 2010 return ENOMEM; 2011 2012 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2013 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config); 2014 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config)); 2015 2016 if (!IS_XE201(sc)) 2017 version = OCE_MBX_VER_V1; 2018 else 2019 version = OCE_MBX_VER_V0; 2020 2021 bzero(&mbx, sizeof(struct oce_mbx)); 2022 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2023 MBX_SUBSYSTEM_COMMON, 2024 OPCODE_COMMON_GET_PROFILE_CONFIG, 2025 MBX_TIMEOUT_SEC, 2026 sizeof(struct mbx_common_get_profile_config), 2027 version); 2028 /* fill rest of mbx */ 2029 mbx.u0.s.embedded = 0; 2030 mbx.payload_length = sizeof(struct mbx_common_get_profile_config); 2031 mbx.u0.s.sge_count = 1; 2032 sgl = &mbx.payload.u0.u1.sgl[0]; 2033 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2034 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2035 sgl->length = htole32(mbx.payload_length); 2036 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2037 2038 fwcmd->params.req.type = ACTIVE_PROFILE; 2039 2040 /* command post */ 2041 rc = oce_mbox_post(sc, &mbx, NULL); 2042 if (!rc) 2043 rc = fwcmd->hdr.u0.rsp.status; 2044 if (rc) { 2045 device_printf(sc->dev, 2046 "%s failed - cmd status: %d addi status: %d\n", 2047 __FUNCTION__, rc, 2048 fwcmd->hdr.u0.rsp.additional_status); 2049 goto error; 2050 } 2051 2052 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2053 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2054 for (i = 0; i < desc_count; i++) { 2055 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2056 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2057 nic_desc_valid = TRUE; 2058 break; 2059 } 2060 nic_desc = (struct oce_nic_resc_desc *) \ 2061 ((char *)nic_desc + nic_desc->desc_len); 2062 } 2063 if (!nic_desc_valid) { 2064 rc = -1; 2065 goto error; 2066 } 2067 else { 2068 sc->max_vlans = HOST_16(nic_desc->vlan_count); 2069 sc->nwqs = HOST_16(nic_desc->txq_count); 2070 if (sc->nwqs) 2071 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2072 else 2073 sc->nwqs = OCE_MAX_WQ; 2074 2075 sc->nrssqs = HOST_16(nic_desc->rssq_count); 2076 if (sc->nrssqs) 2077 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2078 else 2079 sc->nrssqs = max_rss; 2080 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ 2081 } 2082 error: 2083 oce_dma_free(sc, &dma); 2084 return rc; 2085 2086 } 2087 2088 int 2089 oce_get_func_config(POCE_SOFTC sc) 2090 { 2091 struct oce_mbx mbx; 2092 struct mbx_common_get_func_config *fwcmd; 2093 int rc = 0; 2094 int version = 0; 2095 struct oce_mq_sge *sgl; 2096 OCE_DMA_MEM dma; 2097 uint32_t desc_count = 0; 2098 struct oce_nic_resc_desc *nic_desc = NULL; 2099 int i; 2100 boolean_t nic_desc_valid = FALSE; 2101 uint32_t max_rss = 0; 2102 2103 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native)) 2104 max_rss = OCE_LEGACY_MODE_RSS; 2105 else 2106 max_rss = OCE_MAX_RSS; 2107 2108 /* Allocate DMA mem*/ 2109 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config), 2110 &dma, 0)) 2111 return ENOMEM; 2112 2113 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2114 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config); 2115 bzero(fwcmd, sizeof(struct mbx_common_get_func_config)); 2116 2117 if (IS_SH(sc)) 2118 version = OCE_MBX_VER_V1; 2119 else 2120 version = OCE_MBX_VER_V0; 2121 2122 bzero(&mbx, sizeof(struct oce_mbx)); 2123 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2124 MBX_SUBSYSTEM_COMMON, 2125 OPCODE_COMMON_GET_FUNCTION_CONFIG, 2126 MBX_TIMEOUT_SEC, 2127 sizeof(struct mbx_common_get_func_config), 2128 version); 2129 /* fill rest of mbx */ 2130 mbx.u0.s.embedded = 0; 2131 mbx.payload_length = sizeof(struct mbx_common_get_func_config); 2132 mbx.u0.s.sge_count = 1; 2133 sgl = &mbx.payload.u0.u1.sgl[0]; 2134 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2135 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2136 sgl->length = htole32(mbx.payload_length); 2137 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2138 2139 /* command post */ 2140 rc = oce_mbox_post(sc, &mbx, NULL); 2141 if (!rc) 2142 rc = fwcmd->hdr.u0.rsp.status; 2143 if (rc) { 2144 device_printf(sc->dev, 2145 "%s failed - cmd status: %d addi status: %d\n", 2146 __FUNCTION__, rc, 2147 fwcmd->hdr.u0.rsp.additional_status); 2148 goto error; 2149 } 2150 2151 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2152 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2153 for (i = 0; i < desc_count; i++) { 2154 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2155 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2156 nic_desc_valid = TRUE; 2157 break; 2158 } 2159 nic_desc = (struct oce_nic_resc_desc *) \ 2160 ((char *)nic_desc + nic_desc->desc_len); 2161 } 2162 if (!nic_desc_valid) { 2163 rc = -1; 2164 goto error; 2165 } 2166 else { 2167 sc->max_vlans = nic_desc->vlan_count; 2168 sc->nwqs = HOST_32(nic_desc->txq_count); 2169 if (sc->nwqs) 2170 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2171 else 2172 sc->nwqs = OCE_MAX_WQ; 2173 2174 sc->nrssqs = HOST_32(nic_desc->rssq_count); 2175 if (sc->nrssqs) 2176 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2177 else 2178 sc->nrssqs = max_rss; 2179 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ 2180 } 2181 error: 2182 oce_dma_free(sc, &dma); 2183 return rc; 2184 2185 } 2186 2187 /* hw lro functions */ 2188 2189 int 2190 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags) 2191 { 2192 struct oce_mbx mbx; 2193 struct mbx_nic_query_lro_capabilities *fwcmd; 2194 int rc = 0; 2195 2196 bzero(&mbx, sizeof(struct oce_mbx)); 2197 2198 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload; 2199 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2200 MBX_SUBSYSTEM_NIC, 2201 0x20,MBX_TIMEOUT_SEC, 2202 sizeof(struct mbx_nic_query_lro_capabilities), 2203 OCE_MBX_VER_V0); 2204 2205 mbx.u0.s.embedded = 1; 2206 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities); 2207 2208 rc = oce_mbox_post(sc, &mbx, NULL); 2209 if (!rc) 2210 rc = fwcmd->hdr.u0.rsp.status; 2211 if (rc) { 2212 device_printf(sc->dev, 2213 "%s failed - cmd status: %d addi status: %d\n", 2214 __FUNCTION__, rc, 2215 fwcmd->hdr.u0.rsp.additional_status); 2216 2217 return rc; 2218 } 2219 if(lro_flags) 2220 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags); 2221 2222 if(lro_rq_cnt) 2223 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt); 2224 2225 return rc; 2226 } 2227 2228 int 2229 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable) 2230 { 2231 struct oce_mbx mbx; 2232 struct mbx_nic_set_iface_lro_config *fwcmd; 2233 int rc = 0; 2234 2235 bzero(&mbx, sizeof(struct oce_mbx)); 2236 2237 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload; 2238 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2239 MBX_SUBSYSTEM_NIC, 2240 0x26,MBX_TIMEOUT_SEC, 2241 sizeof(struct mbx_nic_set_iface_lro_config), 2242 OCE_MBX_VER_V0); 2243 2244 mbx.u0.s.embedded = 1; 2245 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config); 2246 2247 fwcmd->params.req.iface_id = sc->if_id; 2248 fwcmd->params.req.lro_flags = 0; 2249 2250 if(enable) { 2251 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE; 2252 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6; 2253 2254 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */ 2255 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */ 2256 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */ 2257 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */ 2258 } 2259 2260 rc = oce_mbox_post(sc, &mbx, NULL); 2261 if (!rc) 2262 rc = fwcmd->hdr.u0.rsp.status; 2263 if (rc) { 2264 device_printf(sc->dev, 2265 "%s failed - cmd status: %d addi status: %d\n", 2266 __FUNCTION__, rc, 2267 fwcmd->hdr.u0.rsp.additional_status); 2268 2269 return rc; 2270 } 2271 return rc; 2272 } 2273 2274 int 2275 oce_mbox_create_rq_v2(struct oce_rq *rq) 2276 { 2277 struct oce_mbx mbx; 2278 struct mbx_create_nic_rq_v2 *fwcmd; 2279 POCE_SOFTC sc = rq->parent; 2280 int rc = 0, num_pages = 0; 2281 2282 if (rq->qstate == QCREATED) 2283 return 0; 2284 2285 bzero(&mbx, sizeof(struct oce_mbx)); 2286 2287 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload; 2288 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2289 MBX_SUBSYSTEM_NIC, 2290 0x08, MBX_TIMEOUT_SEC, 2291 sizeof(struct mbx_create_nic_rq_v2), 2292 OCE_MBX_VER_V2); 2293 2294 /* oce_page_list will also prepare pages */ 2295 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); 2296 2297 fwcmd->params.req.cq_id = rq->cq->cq_id; 2298 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; 2299 fwcmd->params.req.num_pages = num_pages; 2300 2301 fwcmd->params.req.if_id = sc->if_id; 2302 2303 fwcmd->params.req.max_frame_size = rq->cfg.mtu; 2304 fwcmd->params.req.page_size = 1; 2305 if(rq->cfg.is_rss_queue) { 2306 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO); 2307 }else { 2308 device_printf(sc->dev, 2309 "non rss lro queue should not be created \n"); 2310 goto error; 2311 } 2312 mbx.u0.s.embedded = 1; 2313 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2); 2314 2315 rc = oce_mbox_post(sc, &mbx, NULL); 2316 if (!rc) 2317 rc = fwcmd->hdr.u0.rsp.status; 2318 if (rc) { 2319 device_printf(sc->dev, 2320 "%s failed - cmd status: %d addi status: %d\n", 2321 __FUNCTION__, rc, 2322 fwcmd->hdr.u0.rsp.additional_status); 2323 goto error; 2324 } 2325 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id); 2326 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid; 2327 2328 error: 2329 return rc; 2330 }
Cache object: cf73f9c44c2bead3b7e287450d160339
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