Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ocs_fc/sli4.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2017 Broadcom. All rights reserved. 3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 /** 35 * @file 36 * Define common SLI-4 structures and function prototypes. 37 */ 38 39 #ifndef _SLI4_H 40 #define _SLI4_H 41 42 #include "ocs_os.h" 43 44 #define SLI_PAGE_SIZE (4096) 45 #define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1) 46 #define SLI_PAGE_SHIFT 12 47 #define SLI_ROUND_PAGE(b) (((b) + SLI_SUB_PAGE_MASK) & ~SLI_SUB_PAGE_MASK) 48 49 #define SLI4_BMBX_TIMEOUT_MSEC 30000 50 #define SLI4_FW_READY_TIMEOUT_MSEC 30000 51 52 static inline uint32_t 53 sli_page_count(size_t bytes, uint32_t page_size) 54 { 55 uint32_t mask = page_size - 1; 56 uint32_t shift = 0; 57 58 switch (page_size) { 59 case 4096: 60 shift = 12; 61 break; 62 case 8192: 63 shift = 13; 64 break; 65 case 16384: 66 shift = 14; 67 break; 68 case 32768: 69 shift = 15; 70 break; 71 case 65536: 72 shift = 16; 73 break; 74 default: 75 return 0; 76 } 77 78 return (bytes + mask) >> shift; 79 } 80 81 /************************************************************************* 82 * Common PCI configuration space register definitions 83 */ 84 85 #define SLI4_PCI_CLASS_REVISION 0x0008 /** register offset */ 86 #define SLI4_PCI_REV_ID_SHIFT 0 87 #define SLI4_PCI_REV_ID_MASK 0xff 88 #define SLI4_PCI_CLASS_SHIFT 8 89 #define SLI4_PCI_CLASS_MASK 0xfff 90 91 #define SLI4_PCI_SOFT_RESET_CSR 0x005c /** register offset */ 92 #define SLI4_PCI_SOFT_RESET_MASK 0x0080 93 94 /************************************************************************* 95 * Common SLI-4 register offsets and field definitions 96 */ 97 98 /** 99 * @brief SLI_INTF - SLI Interface Definition Register 100 */ 101 #define SLI4_INTF_REG 0x0058 /** register offset */ 102 #define SLI4_INTF_VALID_SHIFT 29 103 #define SLI4_INTF_VALID_MASK 0x7 104 #define SLI4_INTF_VALID 0x6 105 #define SLI4_INTF_IF_TYPE_SHIFT 12 106 #define SLI4_INTF_IF_TYPE_MASK 0xf 107 #define SLI4_INTF_SLI_FAMILY_SHIFT 8 108 #define SLI4_INTF_SLI_FAMILY_MASK 0xf 109 #define SLI4_INTF_SLI_REVISION_SHIFT 4 110 #define SLI4_INTF_SLI_REVISION_MASK 0xf 111 #define SLI4_FAMILY_CHECK_ASIC_TYPE 0xf 112 113 #define SLI4_IF_TYPE_BE3_SKH_PF 0 114 #define SLI4_IF_TYPE_BE3_SKH_VF 1 115 #define SLI4_IF_TYPE_LANCER_FC_ETH 2 116 #define SLI4_IF_TYPE_LANCER_RDMA 3 117 #define SLI4_MAX_IF_TYPES 4 118 119 /** 120 * @brief ASIC_ID - SLI ASIC Type and Revision Register 121 */ 122 #define SLI4_ASIC_ID_REG 0x009c /* register offset */ 123 #define SLI4_ASIC_REV_SHIFT 0 124 #define SLI4_ASIC_REV_MASK 0xf 125 #define SLI4_ASIC_VER_SHIFT 4 126 #define SLI4_ASIC_VER_MASK 0xf 127 #define SLI4_ASIC_GEN_SHIFT 8 128 #define SLI4_ASIC_GEN_MASK 0xff 129 #define SLI4_ASIC_GEN_BE2 0x00 130 #define SLI4_ASIC_GEN_BE3 0x03 131 #define SLI4_ASIC_GEN_SKYHAWK 0x04 132 #define SLI4_ASIC_GEN_CORSAIR 0x05 133 #define SLI4_ASIC_GEN_LANCER 0x0b 134 135 /** 136 * @brief BMBX - Bootstrap Mailbox Register 137 */ 138 #define SLI4_BMBX_REG 0x0160 /* register offset */ 139 #define SLI4_BMBX_MASK_HI 0x3 140 #define SLI4_BMBX_MASK_LO 0xf 141 #define SLI4_BMBX_RDY BIT(0) 142 #define SLI4_BMBX_HI BIT(1) 143 #define SLI4_BMBX_WRITE_HI(r) ((ocs_addr32_hi(r) & ~SLI4_BMBX_MASK_HI) | \ 144 SLI4_BMBX_HI) 145 #define SLI4_BMBX_WRITE_LO(r) (((ocs_addr32_hi(r) & SLI4_BMBX_MASK_HI) << 30) | \ 146 (((r) & ~SLI4_BMBX_MASK_LO) >> 2)) 147 148 #define SLI4_BMBX_SIZE 256 149 150 /** 151 * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register 152 */ 153 #define SLI4_EQCQ_DOORBELL_REG 0x120 154 #define SLI4_EQCQ_DOORBELL_CI BIT(9) 155 #define SLI4_EQCQ_DOORBELL_QT BIT(10) 156 #define SLI4_EQCQ_DOORBELL_ARM BIT(29) 157 #define SLI4_EQCQ_DOORBELL_SE BIT(31) 158 #define SLI4_EQCQ_NUM_SHIFT 16 159 #define SLI4_EQCQ_NUM_MASK 0x01ff 160 #define SLI4_EQCQ_EQ_ID_MASK 0x3fff 161 #define SLI4_EQCQ_CQ_ID_MASK 0x7fff 162 #define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff 163 #define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff 164 #define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800 165 166 /** 167 * @brief SLIPORT_CONTROL - SLI Port Control Register 168 */ 169 #define SLI4_SLIPORT_CONTROL_REG 0x0408 170 #define SLI4_SLIPORT_CONTROL_END BIT(30) 171 #define SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN (0) 172 #define SLI4_SLIPORT_CONTROL_BIG_ENDIAN BIT(30) 173 #define SLI4_SLIPORT_CONTROL_IP BIT(27) 174 #define SLI4_SLIPORT_CONTROL_IDIS BIT(22) 175 #define SLI4_SLIPORT_CONTROL_FDD BIT(31) 176 177 /** 178 * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register 179 */ 180 #define SLI4_SLIPORT_ERROR1 0x040c 181 182 /** 183 * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register 184 */ 185 #define SLI4_SLIPORT_ERROR2 0x0410 186 187 /** 188 * @brief User error registers 189 */ 190 #define SLI4_UERR_STATUS_LOW_REG 0xA0 191 #define SLI4_UERR_STATUS_HIGH_REG 0xA4 192 #define SLI4_UERR_MASK_LOW_REG 0xA8 193 #define SLI4_UERR_MASK_HIGH_REG 0xAC 194 195 /** 196 * @brief Registers for generating software UE (BE3) 197 */ 198 #define SLI4_SW_UE_CSR1 0x138 199 #define SLI4_SW_UE_CSR2 0x1FFFC 200 201 /** 202 * @brief Registers for generating software UE (Skyhawk) 203 */ 204 #define SLI4_SW_UE_REG 0x5C /* register offset */ 205 206 static inline uint32_t sli_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 207 { 208 uint32_t reg = 0; 209 #if BYTE_ORDER == LITTLE_ENDIAN 210 struct { 211 uint32_t eq_id_lo:9, 212 ci:1, /* clear interrupt */ 213 qt:1, /* queue type */ 214 eq_id_hi:5, 215 number_popped:13, 216 arm:1, 217 :1, 218 se:1; 219 } * eq_doorbell = (void *)® 220 #else 221 #error big endian version not defined 222 #endif 223 224 eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO; 225 eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */ 226 eq_doorbell->eq_id_hi = (id >> 9) & 0x1f; 227 eq_doorbell->number_popped = n_popped; 228 eq_doorbell->arm = arm; 229 eq_doorbell->ci = TRUE; 230 231 return reg; 232 } 233 234 static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) 235 { 236 uint32_t reg = 0; 237 #if BYTE_ORDER == LITTLE_ENDIAN 238 struct { 239 uint32_t cq_id_lo:10, 240 qt:1, /* queue type */ 241 cq_id_hi:5, 242 number_popped:13, 243 arm:1, 244 :1, 245 se:1; 246 } * cq_doorbell = (void *)® 247 #else 248 #error big endian version not defined 249 #endif 250 251 cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO; 252 cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */ 253 cq_doorbell->cq_id_hi = (id >> 10) & 0x1f; 254 cq_doorbell->number_popped = n_popped; 255 cq_doorbell->arm = arm; 256 257 return reg; 258 } 259 260 /** 261 * @brief MQ_DOORBELL - MQ Doorbell Register 262 */ 263 #define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */ 264 #define SLI4_MQ_DOORBELL_NUM_SHIFT 16 265 #define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff 266 #define SLI4_MQ_DOORBELL_ID_MASK 0xffff 267 #define SLI4_MQ_DOORBELL(n, i) ((((n) & SLI4_MQ_DOORBELL_NUM_MASK) << SLI4_MQ_DOORBELL_NUM_SHIFT) | \ 268 ((i) & SLI4_MQ_DOORBELL_ID_MASK)) 269 270 /** 271 * @brief RQ_DOORBELL - RQ Doorbell Register 272 */ 273 #define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */ 274 #define SLI4_RQ_DOORBELL_NUM_SHIFT 16 275 #define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff 276 #define SLI4_RQ_DOORBELL_ID_MASK 0xffff 277 #define SLI4_RQ_DOORBELL(n, i) ((((n) & SLI4_RQ_DOORBELL_NUM_MASK) << SLI4_RQ_DOORBELL_NUM_SHIFT) | \ 278 ((i) & SLI4_RQ_DOORBELL_ID_MASK)) 279 280 /** 281 * @brief WQ_DOORBELL - WQ Doorbell Register 282 */ 283 #define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */ 284 #define SLI4_WQ_DOORBELL_IDX_SHIFT 16 285 #define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff 286 #define SLI4_WQ_DOORBELL_NUM_SHIFT 24 287 #define SLI4_WQ_DOORBELL_NUM_MASK 0x00ff 288 #define SLI4_WQ_DOORBELL_ID_MASK 0xffff 289 #define SLI4_WQ_DOORBELL(n, x, i) ((((n) & SLI4_WQ_DOORBELL_NUM_MASK) << SLI4_WQ_DOORBELL_NUM_SHIFT) | \ 290 (((x) & SLI4_WQ_DOORBELL_IDX_MASK) << SLI4_WQ_DOORBELL_IDX_SHIFT) | \ 291 ((i) & SLI4_WQ_DOORBELL_ID_MASK)) 292 293 /** 294 * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register 295 */ 296 #define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */ 297 #define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */ 298 #define SLI4_PORT_SEMAPHORE_REG_23 0x0400 /** register offset Interface Type 2 + 3 */ 299 #define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff 300 #define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK) 301 #define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000 302 #define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16 303 #define SLI4_PORT_SEMAPHORE_HOST(r) (((r) & SLI4_PORT_SEMAPHORE_HOST_MASK) >> \ 304 SLI4_PORT_SEMAPHORE_HOST_SHIFT) 305 #define SLI4_PORT_SEMAPHORE_SCR2 BIT(26) /** scratch area 2 */ 306 #define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */ 307 #define SLI4_PORT_SEMAPHORE_IPC BIT(28) /** IP conflict */ 308 #define SLI4_PORT_SEMAPHORE_NIP BIT(29) /** no IP address */ 309 #define SLI4_PORT_SEMAPHORE_SFI BIT(30) /** secondary firmware image used */ 310 #define SLI4_PORT_SEMAPHORE_PERR BIT(31) /** POST fatal error */ 311 312 #define SLI4_PORT_SEMAPHORE_STATUS_POST_READY 0xc000 313 #define SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR 0xf000 314 #define SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK 0xf000 315 #define SLI4_PORT_SEMAPHORE_IN_ERR(r) (SLI4_PORT_SEMAPHORE_STATUS_UNRECOV_ERR == ((r) & \ 316 SLI4_PORT_SEMAPHORE_STATUS_ERR_MASK)) 317 318 /** 319 * @brief SLIPORT_STATUS - SLI Port Status Register 320 */ 321 322 #define SLI4_PORT_STATUS_REG_23 0x0404 /** register offset Interface Type 2 + 3 */ 323 #define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */ 324 #define SLI4_PORT_STATUS_RDY BIT(23) /** ready */ 325 #define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */ 326 #define SLI4_PORT_STATUS_DIP BIT(25) /** dump present */ 327 #define SLI4_PORT_STATUS_OTI BIT(29) /** over temp indicator */ 328 #define SLI4_PORT_STATUS_END BIT(30) /** endianness */ 329 #define SLI4_PORT_STATUS_ERR BIT(31) /** SLI port error */ 330 #define SLI4_PORT_STATUS_READY(r) ((r) & SLI4_PORT_STATUS_RDY) 331 #define SLI4_PORT_STATUS_ERROR(r) ((r) & SLI4_PORT_STATUS_ERR) 332 #define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP) 333 #define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP) 334 335 #define SLI4_PHSDEV_CONTROL_REG_23 0x0414 /** register offset Interface Type 2 + 3 */ 336 #define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */ 337 #define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */ 338 #define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */ 339 #define SLI4_PHYDEV_CONTROL_FRL_MASK 0x000000f0 340 #define SLI4_PHYDEV_CONTROL_FRL_SHIFT 4 341 #define SLI4_PHYDEV_CONTROL_FRL(r) (((r) & SLI4_PHYDEV_CONTROL_FRL_MASK) >> \ 342 SLI4_PHYDEV_CONTROL_FRL_SHIFT_SHIFT) 343 344 /************************************************************************* 345 * SLI-4 mailbox command formats and definitions 346 */ 347 348 typedef struct sli4_mbox_command_header_s { 349 #if BYTE_ORDER == LITTLE_ENDIAN 350 uint32_t :8, 351 command:8, 352 status:16; /** Port writes to indicate success / fail */ 353 #else 354 #error big endian version not defined 355 #endif 356 } sli4_mbox_command_header_t; 357 358 #define SLI4_MBOX_COMMAND_CONFIG_LINK 0x07 359 #define SLI4_MBOX_COMMAND_DUMP 0x17 360 #define SLI4_MBOX_COMMAND_DOWN_LINK 0x06 361 #define SLI4_MBOX_COMMAND_INIT_LINK 0x05 362 #define SLI4_MBOX_COMMAND_INIT_VFI 0xa3 363 #define SLI4_MBOX_COMMAND_INIT_VPI 0xa4 364 #define SLI4_MBOX_COMMAND_POST_XRI 0xa7 365 #define SLI4_MBOX_COMMAND_RELEASE_XRI 0xac 366 #define SLI4_MBOX_COMMAND_READ_CONFIG 0x0b 367 #define SLI4_MBOX_COMMAND_READ_STATUS 0x0e 368 #define SLI4_MBOX_COMMAND_READ_NVPARMS 0x02 369 #define SLI4_MBOX_COMMAND_READ_REV 0x11 370 #define SLI4_MBOX_COMMAND_READ_LNK_STAT 0x12 371 #define SLI4_MBOX_COMMAND_READ_SPARM64 0x8d 372 #define SLI4_MBOX_COMMAND_READ_TOPOLOGY 0x95 373 #define SLI4_MBOX_COMMAND_REG_FCFI 0xa0 374 #define SLI4_MBOX_COMMAND_REG_FCFI_MRQ 0xaf 375 #define SLI4_MBOX_COMMAND_REG_RPI 0x93 376 #define SLI4_MBOX_COMMAND_REG_RX_RQ 0xa6 377 #define SLI4_MBOX_COMMAND_REG_VFI 0x9f 378 #define SLI4_MBOX_COMMAND_REG_VPI 0x96 379 #define SLI4_MBOX_COMMAND_REQUEST_FEATURES 0x9d 380 #define SLI4_MBOX_COMMAND_SLI_CONFIG 0x9b 381 #define SLI4_MBOX_COMMAND_UNREG_FCFI 0xa2 382 #define SLI4_MBOX_COMMAND_UNREG_RPI 0x14 383 #define SLI4_MBOX_COMMAND_UNREG_VFI 0xa1 384 #define SLI4_MBOX_COMMAND_UNREG_VPI 0x97 385 #define SLI4_MBOX_COMMAND_WRITE_NVPARMS 0x03 386 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY 0xAD 387 #define SLI4_MBOX_COMMAND_CONFIG_AUTO_XFER_RDY_HP 0xAE 388 389 #define SLI4_MBOX_STATUS_SUCCESS 0x0000 390 #define SLI4_MBOX_STATUS_FAILURE 0x0001 391 #define SLI4_MBOX_STATUS_RPI_NOT_REG 0x1400 392 393 /** 394 * @brief Buffer Descriptor Entry (BDE) 395 */ 396 typedef struct sli4_bde_s { 397 #if BYTE_ORDER == LITTLE_ENDIAN 398 uint32_t buffer_length:24, 399 bde_type:8; 400 union { 401 struct { 402 uint32_t buffer_address_low; 403 uint32_t buffer_address_high; 404 } data; 405 struct { 406 uint32_t offset; 407 uint32_t rsvd2; 408 } imm; 409 struct { 410 uint32_t sgl_segment_address_low; 411 uint32_t sgl_segment_address_high; 412 } blp; 413 } u; 414 #else 415 #error big endian version not defined 416 #endif 417 } sli4_bde_t; 418 419 #define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */ 420 #define SLI4_BDE_TYPE_BDE_IMM 0x01 /** Immediate data */ 421 #define SLI4_BDE_TYPE_BLP 0x40 /** Buffer List Pointer */ 422 423 /** 424 * @brief Scatter-Gather Entry (SGE) 425 */ 426 typedef struct sli4_sge_s { 427 #if BYTE_ORDER == LITTLE_ENDIAN 428 uint32_t buffer_address_high; 429 uint32_t buffer_address_low; 430 uint32_t data_offset:27, 431 sge_type:4, 432 last:1; 433 uint32_t buffer_length; 434 #else 435 #error big endian version not defined 436 #endif 437 } sli4_sge_t; 438 439 /** 440 * @brief T10 DIF Scatter-Gather Entry (SGE) 441 */ 442 typedef struct sli4_dif_sge_s { 443 #if BYTE_ORDER == LITTLE_ENDIAN 444 uint32_t buffer_address_high; 445 uint32_t buffer_address_low; 446 uint32_t :27, 447 sge_type:4, 448 last:1; 449 uint32_t :32; 450 #else 451 #error big endian version not defined 452 #endif 453 } sli4_dif_sge_t; 454 455 /** 456 * @brief T10 DIF Seed Scatter-Gather Entry (SGE) 457 */ 458 typedef struct sli4_diseed_sge_s { 459 #if BYTE_ORDER == LITTLE_ENDIAN 460 uint32_t ref_tag_cmp; 461 uint32_t ref_tag_repl; 462 uint32_t app_tag_repl:16, 463 :2, 464 hs:1, 465 ws:1, 466 ic:1, 467 ics:1, 468 atrt:1, 469 at:1, 470 fwd_app_tag:1, 471 repl_app_tag:1, 472 head_insert:1, 473 sge_type:4, 474 last:1; 475 uint32_t app_tag_cmp:16, 476 dif_blk_size:3, 477 auto_incr_ref_tag:1, 478 check_app_tag:1, 479 check_ref_tag:1, 480 check_crc:1, 481 new_ref_tag:1, 482 dif_op_rx:4, 483 dif_op_tx:4; 484 #else 485 #error big endian version not defined 486 #endif 487 } sli4_diseed_sge_t; 488 489 /** 490 * @brief List Segment Pointer Scatter-Gather Entry (SGE) 491 */ 492 typedef struct sli4_lsp_sge_s { 493 #if BYTE_ORDER == LITTLE_ENDIAN 494 uint32_t buffer_address_high; 495 uint32_t buffer_address_low; 496 uint32_t :27, 497 sge_type:4, 498 last:1; 499 uint32_t segment_length:24, 500 :8; 501 #else 502 #error big endian version not defined 503 #endif 504 } sli4_lsp_sge_t; 505 506 #define SLI4_SGE_MAX_RESERVED 3 507 508 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CRC 0x00 509 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_NODIF 0x01 510 #define SLI4_SGE_DIF_OP_IN_NODIF_OUT_CHKSUM 0x02 511 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_NODIF 0x03 512 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CRC 0x04 513 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CHKSUM 0x05 514 #define SLI4_SGE_DIF_OP_IN_CRC_OUT_CHKSUM 0x06 515 #define SLI4_SGE_DIF_OP_IN_CHKSUM_OUT_CRC 0x07 516 #define SLI4_SGE_DIF_OP_IN_RAW_OUT_RAW 0x08 517 518 #define SLI4_SGE_TYPE_DATA 0x00 519 #define SLI4_SGE_TYPE_CHAIN 0x03 /** Skyhawk only */ 520 #define SLI4_SGE_TYPE_DIF 0x04 /** Data Integrity Field */ 521 #define SLI4_SGE_TYPE_LSP 0x05 /** List Segment Pointer */ 522 #define SLI4_SGE_TYPE_PEDIF 0x06 /** Post Encryption Engine DIF */ 523 #define SLI4_SGE_TYPE_PESEED 0x07 /** Post Encryption Engine DIF Seed */ 524 #define SLI4_SGE_TYPE_DISEED 0x08 /** DIF Seed */ 525 #define SLI4_SGE_TYPE_ENC 0x09 /** Encryption */ 526 #define SLI4_SGE_TYPE_ATM 0x0a /** DIF Application Tag Mask */ 527 #define SLI4_SGE_TYPE_SKIP 0x0c /** SKIP */ 528 529 #define OCS_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */ 530 531 /** 532 * @brief CONFIG_LINK 533 */ 534 typedef struct sli4_cmd_config_link_s { 535 sli4_mbox_command_header_t hdr; 536 #if BYTE_ORDER == LITTLE_ENDIAN 537 uint32_t maxbbc:8, /** Max buffer-to-buffer credit */ 538 :24; 539 uint32_t alpa:8, 540 n_port_id:16, 541 :8; 542 uint32_t rsvd3; 543 uint32_t e_d_tov; 544 uint32_t lp_tov; 545 uint32_t r_a_tov; 546 uint32_t r_t_tov; 547 uint32_t al_tov; 548 uint32_t rsvd9; 549 uint32_t :8, 550 bbscn:4, /** buffer-to-buffer state change number */ 551 cscn:1, /** configure BBSCN */ 552 :19; 553 #else 554 #error big endian version not defined 555 #endif 556 } sli4_cmd_config_link_t; 557 558 /** 559 * @brief DUMP Type 4 560 */ 561 #define SLI4_WKI_TAG_SAT_TEM 0x1040 562 typedef struct sli4_cmd_dump4_s { 563 sli4_mbox_command_header_t hdr; 564 #if BYTE_ORDER == LITTLE_ENDIAN 565 uint32_t type:4, 566 :28; 567 uint32_t wki_selection:16, 568 :16; 569 uint32_t resv; 570 uint32_t returned_byte_cnt; 571 uint32_t resp_data[59]; 572 #else 573 #error big endian version not defined 574 #endif 575 } sli4_cmd_dump4_t; 576 577 /** 578 * @brief FW_INITIALIZE - initialize a SLI port 579 * 580 * @note This command uses a different format than all others. 581 */ 582 583 extern const uint8_t sli4_fw_initialize[8]; 584 585 /** 586 * @brief FW_DEINITIALIZE - deinitialize a SLI port 587 * 588 * @note This command uses a different format than all others. 589 */ 590 591 extern const uint8_t sli4_fw_deinitialize[8]; 592 593 /** 594 * @brief INIT_LINK - initialize the link for a FC/FCoE port 595 */ 596 typedef struct sli4_cmd_init_link_flags_s { 597 uint32_t loopback:1, 598 topology:2, 599 #define FC_TOPOLOGY_FCAL 0 600 #define FC_TOPOLOGY_P2P 1 601 :3, 602 unfair:1, 603 skip_lirp_lilp:1, 604 gen_loop_validity_check:1, 605 skip_lisa:1, 606 enable_topology_failover:1, 607 fixed_speed:1, 608 :3, 609 select_hightest_al_pa:1, 610 :16; /* pad to 32 bits */ 611 } sli4_cmd_init_link_flags_t; 612 613 #define SLI4_INIT_LINK_F_LOOP_BACK BIT(0) 614 #define SLI4_INIT_LINK_F_UNFAIR BIT(6) 615 #define SLI4_INIT_LINK_F_NO_LIRP BIT(7) 616 #define SLI4_INIT_LINK_F_LOOP_VALID_CHK BIT(8) 617 #define SLI4_INIT_LINK_F_NO_LISA BIT(9) 618 #define SLI4_INIT_LINK_F_FAIL_OVER BIT(10) 619 #define SLI4_INIT_LINK_F_NO_AUTOSPEED BIT(11) 620 #define SLI4_INIT_LINK_F_PICK_HI_ALPA BIT(15) 621 622 #define SLI4_INIT_LINK_F_P2P_ONLY 1 623 #define SLI4_INIT_LINK_F_FCAL_ONLY 2 624 625 #define SLI4_INIT_LINK_F_FCAL_FAIL_OVER 0 626 #define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1 627 628 typedef struct sli4_cmd_init_link_s { 629 sli4_mbox_command_header_t hdr; 630 #if BYTE_ORDER == LITTLE_ENDIAN 631 uint32_t selective_reset_al_pa:8, 632 :24; 633 sli4_cmd_init_link_flags_t link_flags; 634 uint32_t link_speed_selection_code; 635 #define FC_LINK_SPEED_1G 1 636 #define FC_LINK_SPEED_2G 2 637 #define FC_LINK_SPEED_AUTO_1_2 3 638 #define FC_LINK_SPEED_4G 4 639 #define FC_LINK_SPEED_AUTO_4_1 5 640 #define FC_LINK_SPEED_AUTO_4_2 6 641 #define FC_LINK_SPEED_AUTO_4_2_1 7 642 #define FC_LINK_SPEED_8G 8 643 #define FC_LINK_SPEED_AUTO_8_1 9 644 #define FC_LINK_SPEED_AUTO_8_2 10 645 #define FC_LINK_SPEED_AUTO_8_2_1 11 646 #define FC_LINK_SPEED_AUTO_8_4 12 647 #define FC_LINK_SPEED_AUTO_8_4_1 13 648 #define FC_LINK_SPEED_AUTO_8_4_2 14 649 #define FC_LINK_SPEED_10G 16 650 #define FC_LINK_SPEED_16G 17 651 #define FC_LINK_SPEED_AUTO_16_8_4 18 652 #define FC_LINK_SPEED_AUTO_16_8 19 653 #define FC_LINK_SPEED_32G 20 654 #define FC_LINK_SPEED_AUTO_32_16_8 21 655 #define FC_LINK_SPEED_AUTO_32_16 22 656 #else 657 #error big endian version not defined 658 #endif 659 } sli4_cmd_init_link_t; 660 661 /** 662 * @brief INIT_VFI - initialize the VFI resource 663 */ 664 typedef struct sli4_cmd_init_vfi_s { 665 sli4_mbox_command_header_t hdr; 666 #if BYTE_ORDER == LITTLE_ENDIAN 667 uint32_t vfi:16, 668 :12, 669 vp:1, 670 vf:1, 671 vt:1, 672 vr:1; 673 uint32_t fcfi:16, 674 vpi:16; 675 uint32_t vf_id:13, 676 pri:3, 677 :16; 678 uint32_t :24, 679 hop_count:8; 680 #else 681 #error big endian version not defined 682 #endif 683 } sli4_cmd_init_vfi_t; 684 685 /** 686 * @brief INIT_VPI - initialize the VPI resource 687 */ 688 typedef struct sli4_cmd_init_vpi_s { 689 sli4_mbox_command_header_t hdr; 690 #if BYTE_ORDER == LITTLE_ENDIAN 691 uint32_t vpi:16, 692 vfi:16; 693 #else 694 #error big endian version not defined 695 #endif 696 } sli4_cmd_init_vpi_t; 697 698 /** 699 * @brief POST_XRI - post XRI resources to the SLI Port 700 */ 701 typedef struct sli4_cmd_post_xri_s { 702 sli4_mbox_command_header_t hdr; 703 #if BYTE_ORDER == LITTLE_ENDIAN 704 uint32_t xri_base:16, 705 xri_count:12, 706 enx:1, 707 dl:1, 708 di:1, 709 val:1; 710 #else 711 #error big endian version not defined 712 #endif 713 } sli4_cmd_post_xri_t; 714 715 /** 716 * @brief RELEASE_XRI - Release XRI resources from the SLI Port 717 */ 718 typedef struct sli4_cmd_release_xri_s { 719 sli4_mbox_command_header_t hdr; 720 #if BYTE_ORDER == LITTLE_ENDIAN 721 uint32_t released_xri_count:5, 722 :11, 723 xri_count:5, 724 :11; 725 struct { 726 uint32_t xri_tag0:16, 727 xri_tag1:16; 728 } xri_tbl[62]; 729 #else 730 #error big endian version not defined 731 #endif 732 } sli4_cmd_release_xri_t; 733 734 /** 735 * @brief READ_CONFIG - read SLI port configuration parameters 736 */ 737 typedef struct sli4_cmd_read_config_s { 738 sli4_mbox_command_header_t hdr; 739 } sli4_cmd_read_config_t; 740 741 typedef struct sli4_res_read_config_s { 742 sli4_mbox_command_header_t hdr; 743 #if BYTE_ORDER == LITTLE_ENDIAN 744 uint32_t :31, 745 ext:1; /** Resource Extents */ 746 uint32_t :24, 747 topology:8; 748 uint32_t rsvd3; 749 uint32_t e_d_tov:16, 750 :16; 751 uint32_t rsvd5; 752 uint32_t r_a_tov:16, 753 :16; 754 uint32_t rsvd7; 755 uint32_t rsvd8; 756 uint32_t lmt:16, /** Link Module Type */ 757 :16; 758 uint32_t rsvd10; 759 uint32_t rsvd11; 760 uint32_t xri_base:16, 761 xri_count:16; 762 uint32_t rpi_base:16, 763 rpi_count:16; 764 uint32_t vpi_base:16, 765 vpi_count:16; 766 uint32_t vfi_base:16, 767 vfi_count:16; 768 uint32_t :16, 769 fcfi_count:16; 770 uint32_t rq_count:16, 771 eq_count:16; 772 uint32_t wq_count:16, 773 cq_count:16; 774 uint32_t pad[45]; 775 #else 776 #error big endian version not defined 777 #endif 778 } sli4_res_read_config_t; 779 780 #define SLI4_READ_CFG_TOPO_FCOE 0x0 /** FCoE topology */ 781 #define SLI4_READ_CFG_TOPO_FC 0x1 /** FC topology unknown */ 782 #define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */ 783 #define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */ 784 785 /** 786 * @brief READ_NVPARMS - read SLI port configuration parameters 787 */ 788 typedef struct sli4_cmd_read_nvparms_s { 789 sli4_mbox_command_header_t hdr; 790 #if BYTE_ORDER == LITTLE_ENDIAN 791 uint32_t rsvd1; 792 uint32_t rsvd2; 793 uint32_t rsvd3; 794 uint32_t rsvd4; 795 uint8_t wwpn[8]; 796 uint8_t wwnn[8]; 797 uint32_t hard_alpa:8, 798 preferred_d_id:24; 799 #else 800 #error big endian version not defined 801 #endif 802 } sli4_cmd_read_nvparms_t; 803 804 /** 805 * @brief WRITE_NVPARMS - write SLI port configuration parameters 806 */ 807 typedef struct sli4_cmd_write_nvparms_s { 808 sli4_mbox_command_header_t hdr; 809 #if BYTE_ORDER == LITTLE_ENDIAN 810 uint32_t rsvd1; 811 uint32_t rsvd2; 812 uint32_t rsvd3; 813 uint32_t rsvd4; 814 uint8_t wwpn[8]; 815 uint8_t wwnn[8]; 816 uint32_t hard_alpa:8, 817 preferred_d_id:24; 818 #else 819 #error big endian version not defined 820 #endif 821 } sli4_cmd_write_nvparms_t; 822 823 /** 824 * @brief READ_REV - read the Port revision levels 825 */ 826 typedef struct sli4_cmd_read_rev_s { 827 sli4_mbox_command_header_t hdr; 828 #if BYTE_ORDER == LITTLE_ENDIAN 829 uint32_t :16, 830 sli_level:4, 831 fcoem:1, 832 ceev:2, 833 :6, 834 vpd:1, 835 :2; 836 uint32_t first_hw_revision; 837 uint32_t second_hw_revision; 838 uint32_t rsvd4; 839 uint32_t third_hw_revision; 840 uint32_t fc_ph_low:8, 841 fc_ph_high:8, 842 feature_level_low:8, 843 feature_level_high:8; 844 uint32_t rsvd7; 845 uint32_t first_fw_id; 846 char first_fw_name[16]; 847 uint32_t second_fw_id; 848 char second_fw_name[16]; 849 uint32_t rsvd18[30]; 850 uint32_t available_length:24, 851 :8; 852 uint32_t physical_address_low; 853 uint32_t physical_address_high; 854 uint32_t returned_vpd_length; 855 uint32_t actual_vpd_length; 856 #else 857 #error big endian version not defined 858 #endif 859 } sli4_cmd_read_rev_t; 860 861 /** 862 * @brief READ_SPARM64 - read the Port service parameters 863 */ 864 typedef struct sli4_cmd_read_sparm64_s { 865 sli4_mbox_command_header_t hdr; 866 #if BYTE_ORDER == LITTLE_ENDIAN 867 uint32_t rsvd1; 868 uint32_t rsvd2; 869 sli4_bde_t bde_64; 870 uint32_t vpi:16, 871 :16; 872 uint32_t port_name_start:16, 873 port_name_length:16; 874 uint32_t node_name_start:16, 875 node_name_length:16; 876 #else 877 #error big endian version not defined 878 #endif 879 } sli4_cmd_read_sparm64_t; 880 881 #define SLI4_READ_SPARM64_VPI_DEFAULT 0 882 #define SLI4_READ_SPARM64_VPI_SPECIAL UINT16_MAX 883 884 #define SLI4_READ_SPARM64_WWPN_OFFSET (4 * sizeof(uint32_t)) 885 #define SLI4_READ_SPARM64_WWNN_OFFSET (SLI4_READ_SPARM64_WWPN_OFFSET + sizeof(uint64_t)) 886 887 typedef struct sli4_port_state_s { 888 #if BYTE_ORDER == LITTLE_ENDIAN 889 uint32_t nx_port_recv_state:2, 890 nx_port_trans_state:2, 891 nx_port_state_machine:4, 892 link_speed:8, 893 :14, 894 tf:1, 895 lu:1; 896 #else 897 #error big endian version not defined 898 #endif 899 } sli4_port_state_t; 900 901 /** 902 * @brief READ_TOPOLOGY - read the link event information 903 */ 904 typedef struct sli4_cmd_read_topology_s { 905 sli4_mbox_command_header_t hdr; 906 #if BYTE_ORDER == LITTLE_ENDIAN 907 uint32_t event_tag; 908 uint32_t attention_type:8, 909 il:1, 910 pb_recvd:1, 911 :22; 912 uint32_t topology:8, 913 lip_type:8, 914 lip_al_ps:8, 915 al_pa_granted:8; 916 sli4_bde_t bde_loop_map; 917 sli4_port_state_t link_down; 918 sli4_port_state_t link_current; 919 uint32_t max_bbc:8, 920 init_bbc:8, 921 bbscn:4, 922 cbbscn:4, 923 :8; 924 uint32_t r_t_tov:9, 925 :3, 926 al_tov:4, 927 lp_tov:16; 928 uint32_t acquired_al_pa:8, 929 :7, 930 pb:1, 931 specified_al_pa:16; 932 uint32_t initial_n_port_id:24, 933 :8; 934 #else 935 #error big endian version not defined 936 #endif 937 } sli4_cmd_read_topology_t; 938 939 #define SLI4_MIN_LOOP_MAP_BYTES 128 940 941 #define SLI4_READ_TOPOLOGY_LINK_UP 0x1 942 #define SLI4_READ_TOPOLOGY_LINK_DOWN 0x2 943 #define SLI4_READ_TOPOLOGY_LINK_NO_ALPA 0x3 944 945 #define SLI4_READ_TOPOLOGY_UNKNOWN 0x0 946 #define SLI4_READ_TOPOLOGY_NPORT 0x1 947 #define SLI4_READ_TOPOLOGY_FC_AL 0x2 948 949 #define SLI4_READ_TOPOLOGY_SPEED_NONE 0x00 950 #define SLI4_READ_TOPOLOGY_SPEED_1G 0x04 951 #define SLI4_READ_TOPOLOGY_SPEED_2G 0x08 952 #define SLI4_READ_TOPOLOGY_SPEED_4G 0x10 953 #define SLI4_READ_TOPOLOGY_SPEED_8G 0x20 954 #define SLI4_READ_TOPOLOGY_SPEED_10G 0x40 955 #define SLI4_READ_TOPOLOGY_SPEED_16G 0x80 956 #define SLI4_READ_TOPOLOGY_SPEED_32G 0x90 957 958 /** 959 * @brief REG_FCFI - activate a FC Forwarder 960 */ 961 #define SLI4_CMD_REG_FCFI_NUM_RQ_CFG 4 962 typedef struct sli4_cmd_reg_fcfi_s { 963 sli4_mbox_command_header_t hdr; 964 #if BYTE_ORDER == LITTLE_ENDIAN 965 uint32_t fcf_index:16, 966 fcfi:16; 967 uint32_t rq_id_1:16, 968 rq_id_0:16; 969 uint32_t rq_id_3:16, 970 rq_id_2:16; 971 struct { 972 uint32_t r_ctl_mask:8, 973 r_ctl_match:8, 974 type_mask:8, 975 type_match:8; 976 } rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG]; 977 uint32_t vlan_tag:12, 978 vv:1, 979 :19; 980 #else 981 #error big endian version not defined 982 #endif 983 } sli4_cmd_reg_fcfi_t; 984 985 #define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG 4 986 #define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ 32 987 #define SLI4_CMD_REG_FCFI_SET_FCFI_MODE 0 988 #define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1 989 990 typedef struct sli4_cmd_reg_fcfi_mrq_s { 991 sli4_mbox_command_header_t hdr; 992 #if BYTE_ORDER == LITTLE_ENDIAN 993 uint32_t fcf_index:16, 994 fcfi:16; 995 996 uint32_t rq_id_1:16, 997 rq_id_0:16; 998 999 uint32_t rq_id_3:16, 1000 rq_id_2:16; 1001 1002 struct { 1003 uint32_t r_ctl_mask:8, 1004 r_ctl_match:8, 1005 type_mask:8, 1006 type_match:8; 1007 } rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG]; 1008 1009 uint32_t vlan_tag:12, 1010 vv:1, 1011 mode:1, 1012 :18; 1013 1014 uint32_t num_mrq_pairs:8, 1015 mrq_filter_bitmask:4, 1016 rq_selection_policy:4, 1017 :16; 1018 #endif 1019 } sli4_cmd_reg_fcfi_mrq_t; 1020 1021 /** 1022 * @brief REG_RPI - register a Remote Port Indicator 1023 */ 1024 typedef struct sli4_cmd_reg_rpi_s { 1025 sli4_mbox_command_header_t hdr; 1026 #if BYTE_ORDER == LITTLE_ENDIAN 1027 uint32_t rpi:16, 1028 :16; 1029 uint32_t remote_n_port_id:24, 1030 upd:1, 1031 :2, 1032 etow:1, 1033 :1, 1034 terp:1, 1035 :1, 1036 ci:1; 1037 sli4_bde_t bde_64; 1038 uint32_t vpi:16, 1039 :16; 1040 #else 1041 #error big endian version not defined 1042 #endif 1043 } sli4_cmd_reg_rpi_t; 1044 #define SLI4_REG_RPI_BUF_LEN 0x70 1045 1046 /** 1047 * @brief REG_VFI - register a Virtual Fabric Indicator 1048 */ 1049 typedef struct sli4_cmd_reg_vfi_s { 1050 sli4_mbox_command_header_t hdr; 1051 #if BYTE_ORDER == LITTLE_ENDIAN 1052 uint32_t vfi:16, 1053 :12, 1054 vp:1, 1055 upd:1, 1056 :2; 1057 uint32_t fcfi:16, 1058 vpi:16; /* vp=TRUE */ 1059 uint8_t wwpn[8]; /* vp=TRUE */ 1060 sli4_bde_t sparm; /* either FLOGI or PLOGI */ 1061 uint32_t e_d_tov; 1062 uint32_t r_a_tov; 1063 uint32_t local_n_port_id:24, /* vp=TRUE */ 1064 :8; 1065 #else 1066 #error big endian version not defined 1067 #endif 1068 } sli4_cmd_reg_vfi_t; 1069 1070 /** 1071 * @brief REG_VPI - register a Virtual Port Indicator 1072 */ 1073 typedef struct sli4_cmd_reg_vpi_s { 1074 sli4_mbox_command_header_t hdr; 1075 #if BYTE_ORDER == LITTLE_ENDIAN 1076 uint32_t rsvd1; 1077 uint32_t local_n_port_id:24, 1078 upd:1, 1079 :7; 1080 uint8_t wwpn[8]; 1081 uint32_t rsvd5; 1082 uint32_t vpi:16, 1083 vfi:16; 1084 #else 1085 #error big endian version not defined 1086 #endif 1087 } sli4_cmd_reg_vpi_t; 1088 1089 /** 1090 * @brief REQUEST_FEATURES - request / query SLI features 1091 */ 1092 typedef union { 1093 #if BYTE_ORDER == LITTLE_ENDIAN 1094 struct { 1095 uint32_t iaab:1, /** inhibit auto-ABTS originator */ 1096 npiv:1, /** NPIV support */ 1097 dif:1, /** DIF/DIX support */ 1098 vf:1, /** virtual fabric support */ 1099 fcpi:1, /** FCP initiator support */ 1100 fcpt:1, /** FCP target support */ 1101 fcpc:1, /** combined FCP initiator/target */ 1102 :1, 1103 rqd:1, /** recovery qualified delay */ 1104 iaar:1, /** inhibit auto-ABTS responder */ 1105 hlm:1, /** High Login Mode */ 1106 perfh:1, /** performance hints */ 1107 rxseq:1, /** RX Sequence Coalescing */ 1108 rxri:1, /** Release XRI variant of Coalescing */ 1109 dcl2:1, /** Disable Class 2 */ 1110 rsco:1, /** Receive Sequence Coalescing Optimizations */ 1111 mrqp:1, /** Multi RQ Pair Mode Support */ 1112 :15; 1113 } flag; 1114 uint32_t dword; 1115 #else 1116 #error big endian version not defined 1117 #endif 1118 } sli4_features_t; 1119 1120 typedef struct sli4_cmd_request_features_s { 1121 sli4_mbox_command_header_t hdr; 1122 #if BYTE_ORDER == LITTLE_ENDIAN 1123 uint32_t qry:1, 1124 :31; 1125 #else 1126 #error big endian version not defined 1127 #endif 1128 sli4_features_t command; 1129 sli4_features_t response; 1130 } sli4_cmd_request_features_t; 1131 1132 /** 1133 * @brief SLI_CONFIG - submit a configuration command to Port 1134 * 1135 * Command is either embedded as part of the payload (embed) or located 1136 * in a separate memory buffer (mem) 1137 */ 1138 1139 typedef struct sli4_sli_config_pmd_s { 1140 uint32_t address_low; 1141 uint32_t address_high; 1142 uint32_t length:24, 1143 :8; 1144 } sli4_sli_config_pmd_t; 1145 1146 typedef struct sli4_cmd_sli_config_s { 1147 sli4_mbox_command_header_t hdr; 1148 #if BYTE_ORDER == LITTLE_ENDIAN 1149 uint32_t emb:1, 1150 :2, 1151 pmd_count:5, 1152 :24; 1153 uint32_t payload_length; 1154 uint32_t rsvd3; 1155 uint32_t rsvd4; 1156 uint32_t rsvd5; 1157 union { 1158 uint8_t embed[58 * sizeof(uint32_t)]; 1159 sli4_sli_config_pmd_t mem; 1160 } payload; 1161 #else 1162 #error big endian version not defined 1163 #endif 1164 } sli4_cmd_sli_config_t; 1165 1166 /** 1167 * @brief READ_STATUS - read tx/rx status of a particular port 1168 * 1169 */ 1170 1171 typedef struct sli4_cmd_read_status_s { 1172 sli4_mbox_command_header_t hdr; 1173 #if BYTE_ORDER == LITTLE_ENDIAN 1174 uint32_t cc:1, 1175 :31; 1176 uint32_t rsvd2; 1177 uint32_t transmit_kbyte_count; 1178 uint32_t receive_kbyte_count; 1179 uint32_t transmit_frame_count; 1180 uint32_t receive_frame_count; 1181 uint32_t transmit_sequence_count; 1182 uint32_t receive_sequence_count; 1183 uint32_t total_exchanges_originator; 1184 uint32_t total_exchanges_responder; 1185 uint32_t receive_p_bsy_count; 1186 uint32_t receive_f_bsy_count; 1187 uint32_t dropped_frames_due_to_no_rq_buffer_count; 1188 uint32_t empty_rq_timeout_count; 1189 uint32_t dropped_frames_due_to_no_xri_count; 1190 uint32_t empty_xri_pool_count; 1191 1192 #else 1193 #error big endian version not defined 1194 #endif 1195 } sli4_cmd_read_status_t; 1196 1197 /** 1198 * @brief READ_LNK_STAT - read link status of a particular port 1199 * 1200 */ 1201 1202 typedef struct sli4_cmd_read_link_stats_s { 1203 sli4_mbox_command_header_t hdr; 1204 #if BYTE_ORDER == LITTLE_ENDIAN 1205 uint32_t rec:1, 1206 gec:1, 1207 w02of:1, 1208 w03of:1, 1209 w04of:1, 1210 w05of:1, 1211 w06of:1, 1212 w07of:1, 1213 w08of:1, 1214 w09of:1, 1215 w10of:1, 1216 w11of:1, 1217 w12of:1, 1218 w13of:1, 1219 w14of:1, 1220 w15of:1, 1221 w16of:1, 1222 w17of:1, 1223 w18of:1, 1224 w19of:1, 1225 w20of:1, 1226 w21of:1, 1227 resv0:8, 1228 clrc:1, 1229 clof:1; 1230 uint32_t link_failure_error_count; 1231 uint32_t loss_of_sync_error_count; 1232 uint32_t loss_of_signal_error_count; 1233 uint32_t primitive_sequence_error_count; 1234 uint32_t invalid_transmission_word_error_count; 1235 uint32_t crc_error_count; 1236 uint32_t primitive_sequence_event_timeout_count; 1237 uint32_t elastic_buffer_overrun_error_count; 1238 uint32_t arbitration_fc_al_timout_count; 1239 uint32_t advertised_receive_bufftor_to_buffer_credit; 1240 uint32_t current_receive_buffer_to_buffer_credit; 1241 uint32_t advertised_transmit_buffer_to_buffer_credit; 1242 uint32_t current_transmit_buffer_to_buffer_credit; 1243 uint32_t received_eofa_count; 1244 uint32_t received_eofdti_count; 1245 uint32_t received_eofni_count; 1246 uint32_t received_soff_count; 1247 uint32_t received_dropped_no_aer_count; 1248 uint32_t received_dropped_no_available_rpi_resources_count; 1249 uint32_t received_dropped_no_available_xri_resources_count; 1250 1251 #else 1252 #error big endian version not defined 1253 #endif 1254 } sli4_cmd_read_link_stats_t; 1255 1256 /** 1257 * @brief Format a WQE with WQ_ID Association performance hint 1258 * 1259 * @par Description 1260 * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID. 1261 * 1262 * @param entry Pointer to the WQE. 1263 * @param q_id Queue ID. 1264 * 1265 * @return None. 1266 */ 1267 static inline void 1268 sli_set_wq_id_association(void *entry, uint16_t q_id) 1269 { 1270 uint32_t *wqe = entry; 1271 1272 /* 1273 * Set Word 10, bit 0 to zero 1274 * Set Word 10, bits 15:1 to the WQ ID 1275 */ 1276 #if BYTE_ORDER == LITTLE_ENDIAN 1277 wqe[10] &= ~0xffff; 1278 wqe[10] |= q_id << 1; 1279 #else 1280 #error big endian version not defined 1281 #endif 1282 } 1283 1284 /** 1285 * @brief UNREG_FCFI - unregister a FCFI 1286 */ 1287 typedef struct sli4_cmd_unreg_fcfi_s { 1288 sli4_mbox_command_header_t hdr; 1289 uint32_t rsvd1; 1290 #if BYTE_ORDER == LITTLE_ENDIAN 1291 uint32_t fcfi:16, 1292 :16; 1293 #else 1294 #error big endian version not defined 1295 #endif 1296 } sli4_cmd_unreg_fcfi_t; 1297 1298 /** 1299 * @brief UNREG_RPI - unregister one or more RPI 1300 */ 1301 typedef struct sli4_cmd_unreg_rpi_s { 1302 sli4_mbox_command_header_t hdr; 1303 #if BYTE_ORDER == LITTLE_ENDIAN 1304 uint32_t index:16, 1305 :13, 1306 dp:1, 1307 ii:2; 1308 uint32_t destination_n_port_id:24, 1309 :8; 1310 #else 1311 #error big endian version not defined 1312 #endif 1313 } sli4_cmd_unreg_rpi_t; 1314 1315 #define SLI4_UNREG_RPI_II_RPI 0x0 1316 #define SLI4_UNREG_RPI_II_VPI 0x1 1317 #define SLI4_UNREG_RPI_II_VFI 0x2 1318 #define SLI4_UNREG_RPI_II_FCFI 0x3 1319 1320 /** 1321 * @brief UNREG_VFI - unregister one or more VFI 1322 */ 1323 typedef struct sli4_cmd_unreg_vfi_s { 1324 sli4_mbox_command_header_t hdr; 1325 #if BYTE_ORDER == LITTLE_ENDIAN 1326 uint32_t rsvd1; 1327 uint32_t index:16, 1328 :14, 1329 ii:2; 1330 #else 1331 #error big endian version not defined 1332 #endif 1333 } sli4_cmd_unreg_vfi_t; 1334 1335 #define SLI4_UNREG_VFI_II_VFI 0x0 1336 #define SLI4_UNREG_VFI_II_FCFI 0x3 1337 1338 enum { 1339 SLI4_UNREG_TYPE_PORT, 1340 SLI4_UNREG_TYPE_DOMAIN, 1341 SLI4_UNREG_TYPE_FCF, 1342 SLI4_UNREG_TYPE_ALL 1343 }; 1344 1345 /** 1346 * @brief UNREG_VPI - unregister one or more VPI 1347 */ 1348 typedef struct sli4_cmd_unreg_vpi_s { 1349 sli4_mbox_command_header_t hdr; 1350 #if BYTE_ORDER == LITTLE_ENDIAN 1351 uint32_t rsvd1; 1352 uint32_t index:16, 1353 :14, 1354 ii:2; 1355 #else 1356 #error big endian version not defined 1357 #endif 1358 } sli4_cmd_unreg_vpi_t; 1359 1360 #define SLI4_UNREG_VPI_II_VPI 0x0 1361 #define SLI4_UNREG_VPI_II_VFI 0x2 1362 #define SLI4_UNREG_VPI_II_FCFI 0x3 1363 1364 /** 1365 * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature. 1366 */ 1367 typedef struct sli4_cmd_config_auto_xfer_rdy_s { 1368 sli4_mbox_command_header_t hdr; 1369 #if BYTE_ORDER == LITTLE_ENDIAN 1370 uint32_t resv; 1371 uint32_t max_burst_len; 1372 #else 1373 #error big endian version not defined 1374 #endif 1375 } sli4_cmd_config_auto_xfer_rdy_t; 1376 1377 typedef struct sli4_cmd_config_auto_xfer_rdy_hp_s { 1378 sli4_mbox_command_header_t hdr; 1379 #if BYTE_ORDER == LITTLE_ENDIAN 1380 uint32_t resv; 1381 uint32_t max_burst_len; 1382 uint32_t esoc:1, 1383 :31; 1384 uint32_t block_size:16, 1385 :16; 1386 #else 1387 #error big endian version not defined 1388 #endif 1389 } sli4_cmd_config_auto_xfer_rdy_hp_t; 1390 1391 /************************************************************************* 1392 * SLI-4 common configuration command formats and definitions 1393 */ 1394 1395 #define SLI4_CFG_STATUS_SUCCESS 0x00 1396 #define SLI4_CFG_STATUS_FAILED 0x01 1397 #define SLI4_CFG_STATUS_ILLEGAL_REQUEST 0x02 1398 #define SLI4_CFG_STATUS_ILLEGAL_FIELD 0x03 1399 1400 #define SLI4_MGMT_STATUS_FLASHROM_READ_FAILED 0xcb 1401 1402 #define SLI4_CFG_ADD_STATUS_NO_STATUS 0x00 1403 #define SLI4_CFG_ADD_STATUS_INVALID_OPCODE 0x1e 1404 1405 /** 1406 * Subsystem values. 1407 */ 1408 #define SLI4_SUBSYSTEM_COMMON 0x01 1409 #define SLI4_SUBSYSTEM_LOWLEVEL 0x0B 1410 #define SLI4_SUBSYSTEM_FCFCOE 0x0c 1411 #define SLI4_SUBSYSTEM_DMTF 0x11 1412 1413 #define SLI4_OPC_LOWLEVEL_SET_WATCHDOG 0X36 1414 1415 /** 1416 * Common opcode (OPC) values. 1417 */ 1418 #define SLI4_OPC_COMMON_FUNCTION_RESET 0x3d 1419 #define SLI4_OPC_COMMON_CREATE_CQ 0x0c 1420 #define SLI4_OPC_COMMON_CREATE_CQ_SET 0x1d 1421 #define SLI4_OPC_COMMON_DESTROY_CQ 0x36 1422 #define SLI4_OPC_COMMON_MODIFY_EQ_DELAY 0x29 1423 #define SLI4_OPC_COMMON_CREATE_EQ 0x0d 1424 #define SLI4_OPC_COMMON_DESTROY_EQ 0x37 1425 #define SLI4_OPC_COMMON_CREATE_MQ_EXT 0x5a 1426 #define SLI4_OPC_COMMON_DESTROY_MQ 0x35 1427 #define SLI4_OPC_COMMON_GET_CNTL_ATTRIBUTES 0x20 1428 #define SLI4_OPC_COMMON_NOP 0x21 1429 #define SLI4_OPC_COMMON_GET_RESOURCE_EXTENT_INFO 0x9a 1430 #define SLI4_OPC_COMMON_GET_SLI4_PARAMETERS 0xb5 1431 #define SLI4_OPC_COMMON_QUERY_FW_CONFIG 0x3a 1432 #define SLI4_OPC_COMMON_GET_PORT_NAME 0x4d 1433 1434 #define SLI4_OPC_COMMON_WRITE_FLASHROM 0x07 1435 #define SLI4_OPC_COMMON_MANAGE_FAT 0x44 1436 #define SLI4_OPC_COMMON_READ_TRANSCEIVER_DATA 0x49 1437 #define SLI4_OPC_COMMON_GET_CNTL_ADDL_ATTRIBUTES 0x79 1438 #define SLI4_OPC_COMMON_GET_EXT_FAT_CAPABILITIES 0x7d 1439 #define SLI4_OPC_COMMON_SET_EXT_FAT_CAPABILITIES 0x7e 1440 #define SLI4_OPC_COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 0x7f 1441 #define SLI4_OPC_COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 0x80 1442 #define SLI4_OPC_COMMON_EXT_FAT_READ_STRING_TABLE 0x82 1443 #define SLI4_OPC_COMMON_GET_FUNCTION_CONFIG 0xa0 1444 #define SLI4_OPC_COMMON_GET_PROFILE_CONFIG 0xa4 1445 #define SLI4_OPC_COMMON_SET_PROFILE_CONFIG 0xa5 1446 #define SLI4_OPC_COMMON_GET_PROFILE_LIST 0xa6 1447 #define SLI4_OPC_COMMON_GET_ACTIVE_PROFILE 0xa7 1448 #define SLI4_OPC_COMMON_SET_ACTIVE_PROFILE 0xa8 1449 #define SLI4_OPC_COMMON_READ_OBJECT 0xab 1450 #define SLI4_OPC_COMMON_WRITE_OBJECT 0xac 1451 #define SLI4_OPC_COMMON_DELETE_OBJECT 0xae 1452 #define SLI4_OPC_COMMON_READ_OBJECT_LIST 0xad 1453 #define SLI4_OPC_COMMON_SET_DUMP_LOCATION 0xb8 1454 #define SLI4_OPC_COMMON_SET_FEATURES 0xbf 1455 #define SLI4_OPC_COMMON_GET_RECONFIG_LINK_INFO 0xc9 1456 #define SLI4_OPC_COMMON_SET_RECONFIG_LINK_ID 0xca 1457 1458 /** 1459 * DMTF opcode (OPC) values. 1460 */ 1461 #define SLI4_OPC_DMTF_EXEC_CLP_CMD 0x01 1462 1463 /** 1464 * @brief Generic Command Request header 1465 */ 1466 typedef struct sli4_req_hdr_s { 1467 #if BYTE_ORDER == LITTLE_ENDIAN 1468 uint32_t opcode:8, 1469 subsystem:8, 1470 :16; 1471 uint32_t timeout; 1472 uint32_t request_length; 1473 uint32_t version:8, 1474 :24; 1475 #else 1476 #error big endian version not defined 1477 #endif 1478 } sli4_req_hdr_t; 1479 1480 /** 1481 * @brief Generic Command Response header 1482 */ 1483 typedef struct sli4_res_hdr_s { 1484 #if BYTE_ORDER == LITTLE_ENDIAN 1485 uint32_t opcode:8, 1486 subsystem:8, 1487 :16; 1488 uint32_t status:8, 1489 additional_status:8, 1490 :16; 1491 uint32_t response_length; 1492 uint32_t actual_response_length; 1493 #else 1494 #error big endian version not defined 1495 #endif 1496 } sli4_res_hdr_t; 1497 1498 /** 1499 * @brief COMMON_FUNCTION_RESET 1500 * 1501 * Resets the Port, returning it to a power-on state. This configuration 1502 * command does not have a payload and should set/expect the lengths to 1503 * be zero. 1504 */ 1505 typedef struct sli4_req_common_function_reset_s { 1506 sli4_req_hdr_t hdr; 1507 } sli4_req_common_function_reset_t; 1508 1509 typedef struct sli4_res_common_function_reset_s { 1510 sli4_res_hdr_t hdr; 1511 } sli4_res_common_function_reset_t; 1512 1513 /** 1514 * @brief COMMON_CREATE_CQ_V0 1515 * 1516 * Create a Completion Queue. 1517 */ 1518 typedef struct sli4_req_common_create_cq_v0_s { 1519 sli4_req_hdr_t hdr; 1520 #if BYTE_ORDER == LITTLE_ENDIAN 1521 uint32_t num_pages:16, 1522 :16; 1523 uint32_t :12, 1524 clswm:2, 1525 nodelay:1, 1526 :12, 1527 cqecnt:2, 1528 valid:1, 1529 :1, 1530 evt:1; 1531 uint32_t :22, 1532 eq_id:8, 1533 :1, 1534 arm:1; 1535 uint32_t rsvd[2]; 1536 struct { 1537 uint32_t low; 1538 uint32_t high; 1539 } page_physical_address[0]; 1540 #else 1541 #error big endian version not defined 1542 #endif 1543 } sli4_req_common_create_cq_v0_t; 1544 1545 /** 1546 * @brief COMMON_CREATE_CQ_V2 1547 * 1548 * Create a Completion Queue. 1549 */ 1550 typedef struct sli4_req_common_create_cq_v2_s { 1551 sli4_req_hdr_t hdr; 1552 #if BYTE_ORDER == LITTLE_ENDIAN 1553 uint32_t num_pages:16, 1554 page_size:8, 1555 :8, 1556 uint32_t :12, 1557 clswm:2, 1558 nodelay:1, 1559 autovalid:1, 1560 :11, 1561 cqecnt:2, 1562 valid:1, 1563 :1, 1564 evt:1; 1565 uint32_t eq_id:16, 1566 :15, 1567 arm:1; 1568 uint32_t cqe_count:16, 1569 :16; 1570 uint32_t rsvd[1]; 1571 struct { 1572 uint32_t low; 1573 uint32_t high; 1574 } page_physical_address[0]; 1575 #else 1576 #error big endian version not defined 1577 #endif 1578 } sli4_req_common_create_cq_v2_t; 1579 1580 /** 1581 * @brief COMMON_CREATE_CQ_SET_V0 1582 * 1583 * Create a set of Completion Queues. 1584 */ 1585 typedef struct sli4_req_common_create_cq_set_v0_s { 1586 sli4_req_hdr_t hdr; 1587 #if BYTE_ORDER == LITTLE_ENDIAN 1588 uint32_t num_pages:16, 1589 page_size:8, 1590 :8; 1591 uint32_t :12, 1592 clswm:2, 1593 nodelay:1, 1594 autovalid:1, 1595 rsvd:11, 1596 cqecnt:2, 1597 valid:1, 1598 :1, 1599 evt:1; 1600 uint32_t num_cq_req:16, 1601 cqe_count:15, 1602 arm:1; 1603 uint16_t eq_id[16]; 1604 struct { 1605 uint32_t low; 1606 uint32_t high; 1607 } page_physical_address[0]; 1608 #else 1609 #error big endian version not defined 1610 #endif 1611 } sli4_req_common_create_cq_set_v0_t; 1612 1613 /** 1614 * CQE count. 1615 */ 1616 #define SLI4_CQ_CNT_256 0 1617 #define SLI4_CQ_CNT_512 1 1618 #define SLI4_CQ_CNT_1024 2 1619 #define SLI4_CQ_CNT_LARGE 3 1620 1621 #define SLI4_CQE_BYTES (4 * sizeof(uint32_t)) 1622 1623 #define SLI4_COMMON_CREATE_CQ_V2_MAX_PAGES 8 1624 1625 /** 1626 * @brief Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion 1627 */ 1628 typedef struct sli4_res_common_create_queue_s { 1629 sli4_res_hdr_t hdr; 1630 #if BYTE_ORDER == LITTLE_ENDIAN 1631 uint32_t q_id:16, 1632 :8, 1633 ulp:8; 1634 uint32_t db_offset; 1635 uint32_t db_rs:16, 1636 db_fmt:16; 1637 #else 1638 #error big endian version not defined 1639 #endif 1640 } sli4_res_common_create_queue_t; 1641 1642 typedef struct sli4_res_common_create_queue_set_s { 1643 sli4_res_hdr_t hdr; 1644 #if BYTE_ORDER == LITTLE_ENDIAN 1645 uint32_t q_id:16, 1646 num_q_allocated:16; 1647 #else 1648 #error big endian version not defined 1649 #endif 1650 } sli4_res_common_create_queue_set_t; 1651 1652 /** 1653 * @brief Common Destroy CQ 1654 */ 1655 typedef struct sli4_req_common_destroy_cq_s { 1656 sli4_req_hdr_t hdr; 1657 #if BYTE_ORDER == LITTLE_ENDIAN 1658 uint32_t cq_id:16, 1659 :16; 1660 #else 1661 #error big endian version not defined 1662 #endif 1663 } sli4_req_common_destroy_cq_t; 1664 1665 /** 1666 * @brief COMMON_MODIFY_EQ_DELAY 1667 * 1668 * Modify the delay multiplier for EQs 1669 */ 1670 typedef struct sli4_req_common_modify_eq_delay_s { 1671 sli4_req_hdr_t hdr; 1672 #if BYTE_ORDER == LITTLE_ENDIAN 1673 uint32_t num_eq; 1674 struct { 1675 uint32_t eq_id; 1676 uint32_t phase; 1677 uint32_t delay_multiplier; 1678 } eq_delay_record[8]; 1679 #else 1680 #error big endian version not defined 1681 #endif 1682 } sli4_req_common_modify_eq_delay_t; 1683 1684 /** 1685 * @brief COMMON_CREATE_EQ 1686 * 1687 * Create an Event Queue. 1688 */ 1689 typedef struct sli4_req_common_create_eq_s { 1690 sli4_req_hdr_t hdr; 1691 #if BYTE_ORDER == LITTLE_ENDIAN 1692 uint32_t num_pages:16, 1693 :16; 1694 uint32_t :29, 1695 valid:1, 1696 :1, 1697 eqesz:1; 1698 uint32_t :26, 1699 count:3, 1700 :2, 1701 arm:1; 1702 uint32_t :13, 1703 delay_multiplier:10, 1704 :9; 1705 uint32_t rsvd; 1706 struct { 1707 uint32_t low; 1708 uint32_t high; 1709 } page_address[8]; 1710 #else 1711 #error big endian version not defined 1712 #endif 1713 } sli4_req_common_create_eq_t; 1714 1715 #define SLI4_EQ_CNT_256 0 1716 #define SLI4_EQ_CNT_512 1 1717 #define SLI4_EQ_CNT_1024 2 1718 #define SLI4_EQ_CNT_2048 3 1719 #define SLI4_EQ_CNT_4096 4 1720 1721 #define SLI4_EQE_SIZE_4 0 1722 #define SLI4_EQE_SIZE_16 1 1723 1724 /** 1725 * @brief Common Destroy EQ 1726 */ 1727 typedef struct sli4_req_common_destroy_eq_s { 1728 sli4_req_hdr_t hdr; 1729 #if BYTE_ORDER == LITTLE_ENDIAN 1730 uint32_t eq_id:16, 1731 :16; 1732 #else 1733 #error big endian version not defined 1734 #endif 1735 } sli4_req_common_destroy_eq_t; 1736 1737 /** 1738 * @brief COMMON_CREATE_MQ_EXT 1739 * 1740 * Create a Mailbox Queue; accommodate v0 and v1 forms. 1741 */ 1742 typedef struct sli4_req_common_create_mq_ext_s { 1743 sli4_req_hdr_t hdr; 1744 #if BYTE_ORDER == LITTLE_ENDIAN 1745 uint32_t num_pages:16, 1746 cq_id_v1:16; 1747 uint32_t async_event_bitmap; 1748 uint32_t async_cq_id_v1:16, 1749 ring_size:4, 1750 :2, 1751 cq_id_v0:10; 1752 uint32_t :31, 1753 val:1; 1754 uint32_t acqv:1, 1755 async_cq_id_v0:10, 1756 :21; 1757 uint32_t rsvd9; 1758 struct { 1759 uint32_t low; 1760 uint32_t high; 1761 } page_physical_address[8]; 1762 #else 1763 #error big endian version not defined 1764 #endif 1765 } sli4_req_common_create_mq_ext_t; 1766 1767 #define SLI4_MQE_SIZE_16 0x05 1768 #define SLI4_MQE_SIZE_32 0x06 1769 #define SLI4_MQE_SIZE_64 0x07 1770 #define SLI4_MQE_SIZE_128 0x08 1771 1772 #define SLI4_ASYNC_EVT_LINK_STATE BIT(1) 1773 #define SLI4_ASYNC_EVT_FCOE_FIP BIT(2) 1774 #define SLI4_ASYNC_EVT_DCBX BIT(3) 1775 #define SLI4_ASYNC_EVT_ISCSI BIT(4) 1776 #define SLI4_ASYNC_EVT_GRP5 BIT(5) 1777 #define SLI4_ASYNC_EVT_FC BIT(16) 1778 #define SLI4_ASYNC_EVT_SLI_PORT BIT(17) 1779 #define SLI4_ASYNC_EVT_VF BIT(18) 1780 #define SLI4_ASYNC_EVT_MR BIT(19) 1781 1782 #define SLI4_ASYNC_EVT_ALL \ 1783 SLI4_ASYNC_EVT_LINK_STATE | \ 1784 SLI4_ASYNC_EVT_FCOE_FIP | \ 1785 SLI4_ASYNC_EVT_DCBX | \ 1786 SLI4_ASYNC_EVT_ISCSI | \ 1787 SLI4_ASYNC_EVT_GRP5 | \ 1788 SLI4_ASYNC_EVT_FC | \ 1789 SLI4_ASYNC_EVT_SLI_PORT | \ 1790 SLI4_ASYNC_EVT_VF |\ 1791 SLI4_ASYNC_EVT_MR 1792 1793 #define SLI4_ASYNC_EVT_FC_FCOE \ 1794 SLI4_ASYNC_EVT_LINK_STATE | \ 1795 SLI4_ASYNC_EVT_FCOE_FIP | \ 1796 SLI4_ASYNC_EVT_GRP5 | \ 1797 SLI4_ASYNC_EVT_FC | \ 1798 SLI4_ASYNC_EVT_SLI_PORT 1799 1800 /** 1801 * @brief Common Destroy MQ 1802 */ 1803 typedef struct sli4_req_common_destroy_mq_s { 1804 sli4_req_hdr_t hdr; 1805 #if BYTE_ORDER == LITTLE_ENDIAN 1806 uint32_t mq_id:16, 1807 :16; 1808 #else 1809 #error big endian version not defined 1810 #endif 1811 } sli4_req_common_destroy_mq_t; 1812 1813 /** 1814 * @brief COMMON_GET_CNTL_ATTRIBUTES 1815 * 1816 * Query for information about the SLI Port 1817 */ 1818 typedef struct sli4_res_common_get_cntl_attributes_s { 1819 sli4_res_hdr_t hdr; 1820 #if BYTE_ORDER == LITTLE_ENDIAN 1821 uint8_t version_string[32]; 1822 uint8_t manufacturer_name[32]; 1823 uint32_t supported_modes; 1824 uint32_t eprom_version_lo:8, 1825 eprom_version_hi:8, 1826 :16; 1827 uint32_t mbx_data_structure_version; 1828 uint32_t ep_firmware_data_structure_version; 1829 uint8_t ncsi_version_string[12]; 1830 uint32_t default_extended_timeout; 1831 uint8_t model_number[32]; 1832 uint8_t description[64]; 1833 uint8_t serial_number[32]; 1834 uint8_t ip_version_string[32]; 1835 uint8_t fw_version_string[32]; 1836 uint8_t bios_version_string[32]; 1837 uint8_t redboot_version_string[32]; 1838 uint8_t driver_version_string[32]; 1839 uint8_t fw_on_flash_version_string[32]; 1840 uint32_t functionalities_supported; 1841 uint32_t max_cdb_length:16, 1842 asic_revision:8, 1843 generational_guid0:8; 1844 uint32_t generational_guid1_12[3]; 1845 uint32_t generational_guid13:24, 1846 hba_port_count:8; 1847 uint32_t default_link_down_timeout:16, 1848 iscsi_version_min_max:8, 1849 multifunctional_device:8; 1850 uint32_t cache_valid:8, 1851 hba_status:8, 1852 max_domains_supported:8, 1853 port_number:6, 1854 port_type:2; 1855 uint32_t firmware_post_status; 1856 uint32_t hba_mtu; 1857 uint32_t iscsi_features:8, 1858 rsvd121:24; 1859 uint32_t pci_vendor_id:16, 1860 pci_device_id:16; 1861 uint32_t pci_sub_vendor_id:16, 1862 pci_sub_system_id:16; 1863 uint32_t pci_bus_number:8, 1864 pci_device_number:8, 1865 pci_function_number:8, 1866 interface_type:8; 1867 uint64_t unique_identifier; 1868 uint32_t number_of_netfilters:8, 1869 rsvd130:24; 1870 #else 1871 #error big endian version not defined 1872 #endif 1873 } sli4_res_common_get_cntl_attributes_t; 1874 1875 /** 1876 * @brief COMMON_GET_CNTL_ATTRIBUTES 1877 * 1878 * This command queries the controller information from the Flash ROM. 1879 */ 1880 typedef struct sli4_req_common_get_cntl_addl_attributes_s { 1881 sli4_req_hdr_t hdr; 1882 } sli4_req_common_get_cntl_addl_attributes_t; 1883 1884 typedef struct sli4_res_common_get_cntl_addl_attributes_s { 1885 sli4_res_hdr_t hdr; 1886 uint16_t ipl_file_number; 1887 uint8_t ipl_file_version; 1888 uint8_t rsvd0; 1889 uint8_t on_die_temperature; 1890 uint8_t rsvd1[3]; 1891 uint32_t driver_advanced_features_supported; 1892 uint32_t rsvd2[4]; 1893 char fcoe_universal_bios_version[32]; 1894 char fcoe_x86_bios_version[32]; 1895 char fcoe_efi_bios_version[32]; 1896 char fcoe_fcode_version[32]; 1897 char uefi_bios_version[32]; 1898 char uefi_nic_version[32]; 1899 char uefi_fcode_version[32]; 1900 char uefi_iscsi_version[32]; 1901 char iscsi_x86_bios_version[32]; 1902 char pxe_x86_bios_version[32]; 1903 uint8_t fcoe_default_wwpn[8]; 1904 uint8_t ext_phy_version[32]; 1905 uint8_t fc_universal_bios_version[32]; 1906 uint8_t fc_x86_bios_version[32]; 1907 uint8_t fc_efi_bios_version[32]; 1908 uint8_t fc_fcode_version[32]; 1909 uint8_t ext_phy_crc_label[8]; 1910 uint8_t ipl_file_name[16]; 1911 uint8_t rsvd3[72]; 1912 } sli4_res_common_get_cntl_addl_attributes_t; 1913 1914 /** 1915 * @brief COMMON_NOP 1916 * 1917 * This command does not do anything; it only returns the payload in the completion. 1918 */ 1919 typedef struct sli4_req_common_nop_s { 1920 sli4_req_hdr_t hdr; 1921 #if BYTE_ORDER == LITTLE_ENDIAN 1922 uint32_t context[2]; 1923 #else 1924 #error big endian version not defined 1925 #endif 1926 } sli4_req_common_nop_t; 1927 1928 typedef struct sli4_res_common_nop_s { 1929 sli4_res_hdr_t hdr; 1930 #if BYTE_ORDER == LITTLE_ENDIAN 1931 uint32_t context[2]; 1932 #else 1933 #error big endian version not defined 1934 #endif 1935 } sli4_res_common_nop_t; 1936 1937 /** 1938 * @brief COMMON_GET_RESOURCE_EXTENT_INFO 1939 */ 1940 typedef struct sli4_req_common_get_resource_extent_info_s { 1941 sli4_req_hdr_t hdr; 1942 #if BYTE_ORDER == LITTLE_ENDIAN 1943 uint32_t resource_type:16, 1944 :16; 1945 #else 1946 #error big endian version not defined 1947 #endif 1948 } sli4_req_common_get_resource_extent_info_t; 1949 1950 #define SLI4_RSC_TYPE_ISCSI_INI_XRI 0x0c 1951 #define SLI4_RSC_TYPE_FCOE_VFI 0x20 1952 #define SLI4_RSC_TYPE_FCOE_VPI 0x21 1953 #define SLI4_RSC_TYPE_FCOE_RPI 0x22 1954 #define SLI4_RSC_TYPE_FCOE_XRI 0x23 1955 1956 typedef struct sli4_res_common_get_resource_extent_info_s { 1957 sli4_res_hdr_t hdr; 1958 #if BYTE_ORDER == LITTLE_ENDIAN 1959 uint32_t resource_extent_count:16, 1960 resource_extent_size:16; 1961 #else 1962 #error big endian version not defined 1963 #endif 1964 } sli4_res_common_get_resource_extent_info_t; 1965 1966 #define SLI4_128BYTE_WQE_SUPPORT 0x02 1967 /** 1968 * @brief COMMON_GET_SLI4_PARAMETERS 1969 */ 1970 typedef struct sli4_res_common_get_sli4_parameters_s { 1971 sli4_res_hdr_t hdr; 1972 #if BYTE_ORDER == LITTLE_ENDIAN 1973 uint32_t protocol_type:8, 1974 :24; 1975 uint32_t ft:1, 1976 :3, 1977 sli_revision:4, 1978 sli_family:4, 1979 if_type:4, 1980 sli_hint_1:8, 1981 sli_hint_2:5, 1982 :3; 1983 uint32_t eq_page_cnt:4, 1984 :4, 1985 eqe_sizes:4, 1986 :4, 1987 eq_page_sizes:8, 1988 eqe_count_method:4, 1989 :4; 1990 uint32_t eqe_count_mask:16, 1991 :16; 1992 uint32_t cq_page_cnt:4, 1993 :4, 1994 cqe_sizes:4, 1995 :2, 1996 cqv:2, 1997 cq_page_sizes:8, 1998 cqe_count_method:4, 1999 :4; 2000 uint32_t cqe_count_mask:16, 2001 :16; 2002 uint32_t mq_page_cnt:4, 2003 :10, 2004 mqv:2, 2005 mq_page_sizes:8, 2006 mqe_count_method:4, 2007 :4; 2008 uint32_t mqe_count_mask:16, 2009 :16; 2010 uint32_t wq_page_cnt:4, 2011 :4, 2012 wqe_sizes:4, 2013 :2, 2014 wqv:2, 2015 wq_page_sizes:8, 2016 wqe_count_method:4, 2017 :4; 2018 uint32_t wqe_count_mask:16, 2019 :16; 2020 uint32_t rq_page_cnt:4, 2021 :4, 2022 rqe_sizes:4, 2023 :2, 2024 rqv:2, 2025 rq_page_sizes:8, 2026 rqe_count_method:4, 2027 :4; 2028 uint32_t rqe_count_mask:16, 2029 :12, 2030 rq_db_window:4; 2031 uint32_t fcoe:1, 2032 ext:1, 2033 hdrr:1, 2034 sglr:1, 2035 fbrr:1, 2036 areg:1, 2037 tgt:1, 2038 terp:1, 2039 assi:1, 2040 wchn:1, 2041 tcca:1, 2042 trty:1, 2043 trir:1, 2044 phoff:1, 2045 phon:1, 2046 phwq:1, /** Performance Hint WQ_ID Association */ 2047 boundary_4ga:1, 2048 rxc:1, 2049 hlm:1, 2050 ipr:1, 2051 rxri:1, 2052 sglc:1, 2053 timm:1, 2054 tsmm:1, 2055 :1, 2056 oas:1, 2057 lc:1, 2058 agxf:1, 2059 loopback_scope:4; 2060 uint32_t sge_supported_length; 2061 uint32_t sgl_page_cnt:4, 2062 :4, 2063 sgl_page_sizes:8, 2064 sgl_pp_align:8, 2065 :8; 2066 uint32_t min_rq_buffer_size:16, 2067 :16; 2068 uint32_t max_rq_buffer_size; 2069 uint32_t physical_xri_max:16, 2070 physical_rpi_max:16; 2071 uint32_t physical_vpi_max:16, 2072 physical_vfi_max:16; 2073 uint32_t rsvd19; 2074 uint32_t frag_num_field_offset:16, /* dword 20 */ 2075 frag_num_field_size:16; 2076 uint32_t sgl_index_field_offset:16, /* dword 21 */ 2077 sgl_index_field_size:16; 2078 uint32_t chain_sge_initial_value_lo; /* dword 22 */ 2079 uint32_t chain_sge_initial_value_hi; /* dword 23 */ 2080 #else 2081 #error big endian version not defined 2082 #endif 2083 } sli4_res_common_get_sli4_parameters_t; 2084 2085 /** 2086 * @brief COMMON_QUERY_FW_CONFIG 2087 * 2088 * This command retrieves firmware configuration parameters and adapter 2089 * resources available to the driver. 2090 */ 2091 typedef struct sli4_req_common_query_fw_config_s { 2092 sli4_req_hdr_t hdr; 2093 } sli4_req_common_query_fw_config_t; 2094 2095 #define SLI4_FUNCTION_MODE_FCOE_INI_MODE 0x40 2096 #define SLI4_FUNCTION_MODE_FCOE_TGT_MODE 0x80 2097 #define SLI4_FUNCTION_MODE_DUA_MODE 0x800 2098 2099 #define SLI4_ULP_MODE_FCOE_INI 0x40 2100 #define SLI4_ULP_MODE_FCOE_TGT 0x80 2101 2102 typedef struct sli4_res_common_query_fw_config_s { 2103 sli4_res_hdr_t hdr; 2104 uint32_t config_number; 2105 uint32_t asic_rev; 2106 uint32_t physical_port; 2107 uint32_t function_mode; 2108 uint32_t ulp0_mode; 2109 uint32_t ulp0_nic_wqid_base; 2110 uint32_t ulp0_nic_wq_total; /* Dword 10 */ 2111 uint32_t ulp0_toe_wqid_base; 2112 uint32_t ulp0_toe_wq_total; 2113 uint32_t ulp0_toe_rqid_base; 2114 uint32_t ulp0_toe_rq_total; 2115 uint32_t ulp0_toe_defrqid_base; 2116 uint32_t ulp0_toe_defrq_total; 2117 uint32_t ulp0_lro_rqid_base; 2118 uint32_t ulp0_lro_rq_total; 2119 uint32_t ulp0_iscsi_icd_base; 2120 uint32_t ulp0_iscsi_icd_total; /* Dword 20 */ 2121 uint32_t ulp1_mode; 2122 uint32_t ulp1_nic_wqid_base; 2123 uint32_t ulp1_nic_wq_total; 2124 uint32_t ulp1_toe_wqid_base; 2125 uint32_t ulp1_toe_wq_total; 2126 uint32_t ulp1_toe_rqid_base; 2127 uint32_t ulp1_toe_rq_total; 2128 uint32_t ulp1_toe_defrqid_base; 2129 uint32_t ulp1_toe_defrq_total; 2130 uint32_t ulp1_lro_rqid_base; /* Dword 30 */ 2131 uint32_t ulp1_lro_rq_total; 2132 uint32_t ulp1_iscsi_icd_base; 2133 uint32_t ulp1_iscsi_icd_total; 2134 uint32_t function_capabilities; 2135 uint32_t ulp0_cq_base; 2136 uint32_t ulp0_cq_total; 2137 uint32_t ulp0_eq_base; 2138 uint32_t ulp0_eq_total; 2139 uint32_t ulp0_iscsi_chain_icd_base; 2140 uint32_t ulp0_iscsi_chain_icd_total; /* Dword 40 */ 2141 uint32_t ulp1_iscsi_chain_icd_base; 2142 uint32_t ulp1_iscsi_chain_icd_total; 2143 } sli4_res_common_query_fw_config_t; 2144 2145 /** 2146 * @brief COMMON_GET_PORT_NAME 2147 */ 2148 typedef struct sli4_req_common_get_port_name_s { 2149 sli4_req_hdr_t hdr; 2150 #if BYTE_ORDER == LITTLE_ENDIAN 2151 uint32_t pt:2, /* only COMMON_GET_PORT_NAME_V1 */ 2152 :30; 2153 #else 2154 #error big endian version not defined 2155 #endif 2156 } sli4_req_common_get_port_name_t; 2157 2158 typedef struct sli4_res_common_get_port_name_s { 2159 sli4_res_hdr_t hdr; 2160 char port_name[4]; 2161 } sli4_res_common_get_port_name_t; 2162 2163 /** 2164 * @brief COMMON_WRITE_FLASHROM 2165 */ 2166 typedef struct sli4_req_common_write_flashrom_s { 2167 sli4_req_hdr_t hdr; 2168 #if BYTE_ORDER == LITTLE_ENDIAN 2169 uint32_t flash_rom_access_opcode; 2170 uint32_t flash_rom_access_operation_type; 2171 uint32_t data_buffer_size; 2172 uint32_t offset; 2173 uint8_t data_buffer[4]; 2174 #else 2175 #error big endian version not defined 2176 #endif 2177 } sli4_req_common_write_flashrom_t; 2178 2179 #define SLI4_MGMT_FLASHROM_OPCODE_FLASH 0x01 2180 #define SLI4_MGMT_FLASHROM_OPCODE_SAVE 0x02 2181 #define SLI4_MGMT_FLASHROM_OPCODE_CLEAR 0x03 2182 #define SLI4_MGMT_FLASHROM_OPCODE_REPORT 0x04 2183 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_INFO 0x05 2184 #define SLI4_MGMT_FLASHROM_OPCODE_IMAGE_CRC 0x06 2185 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_FLASH 0x07 2186 #define SLI4_MGMT_FLASHROM_OPCODE_OFFSET_BASED_SAVE 0x08 2187 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_FLASH 0x09 2188 #define SLI4_MGMT_PHY_FLASHROM_OPCODE_SAVE 0x0a 2189 2190 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI 0x00 2191 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_REDBOOT 0x01 2192 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_BIOS 0x02 2193 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS 0x03 2194 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CONTROL 0x04 2195 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_IPSEC_CFG 0x05 2196 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_INIT_DATA 0x06 2197 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ROM_OFFSET 0x07 2198 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BIOS 0x08 2199 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ISCSI_BAK 0x09 2200 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_ACT 0x0a 2201 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_FCOE_BAK 0x0b 2202 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_CODE_CTRL_P 0x0c 2203 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NCSI 0x0d 2204 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_NIC 0x0e 2205 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_DCBX 0x0f 2206 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_PXE_BIOS_CFG 0x10 2207 #define SLI4_FLASH_ROM_ACCESS_OP_TYPE_ALL_CFG_DATA 0x11 2208 2209 /** 2210 * @brief COMMON_MANAGE_FAT 2211 */ 2212 typedef struct sli4_req_common_manage_fat_s { 2213 sli4_req_hdr_t hdr; 2214 #if BYTE_ORDER == LITTLE_ENDIAN 2215 uint32_t fat_operation; 2216 uint32_t read_log_offset; 2217 uint32_t read_log_length; 2218 uint32_t data_buffer_size; 2219 uint32_t data_buffer; /* response only */ 2220 #else 2221 #error big endian version not defined 2222 #endif 2223 } sli4_req_common_manage_fat_t; 2224 2225 /** 2226 * @brief COMMON_GET_EXT_FAT_CAPABILITIES 2227 */ 2228 typedef struct sli4_req_common_get_ext_fat_capabilities_s { 2229 sli4_req_hdr_t hdr; 2230 #if BYTE_ORDER == LITTLE_ENDIAN 2231 uint32_t parameter_type; 2232 #else 2233 #error big endian version not defined 2234 #endif 2235 } sli4_req_common_get_ext_fat_capabilities_t; 2236 2237 /** 2238 * @brief COMMON_SET_EXT_FAT_CAPABILITIES 2239 */ 2240 typedef struct sli4_req_common_set_ext_fat_capabilities_s { 2241 sli4_req_hdr_t hdr; 2242 #if BYTE_ORDER == LITTLE_ENDIAN 2243 uint32_t maximum_log_entries; 2244 uint32_t log_entry_size; 2245 uint32_t logging_type:8, 2246 maximum_logging_functions:8, 2247 maximum_logging_ports:8, 2248 :8; 2249 uint32_t supported_modes; 2250 uint32_t number_modules; 2251 uint32_t debug_module[14]; 2252 #else 2253 #error big endian version not defined 2254 #endif 2255 } sli4_req_common_set_ext_fat_capabilities_t; 2256 2257 /** 2258 * @brief COMMON_EXT_FAT_CONFIGURE_SNAPSHOT 2259 */ 2260 typedef struct sli4_req_common_ext_fat_configure_snapshot_s { 2261 sli4_req_hdr_t hdr; 2262 #if BYTE_ORDER == LITTLE_ENDIAN 2263 uint32_t total_log_entries; 2264 #else 2265 #error big endian version not defined 2266 #endif 2267 } sli4_req_common_ext_fat_configure_snapshot_t; 2268 2269 /** 2270 * @brief COMMON_EXT_FAT_RETRIEVE_SNAPSHOT 2271 */ 2272 typedef struct sli4_req_common_ext_fat_retrieve_snapshot_s { 2273 sli4_req_hdr_t hdr; 2274 #if BYTE_ORDER == LITTLE_ENDIAN 2275 uint32_t snapshot_mode; 2276 uint32_t start_index; 2277 uint32_t number_log_entries; 2278 #else 2279 #error big endian version not defined 2280 #endif 2281 } sli4_req_common_ext_fat_retrieve_snapshot_t; 2282 2283 typedef struct sli4_res_common_ext_fat_retrieve_snapshot_s { 2284 sli4_res_hdr_t hdr; 2285 #if BYTE_ORDER == LITTLE_ENDIAN 2286 uint32_t number_log_entries; 2287 uint32_t version:8, 2288 physical_port:8, 2289 function_id:16; 2290 uint32_t trace_level; 2291 uint32_t module_mask[2]; 2292 uint32_t trace_table_index; 2293 uint32_t timestamp; 2294 uint8_t string_data[16]; 2295 uint32_t data[6]; 2296 #else 2297 #error big endian version not defined 2298 #endif 2299 } sli4_res_common_ext_fat_retrieve_snapshot_t; 2300 2301 /** 2302 * @brief COMMON_EXT_FAT_READ_STRING_TABLE 2303 */ 2304 typedef struct sli4_req_common_ext_fat_read_string_table_s { 2305 sli4_req_hdr_t hdr; 2306 #if BYTE_ORDER == LITTLE_ENDIAN 2307 uint32_t byte_offset; 2308 uint32_t number_bytes; 2309 #else 2310 #error big endian version not defined 2311 #endif 2312 } sli4_req_common_ext_fat_read_string_table_t; 2313 2314 typedef struct sli4_res_common_ext_fat_read_string_table_s { 2315 sli4_res_hdr_t hdr; 2316 #if BYTE_ORDER == LITTLE_ENDIAN 2317 uint32_t number_returned_bytes; 2318 uint32_t number_remaining_bytes; 2319 uint32_t table_data0:8, 2320 :24; 2321 uint8_t table_data[0]; 2322 #else 2323 #error big endian version not defined 2324 #endif 2325 } sli4_res_common_ext_fat_read_string_table_t; 2326 2327 /** 2328 * @brief COMMON_READ_TRANSCEIVER_DATA 2329 * 2330 * This command reads SFF transceiver data(Format is defined 2331 * by the SFF-8472 specification). 2332 */ 2333 typedef struct sli4_req_common_read_transceiver_data_s { 2334 sli4_req_hdr_t hdr; 2335 #if BYTE_ORDER == LITTLE_ENDIAN 2336 uint32_t page_number; 2337 uint32_t port; 2338 #else 2339 #error big endian version not defined 2340 #endif 2341 } sli4_req_common_read_transceiver_data_t; 2342 2343 typedef struct sli4_res_common_read_transceiver_data_s { 2344 sli4_res_hdr_t hdr; 2345 #if BYTE_ORDER == LITTLE_ENDIAN 2346 uint32_t page_number; 2347 uint32_t port; 2348 uint32_t page_data[32]; 2349 uint32_t page_data_2[32]; 2350 #else 2351 #error big endian version not defined 2352 #endif 2353 } sli4_res_common_read_transceiver_data_t; 2354 2355 /** 2356 * @brief COMMON_READ_OBJECT 2357 */ 2358 typedef struct sli4_req_common_read_object_s { 2359 sli4_req_hdr_t hdr; 2360 #if BYTE_ORDER == LITTLE_ENDIAN 2361 uint32_t desired_read_length:24, 2362 :8; 2363 uint32_t read_offset; 2364 uint8_t object_name[104]; 2365 uint32_t host_buffer_descriptor_count; 2366 sli4_bde_t host_buffer_descriptor[0]; 2367 #else 2368 #error big endian version not defined 2369 #endif 2370 } sli4_req_common_read_object_t; 2371 2372 typedef struct sli4_res_common_read_object_s { 2373 sli4_res_hdr_t hdr; 2374 #if BYTE_ORDER == LITTLE_ENDIAN 2375 uint32_t actual_read_length; 2376 uint32_t resv:31, 2377 eof:1; 2378 #else 2379 #error big endian version not defined 2380 #endif 2381 } sli4_res_common_read_object_t; 2382 2383 /** 2384 * @brief COMMON_WRITE_OBJECT 2385 */ 2386 typedef struct sli4_req_common_write_object_s { 2387 sli4_req_hdr_t hdr; 2388 #if BYTE_ORDER == LITTLE_ENDIAN 2389 uint32_t desired_write_length:24, 2390 :6, 2391 noc:1, 2392 eof:1; 2393 uint32_t write_offset; 2394 uint8_t object_name[104]; 2395 uint32_t host_buffer_descriptor_count; 2396 sli4_bde_t host_buffer_descriptor[0]; 2397 #else 2398 #error big endian version not defined 2399 #endif 2400 } sli4_req_common_write_object_t; 2401 2402 typedef struct sli4_res_common_write_object_s { 2403 sli4_res_hdr_t hdr; 2404 #if BYTE_ORDER == LITTLE_ENDIAN 2405 uint32_t actual_write_length; 2406 uint32_t change_status:8, 2407 :24; 2408 #else 2409 #error big endian version not defined 2410 #endif 2411 } sli4_res_common_write_object_t; 2412 2413 /** 2414 * @brief COMMON_DELETE_OBJECT 2415 */ 2416 typedef struct sli4_req_common_delete_object_s { 2417 sli4_req_hdr_t hdr; 2418 #if BYTE_ORDER == LITTLE_ENDIAN 2419 uint32_t rsvd4; 2420 uint32_t rsvd5; 2421 uint8_t object_name[104]; 2422 #else 2423 #error big endian version not defined 2424 #endif 2425 } sli4_req_common_delete_object_t; 2426 2427 /** 2428 * @brief COMMON_READ_OBJECT_LIST 2429 */ 2430 typedef struct sli4_req_common_read_object_list_s { 2431 sli4_req_hdr_t hdr; 2432 #if BYTE_ORDER == LITTLE_ENDIAN 2433 uint32_t desired_read_length:24, 2434 :8; 2435 uint32_t read_offset; 2436 uint8_t object_name[104]; 2437 uint32_t host_buffer_descriptor_count; 2438 sli4_bde_t host_buffer_descriptor[0]; 2439 #else 2440 #error big endian version not defined 2441 #endif 2442 } sli4_req_common_read_object_list_t; 2443 2444 /** 2445 * @brief COMMON_SET_DUMP_LOCATION 2446 */ 2447 typedef struct sli4_req_common_set_dump_location_s { 2448 sli4_req_hdr_t hdr; 2449 #if BYTE_ORDER == LITTLE_ENDIAN 2450 uint32_t buffer_length:24, 2451 :5, 2452 fdb:1, 2453 blp:1, 2454 qry:1; 2455 uint32_t buf_addr_low; 2456 uint32_t buf_addr_high; 2457 #else 2458 #error big endian version not defined 2459 #endif 2460 } sli4_req_common_set_dump_location_t; 2461 2462 typedef struct sli4_res_common_set_dump_location_s { 2463 sli4_res_hdr_t hdr; 2464 #if BYTE_ORDER == LITTLE_ENDIAN 2465 uint32_t buffer_length:24, 2466 :8; 2467 #else 2468 #error big endian version not defined 2469 #endif 2470 }sli4_res_common_set_dump_location_t; 2471 2472 /** 2473 * @brief COMMON_SET_SET_FEATURES 2474 */ 2475 #define SLI4_SET_FEATURES_DIF_SEED 0x01 2476 #define SLI4_SET_FEATURES_XRI_TIMER 0x03 2477 #define SLI4_SET_FEATURES_MAX_PCIE_SPEED 0x04 2478 #define SLI4_SET_FEATURES_FCTL_CHECK 0x05 2479 #define SLI4_SET_FEATURES_FEC 0x06 2480 #define SLI4_SET_FEATURES_PCIE_RECV_DETECT 0x07 2481 #define SLI4_SET_FEATURES_DIF_MEMORY_MODE 0x08 2482 #define SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE 0x09 2483 #define SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS 0x0A 2484 #define SLI4_SET_FEATURES_SET_CONFIG_AUTO_XFER_RDY_T10PI 0x0C 2485 #define SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE 0x0D 2486 #define SLI4_SET_FEATURES_SET_FTD_XFER_HINT 0x0F 2487 #define SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK 0x11 2488 2489 typedef struct sli4_req_common_set_features_s { 2490 sli4_req_hdr_t hdr; 2491 #if BYTE_ORDER == LITTLE_ENDIAN 2492 uint32_t feature; 2493 uint32_t param_len; 2494 uint32_t params[8]; 2495 #else 2496 #error big endian version not defined 2497 #endif 2498 } sli4_req_common_set_features_t; 2499 2500 typedef struct sli4_req_common_set_features_dif_seed_s { 2501 #if BYTE_ORDER == LITTLE_ENDIAN 2502 uint32_t seed:16, 2503 :16; 2504 #else 2505 #error big endian version not defined 2506 #endif 2507 } sli4_req_common_set_features_dif_seed_t; 2508 2509 typedef struct sli4_req_common_set_features_t10_pi_mem_model_s { 2510 #if BYTE_ORDER == LITTLE_ENDIAN 2511 uint32_t tmm:1, 2512 :31; 2513 #else 2514 #error big endian version not defined 2515 #endif 2516 } sli4_req_common_set_features_t10_pi_mem_model_t; 2517 2518 typedef struct sli4_req_common_set_features_multirq_s { 2519 #if BYTE_ORDER == LITTLE_ENDIAN 2520 uint32_t isr:1, /*<< Include Sequence Reporting */ 2521 agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */ 2522 :30; 2523 uint32_t num_rqs:8, 2524 rq_select_policy:4, 2525 :20; 2526 #else 2527 #error big endian version not defined 2528 #endif 2529 } sli4_req_common_set_features_multirq_t; 2530 2531 typedef struct sli4_req_common_set_features_xfer_rdy_t10pi_s { 2532 #if BYTE_ORDER == LITTLE_ENDIAN 2533 uint32_t rtc:1, 2534 atv:1, 2535 tmm:1, 2536 :1, 2537 p_type:3, 2538 blk_size:3, 2539 :22; 2540 uint32_t app_tag:16, 2541 :16; 2542 #else 2543 #error big endian version not defined 2544 #endif 2545 } sli4_req_common_set_features_xfer_rdy_t10pi_t; 2546 2547 typedef struct sli4_req_common_set_features_health_check_s { 2548 #if BYTE_ORDER == LITTLE_ENDIAN 2549 uint32_t hck:1, 2550 qry:1, 2551 :30; 2552 #else 2553 #error big endian version not defined 2554 #endif 2555 } sli4_req_common_set_features_health_check_t; 2556 2557 typedef struct sli4_req_common_set_features_set_fdt_xfer_hint_s { 2558 #if BYTE_ORDER == LITTLE_ENDIAN 2559 uint32_t fdt_xfer_hint; 2560 #else 2561 #error big endian version not defined 2562 #endif 2563 } sli4_req_common_set_features_set_fdt_xfer_hint_t; 2564 2565 /** 2566 * @brief DMTF_EXEC_CLP_CMD 2567 */ 2568 typedef struct sli4_req_dmtf_exec_clp_cmd_s { 2569 sli4_req_hdr_t hdr; 2570 #if BYTE_ORDER == LITTLE_ENDIAN 2571 uint32_t cmd_buf_length; 2572 uint32_t resp_buf_length; 2573 uint32_t cmd_buf_addr_low; 2574 uint32_t cmd_buf_addr_high; 2575 uint32_t resp_buf_addr_low; 2576 uint32_t resp_buf_addr_high; 2577 #else 2578 #error big endian version not defined 2579 #endif 2580 } sli4_req_dmtf_exec_clp_cmd_t; 2581 2582 typedef struct sli4_res_dmtf_exec_clp_cmd_s { 2583 sli4_res_hdr_t hdr; 2584 #if BYTE_ORDER == LITTLE_ENDIAN 2585 uint32_t :32; 2586 uint32_t resp_length; 2587 uint32_t :32; 2588 uint32_t :32; 2589 uint32_t :32; 2590 uint32_t :32; 2591 uint32_t clp_status; 2592 uint32_t clp_detailed_status; 2593 #else 2594 #error big endian version not defined 2595 #endif 2596 } sli4_res_dmtf_exec_clp_cmd_t; 2597 2598 /** 2599 * @brief Resource descriptor 2600 */ 2601 2602 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PCIE 0x50 2603 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_NIC 0x51 2604 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISCSI 0x52 2605 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_FCFCOE 0x53 2606 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_RDMA 0x54 2607 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_PORT 0x55 2608 #define SLI4_RESOURCE_DESCRIPTOR_TYPE_ISAP 0x56 2609 2610 #define SLI4_PROTOCOL_NIC_TOE 0x01 2611 #define SLI4_PROTOCOL_ISCSI 0x02 2612 #define SLI4_PROTOCOL_FCOE 0x04 2613 #define SLI4_PROTOCOL_NIC_TOE_RDMA 0x08 2614 #define SLI4_PROTOCOL_FC 0x10 2615 #define SLI4_PROTOCOL_DEFAULT 0xff 2616 2617 typedef struct sli4_resource_descriptor_v1_s { 2618 uint32_t descriptor_type:8, 2619 descriptor_length:8, 2620 :16; 2621 uint32_t type_specific[0]; 2622 } sli4_resource_descriptor_v1_t; 2623 2624 typedef struct sli4_pcie_resource_descriptor_v1_s { 2625 uint32_t descriptor_type:8, 2626 descriptor_length:8, 2627 :14, 2628 imm:1, 2629 nosv:1; 2630 uint32_t :16, 2631 pf_number:10, 2632 :6; 2633 uint32_t rsvd1; 2634 uint32_t sriov_state:8, 2635 pf_state:8, 2636 pf_type:8, 2637 :8; 2638 uint32_t number_of_vfs:16, 2639 :16; 2640 uint32_t mission_roles:8, 2641 :19, 2642 pchg:1, 2643 schg:1, 2644 xchg:1, 2645 xrom:2; 2646 uint32_t rsvd2[16]; 2647 } sli4_pcie_resource_descriptor_v1_t; 2648 2649 typedef struct sli4_isap_resource_descriptor_v1_s { 2650 uint32_t descriptor_type:8, 2651 descriptor_length:8, 2652 :16; 2653 uint32_t iscsi_tgt:1, 2654 iscsi_ini:1, 2655 iscsi_dif:1, 2656 :29; 2657 uint32_t rsvd1[3]; 2658 uint32_t fcoe_tgt:1, 2659 fcoe_ini:1, 2660 fcoe_dif:1, 2661 :29; 2662 uint32_t rsvd2[7]; 2663 uint32_t mc_type0:8, 2664 mc_type1:8, 2665 mc_type2:8, 2666 mc_type3:8; 2667 uint32_t rsvd3[3]; 2668 } sli4_isap_resouce_descriptor_v1_t; 2669 2670 /** 2671 * @brief COMMON_GET_FUNCTION_CONFIG 2672 */ 2673 typedef struct sli4_req_common_get_function_config_s { 2674 sli4_req_hdr_t hdr; 2675 } sli4_req_common_get_function_config_t; 2676 2677 typedef struct sli4_res_common_get_function_config_s { 2678 sli4_res_hdr_t hdr; 2679 #if BYTE_ORDER == LITTLE_ENDIAN 2680 uint32_t desc_count; 2681 uint32_t desc[54]; 2682 #else 2683 #error big endian version not defined 2684 #endif 2685 } sli4_res_common_get_function_config_t; 2686 2687 /** 2688 * @brief COMMON_GET_PROFILE_CONFIG 2689 */ 2690 typedef struct sli4_req_common_get_profile_config_s { 2691 sli4_req_hdr_t hdr; 2692 uint32_t profile_id:8, 2693 typ:2, 2694 :22; 2695 } sli4_req_common_get_profile_config_t; 2696 2697 typedef struct sli4_res_common_get_profile_config_s { 2698 sli4_res_hdr_t hdr; 2699 #if BYTE_ORDER == LITTLE_ENDIAN 2700 uint32_t desc_count; 2701 uint32_t desc[0]; 2702 #else 2703 #error big endian version not defined 2704 #endif 2705 } sli4_res_common_get_profile_config_t; 2706 2707 /** 2708 * @brief COMMON_SET_PROFILE_CONFIG 2709 */ 2710 typedef struct sli4_req_common_set_profile_config_s { 2711 sli4_req_hdr_t hdr; 2712 uint32_t profile_id:8, 2713 :23, 2714 isap:1; 2715 uint32_t desc_count; 2716 uint32_t desc[0]; 2717 } sli4_req_common_set_profile_config_t; 2718 2719 typedef struct sli4_res_common_set_profile_config_s { 2720 sli4_res_hdr_t hdr; 2721 #if BYTE_ORDER == LITTLE_ENDIAN 2722 #else 2723 #error big endian version not defined 2724 #endif 2725 } sli4_res_common_set_profile_config_t; 2726 2727 /** 2728 * @brief Profile Descriptor for profile functions 2729 */ 2730 typedef struct sli4_profile_descriptor_s { 2731 #if BYTE_ORDER == LITTLE_ENDIAN 2732 uint32_t profile_id:8, 2733 :8, 2734 profile_index:8, 2735 :8; 2736 uint32_t profile_description[128]; 2737 #else 2738 #error big endian version not defined 2739 #endif 2740 } sli4_profile_descriptor_t; 2741 2742 /* We don't know in advance how many descriptors there are. We have 2743 to pick a number that we think will be big enough and ask for that 2744 many. */ 2745 2746 #define MAX_PRODUCT_DESCRIPTORS 40 2747 2748 /** 2749 * @brief COMMON_GET_PROFILE_LIST 2750 */ 2751 typedef struct sli4_req_common_get_profile_list_s { 2752 sli4_req_hdr_t hdr; 2753 #if BYTE_ORDER == LITTLE_ENDIAN 2754 uint32_t start_profile_index:8, 2755 :24; 2756 #else 2757 #error big endian version not defined 2758 #endif 2759 } sli4_req_common_get_profile_list_t; 2760 2761 typedef struct sli4_res_common_get_profile_list_s { 2762 sli4_res_hdr_t hdr; 2763 #if BYTE_ORDER == LITTLE_ENDIAN 2764 uint32_t profile_descriptor_count; 2765 sli4_profile_descriptor_t profile_descriptor[MAX_PRODUCT_DESCRIPTORS]; 2766 #else 2767 #error big endian version not defined 2768 #endif 2769 } sli4_res_common_get_profile_list_t; 2770 2771 /** 2772 * @brief COMMON_GET_ACTIVE_PROFILE 2773 */ 2774 typedef struct sli4_req_common_get_active_profile_s { 2775 sli4_req_hdr_t hdr; 2776 } sli4_req_common_get_active_profile_t; 2777 2778 typedef struct sli4_res_common_get_active_profile_s { 2779 sli4_res_hdr_t hdr; 2780 #if BYTE_ORDER == LITTLE_ENDIAN 2781 uint32_t active_profile_id:8, 2782 :8, 2783 next_profile_id:8, 2784 :8; 2785 #else 2786 #error big endian version not defined 2787 #endif 2788 } sli4_res_common_get_active_profile_t; 2789 2790 /** 2791 * @brief COMMON_SET_ACTIVE_PROFILE 2792 */ 2793 typedef struct sli4_req_common_set_active_profile_s { 2794 sli4_req_hdr_t hdr; 2795 #if BYTE_ORDER == LITTLE_ENDIAN 2796 uint32_t active_profile_id:8, 2797 :23, 2798 fd:1; 2799 #else 2800 #error big endian version not defined 2801 #endif 2802 } sli4_req_common_set_active_profile_t; 2803 2804 typedef struct sli4_res_common_set_active_profile_s { 2805 sli4_res_hdr_t hdr; 2806 } sli4_res_common_set_active_profile_t; 2807 2808 /** 2809 * @brief Link Config Descriptor for link config functions 2810 */ 2811 typedef struct sli4_link_config_descriptor_s { 2812 #if BYTE_ORDER == LITTLE_ENDIAN 2813 uint32_t link_config_id:8, 2814 :24; 2815 uint32_t config_description[8]; 2816 #else 2817 #error big endian version not defined 2818 #endif 2819 } sli4_link_config_descriptor_t; 2820 2821 #define MAX_LINK_CONFIG_DESCRIPTORS 10 2822 2823 /** 2824 * @brief COMMON_GET_RECONFIG_LINK_INFO 2825 */ 2826 typedef struct sli4_req_common_get_reconfig_link_info_s { 2827 sli4_req_hdr_t hdr; 2828 #if BYTE_ORDER == LITTLE_ENDIAN 2829 #else 2830 #error big endian version not defined 2831 #endif 2832 } sli4_req_common_get_reconfig_link_info_t; 2833 2834 typedef struct sli4_res_common_get_reconfig_link_info_s { 2835 sli4_res_hdr_t hdr; 2836 #if BYTE_ORDER == LITTLE_ENDIAN 2837 uint32_t active_link_config_id:8, 2838 :8, 2839 next_link_config_id:8, 2840 :8; 2841 uint32_t link_configuration_descriptor_count; 2842 sli4_link_config_descriptor_t desc[MAX_LINK_CONFIG_DESCRIPTORS]; 2843 #else 2844 #error big endian version not defined 2845 #endif 2846 } sli4_res_common_get_reconfig_link_info_t; 2847 2848 /** 2849 * @brief COMMON_SET_RECONFIG_LINK_ID 2850 */ 2851 typedef struct sli4_req_common_set_reconfig_link_id_s { 2852 sli4_req_hdr_t hdr; 2853 #if BYTE_ORDER == LITTLE_ENDIAN 2854 uint32_t next_link_config_id:8, 2855 :23, 2856 fd:1; 2857 #else 2858 #error big endian version not defined 2859 #endif 2860 } sli4_req_common_set_reconfig_link_id_t; 2861 2862 typedef struct sli4_res_common_set_reconfig_link_id_s { 2863 sli4_res_hdr_t hdr; 2864 #if BYTE_ORDER == LITTLE_ENDIAN 2865 #else 2866 #error big endian version not defined 2867 #endif 2868 } sli4_res_common_set_reconfig_link_id_t; 2869 2870 typedef struct sli4_req_lowlevel_set_watchdog_s { 2871 sli4_req_hdr_t hdr; 2872 #if BYTE_ORDER == LITTLE_ENDIAN 2873 uint32_t watchdog_timeout:16, 2874 :16; 2875 #else 2876 #error big endian version not defined 2877 #endif 2878 2879 } sli4_req_lowlevel_set_watchdog_t; 2880 2881 typedef struct sli4_res_lowlevel_set_watchdog_s { 2882 sli4_res_hdr_t hdr; 2883 #if BYTE_ORDER == LITTLE_ENDIAN 2884 uint32_t rsvd; 2885 #else 2886 #error big endian version not defined 2887 #endif 2888 } sli4_res_lowlevel_set_watchdog_t; 2889 2890 /** 2891 * @brief Event Queue Entry 2892 */ 2893 typedef struct sli4_eqe_s { 2894 #if BYTE_ORDER == LITTLE_ENDIAN 2895 uint32_t vld:1, /** valid */ 2896 major_code:3, 2897 minor_code:12, 2898 resource_id:16; 2899 #else 2900 #error big endian version not defined 2901 #endif 2902 } sli4_eqe_t; 2903 2904 #define SLI4_MAJOR_CODE_STANDARD 0 2905 #define SLI4_MAJOR_CODE_SENTINEL 1 2906 2907 /** 2908 * @brief Mailbox Completion Queue Entry 2909 * 2910 * A CQE generated on the completion of a MQE from a MQ. 2911 */ 2912 typedef struct sli4_mcqe_s { 2913 #if BYTE_ORDER == LITTLE_ENDIAN 2914 uint32_t completion_status:16, /** values are protocol specific */ 2915 extended_status:16; 2916 uint32_t mqe_tag_low; 2917 uint32_t mqe_tag_high; 2918 uint32_t :27, 2919 con:1, /** consumed - command now being executed */ 2920 cmp:1, /** completed - command still executing if clear */ 2921 :1, 2922 ae:1, /** async event - this is an ACQE */ 2923 val:1; /** valid - contents of CQE are valid */ 2924 #else 2925 #error big endian version not defined 2926 #endif 2927 } sli4_mcqe_t; 2928 2929 /** 2930 * @brief Asynchronous Completion Queue Entry 2931 * 2932 * A CQE generated asynchronously in response to the link or other internal events. 2933 */ 2934 typedef struct sli4_acqe_s { 2935 #if BYTE_ORDER == LITTLE_ENDIAN 2936 uint32_t event_data[3]; 2937 uint32_t :8, 2938 event_code:8, 2939 event_type:8, /** values are protocol specific */ 2940 :6, 2941 ae:1, /** async event - this is an ACQE */ 2942 val:1; /** valid - contents of CQE are valid */ 2943 #else 2944 #error big endian version not defined 2945 #endif 2946 } sli4_acqe_t; 2947 2948 #define SLI4_ACQE_EVENT_CODE_LINK_STATE 0x01 2949 #define SLI4_ACQE_EVENT_CODE_FCOE_FIP 0x02 2950 #define SLI4_ACQE_EVENT_CODE_DCBX 0x03 2951 #define SLI4_ACQE_EVENT_CODE_ISCSI 0x04 2952 #define SLI4_ACQE_EVENT_CODE_GRP_5 0x05 2953 #define SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT 0x10 2954 #define SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT 0x11 2955 #define SLI4_ACQE_EVENT_CODE_VF_EVENT 0x12 2956 #define SLI4_ACQE_EVENT_CODE_MR_EVENT 0x13 2957 2958 /** 2959 * @brief Register name enums 2960 */ 2961 typedef enum { 2962 SLI4_REG_BMBX, 2963 SLI4_REG_EQCQ_DOORBELL, 2964 SLI4_REG_FCOE_RQ_DOORBELL, 2965 SLI4_REG_IO_WQ_DOORBELL, 2966 SLI4_REG_MQ_DOORBELL, 2967 SLI4_REG_PHYSDEV_CONTROL, 2968 SLI4_REG_SLIPORT_CONTROL, 2969 SLI4_REG_SLIPORT_ERROR1, 2970 SLI4_REG_SLIPORT_ERROR2, 2971 SLI4_REG_SLIPORT_SEMAPHORE, 2972 SLI4_REG_SLIPORT_STATUS, 2973 SLI4_REG_UERR_MASK_HI, 2974 SLI4_REG_UERR_MASK_LO, 2975 SLI4_REG_UERR_STATUS_HI, 2976 SLI4_REG_UERR_STATUS_LO, 2977 SLI4_REG_SW_UE_CSR1, 2978 SLI4_REG_SW_UE_CSR2, 2979 SLI4_REG_MAX /* must be last */ 2980 } sli4_regname_e; 2981 2982 typedef struct sli4_reg_s { 2983 uint32_t rset; 2984 uint32_t off; 2985 } sli4_reg_t; 2986 2987 typedef enum { 2988 SLI_QTYPE_EQ, 2989 SLI_QTYPE_CQ, 2990 SLI_QTYPE_MQ, 2991 SLI_QTYPE_WQ, 2992 SLI_QTYPE_RQ, 2993 SLI_QTYPE_MAX, /* must be last */ 2994 } sli4_qtype_e; 2995 2996 #define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */ 2997 #define SLI_MAX_CQ_SET_COUNT 16 2998 #define SLI_MAX_RQ_SET_COUNT 16 2999 3000 typedef enum { 3001 SLI_QENTRY_ASYNC, 3002 SLI_QENTRY_MQ, 3003 SLI_QENTRY_RQ, 3004 SLI_QENTRY_WQ, 3005 SLI_QENTRY_WQ_RELEASE, 3006 SLI_QENTRY_OPT_WRITE_CMD, 3007 SLI_QENTRY_OPT_WRITE_DATA, 3008 SLI_QENTRY_XABT, 3009 SLI_QENTRY_MAX /* must be last */ 3010 } sli4_qentry_e; 3011 3012 typedef struct sli4_queue_s { 3013 /* Common to all queue types */ 3014 ocs_dma_t dma; 3015 ocs_lock_t lock; 3016 uint32_t index; /** current host entry index */ 3017 uint16_t size; /** entry size */ 3018 uint16_t length; /** number of entries */ 3019 uint16_t n_posted; /** number entries posted */ 3020 uint16_t id; /** Port assigned xQ_ID */ 3021 uint16_t ulp; /** ULP assigned to this queue */ 3022 uint32_t doorbell_offset;/** The offset for the doorbell */ 3023 uint16_t doorbell_rset; /** register set for the doorbell */ 3024 uint8_t type; /** queue type ie EQ, CQ, ... */ 3025 uint32_t proc_limit; /** limit number of CQE processed per iteration */ 3026 uint32_t posted_limit; /** number of CQE/EQE to process before ringing doorbell */ 3027 uint32_t max_num_processed; 3028 time_t max_process_time; 3029 3030 /* Type specific gunk */ 3031 union { 3032 uint32_t r_idx; /** "read" index (MQ only) */ 3033 struct { 3034 uint32_t is_mq:1,/** CQ contains MQ/Async completions */ 3035 is_hdr:1,/** is a RQ for packet headers */ 3036 rq_batch:1;/** RQ index incremented by 8 */ 3037 } flag; 3038 } u; 3039 } sli4_queue_t; 3040 3041 static inline void 3042 sli_queue_lock(sli4_queue_t *q) 3043 { 3044 ocs_lock(&q->lock); 3045 } 3046 3047 static inline void 3048 sli_queue_unlock(sli4_queue_t *q) 3049 { 3050 ocs_unlock(&q->lock); 3051 } 3052 3053 #define SLI4_QUEUE_DEFAULT_CQ UINT16_MAX /** Use the default CQ */ 3054 3055 #define SLI4_QUEUE_RQ_BATCH 8 3056 3057 typedef enum { 3058 SLI4_CB_LINK, 3059 SLI4_CB_FIP, 3060 SLI4_CB_MAX /* must be last */ 3061 } sli4_callback_e; 3062 3063 typedef enum { 3064 SLI_LINK_STATUS_UP, 3065 SLI_LINK_STATUS_DOWN, 3066 SLI_LINK_STATUS_NO_ALPA, 3067 SLI_LINK_STATUS_MAX, 3068 } sli4_link_status_e; 3069 3070 typedef enum { 3071 SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */ 3072 SLI_LINK_TOPO_LOOP, 3073 SLI_LINK_TOPO_LOOPBACK_INTERNAL, 3074 SLI_LINK_TOPO_LOOPBACK_EXTERNAL, 3075 SLI_LINK_TOPO_NONE, 3076 SLI_LINK_TOPO_MAX, 3077 } sli4_link_topology_e; 3078 3079 /* TODO do we need both sli4_port_type_e & sli4_link_medium_e */ 3080 typedef enum { 3081 SLI_LINK_MEDIUM_ETHERNET, 3082 SLI_LINK_MEDIUM_FC, 3083 SLI_LINK_MEDIUM_MAX, 3084 } sli4_link_medium_e; 3085 3086 typedef struct sli4_link_event_s { 3087 sli4_link_status_e status; /* link up/down */ 3088 sli4_link_topology_e topology; 3089 sli4_link_medium_e medium; /* Ethernet / FC */ 3090 uint32_t speed; /* Mbps */ 3091 uint8_t *loop_map; 3092 uint32_t fc_id; 3093 } sli4_link_event_t; 3094 3095 /** 3096 * @brief Fields retrieved from skyhawk that used used to build chained SGL 3097 */ 3098 typedef struct sli4_sgl_chaining_params_s { 3099 uint8_t chaining_capable; 3100 uint16_t frag_num_field_offset; 3101 uint16_t sgl_index_field_offset; 3102 uint64_t frag_num_field_mask; 3103 uint64_t sgl_index_field_mask; 3104 uint32_t chain_sge_initial_value_lo; 3105 uint32_t chain_sge_initial_value_hi; 3106 } sli4_sgl_chaining_params_t; 3107 3108 typedef struct sli4_fip_event_s { 3109 uint32_t type; 3110 uint32_t index; /* FCF index or UINT32_MAX if invalid */ 3111 } sli4_fip_event_t; 3112 3113 typedef enum { 3114 SLI_RSRC_FCOE_VFI, 3115 SLI_RSRC_FCOE_VPI, 3116 SLI_RSRC_FCOE_RPI, 3117 SLI_RSRC_FCOE_XRI, 3118 SLI_RSRC_FCOE_FCFI, 3119 SLI_RSRC_MAX /* must be last */ 3120 } sli4_resource_e; 3121 3122 typedef enum { 3123 SLI4_PORT_TYPE_FC, 3124 SLI4_PORT_TYPE_NIC, 3125 SLI4_PORT_TYPE_MAX /* must be last */ 3126 } sli4_port_type_e; 3127 3128 typedef enum { 3129 SLI4_ASIC_TYPE_BE3 = 1, 3130 SLI4_ASIC_TYPE_SKYHAWK, 3131 SLI4_ASIC_TYPE_LANCER, 3132 SLI4_ASIC_TYPE_CORSAIR, 3133 SLI4_ASIC_TYPE_LANCERG6, 3134 } sli4_asic_type_e; 3135 3136 typedef enum { 3137 SLI4_ASIC_REV_FPGA = 1, 3138 SLI4_ASIC_REV_A0, 3139 SLI4_ASIC_REV_A1, 3140 SLI4_ASIC_REV_A2, 3141 SLI4_ASIC_REV_A3, 3142 SLI4_ASIC_REV_B0, 3143 SLI4_ASIC_REV_B1, 3144 SLI4_ASIC_REV_C0, 3145 SLI4_ASIC_REV_D0, 3146 } sli4_asic_rev_e; 3147 3148 typedef struct sli4_s { 3149 ocs_os_handle_t os; 3150 sli4_port_type_e port_type; 3151 3152 uint32_t sli_rev; /* SLI revision number */ 3153 uint32_t sli_family; 3154 uint32_t if_type; /* SLI Interface type */ 3155 3156 sli4_asic_type_e asic_type; /*<< ASIC type */ 3157 sli4_asic_rev_e asic_rev; /*<< ASIC revision */ 3158 uint32_t physical_port; 3159 3160 struct { 3161 uint16_t e_d_tov; 3162 uint16_t r_a_tov; 3163 uint16_t max_qcount[SLI_QTYPE_MAX]; 3164 uint32_t max_qentries[SLI_QTYPE_MAX]; 3165 uint16_t count_mask[SLI_QTYPE_MAX]; 3166 uint16_t count_method[SLI_QTYPE_MAX]; 3167 uint32_t qpage_count[SLI_QTYPE_MAX]; 3168 uint16_t link_module_type; 3169 uint8_t rq_batch; 3170 uint16_t rq_min_buf_size; 3171 uint32_t rq_max_buf_size; 3172 uint8_t topology; 3173 uint8_t wwpn[8]; 3174 uint8_t wwnn[8]; 3175 uint32_t fw_rev[2]; 3176 uint8_t fw_name[2][16]; 3177 char ipl_name[16]; 3178 uint32_t hw_rev[3]; 3179 uint8_t port_number; 3180 char port_name[2]; 3181 char bios_version_string[32]; 3182 uint8_t dual_ulp_capable; 3183 uint8_t is_ulp_fc[2]; 3184 /* 3185 * Tracks the port resources using extents metaphor. For 3186 * devices that don't implement extents (i.e. 3187 * has_extents == FALSE), the code models each resource as 3188 * a single large extent. 3189 */ 3190 struct { 3191 uint32_t number; /* number of extents */ 3192 uint32_t size; /* number of elements in each extent */ 3193 uint32_t n_alloc;/* number of elements allocated */ 3194 uint32_t *base; 3195 ocs_bitmap_t *use_map;/* bitmap showing resources in use */ 3196 uint32_t map_size;/* number of bits in bitmap */ 3197 } extent[SLI_RSRC_MAX]; 3198 sli4_features_t features; 3199 uint32_t has_extents:1, 3200 auto_reg:1, 3201 auto_xfer_rdy:1, 3202 hdr_template_req:1, 3203 perf_hint:1, 3204 perf_wq_id_association:1, 3205 cq_create_version:2, 3206 mq_create_version:2, 3207 high_login_mode:1, 3208 sgl_pre_registered:1, 3209 sgl_pre_registration_required:1, 3210 t10_dif_inline_capable:1, 3211 t10_dif_separate_capable:1; 3212 uint32_t sge_supported_length; 3213 uint32_t sgl_page_sizes; 3214 uint32_t max_sgl_pages; 3215 sli4_sgl_chaining_params_t sgl_chaining_params; 3216 size_t wqe_size; 3217 } config; 3218 3219 /* 3220 * Callback functions 3221 */ 3222 int32_t (*link)(void *, void *); 3223 void *link_arg; 3224 int32_t (*fip)(void *, void *); 3225 void *fip_arg; 3226 3227 ocs_dma_t bmbx; 3228 #if defined(OCS_INCLUDE_DEBUG) 3229 /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG 3230 * commands for BMBX dumping purposes */ 3231 ocs_dma_t *bmbx_non_emb_pmd; 3232 #endif 3233 3234 struct { 3235 ocs_dma_t data; 3236 uint32_t length; 3237 } vpd; 3238 } sli4_t; 3239 3240 /** 3241 * Get / set parameter functions 3242 */ 3243 static inline uint32_t 3244 sli_get_max_rsrc(sli4_t *sli4, sli4_resource_e rsrc) 3245 { 3246 if (rsrc >= SLI_RSRC_MAX) { 3247 return 0; 3248 } 3249 3250 return sli4->config.extent[rsrc].size; 3251 } 3252 3253 static inline uint32_t 3254 sli_get_max_queue(sli4_t *sli4, sli4_qtype_e qtype) 3255 { 3256 if (qtype >= SLI_QTYPE_MAX) { 3257 return 0; 3258 } 3259 return sli4->config.max_qcount[qtype]; 3260 } 3261 3262 static inline uint32_t 3263 sli_get_max_qentries(sli4_t *sli4, sli4_qtype_e qtype) 3264 { 3265 3266 return sli4->config.max_qentries[qtype]; 3267 } 3268 3269 static inline uint32_t 3270 sli_get_max_sge(sli4_t *sli4) 3271 { 3272 return sli4->config.sge_supported_length; 3273 } 3274 3275 static inline uint32_t 3276 sli_get_max_sgl(sli4_t *sli4) 3277 { 3278 3279 if (sli4->config.sgl_page_sizes != 1) { 3280 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n", 3281 sli4->config.sgl_page_sizes); 3282 return 0; 3283 } 3284 3285 return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t)); 3286 } 3287 3288 static inline sli4_link_medium_e 3289 sli_get_medium(sli4_t *sli4) 3290 { 3291 switch (sli4->config.topology) { 3292 case SLI4_READ_CFG_TOPO_FCOE: 3293 return SLI_LINK_MEDIUM_ETHERNET; 3294 case SLI4_READ_CFG_TOPO_FC: 3295 case SLI4_READ_CFG_TOPO_FC_DA: 3296 case SLI4_READ_CFG_TOPO_FC_AL: 3297 return SLI_LINK_MEDIUM_FC; 3298 default: 3299 return SLI_LINK_MEDIUM_MAX; 3300 } 3301 } 3302 3303 static inline void 3304 sli_skh_chain_sge_build(sli4_t *sli4, sli4_sge_t *sge, uint32_t xri_index, uint32_t frag_num, uint32_t offset) 3305 { 3306 sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params; 3307 3308 ocs_memset(sge, 0, sizeof(*sge)); 3309 sge->sge_type = SLI4_SGE_TYPE_CHAIN; 3310 sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi; 3311 sge->buffer_address_low = 3312 (uint32_t)((cparms->chain_sge_initial_value_lo | 3313 (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) << 3314 cparms->sgl_index_field_offset) | 3315 (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) << 3316 cparms->frag_num_field_offset) | 3317 offset) >> 3); 3318 } 3319 3320 static inline uint32_t 3321 sli_get_sli_rev(sli4_t *sli4) 3322 { 3323 return sli4->sli_rev; 3324 } 3325 3326 static inline uint32_t 3327 sli_get_sli_family(sli4_t *sli4) 3328 { 3329 return sli4->sli_family; 3330 } 3331 3332 static inline uint32_t 3333 sli_get_if_type(sli4_t *sli4) 3334 { 3335 return sli4->if_type; 3336 } 3337 3338 static inline void * 3339 sli_get_wwn_port(sli4_t *sli4) 3340 { 3341 return sli4->config.wwpn; 3342 } 3343 3344 static inline void * 3345 sli_get_wwn_node(sli4_t *sli4) 3346 { 3347 return sli4->config.wwnn; 3348 } 3349 3350 static inline void * 3351 sli_get_vpd(sli4_t *sli4) 3352 { 3353 return sli4->vpd.data.virt; 3354 } 3355 3356 static inline uint32_t 3357 sli_get_vpd_len(sli4_t *sli4) 3358 { 3359 return sli4->vpd.length; 3360 } 3361 3362 static inline uint32_t 3363 sli_get_fw_revision(sli4_t *sli4, uint32_t which) 3364 { 3365 return sli4->config.fw_rev[which]; 3366 } 3367 3368 static inline void * 3369 sli_get_fw_name(sli4_t *sli4, uint32_t which) 3370 { 3371 return sli4->config.fw_name[which]; 3372 } 3373 3374 static inline char * 3375 sli_get_ipl_name(sli4_t *sli4) 3376 { 3377 return sli4->config.ipl_name; 3378 } 3379 3380 static inline uint32_t 3381 sli_get_hw_revision(sli4_t *sli4, uint32_t which) 3382 { 3383 return sli4->config.hw_rev[which]; 3384 } 3385 3386 static inline uint32_t 3387 sli_get_auto_xfer_rdy_capable(sli4_t *sli4) 3388 { 3389 return sli4->config.auto_xfer_rdy; 3390 } 3391 3392 static inline uint32_t 3393 sli_get_dif_capable(sli4_t *sli4) 3394 { 3395 return sli4->config.features.flag.dif; 3396 } 3397 3398 static inline uint32_t 3399 sli_is_dif_inline_capable(sli4_t *sli4) 3400 { 3401 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable; 3402 } 3403 3404 static inline uint32_t 3405 sli_is_dif_separate_capable(sli4_t *sli4) 3406 { 3407 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable; 3408 } 3409 3410 static inline uint32_t 3411 sli_get_is_dual_ulp_capable(sli4_t *sli4) 3412 { 3413 return sli4->config.dual_ulp_capable; 3414 } 3415 3416 static inline uint32_t 3417 sli_get_is_sgl_chaining_capable(sli4_t *sli4) 3418 { 3419 return sli4->config.sgl_chaining_params.chaining_capable; 3420 } 3421 3422 static inline uint32_t 3423 sli_get_is_ulp_enabled(sli4_t *sli4, uint16_t ulp) 3424 { 3425 return sli4->config.is_ulp_fc[ulp]; 3426 } 3427 3428 static inline uint32_t 3429 sli_get_hlm_capable(sli4_t *sli4) 3430 { 3431 return sli4->config.features.flag.hlm; 3432 } 3433 3434 static inline int32_t 3435 sli_set_hlm(sli4_t *sli4, uint32_t value) 3436 { 3437 if (value && !sli4->config.features.flag.hlm) { 3438 ocs_log_test(sli4->os, "HLM not supported\n"); 3439 return -1; 3440 } 3441 3442 sli4->config.high_login_mode = value != 0 ? TRUE : FALSE; 3443 3444 return 0; 3445 } 3446 3447 static inline uint32_t 3448 sli_get_hlm(sli4_t *sli4) 3449 { 3450 return sli4->config.high_login_mode; 3451 } 3452 3453 static inline uint32_t 3454 sli_get_sgl_preregister_required(sli4_t *sli4) 3455 { 3456 return sli4->config.sgl_pre_registration_required; 3457 } 3458 3459 static inline uint32_t 3460 sli_get_sgl_preregister(sli4_t *sli4) 3461 { 3462 return sli4->config.sgl_pre_registered; 3463 } 3464 3465 static inline int32_t 3466 sli_set_sgl_preregister(sli4_t *sli4, uint32_t value) 3467 { 3468 if ((value == 0) && sli4->config.sgl_pre_registration_required) { 3469 ocs_log_test(sli4->os, "SGL pre-registration required\n"); 3470 return -1; 3471 } 3472 3473 sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE; 3474 3475 return 0; 3476 } 3477 3478 static inline sli4_asic_type_e 3479 sli_get_asic_type(sli4_t *sli4) 3480 { 3481 return sli4->asic_type; 3482 } 3483 3484 static inline sli4_asic_rev_e 3485 sli_get_asic_rev(sli4_t *sli4) 3486 { 3487 return sli4->asic_rev; 3488 } 3489 3490 static inline int32_t 3491 sli_set_topology(sli4_t *sli4, uint32_t value) 3492 { 3493 int32_t rc = 0; 3494 3495 switch (value) { 3496 case SLI4_READ_CFG_TOPO_FCOE: 3497 case SLI4_READ_CFG_TOPO_FC: 3498 case SLI4_READ_CFG_TOPO_FC_DA: 3499 case SLI4_READ_CFG_TOPO_FC_AL: 3500 sli4->config.topology = value; 3501 break; 3502 default: 3503 ocs_log_test(sli4->os, "unsupported topology %#x\n", value); 3504 rc = -1; 3505 } 3506 3507 return rc; 3508 } 3509 3510 static inline uint16_t 3511 sli_get_link_module_type(sli4_t *sli4) 3512 { 3513 return sli4->config.link_module_type; 3514 } 3515 3516 static inline char * 3517 sli_get_portnum(sli4_t *sli4) 3518 { 3519 return sli4->config.port_name; 3520 } 3521 3522 static inline char * 3523 sli_get_bios_version_string(sli4_t *sli4) 3524 { 3525 return sli4->config.bios_version_string; 3526 } 3527 3528 static inline uint32_t 3529 sli_convert_mask_to_count(uint32_t method, uint32_t mask) 3530 { 3531 uint32_t count = 0; 3532 3533 if (method) { 3534 count = 1 << ocs_lg2(mask); 3535 count *= 16; 3536 } else { 3537 count = mask; 3538 } 3539 3540 return count; 3541 } 3542 3543 /** 3544 * @brief Common Create Queue function prototype 3545 */ 3546 typedef int32_t (*sli4_create_q_fn_t)(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 3547 3548 /** 3549 * @brief Common Destroy Queue function prototype 3550 */ 3551 typedef int32_t (*sli4_destroy_q_fn_t)(sli4_t *, void *, size_t, uint16_t); 3552 3553 /**************************************************************************** 3554 * Function prototypes 3555 */ 3556 extern int32_t sli_cmd_config_auto_xfer_rdy(sli4_t *, void *, size_t, uint32_t); 3557 extern int32_t sli_cmd_config_auto_xfer_rdy_hp(sli4_t *, void *, size_t, uint32_t, uint32_t, uint32_t); 3558 extern int32_t sli_cmd_config_link(sli4_t *, void *, size_t); 3559 extern int32_t sli_cmd_down_link(sli4_t *, void *, size_t); 3560 extern int32_t sli_cmd_dump_type4(sli4_t *, void *, size_t, uint16_t); 3561 extern int32_t sli_cmd_common_read_transceiver_data(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3562 extern int32_t sli_cmd_read_link_stats(sli4_t *, void *, size_t,uint8_t, uint8_t, uint8_t); 3563 extern int32_t sli_cmd_read_status(sli4_t *sli4, void *buf, size_t size, uint8_t clear_counters); 3564 extern int32_t sli_cmd_init_link(sli4_t *, void *, size_t, uint32_t, uint8_t); 3565 extern int32_t sli_cmd_init_vfi(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 3566 extern int32_t sli_cmd_init_vpi(sli4_t *, void *, size_t, uint16_t, uint16_t); 3567 extern int32_t sli_cmd_post_xri(sli4_t *, void *, size_t, uint16_t, uint16_t); 3568 extern int32_t sli_cmd_release_xri(sli4_t *, void *, size_t, uint8_t); 3569 extern int32_t sli_cmd_read_sparm64(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 3570 extern int32_t sli_cmd_read_topology(sli4_t *, void *, size_t, ocs_dma_t *); 3571 extern int32_t sli_cmd_read_nvparms(sli4_t *, void *, size_t); 3572 extern int32_t sli_cmd_write_nvparms(sli4_t *, void *, size_t, uint8_t *, uint8_t *, uint8_t, uint32_t); 3573 typedef struct { 3574 uint16_t rq_id; 3575 uint8_t r_ctl_mask; 3576 uint8_t r_ctl_match; 3577 uint8_t type_mask; 3578 uint8_t type_match; 3579 } sli4_cmd_rq_cfg_t; 3580 extern int32_t sli_cmd_reg_fcfi(sli4_t *, void *, size_t, uint16_t, 3581 sli4_cmd_rq_cfg_t rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG], uint16_t); 3582 extern int32_t sli_cmd_reg_fcfi_mrq(sli4_t *, void *, size_t, uint8_t, uint16_t, uint16_t, uint8_t, uint8_t , uint16_t, sli4_cmd_rq_cfg_t *); 3583 3584 extern int32_t sli_cmd_reg_rpi(sli4_t *, void *, size_t, uint32_t, uint16_t, uint16_t, ocs_dma_t *, uint8_t, uint8_t); 3585 extern int32_t sli_cmd_reg_vfi(sli4_t *, void *, size_t, ocs_domain_t *); 3586 extern int32_t sli_cmd_reg_vpi(sli4_t *, void *, size_t, ocs_sli_port_t *, uint8_t); 3587 extern int32_t sli_cmd_sli_config(sli4_t *, void *, size_t, uint32_t, ocs_dma_t *); 3588 extern int32_t sli_cmd_unreg_fcfi(sli4_t *, void *, size_t, uint16_t); 3589 extern int32_t sli_cmd_unreg_rpi(sli4_t *, void *, size_t, uint16_t, sli4_resource_e, uint32_t); 3590 extern int32_t sli_cmd_unreg_vfi(sli4_t *, void *, size_t, ocs_domain_t *, uint32_t); 3591 extern int32_t sli_cmd_unreg_vpi(sli4_t *, void *, size_t, uint16_t, uint32_t); 3592 extern int32_t sli_cmd_common_nop(sli4_t *, void *, size_t, uint64_t); 3593 extern int32_t sli_cmd_common_get_resource_extent_info(sli4_t *, void *, size_t, uint16_t); 3594 extern int32_t sli_cmd_common_get_sli4_parameters(sli4_t *, void *, size_t); 3595 extern int32_t sli_cmd_common_write_object(sli4_t *, void *, size_t, 3596 uint16_t, uint16_t, uint32_t, uint32_t, char *, ocs_dma_t *); 3597 extern int32_t sli_cmd_common_delete_object(sli4_t *, void *, size_t, char *); 3598 extern int32_t sli_cmd_common_read_object(sli4_t *, void *, size_t, uint32_t, 3599 uint32_t, char *, ocs_dma_t *); 3600 extern int32_t sli_cmd_dmtf_exec_clp_cmd(sli4_t *sli4, void *buf, size_t size, 3601 ocs_dma_t *cmd, 3602 ocs_dma_t *resp); 3603 extern int32_t sli_cmd_common_set_dump_location(sli4_t *sli4, void *buf, size_t size, 3604 uint8_t query, uint8_t is_buffer_list, 3605 ocs_dma_t *buffer, uint8_t fdb); 3606 extern int32_t sli_cmd_common_set_features(sli4_t *, void *, size_t, uint32_t, uint32_t, void*); 3607 extern int32_t sli_cmd_common_get_profile_list(sli4_t *sli4, void *buf, 3608 size_t size, uint32_t start_profile_index, ocs_dma_t *dma); 3609 extern int32_t sli_cmd_common_get_active_profile(sli4_t *sli4, void *buf, 3610 size_t size); 3611 extern int32_t sli_cmd_common_set_active_profile(sli4_t *sli4, void *buf, 3612 size_t size, 3613 uint32_t fd, 3614 uint32_t active_profile_id); 3615 extern int32_t sli_cmd_common_get_reconfig_link_info(sli4_t *sli4, void *buf, 3616 size_t size, ocs_dma_t *dma); 3617 extern int32_t sli_cmd_common_set_reconfig_link_id(sli4_t *sli4, void *buf, 3618 size_t size, ocs_dma_t *dma, 3619 uint32_t fd, uint32_t active_link_config_id); 3620 extern int32_t sli_cmd_common_get_function_config(sli4_t *sli4, void *buf, 3621 size_t size); 3622 extern int32_t sli_cmd_common_get_profile_config(sli4_t *sli4, void *buf, 3623 size_t size, ocs_dma_t *dma); 3624 extern int32_t sli_cmd_common_set_profile_config(sli4_t *sli4, void *buf, 3625 size_t size, ocs_dma_t *dma, 3626 uint8_t profile_id, uint32_t descriptor_count, 3627 uint8_t isap); 3628 3629 extern int32_t sli_cqe_mq(void *); 3630 extern int32_t sli_cqe_async(sli4_t *, void *); 3631 3632 extern int32_t sli_setup(sli4_t *, ocs_os_handle_t, sli4_port_type_e); 3633 extern void sli_calc_max_qentries(sli4_t *sli4); 3634 extern int32_t sli_init(sli4_t *); 3635 extern int32_t sli_reset(sli4_t *); 3636 extern int32_t sli_fw_reset(sli4_t *); 3637 extern int32_t sli_teardown(sli4_t *); 3638 extern int32_t sli_callback(sli4_t *, sli4_callback_e, void *, void *); 3639 extern int32_t sli_bmbx_command(sli4_t *); 3640 extern int32_t __sli_queue_init(sli4_t *, sli4_queue_t *, uint32_t, size_t, uint32_t, uint32_t); 3641 extern int32_t __sli_create_queue(sli4_t *, sli4_queue_t *); 3642 extern int32_t sli_eq_modify_delay(sli4_t *sli4, sli4_queue_t *eq, uint32_t num_eq, uint32_t shift, uint32_t delay_mult); 3643 extern int32_t sli_queue_alloc(sli4_t *, uint32_t, sli4_queue_t *, uint32_t, sli4_queue_t *, uint16_t); 3644 extern int32_t sli_cq_alloc_set(sli4_t *, sli4_queue_t *qs[], uint32_t, uint32_t, sli4_queue_t *eqs[]); 3645 extern int32_t sli_get_queue_entry_size(sli4_t *, uint32_t); 3646 extern int32_t sli_queue_free(sli4_t *, sli4_queue_t *, uint32_t, uint32_t); 3647 extern int32_t sli_queue_reset(sli4_t *, sli4_queue_t *); 3648 extern int32_t sli_queue_is_empty(sli4_t *, sli4_queue_t *); 3649 extern int32_t sli_queue_eq_arm(sli4_t *, sli4_queue_t *, uint8_t); 3650 extern int32_t sli_queue_arm(sli4_t *, sli4_queue_t *, uint8_t); 3651 extern int32_t _sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3652 extern int32_t sli_queue_write(sli4_t *, sli4_queue_t *, uint8_t *); 3653 extern int32_t sli_queue_read(sli4_t *, sli4_queue_t *, uint8_t *); 3654 extern int32_t sli_queue_index(sli4_t *, sli4_queue_t *); 3655 extern int32_t _sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3656 extern int32_t sli_queue_poke(sli4_t *, sli4_queue_t *, uint32_t, uint8_t *); 3657 extern int32_t sli_resource_alloc(sli4_t *, sli4_resource_e, uint32_t *, uint32_t *); 3658 extern int32_t sli_resource_free(sli4_t *, sli4_resource_e, uint32_t); 3659 extern int32_t sli_resource_reset(sli4_t *, sli4_resource_e); 3660 extern int32_t sli_eq_parse(sli4_t *, uint8_t *, uint16_t *); 3661 extern int32_t sli_cq_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 3662 3663 extern int32_t sli_raise_ue(sli4_t *, uint8_t); 3664 extern int32_t sli_dump_is_ready(sli4_t *); 3665 extern int32_t sli_dump_is_present(sli4_t *); 3666 extern int32_t sli_reset_required(sli4_t *); 3667 extern int32_t sli_fw_error_status(sli4_t *); 3668 extern int32_t sli_fw_ready(sli4_t *); 3669 extern uint32_t sli_reg_read(sli4_t *, sli4_regname_e); 3670 extern void sli_reg_write(sli4_t *, sli4_regname_e, uint32_t); 3671 extern int32_t sli_link_is_configurable(sli4_t *); 3672 3673 #include "ocs_fcp.h" 3674 3675 /** 3676 * @brief Maximum value for a FCFI 3677 * 3678 * Note that although most commands provide a 16 bit field for the FCFI, 3679 * the FC/FCoE Asynchronous Recived CQE format only provides 6 bits for 3680 * the returned FCFI. Then effectively, the FCFI cannot be larger than 3681 * 1 << 6 or 64. 3682 */ 3683 #define SLI4_MAX_FCFI 64 3684 3685 /** 3686 * @brief Maximum value for FCF index 3687 * 3688 * The SLI-4 specification uses a 16 bit field in most places for the FCF 3689 * index, but practically, this value will be much smaller. Arbitrarily 3690 * limit the max FCF index to match the max FCFI value. 3691 */ 3692 #define SLI4_MAX_FCF_INDEX SLI4_MAX_FCFI 3693 3694 /************************************************************************* 3695 * SLI-4 FC/FCoE mailbox command formats and definitions. 3696 */ 3697 3698 /** 3699 * FC/FCoE opcode (OPC) values. 3700 */ 3701 #define SLI4_OPC_FCOE_WQ_CREATE 0x1 3702 #define SLI4_OPC_FCOE_WQ_DESTROY 0x2 3703 #define SLI4_OPC_FCOE_POST_SGL_PAGES 0x3 3704 #define SLI4_OPC_FCOE_RQ_CREATE 0x5 3705 #define SLI4_OPC_FCOE_RQ_DESTROY 0x6 3706 #define SLI4_OPC_FCOE_READ_FCF_TABLE 0x8 3707 #define SLI4_OPC_FCOE_POST_HDR_TEMPLATES 0xb 3708 #define SLI4_OPC_FCOE_REDISCOVER_FCF 0x10 3709 3710 /* Use the default CQ associated with the WQ */ 3711 #define SLI4_CQ_DEFAULT 0xffff 3712 3713 typedef struct sli4_physical_page_descriptor_s { 3714 uint32_t low; 3715 uint32_t high; 3716 } sli4_physical_page_descriptor_t; 3717 3718 /** 3719 * @brief FCOE_WQ_CREATE 3720 * 3721 * Create a Work Queue for FC/FCoE use. 3722 */ 3723 #define SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES 4 3724 3725 typedef struct sli4_req_fcoe_wq_create_s { 3726 sli4_req_hdr_t hdr; 3727 #if BYTE_ORDER == LITTLE_ENDIAN 3728 uint32_t num_pages:8, 3729 dua:1, 3730 :7, 3731 cq_id:16; 3732 sli4_physical_page_descriptor_t page_physical_address[SLI4_FCOE_WQ_CREATE_V0_MAX_PAGES]; 3733 uint32_t bqu:1, 3734 :7, 3735 ulp:8, 3736 :16; 3737 #else 3738 #error big endian version not defined 3739 #endif 3740 } sli4_req_fcoe_wq_create_t; 3741 3742 /** 3743 * @brief FCOE_WQ_CREATE_V1 3744 * 3745 * Create a version 1 Work Queue for FC/FCoE use. 3746 */ 3747 typedef struct sli4_req_fcoe_wq_create_v1_s { 3748 sli4_req_hdr_t hdr; 3749 #if BYTE_ORDER == LITTLE_ENDIAN 3750 uint32_t num_pages:16, 3751 cq_id:16; 3752 uint32_t page_size:8, 3753 wqe_size:4, 3754 :4, 3755 wqe_count:16; 3756 uint32_t rsvd6; 3757 sli4_physical_page_descriptor_t page_physical_address[8]; 3758 #else 3759 #error big endian version not defined 3760 #endif 3761 } sli4_req_fcoe_wq_create_v1_t; 3762 3763 #define SLI4_FCOE_WQ_CREATE_V1_MAX_PAGES 8 3764 3765 /** 3766 * @brief FCOE_WQ_DESTROY 3767 * 3768 * Destroy an FC/FCoE Work Queue. 3769 */ 3770 typedef struct sli4_req_fcoe_wq_destroy_s { 3771 sli4_req_hdr_t hdr; 3772 #if BYTE_ORDER == LITTLE_ENDIAN 3773 uint32_t wq_id:16, 3774 :16; 3775 #else 3776 #error big endian version not defined 3777 #endif 3778 } sli4_req_fcoe_wq_destroy_t; 3779 3780 /** 3781 * @brief FCOE_POST_SGL_PAGES 3782 * 3783 * Register the scatter gather list (SGL) memory and associate it with an XRI. 3784 */ 3785 typedef struct sli4_req_fcoe_post_sgl_pages_s { 3786 sli4_req_hdr_t hdr; 3787 #if BYTE_ORDER == LITTLE_ENDIAN 3788 uint32_t xri_start:16, 3789 xri_count:16; 3790 struct { 3791 uint32_t page0_low; 3792 uint32_t page0_high; 3793 uint32_t page1_low; 3794 uint32_t page1_high; 3795 } page_set[10]; 3796 #else 3797 #error big endian version not defined 3798 #endif 3799 } sli4_req_fcoe_post_sgl_pages_t; 3800 3801 /** 3802 * @brief FCOE_RQ_CREATE 3803 * 3804 * Create a Receive Queue for FC/FCoE use. 3805 */ 3806 typedef struct sli4_req_fcoe_rq_create_s { 3807 sli4_req_hdr_t hdr; 3808 #if BYTE_ORDER == LITTLE_ENDIAN 3809 uint32_t num_pages:16, 3810 dua:1, 3811 bqu:1, 3812 :6, 3813 ulp:8; 3814 uint32_t :16, 3815 rqe_count:4, 3816 :12; 3817 uint32_t rsvd6; 3818 uint32_t buffer_size:16, 3819 cq_id:16; 3820 uint32_t rsvd8; 3821 sli4_physical_page_descriptor_t page_physical_address[8]; 3822 #else 3823 #error big endian version not defined 3824 #endif 3825 } sli4_req_fcoe_rq_create_t; 3826 3827 #define SLI4_FCOE_RQ_CREATE_V0_MAX_PAGES 8 3828 #define SLI4_FCOE_RQ_CREATE_V0_MIN_BUF_SIZE 128 3829 #define SLI4_FCOE_RQ_CREATE_V0_MAX_BUF_SIZE 2048 3830 3831 /** 3832 * @brief FCOE_RQ_CREATE_V1 3833 * 3834 * Create a version 1 Receive Queue for FC/FCoE use. 3835 */ 3836 typedef struct sli4_req_fcoe_rq_create_v1_s { 3837 sli4_req_hdr_t hdr; 3838 #if BYTE_ORDER == LITTLE_ENDIAN 3839 uint32_t num_pages:16, 3840 :13, 3841 dim:1, 3842 dfd:1, 3843 dnb:1; 3844 uint32_t page_size:8, 3845 rqe_size:4, 3846 :4, 3847 rqe_count:16; 3848 uint32_t rsvd6; 3849 uint32_t :16, 3850 cq_id:16; 3851 uint32_t buffer_size; 3852 sli4_physical_page_descriptor_t page_physical_address[8]; 3853 #else 3854 #error big endian version not defined 3855 #endif 3856 } sli4_req_fcoe_rq_create_v1_t; 3857 3858 /** 3859 * @brief FCOE_RQ_CREATE_V2 3860 * 3861 * Create a version 2 Receive Queue for FC/FCoE use. 3862 */ 3863 typedef struct sli4_req_fcoe_rq_create_v2_s { 3864 sli4_req_hdr_t hdr; 3865 #if BYTE_ORDER == LITTLE_ENDIAN 3866 uint32_t num_pages:16, 3867 rq_count:8, 3868 :5, 3869 dim:1, 3870 dfd:1, 3871 dnb:1; 3872 uint32_t page_size:8, 3873 rqe_size:4, 3874 :4, 3875 rqe_count:16; 3876 uint32_t hdr_buffer_size:16, 3877 payload_buffer_size:16; 3878 uint32_t base_cq_id:16, 3879 :16; 3880 uint32_t rsvd; 3881 sli4_physical_page_descriptor_t page_physical_address[0]; 3882 #else 3883 #error big endian version not defined 3884 #endif 3885 } sli4_req_fcoe_rq_create_v2_t; 3886 3887 #define SLI4_FCOE_RQ_CREATE_V1_MAX_PAGES 8 3888 #define SLI4_FCOE_RQ_CREATE_V1_MIN_BUF_SIZE 64 3889 #define SLI4_FCOE_RQ_CREATE_V1_MAX_BUF_SIZE 2048 3890 3891 #define SLI4_FCOE_RQE_SIZE_8 0x2 3892 #define SLI4_FCOE_RQE_SIZE_16 0x3 3893 #define SLI4_FCOE_RQE_SIZE_32 0x4 3894 #define SLI4_FCOE_RQE_SIZE_64 0x5 3895 #define SLI4_FCOE_RQE_SIZE_128 0x6 3896 3897 #define SLI4_FCOE_RQ_PAGE_SIZE_4096 0x1 3898 #define SLI4_FCOE_RQ_PAGE_SIZE_8192 0x2 3899 #define SLI4_FCOE_RQ_PAGE_SIZE_16384 0x4 3900 #define SLI4_FCOE_RQ_PAGE_SIZE_32768 0x8 3901 #define SLI4_FCOE_RQ_PAGE_SIZE_64536 0x10 3902 3903 #define SLI4_FCOE_RQE_SIZE 8 3904 3905 /** 3906 * @brief FCOE_RQ_DESTROY 3907 * 3908 * Destroy an FC/FCoE Receive Queue. 3909 */ 3910 typedef struct sli4_req_fcoe_rq_destroy_s { 3911 sli4_req_hdr_t hdr; 3912 #if BYTE_ORDER == LITTLE_ENDIAN 3913 uint32_t rq_id:16, 3914 :16; 3915 #else 3916 #error big endian version not defined 3917 #endif 3918 } sli4_req_fcoe_rq_destroy_t; 3919 3920 /** 3921 * @brief FCOE_READ_FCF_TABLE 3922 * 3923 * Retrieve a FCF database (also known as a table) entry created by the SLI Port 3924 * during FIP discovery. 3925 */ 3926 typedef struct sli4_req_fcoe_read_fcf_table_s { 3927 sli4_req_hdr_t hdr; 3928 #if BYTE_ORDER == LITTLE_ENDIAN 3929 uint32_t fcf_index:16, 3930 :16; 3931 #else 3932 #error big endian version not defined 3933 #endif 3934 } sli4_req_fcoe_read_fcf_table_t; 3935 3936 /* A FCF index of -1 on the request means return the first valid entry */ 3937 #define SLI4_FCOE_FCF_TABLE_FIRST (UINT16_MAX) 3938 3939 /** 3940 * @brief FCF table entry 3941 * 3942 * This is the information returned by the FCOE_READ_FCF_TABLE command. 3943 */ 3944 typedef struct sli4_fcf_entry_s { 3945 #if BYTE_ORDER == LITTLE_ENDIAN 3946 uint32_t max_receive_size; 3947 uint32_t fip_keep_alive; 3948 uint32_t fip_priority; 3949 uint8_t fcf_mac_address[6]; 3950 uint8_t fcf_available; 3951 uint8_t mac_address_provider; 3952 uint8_t fabric_name_id[8]; 3953 uint8_t fc_map[3]; 3954 uint8_t val:1, 3955 fc:1, 3956 :5, 3957 sol:1; 3958 uint32_t fcf_index:16, 3959 fcf_state:16; 3960 uint8_t vlan_bitmap[512]; 3961 uint8_t switch_name[8]; 3962 #else 3963 #error big endian version not defined 3964 #endif 3965 } sli4_fcf_entry_t; 3966 3967 /** 3968 * @brief FCOE_READ_FCF_TABLE response. 3969 */ 3970 typedef struct sli4_res_fcoe_read_fcf_table_s { 3971 sli4_res_hdr_t hdr; 3972 #if BYTE_ORDER == LITTLE_ENDIAN 3973 uint32_t event_tag; 3974 uint32_t next_index:16, 3975 :16; 3976 sli4_fcf_entry_t fcf_entry; 3977 #else 3978 #error big endian version not defined 3979 #endif 3980 } sli4_res_fcoe_read_fcf_table_t; 3981 3982 /* A next FCF index of -1 in the response means this is the last valid entry */ 3983 #define SLI4_FCOE_FCF_TABLE_LAST (UINT16_MAX) 3984 3985 /** 3986 * @brief FCOE_POST_HDR_TEMPLATES 3987 */ 3988 typedef struct sli4_req_fcoe_post_hdr_templates_s { 3989 sli4_req_hdr_t hdr; 3990 #if BYTE_ORDER == LITTLE_ENDIAN 3991 uint32_t rpi_offset:16, 3992 page_count:16; 3993 sli4_physical_page_descriptor_t page_descriptor[0]; 3994 #else 3995 #error big endian version not defined 3996 #endif 3997 } sli4_req_fcoe_post_hdr_templates_t; 3998 3999 #define SLI4_FCOE_HDR_TEMPLATE_SIZE 64 4000 4001 /** 4002 * @brief FCOE_REDISCOVER_FCF 4003 */ 4004 typedef struct sli4_req_fcoe_rediscover_fcf_s { 4005 sli4_req_hdr_t hdr; 4006 #if BYTE_ORDER == LITTLE_ENDIAN 4007 uint32_t fcf_count:16, 4008 :16; 4009 uint32_t rsvd5; 4010 uint16_t fcf_index[16]; 4011 #else 4012 #error big endian version not defined 4013 #endif 4014 } sli4_req_fcoe_rediscover_fcf_t; 4015 4016 /** 4017 * Work Queue Entry (WQE) types. 4018 */ 4019 #define SLI4_WQE_ABORT 0x0f 4020 #define SLI4_WQE_ELS_REQUEST64 0x8a 4021 #define SLI4_WQE_FCP_IBIDIR64 0xac 4022 #define SLI4_WQE_FCP_IREAD64 0x9a 4023 #define SLI4_WQE_FCP_IWRITE64 0x98 4024 #define SLI4_WQE_FCP_ICMND64 0x9c 4025 #define SLI4_WQE_FCP_TRECEIVE64 0xa1 4026 #define SLI4_WQE_FCP_CONT_TRECEIVE64 0xe5 4027 #define SLI4_WQE_FCP_TRSP64 0xa3 4028 #define SLI4_WQE_FCP_TSEND64 0x9f 4029 #define SLI4_WQE_GEN_REQUEST64 0xc2 4030 #define SLI4_WQE_SEND_FRAME 0xe1 4031 #define SLI4_WQE_XMIT_BCAST64 0X84 4032 #define SLI4_WQE_XMIT_BLS_RSP 0x97 4033 #define SLI4_WQE_ELS_RSP64 0x95 4034 #define SLI4_WQE_XMIT_SEQUENCE64 0x82 4035 #define SLI4_WQE_REQUEUE_XRI 0x93 4036 4037 /** 4038 * WQE command types. 4039 */ 4040 #define SLI4_CMD_FCP_IREAD64_WQE 0x00 4041 #define SLI4_CMD_FCP_ICMND64_WQE 0x00 4042 #define SLI4_CMD_FCP_IWRITE64_WQE 0x01 4043 #define SLI4_CMD_FCP_TRECEIVE64_WQE 0x02 4044 #define SLI4_CMD_FCP_TRSP64_WQE 0x03 4045 #define SLI4_CMD_FCP_TSEND64_WQE 0x07 4046 #define SLI4_CMD_GEN_REQUEST64_WQE 0x08 4047 #define SLI4_CMD_XMIT_BCAST64_WQE 0x08 4048 #define SLI4_CMD_XMIT_BLS_RSP64_WQE 0x08 4049 #define SLI4_CMD_ABORT_WQE 0x08 4050 #define SLI4_CMD_XMIT_SEQUENCE64_WQE 0x08 4051 #define SLI4_CMD_REQUEUE_XRI_WQE 0x0A 4052 #define SLI4_CMD_SEND_FRAME_WQE 0x0a 4053 4054 #define SLI4_WQE_SIZE 0x05 4055 #define SLI4_WQE_EXT_SIZE 0x06 4056 4057 #define SLI4_WQE_BYTES (16 * sizeof(uint32_t)) 4058 #define SLI4_WQE_EXT_BYTES (32 * sizeof(uint32_t)) 4059 4060 /* Mask for ccp (CS_CTL) */ 4061 #define SLI4_MASK_CCP 0xfe /* Upper 7 bits of CS_CTL is priority */ 4062 4063 /** 4064 * @brief Generic WQE 4065 */ 4066 typedef struct sli4_generic_wqe_s { 4067 #if BYTE_ORDER == LITTLE_ENDIAN 4068 uint32_t cmd_spec0_5[6]; 4069 uint32_t xri_tag:16, 4070 context_tag:16; 4071 uint32_t :2, 4072 ct:2, 4073 :4, 4074 command:8, 4075 class:3, 4076 :1, 4077 pu:2, 4078 :2, 4079 timer:8; 4080 uint32_t abort_tag; 4081 uint32_t request_tag:16, 4082 :16; 4083 uint32_t ebde_cnt:4, 4084 :3, 4085 len_loc:2, 4086 qosd:1, 4087 :1, 4088 xbl:1, 4089 hlm:1, 4090 iod:1, 4091 dbde:1, 4092 wqes:1, 4093 pri:3, 4094 pv:1, 4095 eat:1, 4096 xc:1, 4097 :1, 4098 ccpe:1, 4099 ccp:8; 4100 uint32_t cmd_type:4, 4101 :3, 4102 wqec:1, 4103 :8, 4104 cq_id:16; 4105 #else 4106 #error big endian version not defined 4107 #endif 4108 } sli4_generic_wqe_t; 4109 4110 /** 4111 * @brief WQE used to abort exchanges. 4112 */ 4113 typedef struct sli4_abort_wqe_s { 4114 #if BYTE_ORDER == LITTLE_ENDIAN 4115 uint32_t rsvd0; 4116 uint32_t rsvd1; 4117 uint32_t ext_t_tag; 4118 uint32_t ia:1, 4119 ir:1, 4120 :6, 4121 criteria:8, 4122 :16; 4123 uint32_t ext_t_mask; 4124 uint32_t t_mask; 4125 uint32_t xri_tag:16, 4126 context_tag:16; 4127 uint32_t :2, 4128 ct:2, 4129 :4, 4130 command:8, 4131 class:3, 4132 :1, 4133 pu:2, 4134 :2, 4135 timer:8; 4136 uint32_t t_tag; 4137 uint32_t request_tag:16, 4138 :16; 4139 uint32_t ebde_cnt:4, 4140 :3, 4141 len_loc:2, 4142 qosd:1, 4143 :1, 4144 xbl:1, 4145 :1, 4146 iod:1, 4147 dbde:1, 4148 wqes:1, 4149 pri:3, 4150 pv:1, 4151 eat:1, 4152 xc:1, 4153 :1, 4154 ccpe:1, 4155 ccp:8; 4156 uint32_t cmd_type:4, 4157 :3, 4158 wqec:1, 4159 :8, 4160 cq_id:16; 4161 #else 4162 #error big endian version not defined 4163 #endif 4164 } sli4_abort_wqe_t; 4165 4166 #define SLI4_ABORT_CRITERIA_XRI_TAG 0x01 4167 #define SLI4_ABORT_CRITERIA_ABORT_TAG 0x02 4168 #define SLI4_ABORT_CRITERIA_REQUEST_TAG 0x03 4169 #define SLI4_ABORT_CRITERIA_EXT_ABORT_TAG 0x04 4170 4171 typedef enum { 4172 SLI_ABORT_XRI, 4173 SLI_ABORT_ABORT_ID, 4174 SLI_ABORT_REQUEST_ID, 4175 SLI_ABORT_MAX, /* must be last */ 4176 } sli4_abort_type_e; 4177 4178 /** 4179 * @brief WQE used to create an ELS request. 4180 */ 4181 typedef struct sli4_els_request64_wqe_s { 4182 sli4_bde_t els_request_payload; 4183 #if BYTE_ORDER == LITTLE_ENDIAN 4184 uint32_t els_request_payload_length; 4185 uint32_t sid:24, 4186 sp:1, 4187 :7; 4188 uint32_t remote_id:24, 4189 :8; 4190 uint32_t xri_tag:16, 4191 context_tag:16; 4192 uint32_t :2, 4193 ct:2, 4194 :4, 4195 command:8, 4196 class:3, 4197 ar:1, 4198 pu:2, 4199 :2, 4200 timer:8; 4201 uint32_t abort_tag; 4202 uint32_t request_tag:16, 4203 temporary_rpi:16; 4204 uint32_t ebde_cnt:4, 4205 :3, 4206 len_loc:2, 4207 qosd:1, 4208 :1, 4209 xbl:1, 4210 hlm:1, 4211 iod:1, 4212 dbde:1, 4213 wqes:1, 4214 pri:3, 4215 pv:1, 4216 eat:1, 4217 xc:1, 4218 :1, 4219 ccpe:1, 4220 ccp:8; 4221 uint32_t cmd_type:4, 4222 els_id:3, 4223 wqec:1, 4224 :8, 4225 cq_id:16; 4226 sli4_bde_t els_response_payload_bde; 4227 uint32_t max_response_payload_length; 4228 #else 4229 #error big endian version not defined 4230 #endif 4231 } sli4_els_request64_wqe_t; 4232 4233 #define SLI4_ELS_REQUEST64_CONTEXT_RPI 0x0 4234 #define SLI4_ELS_REQUEST64_CONTEXT_VPI 0x1 4235 #define SLI4_ELS_REQUEST64_CONTEXT_VFI 0x2 4236 #define SLI4_ELS_REQUEST64_CONTEXT_FCFI 0x3 4237 4238 #define SLI4_ELS_REQUEST64_CLASS_2 0x1 4239 #define SLI4_ELS_REQUEST64_CLASS_3 0x2 4240 4241 #define SLI4_ELS_REQUEST64_DIR_WRITE 0x0 4242 #define SLI4_ELS_REQUEST64_DIR_READ 0x1 4243 4244 #define SLI4_ELS_REQUEST64_OTHER 0x0 4245 #define SLI4_ELS_REQUEST64_LOGO 0x1 4246 #define SLI4_ELS_REQUEST64_FDISC 0x2 4247 #define SLI4_ELS_REQUEST64_FLOGIN 0x3 4248 #define SLI4_ELS_REQUEST64_PLOGI 0x4 4249 4250 #define SLI4_ELS_REQUEST64_CMD_GEN 0x08 4251 #define SLI4_ELS_REQUEST64_CMD_NON_FABRIC 0x0c 4252 #define SLI4_ELS_REQUEST64_CMD_FABRIC 0x0d 4253 4254 /** 4255 * @brief WQE used to create an FCP initiator no data command. 4256 */ 4257 typedef struct sli4_fcp_icmnd64_wqe_s { 4258 sli4_bde_t bde; 4259 #if BYTE_ORDER == LITTLE_ENDIAN 4260 uint32_t payload_offset_length:16, 4261 fcp_cmd_buffer_length:16; 4262 uint32_t rsvd4; 4263 uint32_t remote_n_port_id:24, 4264 :8; 4265 uint32_t xri_tag:16, 4266 context_tag:16; 4267 uint32_t dif:2, 4268 ct:2, 4269 bs:3, 4270 :1, 4271 command:8, 4272 class:3, 4273 :1, 4274 pu:2, 4275 erp:1, 4276 lnk:1, 4277 timer:8; 4278 uint32_t abort_tag; 4279 uint32_t request_tag:16, 4280 :16; 4281 uint32_t ebde_cnt:4, 4282 :3, 4283 len_loc:2, 4284 qosd:1, 4285 :1, 4286 xbl:1, 4287 hlm:1, 4288 iod:1, 4289 dbde:1, 4290 wqes:1, 4291 pri:3, 4292 pv:1, 4293 eat:1, 4294 xc:1, 4295 :1, 4296 ccpe:1, 4297 ccp:8; 4298 uint32_t cmd_type:4, 4299 :3, 4300 wqec:1, 4301 :8, 4302 cq_id:16; 4303 uint32_t rsvd12; 4304 uint32_t rsvd13; 4305 uint32_t rsvd14; 4306 uint32_t rsvd15; 4307 #else 4308 #error big endian version not defined 4309 #endif 4310 } sli4_fcp_icmnd64_wqe_t; 4311 4312 /** 4313 * @brief WQE used to create an FCP initiator read. 4314 */ 4315 typedef struct sli4_fcp_iread64_wqe_s { 4316 sli4_bde_t bde; 4317 #if BYTE_ORDER == LITTLE_ENDIAN 4318 uint32_t payload_offset_length:16, 4319 fcp_cmd_buffer_length:16; 4320 uint32_t total_transfer_length; 4321 uint32_t remote_n_port_id:24, 4322 :8; 4323 uint32_t xri_tag:16, 4324 context_tag:16; 4325 uint32_t dif:2, 4326 ct:2, 4327 bs:3, 4328 :1, 4329 command:8, 4330 class:3, 4331 :1, 4332 pu:2, 4333 erp:1, 4334 lnk:1, 4335 timer:8; 4336 uint32_t abort_tag; 4337 uint32_t request_tag:16, 4338 :16; 4339 uint32_t ebde_cnt:4, 4340 :3, 4341 len_loc:2, 4342 qosd:1, 4343 :1, 4344 xbl:1, 4345 hlm:1, 4346 iod:1, 4347 dbde:1, 4348 wqes:1, 4349 pri:3, 4350 pv:1, 4351 eat:1, 4352 xc:1, 4353 :1, 4354 ccpe:1, 4355 ccp:8; 4356 uint32_t cmd_type:4, 4357 :3, 4358 wqec:1, 4359 :8, 4360 cq_id:16; 4361 uint32_t rsvd12; 4362 #else 4363 #error big endian version not defined 4364 #endif 4365 sli4_bde_t first_data_bde; /* reserved if performance hints disabled */ 4366 } sli4_fcp_iread64_wqe_t; 4367 4368 /** 4369 * @brief WQE used to create an FCP initiator write. 4370 */ 4371 typedef struct sli4_fcp_iwrite64_wqe_s { 4372 sli4_bde_t bde; 4373 #if BYTE_ORDER == LITTLE_ENDIAN 4374 uint32_t payload_offset_length:16, 4375 fcp_cmd_buffer_length:16; 4376 uint32_t total_transfer_length; 4377 uint32_t initial_transfer_length; 4378 uint32_t xri_tag:16, 4379 context_tag:16; 4380 uint32_t dif:2, 4381 ct:2, 4382 bs:3, 4383 :1, 4384 command:8, 4385 class:3, 4386 :1, 4387 pu:2, 4388 erp:1, 4389 lnk:1, 4390 timer:8; 4391 uint32_t abort_tag; 4392 uint32_t request_tag:16, 4393 :16; 4394 uint32_t ebde_cnt:4, 4395 :3, 4396 len_loc:2, 4397 qosd:1, 4398 :1, 4399 xbl:1, 4400 hlm:1, 4401 iod:1, 4402 dbde:1, 4403 wqes:1, 4404 pri:3, 4405 pv:1, 4406 eat:1, 4407 xc:1, 4408 :1, 4409 ccpe:1, 4410 ccp:8; 4411 uint32_t cmd_type:4, 4412 :3, 4413 wqec:1, 4414 :8, 4415 cq_id:16; 4416 uint32_t remote_n_port_id:24, 4417 :8; 4418 #else 4419 #error big endian version not defined 4420 #endif 4421 sli4_bde_t first_data_bde; 4422 } sli4_fcp_iwrite64_wqe_t; 4423 4424 typedef struct sli4_fcp_128byte_wqe_s { 4425 uint32_t dw[32]; 4426 } sli4_fcp_128byte_wqe_t; 4427 4428 /** 4429 * @brief WQE used to create an FCP target receive, and FCP target 4430 * receive continue. 4431 */ 4432 typedef struct sli4_fcp_treceive64_wqe_s { 4433 sli4_bde_t bde; 4434 #if BYTE_ORDER == LITTLE_ENDIAN 4435 uint32_t payload_offset_length; 4436 uint32_t relative_offset; 4437 /** 4438 * DWord 5 can either be the task retry identifier (HLM=0) or 4439 * the remote N_Port ID (HLM=1), or if implementing the Skyhawk 4440 * T10-PI workaround, the secondary xri tag 4441 */ 4442 union { 4443 uint32_t sec_xri_tag:16, 4444 :16; 4445 uint32_t dword; 4446 } dword5; 4447 uint32_t xri_tag:16, 4448 context_tag:16; 4449 uint32_t dif:2, 4450 ct:2, 4451 bs:3, 4452 :1, 4453 command:8, 4454 class:3, 4455 ar:1, 4456 pu:2, 4457 conf:1, 4458 lnk:1, 4459 timer:8; 4460 uint32_t abort_tag; 4461 uint32_t request_tag:16, 4462 remote_xid:16; 4463 uint32_t ebde_cnt:4, 4464 :1, 4465 app_id_valid:1, 4466 :1, 4467 len_loc:2, 4468 qosd:1, 4469 wchn:1, 4470 xbl:1, 4471 hlm:1, 4472 iod:1, 4473 dbde:1, 4474 wqes:1, 4475 pri:3, 4476 pv:1, 4477 eat:1, 4478 xc:1, 4479 sr:1, 4480 ccpe:1, 4481 ccp:8; 4482 uint32_t cmd_type:4, 4483 :3, 4484 wqec:1, 4485 :8, 4486 cq_id:16; 4487 uint32_t fcp_data_receive_length; 4488 4489 #else 4490 #error big endian version not defined 4491 #endif 4492 sli4_bde_t first_data_bde; /* For performance hints */ 4493 4494 } sli4_fcp_treceive64_wqe_t; 4495 4496 /** 4497 * @brief WQE used to create an FCP target response. 4498 */ 4499 typedef struct sli4_fcp_trsp64_wqe_s { 4500 sli4_bde_t bde; 4501 #if BYTE_ORDER == LITTLE_ENDIAN 4502 uint32_t fcp_response_length; 4503 uint32_t rsvd4; 4504 /** 4505 * DWord 5 can either be the task retry identifier (HLM=0) or 4506 * the remote N_Port ID (HLM=1) 4507 */ 4508 uint32_t dword5; 4509 uint32_t xri_tag:16, 4510 rpi:16; 4511 uint32_t :2, 4512 ct:2, 4513 dnrx:1, 4514 :3, 4515 command:8, 4516 class:3, 4517 ag:1, 4518 pu:2, 4519 conf:1, 4520 lnk:1, 4521 timer:8; 4522 uint32_t abort_tag; 4523 uint32_t request_tag:16, 4524 remote_xid:16; 4525 uint32_t ebde_cnt:4, 4526 :1, 4527 app_id_valid:1, 4528 :1, 4529 len_loc:2, 4530 qosd:1, 4531 wchn:1, 4532 xbl:1, 4533 hlm:1, 4534 iod:1, 4535 dbde:1, 4536 wqes:1, 4537 pri:3, 4538 pv:1, 4539 eat:1, 4540 xc:1, 4541 sr:1, 4542 ccpe:1, 4543 ccp:8; 4544 uint32_t cmd_type:4, 4545 :3, 4546 wqec:1, 4547 :8, 4548 cq_id:16; 4549 uint32_t rsvd12; 4550 uint32_t rsvd13; 4551 uint32_t rsvd14; 4552 uint32_t rsvd15; 4553 #else 4554 #error big endian version not defined 4555 #endif 4556 } sli4_fcp_trsp64_wqe_t; 4557 4558 /** 4559 * @brief WQE used to create an FCP target send (DATA IN). 4560 */ 4561 typedef struct sli4_fcp_tsend64_wqe_s { 4562 sli4_bde_t bde; 4563 #if BYTE_ORDER == LITTLE_ENDIAN 4564 uint32_t payload_offset_length; 4565 uint32_t relative_offset; 4566 /** 4567 * DWord 5 can either be the task retry identifier (HLM=0) or 4568 * the remote N_Port ID (HLM=1) 4569 */ 4570 uint32_t dword5; 4571 uint32_t xri_tag:16, 4572 rpi:16; 4573 uint32_t dif:2, 4574 ct:2, 4575 bs:3, 4576 :1, 4577 command:8, 4578 class:3, 4579 ar:1, 4580 pu:2, 4581 conf:1, 4582 lnk:1, 4583 timer:8; 4584 uint32_t abort_tag; 4585 uint32_t request_tag:16, 4586 remote_xid:16; 4587 uint32_t ebde_cnt:4, 4588 :1, 4589 app_id_valid:1, 4590 :1, 4591 len_loc:2, 4592 qosd:1, 4593 wchn:1, 4594 xbl:1, 4595 hlm:1, 4596 iod:1, 4597 dbde:1, 4598 wqes:1, 4599 pri:3, 4600 pv:1, 4601 eat:1, 4602 xc:1, 4603 sr:1, 4604 ccpe:1, 4605 ccp:8; 4606 uint32_t cmd_type:4, 4607 :3, 4608 wqec:1, 4609 :8, 4610 cq_id:16; 4611 uint32_t fcp_data_transmit_length; 4612 4613 #else 4614 #error big endian version not defined 4615 #endif 4616 sli4_bde_t first_data_bde; /* For performance hints */ 4617 } sli4_fcp_tsend64_wqe_t; 4618 4619 #define SLI4_IO_CONTINUATION BIT(0) /** The XRI associated with this IO is already active */ 4620 #define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */ 4621 #define SLI4_IO_NO_ABORT BIT(2) 4622 #define SLI4_IO_DNRX BIT(3) /** Set the DNRX bit because no auto xref rdy buffer is posted */ 4623 4624 /* WQE DIF field contents */ 4625 #define SLI4_DIF_DISABLED 0 4626 #define SLI4_DIF_PASS_THROUGH 1 4627 #define SLI4_DIF_STRIP 2 4628 #define SLI4_DIF_INSERT 3 4629 4630 /** 4631 * @brief WQE used to create a general request. 4632 */ 4633 typedef struct sli4_gen_request64_wqe_s { 4634 sli4_bde_t bde; 4635 #if BYTE_ORDER == LITTLE_ENDIAN 4636 uint32_t request_payload_length; 4637 uint32_t relative_offset; 4638 uint32_t :8, 4639 df_ctl:8, 4640 type:8, 4641 r_ctl:8; 4642 uint32_t xri_tag:16, 4643 context_tag:16; 4644 uint32_t :2, 4645 ct:2, 4646 :4, 4647 command:8, 4648 class:3, 4649 :1, 4650 pu:2, 4651 :2, 4652 timer:8; 4653 uint32_t abort_tag; 4654 uint32_t request_tag:16, 4655 :16; 4656 uint32_t ebde_cnt:4, 4657 :3, 4658 len_loc:2, 4659 qosd:1, 4660 :1, 4661 xbl:1, 4662 hlm:1, 4663 iod:1, 4664 dbde:1, 4665 wqes:1, 4666 pri:3, 4667 pv:1, 4668 eat:1, 4669 xc:1, 4670 :1, 4671 ccpe:1, 4672 ccp:8; 4673 uint32_t cmd_type:4, 4674 :3, 4675 wqec:1, 4676 :8, 4677 cq_id:16; 4678 uint32_t remote_n_port_id:24, 4679 :8; 4680 uint32_t rsvd13; 4681 uint32_t rsvd14; 4682 uint32_t max_response_payload_length; 4683 #else 4684 #error big endian version not defined 4685 #endif 4686 } sli4_gen_request64_wqe_t; 4687 4688 /** 4689 * @brief WQE used to create a send frame request. 4690 */ 4691 typedef struct sli4_send_frame_wqe_s { 4692 sli4_bde_t bde; 4693 #if BYTE_ORDER == LITTLE_ENDIAN 4694 uint32_t frame_length; 4695 uint32_t fc_header_0_1[2]; 4696 uint32_t xri_tag:16, 4697 context_tag:16; 4698 uint32_t :2, 4699 ct:2, 4700 :4, 4701 command:8, 4702 class:3, 4703 :1, 4704 pu:2, 4705 :2, 4706 timer:8; 4707 uint32_t abort_tag; 4708 uint32_t request_tag:16, 4709 eof:8, 4710 sof:8; 4711 uint32_t ebde_cnt:4, 4712 :3, 4713 lenloc:2, 4714 qosd:1, 4715 wchn:1, 4716 xbl:1, 4717 hlm:1, 4718 iod:1, 4719 dbde:1, 4720 wqes:1, 4721 pri:3, 4722 pv:1, 4723 eat:1, 4724 xc:1, 4725 :1, 4726 ccpe:1, 4727 ccp:8; 4728 uint32_t cmd_type:4, 4729 :3, 4730 wqec:1, 4731 :8, 4732 cq_id:16; 4733 uint32_t fc_header_2_5[4]; 4734 #else 4735 #error big endian version not defined 4736 #endif 4737 } sli4_send_frame_wqe_t; 4738 4739 /** 4740 * @brief WQE used to create a transmit sequence. 4741 */ 4742 typedef struct sli4_xmit_sequence64_wqe_s { 4743 sli4_bde_t bde; 4744 #if BYTE_ORDER == LITTLE_ENDIAN 4745 uint32_t remote_n_port_id:24, 4746 :8; 4747 uint32_t relative_offset; 4748 uint32_t :2, 4749 si:1, 4750 ft:1, 4751 :2, 4752 xo:1, 4753 ls:1, 4754 df_ctl:8, 4755 type:8, 4756 r_ctl:8; 4757 uint32_t xri_tag:16, 4758 context_tag:16; 4759 uint32_t dif:2, 4760 ct:2, 4761 bs:3, 4762 :1, 4763 command:8, 4764 class:3, 4765 :1, 4766 pu:2, 4767 :2, 4768 timer:8; 4769 uint32_t abort_tag; 4770 uint32_t request_tag:16, 4771 remote_xid:16; 4772 uint32_t ebde_cnt:4, 4773 :3, 4774 len_loc:2, 4775 qosd:1, 4776 :1, 4777 xbl:1, 4778 hlm:1, 4779 iod:1, 4780 dbde:1, 4781 wqes:1, 4782 pri:3, 4783 pv:1, 4784 eat:1, 4785 xc:1, 4786 sr:1, 4787 ccpe:1, 4788 ccp:8; 4789 uint32_t cmd_type:4, 4790 :3, 4791 wqec:1, 4792 :8, 4793 cq_id:16; 4794 uint32_t sequence_payload_len; 4795 uint32_t rsvd13; 4796 uint32_t rsvd14; 4797 uint32_t rsvd15; 4798 #else 4799 #error big endian version not defined 4800 #endif 4801 } sli4_xmit_sequence64_wqe_t; 4802 4803 /** 4804 * @brief WQE used unblock the specified XRI and to release it to the SLI Port's free pool. 4805 */ 4806 typedef struct sli4_requeue_xri_wqe_s { 4807 uint32_t rsvd0; 4808 uint32_t rsvd1; 4809 uint32_t rsvd2; 4810 uint32_t rsvd3; 4811 uint32_t rsvd4; 4812 uint32_t rsvd5; 4813 #if BYTE_ORDER == LITTLE_ENDIAN 4814 uint32_t xri_tag:16, 4815 context_tag:16; 4816 uint32_t :2, 4817 ct:2, 4818 :4, 4819 command:8, 4820 class:3, 4821 :1, 4822 pu:2, 4823 :2, 4824 timer:8; 4825 uint32_t rsvd8; 4826 uint32_t request_tag:16, 4827 :16; 4828 uint32_t ebde_cnt:4, 4829 :3, 4830 len_loc:2, 4831 qosd:1, 4832 wchn:1, 4833 xbl:1, 4834 hlm:1, 4835 iod:1, 4836 dbde:1, 4837 wqes:1, 4838 pri:3, 4839 pv:1, 4840 eat:1, 4841 xc:1, 4842 :1, 4843 ccpe:1, 4844 ccp:8; 4845 uint32_t cmd_type:4, 4846 :3, 4847 wqec:1, 4848 :8, 4849 cq_id:16; 4850 uint32_t rsvd12; 4851 uint32_t rsvd13; 4852 uint32_t rsvd14; 4853 uint32_t rsvd15; 4854 #else 4855 #error big endian version not defined 4856 #endif 4857 } sli4_requeue_xri_wqe_t; 4858 4859 /** 4860 * @brief WQE used to send a single frame sequence to broadcast address 4861 */ 4862 typedef struct sli4_xmit_bcast64_wqe_s { 4863 sli4_bde_t sequence_payload; 4864 #if BYTE_ORDER == LITTLE_ENDIAN 4865 uint32_t sequence_payload_length; 4866 uint32_t rsvd4; 4867 uint32_t :8, 4868 df_ctl:8, 4869 type:8, 4870 r_ctl:8; 4871 uint32_t xri_tag:16, 4872 context_tag:16; 4873 uint32_t :2, 4874 ct:2, 4875 :4, 4876 command:8, 4877 class:3, 4878 :1, 4879 pu:2, 4880 :2, 4881 timer:8; 4882 uint32_t abort_tag; 4883 uint32_t request_tag:16, 4884 temporary_rpi:16; 4885 uint32_t ebde_cnt:4, 4886 :3, 4887 len_loc:2, 4888 qosd:1, 4889 :1, 4890 xbl:1, 4891 hlm:1, 4892 iod:1, 4893 dbde:1, 4894 wqes:1, 4895 pri:3, 4896 pv:1, 4897 eat:1, 4898 xc:1, 4899 :1, 4900 ccpe:1, 4901 ccp:8; 4902 uint32_t cmd_type:4, 4903 :3, 4904 wqec:1, 4905 :8, 4906 cq_id:16; 4907 uint32_t rsvd12; 4908 uint32_t rsvd13; 4909 uint32_t rsvd14; 4910 uint32_t rsvd15; 4911 #else 4912 #error big endian version not defined 4913 #endif 4914 } sli4_xmit_bcast64_wqe_t; 4915 4916 /** 4917 * @brief WQE used to create a BLS response. 4918 */ 4919 typedef struct sli4_xmit_bls_rsp_wqe_s { 4920 #if BYTE_ORDER == LITTLE_ENDIAN 4921 uint32_t payload_word0; 4922 uint32_t rx_id:16, 4923 ox_id:16; 4924 uint32_t high_seq_cnt:16, 4925 low_seq_cnt:16; 4926 uint32_t rsvd3; 4927 uint32_t local_n_port_id:24, 4928 :8; 4929 uint32_t remote_id:24, 4930 :6, 4931 ar:1, 4932 xo:1; 4933 uint32_t xri_tag:16, 4934 context_tag:16; 4935 uint32_t :2, 4936 ct:2, 4937 :4, 4938 command:8, 4939 class:3, 4940 :1, 4941 pu:2, 4942 :2, 4943 timer:8; 4944 uint32_t abort_tag; 4945 uint32_t request_tag:16, 4946 :16; 4947 uint32_t ebde_cnt:4, 4948 :3, 4949 len_loc:2, 4950 qosd:1, 4951 :1, 4952 xbl:1, 4953 hlm:1, 4954 iod:1, 4955 dbde:1, 4956 wqes:1, 4957 pri:3, 4958 pv:1, 4959 eat:1, 4960 xc:1, 4961 :1, 4962 ccpe:1, 4963 ccp:8; 4964 uint32_t cmd_type:4, 4965 :3, 4966 wqec:1, 4967 :8, 4968 cq_id:16; 4969 uint32_t temporary_rpi:16, 4970 :16; 4971 uint32_t rsvd13; 4972 uint32_t rsvd14; 4973 uint32_t rsvd15; 4974 #else 4975 #error big endian version not defined 4976 #endif 4977 } sli4_xmit_bls_rsp_wqe_t; 4978 4979 typedef enum { 4980 SLI_BLS_ACC, 4981 SLI_BLS_RJT, 4982 SLI_BLS_MAX 4983 } sli_bls_type_e; 4984 4985 typedef struct sli_bls_payload_s { 4986 sli_bls_type_e type; 4987 uint16_t ox_id; 4988 uint16_t rx_id; 4989 union { 4990 struct { 4991 uint32_t seq_id_validity:8, 4992 seq_id_last:8, 4993 :16; 4994 uint16_t ox_id; 4995 uint16_t rx_id; 4996 uint16_t low_seq_cnt; 4997 uint16_t high_seq_cnt; 4998 } acc; 4999 struct { 5000 uint32_t vendor_unique:8, 5001 reason_explanation:8, 5002 reason_code:8, 5003 :8; 5004 } rjt; 5005 } u; 5006 } sli_bls_payload_t; 5007 5008 /** 5009 * @brief WQE used to create an ELS response. 5010 */ 5011 typedef struct sli4_xmit_els_rsp64_wqe_s { 5012 sli4_bde_t els_response_payload; 5013 #if BYTE_ORDER == LITTLE_ENDIAN 5014 uint32_t els_response_payload_length; 5015 uint32_t s_id:24, 5016 sp:1, 5017 :7; 5018 uint32_t remote_id:24, 5019 :8; 5020 uint32_t xri_tag:16, 5021 context_tag:16; 5022 uint32_t :2, 5023 ct:2, 5024 :4, 5025 command:8, 5026 class:3, 5027 :1, 5028 pu:2, 5029 :2, 5030 timer:8; 5031 uint32_t abort_tag; 5032 uint32_t request_tag:16, 5033 ox_id:16; 5034 uint32_t ebde_cnt:4, 5035 :3, 5036 len_loc:2, 5037 qosd:1, 5038 :1, 5039 xbl:1, 5040 hlm:1, 5041 iod:1, 5042 dbde:1, 5043 wqes:1, 5044 pri:3, 5045 pv:1, 5046 eat:1, 5047 xc:1, 5048 :1, 5049 ccpe:1, 5050 ccp:8; 5051 uint32_t cmd_type:4, 5052 :3, 5053 wqec:1, 5054 :8, 5055 cq_id:16; 5056 uint32_t temporary_rpi:16, 5057 :16; 5058 uint32_t rsvd13; 5059 uint32_t rsvd14; 5060 uint32_t rsvd15; 5061 #else 5062 #error big endian version not defined 5063 #endif 5064 } sli4_xmit_els_rsp64_wqe_t; 5065 5066 /** 5067 * @brief Asynchronouse Event: Link State ACQE. 5068 */ 5069 typedef struct sli4_link_state_s { 5070 #if BYTE_ORDER == LITTLE_ENDIAN 5071 uint32_t link_number:6, 5072 link_type:2, 5073 port_link_status:8, 5074 port_duplex:8, 5075 port_speed:8; 5076 uint32_t port_fault:8, 5077 :8, 5078 logical_link_speed:16; 5079 uint32_t event_tag; 5080 uint32_t :8, 5081 event_code:8, 5082 event_type:8, /** values are protocol specific */ 5083 :6, 5084 ae:1, /** async event - this is an ACQE */ 5085 val:1; /** valid - contents of CQE are valid */ 5086 #else 5087 #error big endian version not defined 5088 #endif 5089 } sli4_link_state_t; 5090 5091 #define SLI4_LINK_ATTN_TYPE_LINK_UP 0x01 5092 #define SLI4_LINK_ATTN_TYPE_LINK_DOWN 0x02 5093 #define SLI4_LINK_ATTN_TYPE_NO_HARD_ALPA 0x03 5094 5095 #define SLI4_LINK_ATTN_P2P 0x01 5096 #define SLI4_LINK_ATTN_FC_AL 0x02 5097 #define SLI4_LINK_ATTN_INTERNAL_LOOPBACK 0x03 5098 #define SLI4_LINK_ATTN_SERDES_LOOPBACK 0x04 5099 5100 #define SLI4_LINK_ATTN_1G 0x01 5101 #define SLI4_LINK_ATTN_2G 0x02 5102 #define SLI4_LINK_ATTN_4G 0x04 5103 #define SLI4_LINK_ATTN_8G 0x08 5104 #define SLI4_LINK_ATTN_10G 0x0a 5105 #define SLI4_LINK_ATTN_16G 0x10 5106 5107 #define SLI4_LINK_TYPE_ETHERNET 0x0 5108 #define SLI4_LINK_TYPE_FC 0x1 5109 5110 /** 5111 * @brief Asynchronouse Event: FC Link Attention Event. 5112 */ 5113 typedef struct sli4_link_attention_s { 5114 #if BYTE_ORDER == LITTLE_ENDIAN 5115 uint32_t link_number:8, 5116 attn_type:8, 5117 topology:8, 5118 port_speed:8; 5119 uint32_t port_fault:8, 5120 shared_link_status:8, 5121 logical_link_speed:16; 5122 uint32_t event_tag; 5123 uint32_t :8, 5124 event_code:8, 5125 event_type:8, /** values are protocol specific */ 5126 :6, 5127 ae:1, /** async event - this is an ACQE */ 5128 val:1; /** valid - contents of CQE are valid */ 5129 #else 5130 #error big endian version not defined 5131 #endif 5132 } sli4_link_attention_t; 5133 5134 /** 5135 * @brief FC/FCoE event types. 5136 */ 5137 #define SLI4_LINK_STATE_PHYSICAL 0x00 5138 #define SLI4_LINK_STATE_LOGICAL 0x01 5139 5140 #define SLI4_FCOE_FIP_FCF_DISCOVERED 0x01 5141 #define SLI4_FCOE_FIP_FCF_TABLE_FULL 0x02 5142 #define SLI4_FCOE_FIP_FCF_DEAD 0x03 5143 #define SLI4_FCOE_FIP_FCF_CLEAR_VLINK 0x04 5144 #define SLI4_FCOE_FIP_FCF_MODIFIED 0x05 5145 5146 #define SLI4_GRP5_QOS_SPEED 0x01 5147 5148 #define SLI4_FC_EVENT_LINK_ATTENTION 0x01 5149 #define SLI4_FC_EVENT_SHARED_LINK_ATTENTION 0x02 5150 5151 #define SLI4_PORT_SPEED_NO_LINK 0x0 5152 #define SLI4_PORT_SPEED_10_MBPS 0x1 5153 #define SLI4_PORT_SPEED_100_MBPS 0x2 5154 #define SLI4_PORT_SPEED_1_GBPS 0x3 5155 #define SLI4_PORT_SPEED_10_GBPS 0x4 5156 5157 #define SLI4_PORT_DUPLEX_NONE 0x0 5158 #define SLI4_PORT_DUPLEX_HWF 0x1 5159 #define SLI4_PORT_DUPLEX_FULL 0x2 5160 5161 #define SLI4_PORT_LINK_STATUS_PHYSICAL_DOWN 0x0 5162 #define SLI4_PORT_LINK_STATUS_PHYSICAL_UP 0x1 5163 #define SLI4_PORT_LINK_STATUS_LOGICAL_DOWN 0x2 5164 #define SLI4_PORT_LINK_STATUS_LOGICAL_UP 0x3 5165 5166 /** 5167 * @brief Asynchronouse Event: FCoE/FIP ACQE. 5168 */ 5169 typedef struct sli4_fcoe_fip_s { 5170 #if BYTE_ORDER == LITTLE_ENDIAN 5171 uint32_t event_information; 5172 uint32_t fcf_count:16, 5173 fcoe_event_type:16; 5174 uint32_t event_tag; 5175 uint32_t :8, 5176 event_code:8, 5177 event_type:8, /** values are protocol specific */ 5178 :6, 5179 ae:1, /** async event - this is an ACQE */ 5180 val:1; /** valid - contents of CQE are valid */ 5181 #else 5182 #error big endian version not defined 5183 #endif 5184 } sli4_fcoe_fip_t; 5185 5186 /** 5187 * @brief FC/FCoE WQ completion queue entry. 5188 */ 5189 typedef struct sli4_fc_wcqe_s { 5190 #if BYTE_ORDER == LITTLE_ENDIAN 5191 uint32_t hw_status:8, 5192 status:8, 5193 request_tag:16; 5194 uint32_t wqe_specific_1; 5195 uint32_t wqe_specific_2; 5196 uint32_t :15, 5197 qx:1, 5198 code:8, 5199 pri:3, 5200 pv:1, 5201 xb:1, 5202 :2, 5203 vld:1; 5204 #else 5205 #error big endian version not defined 5206 #endif 5207 } sli4_fc_wcqe_t; 5208 5209 /** 5210 * @brief FC/FCoE WQ consumed CQ queue entry. 5211 */ 5212 typedef struct sli4_fc_wqec_s { 5213 #if BYTE_ORDER == LITTLE_ENDIAN 5214 uint32_t :32; 5215 uint32_t :32; 5216 uint32_t wqe_index:16, 5217 wq_id:16; 5218 uint32_t :16, 5219 code:8, 5220 :7, 5221 vld:1; 5222 #else 5223 #error big endian version not defined 5224 #endif 5225 } sli4_fc_wqec_t; 5226 5227 /** 5228 * @brief FC/FCoE Completion Status Codes. 5229 */ 5230 #define SLI4_FC_WCQE_STATUS_SUCCESS 0x00 5231 #define SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE 0x01 5232 #define SLI4_FC_WCQE_STATUS_REMOTE_STOP 0x02 5233 #define SLI4_FC_WCQE_STATUS_LOCAL_REJECT 0x03 5234 #define SLI4_FC_WCQE_STATUS_NPORT_RJT 0x04 5235 #define SLI4_FC_WCQE_STATUS_FABRIC_RJT 0x05 5236 #define SLI4_FC_WCQE_STATUS_NPORT_BSY 0x06 5237 #define SLI4_FC_WCQE_STATUS_FABRIC_BSY 0x07 5238 #define SLI4_FC_WCQE_STATUS_LS_RJT 0x09 5239 #define SLI4_FC_WCQE_STATUS_CMD_REJECT 0x0b 5240 #define SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK 0x0c 5241 #define SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 5242 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED 0x12 5243 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC 0x13 5244 #define SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE 0x14 5245 #define SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE 0x15 5246 #define SLI4_FC_WCQE_STATUS_DI_ERROR 0x16 5247 #define SLI4_FC_WCQE_STATUS_BA_RJT 0x17 5248 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED 0x18 5249 #define SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC 0x19 5250 #define SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT 0x1a 5251 #define SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST 0x1b 5252 5253 /* driver generated status codes; better not overlap with chip's status codes! */ 5254 #define SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT 0xff 5255 #define SLI4_FC_WCQE_STATUS_SHUTDOWN 0xfe 5256 #define SLI4_FC_WCQE_STATUS_DISPATCH_ERROR 0xfd 5257 5258 /** 5259 * @brief DI_ERROR Extended Status 5260 */ 5261 #define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */ 5262 #define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */ 5263 #define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */ 5264 #define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */ 5265 #define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */ 5266 #define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */ 5267 5268 /** 5269 * @brief Local Reject Reason Codes. 5270 */ 5271 #define SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE 0x01 5272 #define SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT 0x02 5273 #define SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR 0x03 5274 #define SLI4_FC_LOCAL_REJECT_INVALID_RPI 0x04 5275 #define SLI4_FC_LOCAL_REJECT_NO_XRI 0x05 5276 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND 0x06 5277 #define SLI4_FC_LOCAL_REJECT_XCHG_DROPPED 0x07 5278 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD 0x08 5279 #define SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH 0x0c 5280 #define SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED 0x0d 5281 #define SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED 0x0e 5282 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME 0x0f 5283 #define SLI4_FC_LOCAL_REJECT_NO_RESOURCES 0x11 5284 #define SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE 0x12 5285 #define SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH 0x13 5286 #define SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE 0x14 5287 #define SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS 0x15 5288 #define SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED 0x16 5289 #define SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT 0x17 5290 #define SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE 0x18 5291 #define SLI4_FC_LOCAL_REJECT_LINK_DOWN 0x1a 5292 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA 0x1b 5293 #define SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI 0x1c 5294 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_DATA 0x1d 5295 #define SLI4_FC_LOCAL_REJECT_OUT_OF_ORDER_ACK 0x1e 5296 #define SLI4_FC_LOCAL_REJECT_DUP_FRAME 0x1f 5297 #define SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME 0x20 5298 #define SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS 0x21 5299 #define SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER 0x23 5300 #define SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED 0x24 5301 #define SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED 0x25 5302 #define SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE 0x28 5303 #define SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING 0x29 5304 #define SLI4_FC_LOCAL_REJECT_INVALID_VPI 0x2e 5305 #define SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF 0x30 5306 #define SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET 0x40 5307 #define SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET 0x41 5308 #define SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE 0x42 5309 #define SLI4_FC_LOCAL_REJECT_MISSING_SI 0x43 5310 #define SLI4_FC_LOCAL_REJECT_MISSING_ES 0x44 5311 #define SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER 0x45 5312 #define SLI4_FC_LOCAL_REJECT_SLER_FAILURE 0x46 5313 #define SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE 0x47 5314 #define SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR 0x48 5315 #define SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR 0x49 5316 #define SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR 0x4a 5317 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR 0x4c 5318 #define SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR 0x4d 5319 #define SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR 0x4e 5320 5321 typedef struct sli4_fc_async_rcqe_s { 5322 #if BYTE_ORDER == LITTLE_ENDIAN 5323 uint32_t :8, 5324 status:8, 5325 rq_element_index:12, 5326 :4; 5327 uint32_t rsvd1; 5328 uint32_t fcfi:6, 5329 rq_id:10, 5330 payload_data_placement_length:16; 5331 uint32_t sof_byte:8, 5332 eof_byte:8, 5333 code:8, 5334 header_data_placement_length:6, 5335 :1, 5336 vld:1; 5337 #else 5338 #error big endian version not defined 5339 #endif 5340 } sli4_fc_async_rcqe_t; 5341 5342 typedef struct sli4_fc_async_rcqe_v1_s { 5343 #if BYTE_ORDER == LITTLE_ENDIAN 5344 uint32_t :8, 5345 status:8, 5346 rq_element_index:12, 5347 :4; 5348 uint32_t fcfi:6, 5349 :26; 5350 uint32_t rq_id:16, 5351 payload_data_placement_length:16; 5352 uint32_t sof_byte:8, 5353 eof_byte:8, 5354 code:8, 5355 header_data_placement_length:6, 5356 :1, 5357 vld:1; 5358 #else 5359 #error big endian version not defined 5360 #endif 5361 } sli4_fc_async_rcqe_v1_t; 5362 5363 #define SLI4_FC_ASYNC_RQ_SUCCESS 0x10 5364 #define SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED 0x11 5365 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED 0x12 5366 #define SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC 0x13 5367 #define SLI4_FC_ASYNC_RQ_DMA_FAILURE 0x14 5368 5369 typedef struct sli4_fc_coalescing_rcqe_s { 5370 #if BYTE_ORDER == LITTLE_ENDIAN 5371 uint32_t :8, 5372 status:8, 5373 rq_element_index:12, 5374 :4; 5375 uint32_t rsvd1; 5376 uint32_t rq_id:16, 5377 sequence_reporting_placement_length:16; 5378 uint32_t :16, 5379 code:8, 5380 :7, 5381 vld:1; 5382 #else 5383 #error big endian version not defined 5384 #endif 5385 } sli4_fc_coalescing_rcqe_t; 5386 5387 #define SLI4_FC_COALESCE_RQ_SUCCESS 0x10 5388 #define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED 0x18 5389 5390 typedef struct sli4_fc_optimized_write_cmd_cqe_s { 5391 #if BYTE_ORDER == LITTLE_ENDIAN 5392 uint32_t :8, 5393 status:8, 5394 rq_element_index:15, 5395 iv:1; 5396 uint32_t fcfi:6, 5397 :8, 5398 oox:1, 5399 agxr:1, 5400 xri:16; 5401 uint32_t rq_id:16, 5402 payload_data_placement_length:16; 5403 uint32_t rpi:16, 5404 code:8, 5405 header_data_placement_length:6, 5406 :1, 5407 vld:1; 5408 #else 5409 #error big endian version not defined 5410 #endif 5411 } sli4_fc_optimized_write_cmd_cqe_t; 5412 5413 typedef struct sli4_fc_optimized_write_data_cqe_s { 5414 #if BYTE_ORDER == LITTLE_ENDIAN 5415 uint32_t hw_status:8, 5416 status:8, 5417 xri:16; 5418 uint32_t total_data_placed; 5419 uint32_t extended_status; 5420 uint32_t :16, 5421 code:8, 5422 pri:3, 5423 pv:1, 5424 xb:1, 5425 rha:1, 5426 :1, 5427 vld:1; 5428 #else 5429 #error big endian version not defined 5430 #endif 5431 } sli4_fc_optimized_write_data_cqe_t; 5432 5433 typedef struct sli4_fc_xri_aborted_cqe_s { 5434 #if BYTE_ORDER == LITTLE_ENDIAN 5435 uint32_t :8, 5436 status:8, 5437 :16; 5438 uint32_t extended_status; 5439 uint32_t xri:16, 5440 remote_xid:16; 5441 uint32_t :16, 5442 code:8, 5443 xr:1, 5444 :3, 5445 eo:1, 5446 br:1, 5447 ia:1, 5448 vld:1; 5449 #else 5450 #error big endian version not defined 5451 #endif 5452 } sli4_fc_xri_aborted_cqe_t; 5453 5454 /** 5455 * Code definitions applicable to all FC/FCoE CQE types. 5456 */ 5457 #define SLI4_CQE_CODE_OFFSET 14 5458 5459 #define SLI4_CQE_CODE_WORK_REQUEST_COMPLETION 0x01 5460 #define SLI4_CQE_CODE_RELEASE_WQE 0x02 5461 #define SLI4_CQE_CODE_RQ_ASYNC 0x04 5462 #define SLI4_CQE_CODE_XRI_ABORTED 0x05 5463 #define SLI4_CQE_CODE_RQ_COALESCING 0x06 5464 #define SLI4_CQE_CODE_RQ_CONSUMPTION 0x07 5465 #define SLI4_CQE_CODE_MEASUREMENT_REPORTING 0x08 5466 #define SLI4_CQE_CODE_RQ_ASYNC_V1 0x09 5467 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD 0x0B 5468 #define SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA 0x0C 5469 5470 extern int32_t sli_fc_process_link_state(sli4_t *, void *); 5471 extern int32_t sli_fc_process_link_attention(sli4_t *, void *); 5472 extern int32_t sli_fc_cqe_parse(sli4_t *, sli4_queue_t *, uint8_t *, sli4_qentry_e *, uint16_t *); 5473 extern uint32_t sli_fc_response_length(sli4_t *, uint8_t *); 5474 extern uint32_t sli_fc_io_length(sli4_t *, uint8_t *); 5475 extern int32_t sli_fc_els_did(sli4_t *, uint8_t *, uint32_t *); 5476 extern uint32_t sli_fc_ext_status(sli4_t *, uint8_t *); 5477 extern int32_t sli_fc_rqe_rqid_and_index(sli4_t *, uint8_t *, uint16_t *, uint32_t *); 5478 extern int32_t sli_fc_process_fcoe(sli4_t *, void *); 5479 extern int32_t sli_cmd_fcoe_wq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5480 extern int32_t sli_cmd_fcoe_wq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t); 5481 extern int32_t sli_cmd_fcoe_wq_destroy(sli4_t *, void *, size_t, uint16_t); 5482 extern int32_t sli_cmd_fcoe_post_sgl_pages(sli4_t *, void *, size_t, uint16_t, uint32_t, ocs_dma_t **, ocs_dma_t **, 5483 ocs_dma_t *); 5484 extern int32_t sli_cmd_fcoe_rq_create(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5485 extern int32_t sli_cmd_fcoe_rq_create_v1(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t); 5486 extern int32_t sli_cmd_fcoe_rq_destroy(sli4_t *, void *, size_t, uint16_t); 5487 extern int32_t sli_cmd_fcoe_read_fcf_table(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t); 5488 extern int32_t sli_cmd_fcoe_post_hdr_templates(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, ocs_dma_t *); 5489 extern int32_t sli_cmd_fcoe_rediscover_fcf(sli4_t *, void *, size_t, uint16_t); 5490 extern int32_t sli_fc_rq_alloc(sli4_t *, sli4_queue_t *, uint32_t, uint32_t, sli4_queue_t *, uint16_t, uint8_t); 5491 extern int32_t sli_fc_rq_set_alloc(sli4_t *, uint32_t, sli4_queue_t *[], uint32_t, uint32_t, uint32_t, uint32_t, uint16_t); 5492 extern uint32_t sli_fc_get_rpi_requirements(sli4_t *, uint32_t); 5493 extern int32_t sli_abort_wqe(sli4_t *, void *, size_t, sli4_abort_type_e, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t); 5494 5495 extern int32_t sli_els_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint8_t, uint32_t, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *); 5496 extern int32_t sli_fcp_iread64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5497 extern int32_t sli_fcp_iwrite64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5498 extern int32_t sli_fcp_icmnd64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint8_t); 5499 5500 extern int32_t sli_fcp_treceive64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5501 extern int32_t sli_fcp_trsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint32_t); 5502 extern int32_t sli_fcp_tsend64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5503 extern int32_t sli_fcp_cont_treceive64_wqe(sli4_t *, void*, size_t, ocs_dma_t *, uint32_t, uint32_t, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, uint32_t, ocs_remote_node_t *, uint32_t, uint8_t, uint8_t, uint8_t, uint32_t); 5504 extern int32_t sli_gen_request64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint32_t,uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5505 extern int32_t sli_send_frame_wqe(sli4_t *sli4, void *buf, size_t size, uint8_t sof, uint8_t eof, uint32_t *hdr, 5506 ocs_dma_t *payload, uint32_t req_len, uint8_t timeout, 5507 uint16_t xri, uint16_t req_tag); 5508 extern int32_t sli_xmit_sequence64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5509 extern int32_t sli_xmit_bcast64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint8_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint8_t, uint8_t, uint8_t); 5510 extern int32_t sli_xmit_bls_rsp64_wqe(sli4_t *, void *, size_t, sli_bls_payload_t *, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t); 5511 extern int32_t sli_xmit_els_rsp64_wqe(sli4_t *, void *, size_t, ocs_dma_t *, uint32_t, uint16_t, uint16_t, uint16_t, uint16_t, ocs_remote_node_t *, uint32_t, uint32_t); 5512 extern int32_t sli_requeue_xri_wqe(sli4_t *, void *, size_t, uint16_t, uint16_t, uint16_t); 5513 extern void sli4_cmd_lowlevel_set_watchdog(sli4_t *sli4, void *buf, size_t size, uint16_t timeout); 5514 5515 /** 5516 * @ingroup sli_fc 5517 * @brief Retrieve the received header and payload length. 5518 * 5519 * @param sli4 SLI context. 5520 * @param cqe Pointer to the CQ entry. 5521 * @param len_hdr Pointer where the header length is written. 5522 * @param len_data Pointer where the payload length is written. 5523 * 5524 * @return Returns 0 on success, or a non-zero value on failure. 5525 */ 5526 static inline int32_t 5527 sli_fc_rqe_length(sli4_t *sli4, void *cqe, uint32_t *len_hdr, uint32_t *len_data) 5528 { 5529 sli4_fc_async_rcqe_t *rcqe = cqe; 5530 5531 *len_hdr = *len_data = 0; 5532 5533 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) { 5534 *len_hdr = rcqe->header_data_placement_length; 5535 *len_data = rcqe->payload_data_placement_length; 5536 return 0; 5537 } else { 5538 return -1; 5539 } 5540 } 5541 5542 /** 5543 * @ingroup sli_fc 5544 * @brief Retrieve the received FCFI. 5545 * 5546 * @param sli4 SLI context. 5547 * @param cqe Pointer to the CQ entry. 5548 * 5549 * @return Returns the FCFI in the CQE. or UINT8_MAX if invalid CQE code. 5550 */ 5551 static inline uint8_t 5552 sli_fc_rqe_fcfi(sli4_t *sli4, void *cqe) 5553 { 5554 uint8_t code = ((uint8_t*)cqe)[SLI4_CQE_CODE_OFFSET]; 5555 uint8_t fcfi = UINT8_MAX; 5556 5557 switch(code) { 5558 case SLI4_CQE_CODE_RQ_ASYNC: { 5559 sli4_fc_async_rcqe_t *rcqe = cqe; 5560 fcfi = rcqe->fcfi; 5561 break; 5562 } 5563 case SLI4_CQE_CODE_RQ_ASYNC_V1: { 5564 sli4_fc_async_rcqe_v1_t *rcqev1 = cqe; 5565 fcfi = rcqev1->fcfi; 5566 break; 5567 } 5568 case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: { 5569 sli4_fc_optimized_write_cmd_cqe_t *opt_wr = cqe; 5570 fcfi = opt_wr->fcfi; 5571 break; 5572 } 5573 } 5574 5575 return fcfi; 5576 } 5577 5578 extern const char *sli_fc_get_status_string(uint32_t status); 5579 5580 #endif /* !_SLI4_H */
Cache object: 4d1b686baaa854216a3ed1b75fa4469d
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]