The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dev/pccard/exca/excareg.h

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*      $NetBSD: i82365reg.h,v 1.3 1998/12/20 17:53:28 nathanw Exp $    */
    2 /* $FreeBSD: src/sys/dev/exca/excareg.h,v 1.5 2005/01/06 01:42:40 imp Exp $ */
    3 
    4 /*-
    5  * Copyright (c) 2002 M Warner Losh.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   26  *
   27  * This software may be derived from NetBSD i82365.c and other files with
   28  * the following copyright:
   29  *
   30  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
   31  *
   32  * Redistribution and use in source and binary forms, with or without
   33  * modification, are permitted provided that the following conditions
   34  * are met:
   35  * 1. Redistributions of source code must retain the above copyright
   36  *    notice, this list of conditions and the following disclaimer.
   37  * 2. Redistributions in binary form must reproduce the above copyright
   38  *    notice, this list of conditions and the following disclaimer in the
   39  *    documentation and/or other materials provided with the distribution.
   40  * 3. All advertising materials mentioning features or use of this software
   41  *    must display the following acknowledgement:
   42  *      This product includes software developed by Marc Horowitz.
   43  * 4. The name of the author may not be used to endorse or promote products
   44  *    derived from this software without specific prior written permission.
   45  *
   46  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   47  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   48  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   49  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   50  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   51  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   52  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   53  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   54  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   55  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   56  */
   57 
   58 #ifndef _SYS_DEV_EXCA_EXCAREG_H
   59 #define _SYS_DEV_EXCA_EXCAREG_H
   60 
   61 /*
   62  * All information is from the intel 82365sl PC Card Interface Controller
   63  * (PCIC) data sheet, marked "preliminary".  Order number 290423-002, January
   64  * 1993.
   65  */
   66 
   67 #define EXCA_IOSIZE             2
   68 
   69 #define EXCA_REG_INDEX          0
   70 #define EXCA_REG_DATA           1
   71 
   72 #define EXCA_NSLOTS             4       /* 2 in 2 chips */
   73 
   74 /*
   75  * I/o ports
   76  */
   77 #define EXCA_INDEX0             0x3e0
   78 
   79 /*
   80  * The PCIC allows two chips to share the same address.  In order not to run
   81  * afoul of the bsd device model, this driver will treat those chips as
   82  * the same device.
   83  */
   84 
   85 #define EXCA_CHIP0_BASE         0x00
   86 #define EXCA_CHIP1_BASE         0x80
   87 
   88 /* Each PCIC chip can drive two sockets */
   89 
   90 #define EXCA_SOCKET_SIZE        0x40
   91 #define EXCA_SOCKETA_INDEX      0x00
   92 #define EXCA_SOCKETB_INDEX      EXCA_SOCKET_SIZE
   93 
   94 /* general setup registers */
   95 
   96 #define EXCA_IDENT                              0x00    /* RO */
   97 #define EXCA_IDENT_IFTYPE_MASK                  0xC0
   98 #define EXCA_IDENT_IFTYPE_IO_ONLY               0x00
   99 #define EXCA_IDENT_IFTYPE_MEM_ONLY              0x40
  100 #define EXCA_IDENT_IFTYPE_MEM_AND_IO            0x80
  101 #define EXCA_IDENT_IFTYPE_RESERVED              0xC0
  102 #define EXCA_IDENT_ZERO                         0x30
  103 #define EXCA_IDENT_REV_MASK                     0x0F
  104 #define EXCA_IDENT_REV_I82365SLR0               0x02    /* step a/b */
  105 #define EXCA_IDENT_REV_I82365SLR1               0x03    /* step c */
  106 #define EXCA_IDENT_REV_I82365SLDF               0x04    /* step df */
  107 #define EXCA_IDENT_REV_IBM1                     0x08    /* ibm clone */
  108 #define EXCA_IDENT_REV_IBM2                     0x09    /* ibm clone */
  109 #define EXCA_IDENT_REV_IBM_KING                 0x0a    /* ibm king */
  110 
  111 #define EXCA_IF_STATUS                          0x01    /* RO */
  112 #define EXCA_IF_STATUS_GPI                      0x80 /* General Purpose Input */
  113 #define EXCA_IF_STATUS_POWERACTIVE              0x40
  114 #define EXCA_IF_STATUS_READY                    0x20 /* really READY/!BUSY */
  115 #define EXCA_IF_STATUS_MEM_WP                   0x10
  116 #define EXCA_IF_STATUS_CARDDETECT_MASK          0x0C
  117 #define EXCA_IF_STATUS_CARDDETECT_PRESENT       0x0C
  118 #define EXCA_IF_STATUS_BATTERY_MASK             0x03
  119 #define EXCA_IF_STATUS_BATTERY_DEAD1            0x00
  120 #define EXCA_IF_STATUS_BATTERY_DEAD2            0x01
  121 #define EXCA_IF_STATUS_BATTERY_WARNING          0x02
  122 #define EXCA_IF_STATUS_BATTERY_GOOD             0x03
  123 
  124 #define EXCA_PWRCTL                             0x02    /* RW */
  125 #define EXCA_PWRCTL_OE                          0x80    /* output enable */
  126 #define EXCA_PWRCTL_DISABLE_RESETDRV            0x40
  127 #define EXCA_PWRCTL_AUTOSWITCH_ENABLE           0x20
  128 #define EXCA_PWRCTL_PWR_ENABLE                  0x10
  129 #define EXCA_PWRCTL_VPP2_MASK                   0x0C
  130 /* XXX these are a little unclear from the data sheet */
  131 #define EXCA_PWRCTL_VPP2_RESERVED               0x0C
  132 #define EXCA_PWRCTL_VPP2_EN1                    0x08
  133 #define EXCA_PWRCTL_VPP2_EN0                    0x04
  134 #define EXCA_PWRCTL_VPP2_ENX                    0x00
  135 #define EXCA_PWRCTL_VPP1_MASK                   0x03
  136 /* XXX these are a little unclear from the data sheet */
  137 #define EXCA_PWRCTL_VPP1_RESERVED               0x03
  138 #define EXCA_PWRCTL_VPP1_EN1                    0x02
  139 #define EXCA_PWRCTL_VPP1_EN0                    0x01
  140 #define EXCA_PWRCTL_VPP1_ENX                    0x00
  141 
  142 #define EXCA_CSC                                0x04    /* RW */
  143 #define EXCA_CSC_ZERO                           0xE0
  144 #define EXCA_CSC_GPI                            0x10
  145 #define EXCA_CSC_CD                             0x08 /* Card Detect Change */
  146 #define EXCA_CSC_READY                          0x04
  147 #define EXCA_CSC_BATTWARN                       0x02
  148 #define EXCA_CSC_BATTDEAD                       0x01    /* for memory cards */
  149 #define EXCA_CSC_RI                             0x01    /* for i/o cards */
  150 
  151 #define EXCA_ADDRWIN_ENABLE                     0x06    /* RW */
  152 #define EXCA_ADDRWIN_ENABLE_IO1                 0x80
  153 #define EXCA_ADDRWIN_ENABLE_IO0                 0x40
  154 #define EXCA_ADDRWIN_ENABLE_MEMCS16             0x20    /* rtfds if you care */
  155 #define EXCA_ADDRWIN_ENABLE_MEM4                0x10
  156 #define EXCA_ADDRWIN_ENABLE_MEM3                0x08
  157 #define EXCA_ADDRWIN_ENABLE_MEM2                0x04
  158 #define EXCA_ADDRWIN_ENABLE_MEM1                0x02
  159 #define EXCA_ADDRWIN_ENABLE_MEM0                0x01
  160 
  161 #define EXCA_CARD_DETECT                        0x16    /* RW */
  162 #define EXCA_CARD_DETECT_RESERVED               0xC0
  163 #define EXCA_CARD_DETECT_SW_INTR                0x20
  164 #define EXCA_CARD_DETECT_RESUME_ENABLE          0x10
  165 #define EXCA_CARD_DETECT_GPI_TRANSCTL           0x08
  166 #define EXCA_CARD_DETECT_GPI_ENABLE             0x04
  167 #define EXCA_CARD_DETECT_CFGRST_ENABLE          0x02
  168 #define EXCA_CARD_DETECT_MEMDLY_INHIBIT         0x01
  169 
  170 /* interrupt registers */
  171 
  172 #define EXCA_INTR                               0x03    /* RW */
  173 #define EXCA_INTR_RI_ENABLE                     0x80
  174 #define EXCA_INTR_RESET                         0x40    /* active low (zero) */
  175 #define EXCA_INTR_CARDTYPE_MASK                 0x20
  176 #define EXCA_INTR_CARDTYPE_IO                   0x20
  177 #define EXCA_INTR_CARDTYPE_MEM                  0x00
  178 #define EXCA_INTR_ENABLE                        0x10
  179 #define EXCA_INTR_IRQ_MASK                      0x0F
  180 #define EXCA_INTR_IRQ_SHIFT                     0
  181 #define EXCA_INTR_IRQ_NONE                      0x00
  182 #define EXCA_INTR_IRQ_RESERVED1                 0x01
  183 #define EXCA_INTR_IRQ_RESERVED2                 0x02
  184 #define EXCA_INTR_IRQ3                          0x03
  185 #define EXCA_INTR_IRQ4                          0x04
  186 #define EXCA_INTR_IRQ5                          0x05
  187 #define EXCA_INTR_IRQ_RESERVED6                 0x06
  188 #define EXCA_INTR_IRQ7                          0x07
  189 #define EXCA_INTR_IRQ_RESERVED8                 0x08
  190 #define EXCA_INTR_IRQ9                          0x09
  191 #define EXCA_INTR_IRQ10                         0x0A
  192 #define EXCA_INTR_IRQ11                         0x0B
  193 #define EXCA_INTR_IRQ12                         0x0C
  194 #define EXCA_INTR_IRQ_RESERVED13                0x0D
  195 #define EXCA_INTR_IRQ14                         0x0E
  196 #define EXCA_INTR_IRQ15                         0x0F
  197 
  198 #define EXCA_INTR_IRQ_VALIDMASK                 0xDEB8 /* 1101 1110 1011 1000 */
  199 
  200 #define EXCA_CSC_INTR                           0x05    /* RW */
  201 #define EXCA_CSC_INTR_IRQ_MASK                  0xF0
  202 #define EXCA_CSC_INTR_IRQ_SHIFT                 4
  203 #define EXCA_CSC_INTR_IRQ_NONE                  0x00
  204 #define EXCA_CSC_INTR_IRQ_RESERVED1             0x10
  205 #define EXCA_CSC_INTR_IRQ_RESERVED2             0x20
  206 #define EXCA_CSC_INTR_IRQ3                      0x30
  207 #define EXCA_CSC_INTR_IRQ4                      0x40
  208 #define EXCA_CSC_INTR_IRQ5                      0x50
  209 #define EXCA_CSC_INTR_IRQ_RESERVED6             0x60
  210 #define EXCA_CSC_INTR_IRQ7                      0x70
  211 #define EXCA_CSC_INTR_IRQ_RESERVED8             0x80
  212 #define EXCA_CSC_INTR_IRQ9                      0x90
  213 #define EXCA_CSC_INTR_IRQ10                     0xA0
  214 #define EXCA_CSC_INTR_IRQ11                     0xB0
  215 #define EXCA_CSC_INTR_IRQ12                     0xC0
  216 #define EXCA_CSC_INTR_IRQ_RESERVED13            0xD0
  217 #define EXCA_CSC_INTR_IRQ14                     0xE0
  218 #define EXCA_CSC_INTR_IRQ15                     0xF0
  219 #define EXCA_CSC_INTR_CD_ENABLE                 0x08
  220 #define EXCA_CSC_INTR_READY_ENABLE              0x04
  221 #define EXCA_CSC_INTR_BATTWARN_ENABLE           0x02
  222 #define EXCA_CSC_INTR_BATTDEAD_ENABLE           0x01    /* for memory cards */
  223 #define EXCA_CSC_INTR_RI_ENABLE                 0x01    /* for I/O cards */
  224 
  225 #define EXCA_CSC_INTR_IRQ_VALIDMASK             0xDEB8 /* 1101 1110 1011 1000 */
  226 
  227 /* I/O registers */
  228 
  229 #define EXCA_IO_WINS                            2
  230 
  231 #define EXCA_IOCTL                              0x07    /* RW */
  232 #define EXCA_IOCTL_IO1_WAITSTATE                0x80
  233 #define EXCA_IOCTL_IO1_ZEROWAIT                 0x40
  234 #define EXCA_IOCTL_IO1_IOCS16SRC_MASK           0x20
  235 #define EXCA_IOCTL_IO1_IOCS16SRC_CARD           0x20
  236 #define EXCA_IOCTL_IO1_IOCS16SRC_DATASIZE       0x00
  237 #define EXCA_IOCTL_IO1_DATASIZE_MASK            0x10
  238 #define EXCA_IOCTL_IO1_DATASIZE_16BIT           0x10
  239 #define EXCA_IOCTL_IO1_DATASIZE_8BIT            0x00
  240 #define EXCA_IOCTL_IO0_WAITSTATE                0x08
  241 #define EXCA_IOCTL_IO0_ZEROWAIT                 0x04
  242 #define EXCA_IOCTL_IO0_IOCS16SRC_MASK           0x02
  243 #define EXCA_IOCTL_IO0_IOCS16SRC_CARD           0x02
  244 #define EXCA_IOCTL_IO0_IOCS16SRC_DATASIZE       0x00
  245 #define EXCA_IOCTL_IO0_DATASIZE_MASK            0x01
  246 #define EXCA_IOCTL_IO0_DATASIZE_16BIT           0x01
  247 #define EXCA_IOCTL_IO0_DATASIZE_8BIT            0x00
  248 
  249 #define EXCA_IOADDR0_START_LSB                  0x08
  250 #define EXCA_IOADDR0_START_MSB                  0x09
  251 #define EXCA_IOADDR0_STOP_LSB                   0x0A
  252 #define EXCA_IOADDR0_STOP_MSB                   0x0B
  253 #define EXCA_IOADDR1_START_LSB                  0x0C
  254 #define EXCA_IOADDR1_START_MSB                  0x0D
  255 #define EXCA_IOADDR1_STOP_LSB                   0x0E
  256 #define EXCA_IOADDR1_STOP_MSB                   0x0F
  257 
  258 /* memory registers */
  259 
  260 /*
  261  * memory window addresses refer to bits A23-A12 of the ISA system memory
  262  * address.  This is a shift of 12 bits.  The LSB contains A19-A12, and the
  263  * MSB contains A23-A20, plus some other bits.
  264  */
  265 
  266 #define EXCA_MEM_WINS                           5
  267 
  268 #define EXCA_MEM_SHIFT                          12
  269 #define EXCA_MEM_PAGESIZE                       (1<<EXCA_MEM_SHIFT)
  270 
  271 #define EXCA_SYSMEM_ADDRX_SHIFT                         EXCA_MEM_SHIFT
  272 #define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK       0x80
  273 #define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT      0x80
  274 #define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT       0x00
  275 #define EXCA_SYSMEM_ADDRX_START_MSB_ZEROWAIT            0x40
  276 #define EXCA_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK        0x30
  277 #define EXCA_SYSMEM_ADDRX_START_MSB_ADDR_MASK           0x0F
  278 
  279 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK            0xC0
  280 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT0                0x00
  281 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT1                0x40
  282 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT2                0x80
  283 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT3                0xC0
  284 #define EXCA_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK            0x0F
  285 
  286 /*
  287  * The card side of a memory mapping consists of bits A19-A12 of the card
  288  * memory address in the LSB, and A25-A20 plus some other bits in the MSB.
  289  * Again, the shift is 12 bits.
  290  */
  291 
  292 #define EXCA_CARDMEM_ADDRX_SHIFT                EXCA_MEM_SHIFT
  293 #define EXCA_CARDMEM_ADDRX_MSB_WP               0x80
  294 #define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_MASK   0x40
  295 #define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR   0x40
  296 #define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00
  297 #define EXCA_CARDMEM_ADDRX_MSB_ADDR_MASK        0x3F
  298 
  299 #define EXCA_SYSMEM_ADDR0_START_LSB             0x10
  300 #define EXCA_SYSMEM_ADDR0_START_MSB             0x11
  301 #define EXCA_SYSMEM_ADDR0_STOP_LSB              0x12
  302 #define EXCA_SYSMEM_ADDR0_STOP_MSB              0x13
  303 
  304 #define EXCA_CARDMEM_ADDR0_LSB                  0x14
  305 #define EXCA_CARDMEM_ADDR0_MSB                  0x15
  306 
  307 /* #define      EXCA_RESERVED                   0x17 */
  308 
  309 #define EXCA_SYSMEM_ADDR1_START_LSB             0x18
  310 #define EXCA_SYSMEM_ADDR1_START_MSB             0x19
  311 #define EXCA_SYSMEM_ADDR1_STOP_LSB              0x1A
  312 #define EXCA_SYSMEM_ADDR1_STOP_MSB              0x1B
  313 
  314 #define EXCA_CARDMEM_ADDR1_LSB                  0x1C
  315 #define EXCA_CARDMEM_ADDR1_MSB                  0x1D
  316 
  317 #define EXCA_SYSMEM_ADDR2_START_LSB             0x20
  318 #define EXCA_SYSMEM_ADDR2_START_MSB             0x21
  319 #define EXCA_SYSMEM_ADDR2_STOP_LSB              0x22
  320 #define EXCA_SYSMEM_ADDR2_STOP_MSB              0x23
  321 
  322 #define EXCA_CARDMEM_ADDR2_LSB                  0x24
  323 #define EXCA_CARDMEM_ADDR2_MSB                  0x25
  324 
  325 /* #define      EXCA_RESERVED                   0x26 */
  326 /* #define      EXCA_RESERVED                   0x27 */
  327 
  328 #define EXCA_SYSMEM_ADDR3_START_LSB             0x28
  329 #define EXCA_SYSMEM_ADDR3_START_MSB             0x29
  330 #define EXCA_SYSMEM_ADDR3_STOP_LSB              0x2A
  331 #define EXCA_SYSMEM_ADDR3_STOP_MSB              0x2B
  332 
  333 #define EXCA_CARDMEM_ADDR3_LSB                  0x2C
  334 #define EXCA_CARDMEM_ADDR3_MSB                  0x2D
  335 
  336 /* #define      EXCA_RESERVED                   0x2E */
  337 /* #define      EXCA_RESERVED                   0x2F */
  338 
  339 #define EXCA_SYSMEM_ADDR4_START_LSB             0x30
  340 #define EXCA_SYSMEM_ADDR4_START_MSB             0x31
  341 #define EXCA_SYSMEM_ADDR4_STOP_LSB              0x32
  342 #define EXCA_SYSMEM_ADDR4_STOP_MSB              0x33
  343 
  344 #define EXCA_CARDMEM_ADDR4_LSB                  0x34
  345 #define EXCA_CARDMEM_ADDR4_MSB                  0x35
  346 
  347 /* #define      EXCA_RESERVED                   0x36 */
  348 /* #define      EXCA_RESERVED                   0x37 */
  349 /* #define      EXCA_RESERVED                   0x38 */
  350 /* #define      EXCA_RESERVED                   0x39 */
  351 /* #define      EXCA_RESERVED                   0x3A */
  352 /* #define      EXCA_RESERVED                   0x3B */
  353 /* #define      EXCA_RESERVED                   0x3C */
  354 /* #define      EXCA_RESERVED                   0x3D */
  355 /* #define      EXCA_RESERVED                   0x3E */
  356 /* #define      EXCA_RESERVED                   0x3F */
  357 
  358 /* cardbus extensions - memory window page registers */
  359 
  360 #define EXCA_MEMREG_WIN_SHIFT                   24
  361 #define EXCA_SYSMEM_ADDR0_WIN                   0x40
  362 #define EXCA_SYSMEM_ADDR1_WIN                   0x41
  363 #define EXCA_SYSMEM_ADDR2_WIN                   0x42
  364 #define EXCA_SYSMEM_ADDR3_WIN                   0x43
  365 #define EXCA_SYSMEM_ADDR4_WIN                   0x44
  366 
  367 /* vendor-specific registers */
  368 
  369 #define EXCA_INTEL_GLOBAL_CTL                   0x1E    /* RW */
  370 #define EXCA_INTEL_GLOBAL_CTL_RESERVED          0xF0
  371 #define EXCA_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08
  372 #define EXCA_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK  0x04
  373 #define EXCA_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE   0x02
  374 #define EXCA_INTEL_GLOBAL_CTL_POWERDOWN         0x01
  375 
  376 #define EXCA_CIRRUS_MISC_CTL_2                  0x1E
  377 #define EXCA_CIRRUS_MISC_CTL_2_SUSPEND          0x04
  378 
  379 #define EXCA_CIRRUS_CHIP_INFO                   0x1F
  380 #define EXCA_CIRRUS_CHIP_INFO_CHIP_ID           0xC0
  381 #define EXCA_CIRRUS_CHIP_INFO_SLOTS             0x20
  382 #define EXCA_CIRRUS_CHIP_INFO_REV               0x1F
  383 
  384 #define EXCA_CIRRUS_EXTENDED_INDEX              0x2E
  385 #define EXCA_CIRRUS_EXTENDED_DATA               0x2F
  386 #define EXCA_CIRRUS_EXT_CONTROL_1               0x03
  387 #define EXCA_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
  388 
  389 #define EXCA_VADEM_VMISC                        0x3a
  390 #define EXCA_VADEM_REV                          0x40
  391 #define EXCA_VADEM_COOKIE1                      0x0E
  392 #define EXCA_VADEM_COOKIE2                      0x37
  393 
  394 #define EXCA_RICOH_ID                           0x3a
  395 #define EXCA_RID_296                            0x32
  396 #define EXCA_RID_396                            0xb2
  397 
  398 /*
  399  * o2 micro specific registers
  400  */
  401 #define EXCA_O2MICRO_CTRL_C                     0x3a
  402 #define EXCA_O2CC_IREQ_INTC                     0x80
  403 #define EXCA_O2CC_STSCHG_INTC                   0x20
  404 
  405 /* Plug and play */
  406 #define EXCA_PNP_ACTIONTEC      0x1802A904      /* AEI0218 */
  407 #define EXCA_PNP_IBM3765        0x65374d24      /* IBM3765 */
  408 #define EXCA_PNP_82365          0x000ED041      /* PNP0E00 */
  409 #define EXCA_PNP_CL_PD6720      0x010ED041      /* PNP0E01 */
  410 #define EXCA_PNP_VLSI_82C146    0x020ED041      /* PNP0E02 */
  411 #define EXCA_PNP_82365_CARDBUS  0x030ED041      /* PNP0E03 */
  412 #define EXCA_PNP_SCM_SWAPBOX    0x69046d4c      /* SMC0469 */
  413 
  414 /*
  415  *      Mask of allowable interrupts.
  416  *
  417  *      For IBM-AT machines, irqs 3, 4, 5, 7, 9, 10, 11, 12, 14, 15 are
  418  *      allowed.  Nearly all IBM-AT machines with pcic cards or bridges
  419  *      wire these interrupts (or a subset thereof) to the corresponding
  420  *      pins on the ISA bus.  Some older laptops are reported to not route
  421  *      all the interrupt pins to the bus because the designers knew that
  422  *      some would conflict with builtin devices.  Older versions of Windows
  423  *      NT had a special device that would probe for conflicts early in the
  424  *      boot process and formulate a mapping table.  Maybe we should do
  425  *      something similar.
  426  *
  427  *      For NEC PC-98 machines, irq 3, 5, 6, 9, 10, 11, 12, 13 are allowed.
  428  *      These correspond to the C-BUS signals INT 0, 1, 2, 3, 41, 42, 5, 6
  429  *      respectively.
  430  *
  431  *      Hiroshi TSUKADA-san writes in FreeBSD98-testers that CBUS INT 2
  432  *      (mapped to IRQ 6) is routed to the IRQ 7 pin of the pcic in pc98
  433  *      cbus add-in cards.  He has confirmed this routing with a visual
  434  *      inspection of his card or a VOM.
  435  */
  436 #define EXCA_INT_MASK_ALLOWED   0xDEB8          /* AT */
  437 
  438 #endif /* !_SYS_DEV_EXCA_EXCAREG_H */

Cache object: f61c5a9cae18e67e97d3a27f4ee9e59e


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.