The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/pcf/pcfvar.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 1998 Nicolas Souchu, Marc Bouget
    5  * Copyright (c) 2004 Joerg Wunsch
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD$
   30  */
   31 
   32 #ifndef __PCFVAR_H__
   33 #define __PCFVAR_H__
   34 
   35 #define IO_PCFSIZE      2
   36 
   37 #define TIMEOUT 9999                                    /* XXX */
   38 
   39 /* Status bits of S1 register (read only) */
   40 #define nBB     0x01            /* busy when low set/reset by STOP/START*/
   41 #define LAB     0x02            /* lost arbitration bit in multi-master mode */
   42 #define AAS     0x04            /* addressed as slave */
   43 #define LRB     0x08            /* last received byte when not AAS */
   44 #define AD0     0x08            /* general call received when AAS */
   45 #define BER     0x10            /* bus error, misplaced START or STOP */
   46 #define STS     0x20            /* STOP detected in slave receiver mode */
   47 #define PIN     0x80            /* pending interrupt not (r/w) */
   48 
   49 /* Control bits of S1 register (write only) */
   50 #define ACK     0x01
   51 #define STO     0x02
   52 #define STA     0x04
   53 #define ENI     0x08
   54 #define ES2     0x10
   55 #define ES1     0x20
   56 #define ESO     0x40
   57 
   58 #define BUFSIZE 2048
   59 
   60 #define SLAVE_TRANSMITTER       0x1
   61 #define SLAVE_RECEIVER          0x2
   62 
   63 #define PCF_DEFAULT_ADDR        0xaa
   64 
   65 struct pcf_softc {
   66         u_char  pcf_addr;               /* interface I2C address */
   67         int     pcf_flags;              /* IIC_POLLED? */
   68         int     pcf_slave_mode;         /* receiver or transmitter */
   69         int     pcf_started;            /* 1 if start condition sent */
   70 
   71         struct mtx pcf_lock;
   72         device_t iicbus;                /* the corresponding iicbus */
   73 
   74         /* Resource handling stuff. */
   75         struct resource         *res_ioport;
   76         int                     rid_ioport;
   77         struct resource         *res_irq;
   78         int                     rid_irq;
   79         void                    *intr_cookie;
   80 };
   81 #define DEVTOSOFTC(dev) ((struct pcf_softc *)device_get_softc(dev))
   82 
   83 #define PCF_LOCK(sc)            mtx_lock(&(sc)->pcf_lock)
   84 #define PCF_UNLOCK(sc)          mtx_unlock(&(sc)->pcf_lock)
   85 #define PCF_ASSERT_LOCKED(sc)   mtx_assert(&(sc)->pcf_lock, MA_OWNED)
   86 
   87 /*
   88  * PCF8584 datasheet : when operate at 8 MHz or more, a minimun time of
   89  * 6 clocks cycles must be left between two consecutives access
   90  */
   91 #define pcf_nops()      DELAY(10)
   92 
   93 #define dummy_read(sc)  pcf_get_S0(sc)
   94 #define dummy_write(sc) pcf_set_S0(sc, 0)
   95 
   96 /*
   97  * Specific register access to PCF8584
   98  */
   99 static __inline void
  100 pcf_set_S0(struct pcf_softc *sc, int data)
  101 {
  102 
  103         bus_write_1(sc->res_ioport, 0, data);
  104         pcf_nops();
  105 }
  106 
  107 static __inline void
  108 pcf_set_S1(struct pcf_softc *sc, int data)
  109 {
  110 
  111         bus_write_1(sc->res_ioport, 1, data);
  112         pcf_nops();
  113 }
  114 
  115 static __inline char
  116 pcf_get_S0(struct pcf_softc *sc)
  117 {
  118         char data;
  119 
  120         data = bus_read_1(sc->res_ioport, 0);
  121         pcf_nops();
  122 
  123         return (data);
  124 }
  125 
  126 static __inline char
  127 pcf_get_S1(struct pcf_softc *sc)
  128 {
  129         char data;
  130 
  131         data = bus_read_1(sc->res_ioport, 1);
  132         pcf_nops();
  133 
  134         return (data);
  135 }
  136 
  137 extern int pcf_repeated_start(device_t, u_char, int);
  138 extern int pcf_start(device_t, u_char, int);
  139 extern int pcf_stop(device_t);
  140 extern int pcf_write(device_t, const char *, int, int *, int);
  141 extern int pcf_read(device_t, char *, int, int *, int, int);
  142 extern int pcf_rst_card(device_t, u_char, u_char, u_char *);
  143 extern driver_intr_t pcf_intr;
  144 
  145 #define PCF_MODVER      1
  146 #define PCF_MINVER      1
  147 #define PCF_MAXVER      1
  148 #define PCF_PREFVER     PCF_MODVER
  149 
  150 #endif /* !__PCFVAR_H__ */

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