agp_intel.c

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    1 /*      $NetBSD: agp_intel.c,v 1.14 2003/08/26 18:43:54 tron Exp $      */
    2 
    3 /*-
    4  * Copyright (c) 2000 Doug Rabson
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  *      $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $
   29  */
   30 
   31 #include <sys/cdefs.h>
   32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.14 2003/08/26 18:43:54 tron Exp $");
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/malloc.h>
   37 #include <sys/kernel.h>
   38 #include <sys/lock.h>
   39 #include <sys/proc.h>
   40 #include <sys/agpio.h>
   41 #include <sys/device.h>
   42 #include <sys/agpio.h>
   43 
   44 #include <uvm/uvm_extern.h>
   45 
   46 #include <dev/pci/pcivar.h>
   47 #include <dev/pci/pcireg.h>
   48 #include <dev/pci/pcidevs.h>
   49 #include <dev/pci/agpvar.h>
   50 #include <dev/pci/agpreg.h>
   51 
   52 #include <machine/bus.h>
   53 
   54 struct agp_intel_softc {
   55         u_int32_t               initial_aperture;
   56                                         /* aperture size at startup */
   57         struct agp_gatt         *gatt;
   58         struct pci_attach_args  vga_pa;
   59         u_int                   aperture_mask;
   60         int                     chiptype; /* Chip type */
   61 #define CHIP_INTEL      0x0
   62 #define CHIP_I443       0x1
   63 #define CHIP_I840       0x2
   64 #define CHIP_I845       0x3
   65 #define CHIP_I850       0x4
   66 #define CHIP_I865       0x5
   67 };
   68 
   69 static u_int32_t agp_intel_get_aperture(struct agp_softc *);
   70 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t);
   71 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t);
   72 static int agp_intel_unbind_page(struct agp_softc *, off_t);
   73 static void agp_intel_flush_tlb(struct agp_softc *);
   74 
   75 struct agp_methods agp_intel_methods = {
   76         agp_intel_get_aperture,
   77         agp_intel_set_aperture,
   78         agp_intel_bind_page,
   79         agp_intel_unbind_page,
   80         agp_intel_flush_tlb,
   81         agp_generic_enable,
   82         agp_generic_alloc_memory,
   83         agp_generic_free_memory,
   84         agp_generic_bind_memory,
   85         agp_generic_unbind_memory,
   86 };
   87 
   88 static int
   89 agp_intel_vgamatch(struct pci_attach_args *pa)
   90 {
   91         switch (PCI_PRODUCT(pa->pa_id)) {
   92         case PCI_PRODUCT_INTEL_82855PM_AGP:
   93         case PCI_PRODUCT_INTEL_82443LX_AGP:
   94         case PCI_PRODUCT_INTEL_82443BX_AGP:
   95         case PCI_PRODUCT_INTEL_82443GX_AGP:
   96         case PCI_PRODUCT_INTEL_82850_AGP:       /* i850/i860 */
   97         case PCI_PRODUCT_INTEL_82845_AGP:
   98         case PCI_PRODUCT_INTEL_82840_AGP:
   99         case PCI_PRODUCT_INTEL_82865_AGP:
  100         case PCI_PRODUCT_INTEL_82875P_AGP:
  101                 return (1);
  102         }
  103 
  104         return (0);
  105 }
  106 
  107 int
  108 agp_intel_attach(struct device *parent, struct device *self, void *aux)
  109 {
  110         struct agp_softc *sc = (struct agp_softc *)self;
  111         struct pci_attach_args *pa= aux;
  112         struct agp_intel_softc *isc;
  113         struct agp_gatt *gatt;
  114         pcireg_t reg;
  115         u_int32_t value;
  116 
  117         isc = malloc(sizeof *isc, M_AGP, M_NOWAIT|M_ZERO);
  118         if (isc == NULL) {
  119                 aprint_error(": can't allocate chipset-specific softc\n");
  120                 return ENOMEM;
  121         }
  122 
  123         sc->as_methods = &agp_intel_methods;
  124         sc->as_chipc = isc;
  125 
  126         if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) {
  127                 aprint_normal(": using generic initialization for Intel AGP\n");
  128                 aprint_normal("%s", sc->as_dev.dv_xname);
  129                 isc->chiptype = CHIP_INTEL;
  130         }
  131 
  132         pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
  133             NULL);
  134 
  135         if (agp_map_aperture(pa, sc) != 0) {
  136                 aprint_error(": can't map aperture\n");
  137                 free(isc, M_AGP);
  138                 sc->as_chipc = NULL;
  139                 return ENXIO;
  140         }
  141 
  142         switch (PCI_PRODUCT(isc->vga_pa.pa_id)) {
  143         case PCI_PRODUCT_INTEL_82443LX_AGP:
  144         case PCI_PRODUCT_INTEL_82443BX_AGP:
  145         case PCI_PRODUCT_INTEL_82443GX_AGP:
  146                 isc->chiptype = CHIP_I443;
  147                 break;
  148         case PCI_PRODUCT_INTEL_82840_AGP:
  149                 isc->chiptype = CHIP_I840;
  150                 break;
  151         case PCI_PRODUCT_INTEL_82855PM_AGP:
  152         case PCI_PRODUCT_INTEL_82845_AGP:
  153                 isc->chiptype = CHIP_I845;
  154                 break;
  155         case PCI_PRODUCT_INTEL_82850_AGP:
  156                 isc->chiptype = CHIP_I850;
  157                 break;
  158         case PCI_PRODUCT_INTEL_82865_AGP:
  159         case PCI_PRODUCT_INTEL_82875P_AGP:
  160                 isc->chiptype = CHIP_I865;
  161                 break;
  162         }
  163 
  164         /* Determine maximum supported aperture size. */
  165         value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE);
  166         pci_conf_write(sc->as_pc, sc->as_tag,
  167                 AGP_INTEL_APSIZE, APSIZE_MASK);
  168         isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag,
  169                 AGP_INTEL_APSIZE) & APSIZE_MASK;
  170         pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value);
  171         isc->initial_aperture = AGP_GET_APERTURE(sc);
  172 
  173         for (;;) {
  174                 gatt = agp_alloc_gatt(sc);
  175                 if (gatt)
  176                         break;
  177 
  178                 /*
  179                  * Probably contigmalloc failure. Try reducing the
  180                  * aperture so that the gatt size reduces.
  181                  */
  182                 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
  183                         agp_generic_detach(sc);
  184                         aprint_error(": failed to set aperture\n");
  185                         return ENOMEM;
  186                 }
  187         }
  188         isc->gatt = gatt;
  189 
  190         /* Install the gatt. */
  191         pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE,
  192             gatt->ag_physical);
  193 
  194         /* Enable the GLTB and setup the control register. */
  195         switch (isc->chiptype) {
  196         case CHIP_I443:
  197                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
  198                     AGPCTRL_AGPRSE | AGPCTRL_GTLB);
  199 
  200         default:
  201                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
  202                     pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL)
  203                         | AGPCTRL_GTLB);
  204         }
  205 
  206         /* Enable things, clear errors etc. */
  207         switch (isc->chiptype) {
  208         case CHIP_I845:
  209         case CHIP_I865:
  210                 {
  211                 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG);
  212                 reg |= MCHCFG_AAGN;
  213                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg);
  214                 break;
  215                 }
  216         case CHIP_I840:
  217         case CHIP_I850:
  218                 {
  219                 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD);
  220                 reg |= AGPCMD_AGPEN;
  221                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD,
  222                         reg);
  223                 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG);
  224                 reg |= MCHCFG_AAGN;
  225                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG,
  226                         reg);
  227                 break;
  228                 }
  229         default:
  230                 {
  231                 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG);
  232                 reg &= ~NBXCFG_APAE;
  233                 reg |=  NBXCFG_AAGN;
  234                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg);
  235                 }
  236         }
  237 
  238         /* Clear Error status */
  239         switch (isc->chiptype) {
  240         case CHIP_I840:
  241                 pci_conf_write(sc->as_pc, sc->as_tag,
  242                         AGP_INTEL_I8XX_ERRSTS, 0xc000);
  243                 break;
  244 
  245         case CHIP_I845:
  246         case CHIP_I850:
  247         case CHIP_I865:
  248                 pci_conf_write(sc->as_pc, sc->as_tag,
  249                         AGP_INTEL_I8XX_ERRSTS, 0x00ff);
  250                 break;
  251 
  252         default:
  253                 pci_conf_write(sc->as_pc, sc->as_tag,
  254                         AGP_INTEL_ERRSTS, 0x70);
  255         }
  256 
  257         return (0);
  258 }
  259 
  260 #if 0
  261 static int
  262 agp_intel_detach(struct agp_softc *sc)
  263 {
  264         int error;
  265         pcireg_t reg;
  266         struct agp_intel_softc *isc = sc->as_chipc;
  267 
  268         error = agp_generic_detach(sc);
  269         if (error)
  270                 return error;
  271 
  272         /* XXX i845/i855PM/i840/i850E */
  273         reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG);
  274         reg &= ~(1 << 9);
  275         printf("%s: set NBXCFG to %x\n", __FUNCTION__, reg);
  276         pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg);
  277         pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0);
  278         AGP_SET_APERTURE(sc, isc->initial_aperture);
  279         agp_free_gatt(sc, isc->gatt);
  280 
  281         return 0;
  282 }
  283 #endif
  284 
  285 static u_int32_t
  286 agp_intel_get_aperture(struct agp_softc *sc)
  287 {
  288         struct agp_intel_softc *isc = sc->as_chipc;
  289         u_int32_t apsize;
  290 
  291         apsize = pci_conf_read(sc->as_pc, sc->as_tag,
  292                         AGP_INTEL_APSIZE) & isc->aperture_mask;
  293 
  294         /*
  295          * The size is determined by the number of low bits of
  296          * register APBASE which are forced to zero. The low 22 bits
  297          * are always forced to zero and each zero bit in the apsize
  298          * field just read forces the corresponding bit in the 27:22
  299          * to be zero. We calculate the aperture size accordingly.
  300          */
  301         return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
  302 }
  303 
  304 static int
  305 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture)
  306 {
  307         struct agp_intel_softc *isc = sc->as_chipc;
  308         u_int32_t apsize;
  309 
  310         /*
  311          * Reverse the magic from get_aperture.
  312          */
  313         apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask;
  314 
  315         /*
  316          * Double check for sanity.
  317          */
  318         if ((((apsize ^ isc->aperture_mask) << 22) |
  319                         ((1 << 22) - 1)) + 1 != aperture)
  320                 return EINVAL;
  321 
  322         pci_conf_write(sc->as_pc, sc->as_tag,
  323                 AGP_INTEL_APSIZE, apsize);
  324 
  325         return 0;
  326 }
  327 
  328 static int
  329 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
  330 {
  331         struct agp_intel_softc *isc = sc->as_chipc;
  332 
  333         if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT))
  334                 return EINVAL;
  335 
  336         isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
  337         return 0;
  338 }
  339 
  340 static int
  341 agp_intel_unbind_page(struct agp_softc *sc, off_t offset)
  342 {
  343         struct agp_intel_softc *isc = sc->as_chipc;
  344 
  345         if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT))
  346                 return EINVAL;
  347 
  348         isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
  349         return 0;
  350 }
  351 
  352 static void
  353 agp_intel_flush_tlb(struct agp_softc *sc)
  354 {
  355         struct agp_intel_softc *isc = sc->as_chipc;
  356         pcireg_t reg;
  357 
  358         switch (isc->chiptype) {
  359         case CHIP_I865:
  360         case CHIP_I850:
  361         case CHIP_I845:
  362         case CHIP_I840:
  363         case CHIP_I443:
  364                 {
  365                 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL);
  366                 reg &= ~AGPCTRL_GTLB;
  367                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
  368                         reg);
  369                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
  370                         reg | AGPCTRL_GTLB);
  371                 break;
  372                 }
  373         default: /* XXX */
  374                 {
  375                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
  376                         0x2200);
  377                 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
  378                         0x2280);
  379                 }
  380         }
  381 }
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FreeBSD/Linux Kernel Cross Reference sys/dev/pci/agp_intel.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/agp_intel.c
