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sys/dev/pci/ahc_pci.c
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1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: ahc_pci.c,v 1.45.2.1 2004/11/12 05:55:47 jmc Exp $ 43 * 44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 45 * 46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 47 */ 48 /* 49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.45.2.1 2004/11/12 05:55:47 jmc Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/queue.h> 60 #include <sys/device.h> 61 #include <sys/reboot.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 70 /* XXXX some i386 on-board chips act weird when memory-mapped */ 71 #ifndef __i386__ 72 #define AHC_ALLOW_MEMIO 73 #endif 74 75 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 76 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 77 78 #include <dev/ic/aic7xxx_osm.h> 79 #include <dev/ic/aic7xxx_inline.h> 80 81 #include <dev/ic/smc93cx6var.h> 82 83 84 static __inline uint64_t 85 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 86 { 87 uint64_t id; 88 89 id = subvendor 90 | (subdevice << 16) 91 | ((uint64_t)vendor << 32) 92 | ((uint64_t)device << 48); 93 94 return (id); 95 } 96 97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 98 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 99 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 100 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 101 #define ID_9005_SISL_ID 0x0005900500000000ull 102 #define ID_AIC7850 0x5078900400000000ull 103 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 104 #define ID_AIC7855 0x5578900400000000ull 105 #define ID_AIC7859 0x3860900400000000ull 106 #define ID_AHA_2930CU 0x3860900438699004ull 107 #define ID_AIC7860 0x6078900400000000ull 108 #define ID_AIC7860C 0x6078900478609004ull 109 #define ID_AHA_1480A 0x6075900400000000ull 110 #define ID_AHA_2940AU_0 0x6178900400000000ull 111 #define ID_AHA_2940AU_1 0x6178900478619004ull 112 #define ID_AHA_2940AU_CN 0x2178900478219004ull 113 #define ID_AHA_2930C_VAR 0x6038900438689004ull 114 115 #define ID_AIC7870 0x7078900400000000ull 116 #define ID_AHA_2940 0x7178900400000000ull 117 #define ID_AHA_3940 0x7278900400000000ull 118 #define ID_AHA_398X 0x7378900400000000ull 119 #define ID_AHA_2944 0x7478900400000000ull 120 #define ID_AHA_3944 0x7578900400000000ull 121 #define ID_AHA_4944 0x7678900400000000ull 122 123 #define ID_AIC7880 0x8078900400000000ull 124 #define ID_AIC7880_B 0x8078900478809004ull 125 #define ID_AHA_2940U 0x8178900400000000ull 126 #define ID_AHA_3940U 0x8278900400000000ull 127 #define ID_AHA_2944U 0x8478900400000000ull 128 #define ID_AHA_3944U 0x8578900400000000ull 129 #define ID_AHA_398XU 0x8378900400000000ull 130 #define ID_AHA_4944U 0x8678900400000000ull 131 #define ID_AHA_2940UB 0x8178900478819004ull 132 #define ID_AHA_2930U 0x8878900478889004ull 133 #define ID_AHA_2940U_PRO 0x8778900478879004ull 134 #define ID_AHA_2940U_CN 0x0078900478009004ull 135 136 #define ID_AIC7895 0x7895900478959004ull 137 #define ID_AIC7895_ARO 0x7890900478939004ull 138 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 139 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 140 #define ID_AHA_3940AU 0x7895900478929004ull 141 #define ID_AHA_3944AU 0x7895900478949004ull 142 143 #define ID_AIC7890 0x001F9005000F9005ull 144 #define ID_AIC7890_ARO 0x00139005000F9005ull 145 #define ID_AAA_131U2 0x0013900500039005ull 146 #define ID_AHA_2930U2 0x0011900501819005ull 147 #define ID_AHA_2940U2B 0x00109005A1009005ull 148 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 149 #define ID_AHA_2940U2 0x00109005A1809005ull 150 #define ID_AHA_2950U2B 0x00109005E1009005ull 151 152 #define ID_AIC7892 0x008F9005FFFF9005ull 153 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 154 #define ID_AHA_2915LP 0x0082900502109005ull 155 #define ID_AHA_29160 0x00809005E2A09005ull 156 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 157 #define ID_AHA_29160N 0x0080900562A09005ull 158 #define ID_AHA_29160C 0x0080900562209005ull 159 #define ID_AHA_29160B 0x00809005E2209005ull 160 #define ID_AHA_19160B 0x0081900562A19005ull 161 162 #define ID_AIC7896 0x005F9005FFFF9005ull 163 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 164 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 165 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 166 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 167 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 168 169 #define ID_AIC7899 0x00CF9005FFFF9005ull 170 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 171 #define ID_AHA_3960D 0x00C09005F6209005ull 172 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 173 174 #define ID_AIC7810 0x1078900400000000ull 175 #define ID_AIC7815 0x7815900400000000ull 176 177 #define DEVID_9005_TYPE(id) ((id) & 0xF) 178 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 179 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 180 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 181 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 182 183 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 184 #define DEVID_9005_MAXRATE_U160 0x0 185 #define DEVID_9005_MAXRATE_ULTRA2 0x1 186 #define DEVID_9005_MAXRATE_ULTRA 0x2 187 #define DEVID_9005_MAXRATE_FAST 0x3 188 189 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 190 191 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 192 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 193 194 #define SUBID_9005_TYPE(id) ((id) & 0xF) 195 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 196 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 197 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 198 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 199 200 #define SUBID_9005_TYPE_KNOWN(id) \ 201 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 202 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 203 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 204 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 205 206 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 207 #define SUBID_9005_MAXRATE_ULTRA2 0x0 208 #define SUBID_9005_MAXRATE_ULTRA 0x1 209 #define SUBID_9005_MAXRATE_U160 0x2 210 #define SUBID_9005_MAXRATE_RESERVED 0x3 211 212 #define SUBID_9005_SEEPTYPE(id) \ 213 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 214 ? ((id) & 0xC0) >> 6 \ 215 : ((id) & 0x300) >> 8) 216 #define SUBID_9005_SEEPTYPE_NONE 0x0 217 #define SUBID_9005_SEEPTYPE_1K 0x1 218 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 219 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 220 #define SUBID_9005_AUTOTERM(id) \ 221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 222 ? (((id) & 0x400) >> 10) == 0 \ 223 : (((id) & 0x40) >> 6) == 0) 224 225 #define SUBID_9005_NUMCHAN(id) \ 226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 227 ? ((id) & 0x300) >> 8 \ 228 : ((id) & 0xC00) >> 10) 229 230 #define SUBID_9005_LEGACYCONN(id) \ 231 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 232 ? 0 \ 233 : ((id) & 0x80) >> 7) 234 235 #define SUBID_9005_MFUNCENB(id) \ 236 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 237 ? ((id) & 0x800) >> 11 \ 238 : ((id) & 0x1000) >> 12) 239 /* 240 * Informational only. Should use chip register to be 241 * certain, but may be use in identification strings. 242 */ 243 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 244 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 245 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 246 247 static ahc_device_setup_t ahc_aic785X_setup; 248 static ahc_device_setup_t ahc_aic7860_setup; 249 static ahc_device_setup_t ahc_apa1480_setup; 250 static ahc_device_setup_t ahc_aic7870_setup; 251 static ahc_device_setup_t ahc_aha394X_setup; 252 static ahc_device_setup_t ahc_aha494X_setup; 253 static ahc_device_setup_t ahc_aha398X_setup; 254 static ahc_device_setup_t ahc_aic7880_setup; 255 static ahc_device_setup_t ahc_aha2940Pro_setup; 256 static ahc_device_setup_t ahc_aha394XU_setup; 257 static ahc_device_setup_t ahc_aha398XU_setup; 258 static ahc_device_setup_t ahc_aic7890_setup; 259 static ahc_device_setup_t ahc_aic7892_setup; 260 static ahc_device_setup_t ahc_aic7895_setup; 261 static ahc_device_setup_t ahc_aic7896_setup; 262 static ahc_device_setup_t ahc_aic7899_setup; 263 static ahc_device_setup_t ahc_aha29160C_setup; 264 static ahc_device_setup_t ahc_raid_setup; 265 static ahc_device_setup_t ahc_aha394XX_setup; 266 static ahc_device_setup_t ahc_aha494XX_setup; 267 static ahc_device_setup_t ahc_aha398XX_setup; 268 269 struct ahc_pci_identity ahc_pci_ident_table [] = 270 { 271 /* aic7850 based controllers */ 272 { 273 ID_AHA_2902_04_10_15_20_30C, 274 ID_ALL_MASK, 275 "Adaptec 2902/04/10/15/20/30C SCSI adapter", 276 ahc_aic785X_setup 277 }, 278 /* aic7860 based controllers */ 279 { 280 ID_AHA_2930CU, 281 ID_ALL_MASK, 282 "Adaptec 2930CU SCSI adapter", 283 ahc_aic7860_setup 284 }, 285 { 286 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 "Adaptec 1480A Ultra SCSI adapter", 289 ahc_apa1480_setup 290 }, 291 { 292 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 2940A Ultra SCSI adapter", 295 ahc_aic7860_setup 296 }, 297 { 298 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2940A/CN Ultra SCSI adapter", 301 ahc_aic7860_setup 302 }, 303 { 304 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 305 ID_DEV_VENDOR_MASK, 306 "Adaptec 2930C Ultra SCSI adapter (VAR)", 307 ahc_aic7860_setup 308 }, 309 /* aic7870 based controllers */ 310 { 311 ID_AHA_2940, 312 ID_ALL_MASK, 313 "Adaptec 2940 SCSI adapter", 314 ahc_aic7870_setup 315 }, 316 { 317 ID_AHA_3940, 318 ID_ALL_MASK, 319 "Adaptec 3940 SCSI adapter", 320 ahc_aha394X_setup 321 }, 322 { 323 ID_AHA_398X, 324 ID_ALL_MASK, 325 "Adaptec 398X SCSI RAID adapter", 326 ahc_aha398X_setup 327 }, 328 { 329 ID_AHA_2944, 330 ID_ALL_MASK, 331 "Adaptec 2944 SCSI adapter", 332 ahc_aic7870_setup 333 }, 334 { 335 ID_AHA_3944, 336 ID_ALL_MASK, 337 "Adaptec 3944 SCSI adapter", 338 ahc_aha394X_setup 339 }, 340 { 341 ID_AHA_4944, 342 ID_ALL_MASK, 343 "Adaptec 4944 SCSI adapter", 344 ahc_aha494X_setup 345 }, 346 /* aic7880 based controllers */ 347 { 348 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 349 ID_DEV_VENDOR_MASK, 350 "Adaptec 2940 Ultra SCSI adapter", 351 ahc_aic7880_setup 352 }, 353 { 354 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 355 ID_DEV_VENDOR_MASK, 356 "Adaptec 3940 Ultra SCSI adapter", 357 ahc_aha394XU_setup 358 }, 359 { 360 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 "Adaptec 2944 Ultra SCSI adapter", 363 ahc_aic7880_setup 364 }, 365 { 366 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 367 ID_DEV_VENDOR_MASK, 368 "Adaptec 3944 Ultra SCSI adapter", 369 ahc_aha394XU_setup 370 }, 371 { 372 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 373 ID_DEV_VENDOR_MASK, 374 "Adaptec 398X Ultra SCSI RAID adapter", 375 ahc_aha398XU_setup 376 }, 377 { 378 /* 379 * XXX Don't know the slot numbers 380 * so we can't identify channels 381 */ 382 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 383 ID_DEV_VENDOR_MASK, 384 "Adaptec 4944 Ultra SCSI adapter", 385 ahc_aic7880_setup 386 }, 387 { 388 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 389 ID_DEV_VENDOR_MASK, 390 "Adaptec 2930 Ultra SCSI adapter", 391 ahc_aic7880_setup 392 }, 393 { 394 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 395 ID_DEV_VENDOR_MASK, 396 "Adaptec 2940 Pro Ultra SCSI adapter", 397 ahc_aha2940Pro_setup 398 }, 399 { 400 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 401 ID_DEV_VENDOR_MASK, 402 "Adaptec 2940/CN Ultra SCSI adapter", 403 ahc_aic7880_setup 404 }, 405 /* Ignore all SISL (AAC on MB) based controllers. */ 406 { 407 ID_9005_SISL_ID, 408 ID_9005_SISL_MASK, 409 NULL, 410 NULL 411 }, 412 /* aic7890 based controllers */ 413 { 414 ID_AHA_2930U2, 415 ID_ALL_MASK, 416 "Adaptec 2930 Ultra2 SCSI adapter", 417 ahc_aic7890_setup 418 }, 419 { 420 ID_AHA_2940U2B, 421 ID_ALL_MASK, 422 "Adaptec 2940B Ultra2 SCSI adapter", 423 ahc_aic7890_setup 424 }, 425 { 426 ID_AHA_2940U2_OEM, 427 ID_ALL_MASK, 428 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 429 ahc_aic7890_setup 430 }, 431 { 432 ID_AHA_2940U2, 433 ID_ALL_MASK, 434 "Adaptec 2940 Ultra2 SCSI adapter", 435 ahc_aic7890_setup 436 }, 437 { 438 ID_AHA_2950U2B, 439 ID_ALL_MASK, 440 "Adaptec 2950 Ultra2 SCSI adapter", 441 ahc_aic7890_setup 442 }, 443 { 444 ID_AIC7890_ARO, 445 ID_ALL_MASK, 446 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 447 ahc_aic7890_setup 448 }, 449 { 450 ID_AAA_131U2, 451 ID_ALL_MASK, 452 "Adaptec AAA-131 Ultra2 RAID adapter", 453 ahc_aic7890_setup 454 }, 455 /* aic7892 based controllers */ 456 { 457 ID_AHA_29160, 458 ID_ALL_MASK, 459 "Adaptec 29160 Ultra160 SCSI adapter", 460 ahc_aic7892_setup 461 }, 462 { 463 ID_AHA_29160_CPQ, 464 ID_ALL_MASK, 465 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 466 ahc_aic7892_setup 467 }, 468 { 469 ID_AHA_29160N, 470 ID_ALL_MASK, 471 "Adaptec 29160N Ultra160 SCSI adapter", 472 ahc_aic7892_setup 473 }, 474 { 475 ID_AHA_29160C, 476 ID_ALL_MASK, 477 "Adaptec 29160C Ultra160 SCSI adapter", 478 ahc_aha29160C_setup 479 }, 480 { 481 ID_AHA_29160B, 482 ID_ALL_MASK, 483 "Adaptec 29160B Ultra160 SCSI adapter", 484 ahc_aic7892_setup 485 }, 486 { 487 ID_AHA_19160B, 488 ID_ALL_MASK, 489 "Adaptec 19160B Ultra160 SCSI adapter", 490 ahc_aic7892_setup 491 }, 492 { 493 ID_AIC7892_ARO, 494 ID_ALL_MASK, 495 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 496 ahc_aic7892_setup 497 }, 498 { 499 ID_AHA_2915LP, 500 ID_ALL_MASK, 501 "Adaptec 2915LP Ultra160 SCSI adapter", 502 ahc_aic7892_setup 503 }, 504 /* aic7895 based controllers */ 505 { 506 ID_AHA_2940U_DUAL, 507 ID_ALL_MASK, 508 "Adaptec 2940/DUAL Ultra SCSI adapter", 509 ahc_aic7895_setup 510 }, 511 { 512 ID_AHA_3940AU, 513 ID_ALL_MASK, 514 "Adaptec 3940A Ultra SCSI adapter", 515 ahc_aic7895_setup 516 }, 517 { 518 ID_AHA_3944AU, 519 ID_ALL_MASK, 520 "Adaptec 3944A Ultra SCSI adapter", 521 ahc_aic7895_setup 522 }, 523 { 524 ID_AIC7895_ARO, 525 ID_AIC7895_ARO_MASK, 526 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 527 ahc_aic7895_setup 528 }, 529 /* aic7896/97 based controllers */ 530 { 531 ID_AHA_3950U2B_0, 532 ID_ALL_MASK, 533 "Adaptec 3950B Ultra2 SCSI adapter", 534 ahc_aic7896_setup 535 }, 536 { 537 ID_AHA_3950U2B_1, 538 ID_ALL_MASK, 539 "Adaptec 3950B Ultra2 SCSI adapter", 540 ahc_aic7896_setup 541 }, 542 { 543 ID_AHA_3950U2D_0, 544 ID_ALL_MASK, 545 "Adaptec 3950D Ultra2 SCSI adapter", 546 ahc_aic7896_setup 547 }, 548 { 549 ID_AHA_3950U2D_1, 550 ID_ALL_MASK, 551 "Adaptec 3950D Ultra2 SCSI adapter", 552 ahc_aic7896_setup 553 }, 554 { 555 ID_AIC7896_ARO, 556 ID_ALL_MASK, 557 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 558 ahc_aic7896_setup 559 }, 560 /* aic7899 based controllers */ 561 { 562 ID_AHA_3960D, 563 ID_ALL_MASK, 564 "Adaptec 3960D Ultra160 SCSI adapter", 565 ahc_aic7899_setup 566 }, 567 { 568 ID_AHA_3960D_CPQ, 569 ID_ALL_MASK, 570 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 571 ahc_aic7899_setup 572 }, 573 { 574 ID_AIC7899_ARO, 575 ID_ALL_MASK, 576 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 577 ahc_aic7899_setup 578 }, 579 /* Generic chip probes for devices we don't know 'exactly' */ 580 { 581 ID_AIC7850 & ID_DEV_VENDOR_MASK, 582 ID_DEV_VENDOR_MASK, 583 "Adaptec aic7850 SCSI adapter", 584 ahc_aic785X_setup 585 }, 586 { 587 ID_AIC7855 & ID_DEV_VENDOR_MASK, 588 ID_DEV_VENDOR_MASK, 589 "Adaptec aic7855 SCSI adapter", 590 ahc_aic785X_setup 591 }, 592 { 593 ID_AIC7859 & ID_DEV_VENDOR_MASK, 594 ID_DEV_VENDOR_MASK, 595 "Adaptec aic7859 SCSI adapter", 596 ahc_aic7860_setup 597 }, 598 { 599 ID_AIC7860 & ID_DEV_VENDOR_MASK, 600 ID_DEV_VENDOR_MASK, 601 "Adaptec aic7860 Ultra SCSI adapter", 602 ahc_aic7860_setup 603 }, 604 { 605 ID_AIC7870 & ID_DEV_VENDOR_MASK, 606 ID_DEV_VENDOR_MASK, 607 "Adaptec aic7870 SCSI adapter", 608 ahc_aic7870_setup 609 }, 610 { 611 ID_AIC7880 & ID_DEV_VENDOR_MASK, 612 ID_DEV_VENDOR_MASK, 613 "Adaptec aic7880 Ultra SCSI adapter", 614 ahc_aic7880_setup 615 }, 616 { 617 ID_AIC7890 & ID_9005_GENERIC_MASK, 618 ID_9005_GENERIC_MASK, 619 "Adaptec aic7890/91 Ultra2 SCSI adapter", 620 ahc_aic7890_setup 621 }, 622 { 623 ID_AIC7892 & ID_9005_GENERIC_MASK, 624 ID_9005_GENERIC_MASK, 625 "Adaptec aic7892 Ultra160 SCSI adapter", 626 ahc_aic7892_setup 627 }, 628 { 629 ID_AIC7895 & ID_DEV_VENDOR_MASK, 630 ID_DEV_VENDOR_MASK, 631 "Adaptec aic7895 Ultra SCSI adapter", 632 ahc_aic7895_setup 633 }, 634 { 635 ID_AIC7896 & ID_9005_GENERIC_MASK, 636 ID_9005_GENERIC_MASK, 637 "Adaptec aic7896/97 Ultra2 SCSI adapter", 638 ahc_aic7896_setup 639 }, 640 { 641 ID_AIC7899 & ID_9005_GENERIC_MASK, 642 ID_9005_GENERIC_MASK, 643 "Adaptec aic7899 Ultra160 SCSI adapter", 644 ahc_aic7899_setup 645 }, 646 { 647 ID_AIC7810 & ID_DEV_VENDOR_MASK, 648 ID_DEV_VENDOR_MASK, 649 "Adaptec aic7810 RAID memory controller", 650 ahc_raid_setup 651 }, 652 { 653 ID_AIC7815 & ID_DEV_VENDOR_MASK, 654 ID_DEV_VENDOR_MASK, 655 "Adaptec aic7815 RAID memory controller", 656 ahc_raid_setup 657 } 658 }; 659 660 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 661 662 #define AHC_394X_SLOT_CHANNEL_A 4 663 #define AHC_394X_SLOT_CHANNEL_B 5 664 665 #define AHC_398X_SLOT_CHANNEL_A 4 666 #define AHC_398X_SLOT_CHANNEL_B 8 667 #define AHC_398X_SLOT_CHANNEL_C 12 668 669 #define AHC_494X_SLOT_CHANNEL_A 4 670 #define AHC_494X_SLOT_CHANNEL_B 5 671 #define AHC_494X_SLOT_CHANNEL_C 6 672 #define AHC_494X_SLOT_CHANNEL_D 7 673 674 #define DEVCONFIG 0x40 675 #define PCIERRGENDIS 0x80000000ul 676 #define SCBSIZE32 0x00010000ul /* aic789X only */ 677 #define REXTVALID 0x00001000ul /* ultra cards only */ 678 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 679 #define RAMPSM 0x00000200ul /* aic7870+ only */ 680 #define VOLSENSE 0x00000100ul 681 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 682 #define SCBRAMSEL 0x00000080ul 683 #define MRDCEN 0x00000040ul 684 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 685 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 686 #define BERREN 0x00000008ul 687 #define DACEN 0x00000004ul 688 #define STPWLEVEL 0x00000002ul 689 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 690 691 #define CSIZE_LATTIME 0x0c 692 #define CACHESIZE 0x0000003ful /* only 5 bits */ 693 #define LATTIME 0x0000ff00ul 694 695 /* PCI STATUS definitions */ 696 #define DPE 0x80 697 #define SSE 0x40 698 #define RMA 0x20 699 #define RTA 0x10 700 #define STA 0x08 701 #define DPR 0x01 702 703 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 704 uint16_t subvendor, uint16_t subdevice); 705 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 706 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 707 int pcheck, int fast, int large); 708 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 709 710 int ahc_pci_probe __P((struct device *, struct cfdata *, void *)); 711 void ahc_pci_attach __P((struct device *, struct device *, void *)); 712 713 714 CFATTACH_DECL(ahc_pci, sizeof(struct ahc_softc), 715 ahc_pci_probe, ahc_pci_attach, NULL, NULL); 716 717 const struct ahc_pci_identity * 718 ahc_find_pci_device(id, subid, func) 719 pcireg_t id, subid; 720 u_int func; 721 { 722 u_int64_t full_id; 723 const struct ahc_pci_identity *entry; 724 u_int i; 725 726 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 727 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 728 729 /* 730 * If the second function is not hooked up, ignore it. 731 * Unfortunately, not all MB vendors implement the 732 * subdevice ID as per the Adaptec spec, so do our best 733 * to sanity check it prior to accepting the subdevice 734 * ID as valid. 735 */ 736 if (func > 0 737 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 738 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 739 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 740 return (NULL); 741 742 for (i = 0; i < ahc_num_pci_devs; i++) { 743 entry = &ahc_pci_ident_table[i]; 744 if (entry->full_id == (full_id & entry->id_mask)) 745 return (entry); 746 } 747 return (NULL); 748 } 749 750 int 751 ahc_pci_probe(parent, match, aux) 752 struct device *parent; 753 struct cfdata *match; 754 void *aux; 755 { 756 struct pci_attach_args *pa = aux; 757 const struct ahc_pci_identity *entry; 758 pcireg_t subid; 759 760 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 761 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 762 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 763 } 764 765 void 766 ahc_pci_attach(parent, self, aux) 767 struct device *parent, *self; 768 void *aux; 769 { 770 struct pci_attach_args *pa = aux; 771 const struct ahc_pci_identity *entry; 772 struct ahc_softc *ahc = (void *)self; 773 pcireg_t command; 774 u_int our_id = 0; 775 u_int sxfrctl1; 776 u_int scsiseq; 777 u_int sblkctl; 778 uint8_t dscommand0; 779 uint32_t devconfig; 780 int error; 781 pcireg_t subid; 782 int ioh_valid; 783 bus_space_tag_t st, iot; 784 bus_space_handle_t sh, ioh; 785 #ifdef AHC_ALLOW_MEMIO 786 int memh_valid; 787 bus_space_tag_t memt; 788 bus_space_handle_t memh; 789 pcireg_t memtype; 790 #endif 791 pci_intr_handle_t ih; 792 const char *intrstr; 793 struct ahc_pci_busdata *bd; 794 795 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 796 ahc->parent_dmat = pa->pa_dmat; 797 798 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 799 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 800 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 801 if (entry == NULL) 802 return; 803 printf(": %s\n", entry->name); 804 805 /* Keep information about the PCI bus */ 806 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 807 if (bd == NULL) { 808 printf("%s: unable to allocate bus-specific data\n", 809 ahc_name(ahc)); 810 return; 811 } 812 memset(bd, 0, sizeof(struct ahc_pci_busdata)); 813 814 bd->pc = pa->pa_pc; 815 bd->tag = pa->pa_tag; 816 bd->func = pa->pa_function; 817 bd->dev = pa->pa_device; 818 bd->class = pa->pa_class; 819 820 ahc->bd = bd; 821 822 ahc->description = entry->name; 823 824 error = entry->setup(ahc); 825 if (error != 0) 826 return; 827 828 ioh_valid = 0; 829 830 #ifdef AHC_ALLOW_MEMIO 831 memh_valid = 0; 832 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 833 switch (memtype) { 834 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 835 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 836 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 837 memtype, 0, &memt, &memh, NULL, NULL) == 0); 838 break; 839 default: 840 memh_valid = 0; 841 } 842 #endif 843 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 844 PCI_MAPREG_TYPE_IO, 0, &iot, 845 &ioh, NULL, NULL) == 0); 846 #if 0 847 printf("%s: bus info: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n", 848 ahc_name(ahc), (u_long)memt, (u_long)memh, (u_long)iot, 849 (u_long)ioh); 850 #endif 851 852 if (ioh_valid) { 853 st = iot; 854 sh = ioh; 855 #ifdef AHC_ALLOW_MEMIO 856 } else if (memh_valid) { 857 st = memt; 858 sh = memh; 859 #endif 860 } else { 861 printf(": unable to map registers\n"); 862 return; 863 } 864 ahc->tag = st; 865 ahc->bsh = sh; 866 867 ahc->chip |= AHC_PCI; 868 /* 869 * Before we continue probing the card, ensure that 870 * its interrupts are *disabled*. We don't want 871 * a misstep to hang the machine in an interrupt 872 * storm. 873 */ 874 ahc_intr_enable(ahc, FALSE); 875 876 /* 877 * XXX somehow reading this once fails on some sparc64 systems. 878 * This may be a problem in the sparc64 PCI code. Doing it 879 * twice works around it. 880 */ 881 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 882 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 883 884 /* 885 * If we need to support high memory, enable dual 886 * address cycles. This bit must be set to enable 887 * high address bit generation even if we are on a 888 * 64bit bus (PCI64BIT set in devconfig). 889 */ 890 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 891 892 if (1/*bootverbose*/) 893 printf("%s: Enabling 39Bit Addressing\n", 894 ahc_name(ahc)); 895 devconfig |= DACEN; 896 } 897 898 /* Ensure that pci error generation, a test feature, is disabled. */ 899 devconfig |= PCIERRGENDIS; 900 901 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 902 903 /* Ensure busmastering is enabled */ 904 command |= PCI_COMMAND_MASTER_ENABLE;; 905 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 906 907 /* 908 * Disable PCI parity error reporting. Users typically 909 * do this to work around broken PCI chipsets that get 910 * the parity timing wrong and thus generate lots of spurious 911 * errors. 912 */ 913 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 914 command &= ~PCI_COMMAND_PARITY_ENABLE; 915 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 916 917 /* On all PCI adapters, we allow SCB paging */ 918 ahc->flags |= AHC_PAGESCBS; 919 error = ahc_softc_init(ahc); 920 if (error != 0) 921 goto error_out; 922 923 ahc->bus_intr = ahc_pci_intr; 924 925 /* Remember how the card was setup in case there is no SEEPROM */ 926 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 927 ahc_pause(ahc); 928 if ((ahc->features & AHC_ULTRA2) != 0) 929 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 930 else 931 our_id = ahc_inb(ahc, SCSIID) & OID; 932 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 933 scsiseq = ahc_inb(ahc, SCSISEQ); 934 } else { 935 sxfrctl1 = STPWEN; 936 our_id = 7; 937 scsiseq = 0; 938 } 939 940 error = ahc_reset(ahc); 941 if (error != 0) 942 goto error_out; 943 944 if ((ahc->features & AHC_DT) != 0) { 945 u_int sfunct; 946 947 /* Perform ALT-Mode Setup */ 948 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 949 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 950 ahc_outb(ahc, OPTIONMODE, 951 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 952 ahc_outb(ahc, SFUNCT, sfunct); 953 954 /* Normal mode setup */ 955 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 956 |TARGCRCENDEN); 957 } 958 959 if (pci_intr_map(pa, &ih)) { 960 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 961 ahc_free(ahc); 962 return; 963 } 964 intrstr = pci_intr_string(pa->pa_pc, ih); 965 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc); 966 if (ahc->ih == NULL) { 967 printf("%s: couldn't establish interrupt", 968 ahc->sc_dev.dv_xname); 969 if (intrstr != NULL) 970 printf(" at %s", intrstr); 971 printf("\n"); 972 ahc_free(ahc); 973 return; 974 } 975 if (intrstr != NULL) 976 printf("%s: interrupting at %s\n", ahc_name(ahc), intrstr); 977 978 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 979 dscommand0 |= MPARCKEN|CACHETHEN; 980 if ((ahc->features & AHC_ULTRA2) != 0) { 981 982 /* 983 * DPARCKEN doesn't work correctly on 984 * some MBs so don't use it. 985 */ 986 dscommand0 &= ~DPARCKEN; 987 } 988 989 /* 990 * Handle chips that must have cache line 991 * streaming (dis/en)abled. 992 */ 993 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 994 dscommand0 |= CACHETHEN; 995 996 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 997 dscommand0 &= ~CACHETHEN; 998 999 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1000 1001 ahc->pci_cachesize = 1002 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 1003 ahc->pci_cachesize *= 4; 1004 1005 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 1006 && ahc->pci_cachesize == 4) { 1007 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 1008 ahc->pci_cachesize = 0; 1009 } 1010 1011 /* 1012 * We cannot perform ULTRA speeds without the presence 1013 * of the external precision resistor. 1014 */ 1015 if ((ahc->features & AHC_ULTRA) != 0) { 1016 uint32_t devconfig; 1017 1018 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1019 if ((devconfig & REXTVALID) == 0) 1020 ahc->features &= ~AHC_ULTRA; 1021 } 1022 1023 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 1024 M_DEVBUF, M_NOWAIT); 1025 if (ahc->seep_config == NULL) 1026 goto error_out; 1027 1028 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); 1029 1030 /* See if we have a SEEPROM and perform auto-term */ 1031 ahc_check_extport(ahc, &sxfrctl1); 1032 1033 /* 1034 * Take the LED out of diagnostic mode 1035 */ 1036 sblkctl = ahc_inb(ahc, SBLKCTL); 1037 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 1038 1039 if ((ahc->features & AHC_ULTRA2) != 0) { 1040 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 1041 } else { 1042 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 1043 } 1044 1045 if (ahc->flags & AHC_USEDEFAULTS) { 1046 /* 1047 * PCI Adapter default setup 1048 * Should only be used if the adapter does not have 1049 * a SEEPROM. 1050 */ 1051 /* See if someone else set us up already */ 1052 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 1053 && scsiseq != 0) { 1054 printf("%s: Using left over BIOS settings\n", 1055 ahc_name(ahc)); 1056 ahc->flags &= ~AHC_USEDEFAULTS; 1057 ahc->flags |= AHC_BIOS_ENABLED; 1058 } else { 1059 /* 1060 * Assume only one connector and always turn 1061 * on termination. 1062 */ 1063 our_id = 0x07; 1064 sxfrctl1 = STPWEN; 1065 } 1066 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1067 1068 ahc->our_id = our_id; 1069 } 1070 1071 /* 1072 * Take a look to see if we have external SRAM. 1073 * We currently do not attempt to use SRAM that is 1074 * shared among multiple controllers. 1075 */ 1076 ahc_probe_ext_scbram(ahc); 1077 1078 /* 1079 * Record our termination setting for the 1080 * generic initialization routine. 1081 */ 1082 if ((sxfrctl1 & STPWEN) != 0) 1083 ahc->flags |= AHC_TERM_ENB_A; 1084 1085 if (ahc_init(ahc)) 1086 goto error_out; 1087 1088 ahc_attach(ahc); 1089 1090 return; 1091 1092 error_out: 1093 ahc_free(ahc); 1094 return; 1095 } 1096 1097 static int 1098 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1099 uint16_t subdevice, uint16_t subvendor) 1100 { 1101 int result; 1102 1103 /* Default to invalid. */ 1104 result = 0; 1105 if (vendor == 0x9005 1106 && subvendor == 0x9005 1107 && subdevice != device 1108 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1109 1110 switch (SUBID_9005_TYPE(subdevice)) { 1111 case SUBID_9005_TYPE_MB: 1112 break; 1113 case SUBID_9005_TYPE_CARD: 1114 case SUBID_9005_TYPE_LCCARD: 1115 /* 1116 * Currently only trust Adaptec cards to 1117 * get the sub device info correct. 1118 */ 1119 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1120 result = 1; 1121 break; 1122 case SUBID_9005_TYPE_RAID: 1123 break; 1124 default: 1125 break; 1126 } 1127 } 1128 return (result); 1129 } 1130 1131 1132 /* 1133 * Test for the presense of external sram in an 1134 * "unshared" configuration. 1135 */ 1136 static int 1137 ahc_ext_scbram_present(struct ahc_softc *ahc) 1138 { 1139 u_int chip; 1140 int ramps; 1141 int single_user; 1142 uint32_t devconfig; 1143 1144 chip = ahc->chip & AHC_CHIPID_MASK; 1145 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1146 single_user = (devconfig & MPORTMODE) != 0; 1147 1148 if ((ahc->features & AHC_ULTRA2) != 0) 1149 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1150 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1151 /* 1152 * External SCBRAM arbitration is flakey 1153 * on these chips. Unfortunately this means 1154 * we don't use the extra SCB ram space on the 1155 * 3940AUW. 1156 */ 1157 ramps = 0; 1158 else if (chip >= AHC_AIC7870) 1159 ramps = (devconfig & RAMPSM) != 0; 1160 else 1161 ramps = 0; 1162 1163 if (ramps && single_user) 1164 return (1); 1165 return (0); 1166 } 1167 1168 /* 1169 * Enable external scbram. 1170 */ 1171 static void 1172 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1173 int fast, int large) 1174 { 1175 uint32_t devconfig; 1176 1177 if (ahc->features & AHC_MULTI_FUNC) { 1178 /* 1179 * Set the SCB Base addr (highest address bit) 1180 * depending on which channel we are. 1181 */ 1182 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1183 } 1184 1185 ahc->flags &= ~AHC_LSCBS_ENABLED; 1186 if (large) 1187 ahc->flags |= AHC_LSCBS_ENABLED; 1188 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1189 if ((ahc->features & AHC_ULTRA2) != 0) { 1190 u_int dscommand0; 1191 1192 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1193 if (enable) 1194 dscommand0 &= ~INTSCBRAMSEL; 1195 else 1196 dscommand0 |= INTSCBRAMSEL; 1197 if (large) 1198 dscommand0 &= ~USCBSIZE32; 1199 else 1200 dscommand0 |= USCBSIZE32; 1201 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1202 } else { 1203 if (fast) 1204 devconfig &= ~EXTSCBTIME; 1205 else 1206 devconfig |= EXTSCBTIME; 1207 if (enable) 1208 devconfig &= ~SCBRAMSEL; 1209 else 1210 devconfig |= SCBRAMSEL; 1211 if (large) 1212 devconfig &= ~SCBSIZE32; 1213 else 1214 devconfig |= SCBSIZE32; 1215 } 1216 if (pcheck) 1217 devconfig |= EXTSCBPEN; 1218 else 1219 devconfig &= ~EXTSCBPEN; 1220 1221 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1222 } 1223 1224 /* 1225 * Take a look to see if we have external SRAM. 1226 * We currently do not attempt to use SRAM that is 1227 * shared among multiple controllers. 1228 */ 1229 static void 1230 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1231 { 1232 int num_scbs; 1233 int test_num_scbs; 1234 int enable; 1235 int pcheck; 1236 int fast; 1237 int large; 1238 1239 enable = FALSE; 1240 pcheck = FALSE; 1241 fast = FALSE; 1242 large = FALSE; 1243 num_scbs = 0; 1244 1245 if (ahc_ext_scbram_present(ahc) == 0) 1246 goto done; 1247 1248 /* 1249 * Probe for the best parameters to use. 1250 */ 1251 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1252 num_scbs = ahc_probe_scbs(ahc); 1253 if (num_scbs == 0) { 1254 /* The SRAM wasn't really present. */ 1255 goto done; 1256 } 1257 enable = TRUE; 1258 1259 /* 1260 * Clear any outstanding parity error 1261 * and ensure that parity error reporting 1262 * is enabled. 1263 */ 1264 ahc_outb(ahc, SEQCTL, 0); 1265 ahc_outb(ahc, CLRINT, CLRPARERR); 1266 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1267 1268 /* Now see if we can do parity */ 1269 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1270 num_scbs = ahc_probe_scbs(ahc); 1271 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1272 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1273 pcheck = TRUE; 1274 1275 /* Clear any resulting parity error */ 1276 ahc_outb(ahc, CLRINT, CLRPARERR); 1277 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1278 1279 /* Now see if we can do fast timing */ 1280 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1281 test_num_scbs = ahc_probe_scbs(ahc); 1282 if (test_num_scbs == num_scbs 1283 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1284 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1285 fast = TRUE; 1286 1287 /* 1288 * See if we can use large SCBs and still maintain 1289 * the same overall count of SCBs. 1290 */ 1291 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1292 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1293 test_num_scbs = ahc_probe_scbs(ahc); 1294 if (test_num_scbs >= num_scbs) { 1295 large = TRUE; 1296 num_scbs = test_num_scbs; 1297 if (num_scbs >= 64) { 1298 /* 1299 * We have enough space to move the 1300 * "busy targets table" into SCB space 1301 * and make it qualify all the way to the 1302 * lun level. 1303 */ 1304 ahc->flags |= AHC_SCB_BTT; 1305 } 1306 } 1307 } 1308 done: 1309 /* 1310 * Disable parity error reporting until we 1311 * can load instruction ram. 1312 */ 1313 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1314 /* Clear any latched parity error */ 1315 ahc_outb(ahc, CLRINT, CLRPARERR); 1316 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1317 if (1/*bootverbose*/ && enable) { 1318 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1319 ahc_name(ahc), fast ? "fast" : "slow", 1320 pcheck ? ", parity checking enabled" : "", 1321 large ? 64 : 32); 1322 } 1323 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1324 } 1325 1326 #if 0 1327 /* 1328 * Perform some simple tests that should catch situations where 1329 * our registers are invalidly mapped. 1330 */ 1331 int 1332 ahc_pci_test_register_access(struct ahc_softc *ahc) 1333 { 1334 int error; 1335 u_int status1; 1336 uint32_t cmd; 1337 uint8_t hcntrl; 1338 1339 error = EIO; 1340 1341 /* 1342 * Enable PCI error interrupt status, but suppress NMIs 1343 * generated by SERR raised due to target aborts. 1344 */ 1345 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1346 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1347 cmd & ~PCIM_CMD_SERRESPEN); 1348 1349 /* 1350 * First a simple test to see if any 1351 * registers can be read. Reading 1352 * HCNTRL has no side effects and has 1353 * at least one bit that is guaranteed to 1354 * be zero so it is a good register to 1355 * use for this test. 1356 */ 1357 hcntrl = ahc_inb(ahc, HCNTRL); 1358 if (hcntrl == 0xFF) 1359 goto fail; 1360 1361 /* 1362 * Next create a situation where write combining 1363 * or read prefetching could be initiated by the 1364 * CPU or host bridge. Our device does not support 1365 * either, so look for data corruption and/or flagged 1366 * PCI errors. 1367 */ 1368 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1369 while (ahc_is_paused(ahc) == 0) 1370 ; 1371 ahc_outb(ahc, SEQCTL, PERRORDIS); 1372 ahc_outb(ahc, SCBPTR, 0); 1373 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1374 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1375 goto fail; 1376 1377 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1378 PCI_COMMAND_STATUS_REG + 1); 1379 if ((status1 & STA) != 0) 1380 goto fail; 1381 1382 error = 0; 1383 1384 fail: 1385 /* Silently clear any latched errors. */ 1386 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1387 PCI_COMMAND_STATUS_REG + 1); 1388 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1389 status1, /*bytes*/1); 1390 ahc_outb(ahc, CLRINT, CLRPARERR); 1391 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1392 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1393 return (error); 1394 } 1395 #endif 1396 1397 void 1398 ahc_pci_intr(struct ahc_softc *ahc) 1399 { 1400 u_int error; 1401 u_int status1; 1402 1403 error = ahc_inb(ahc, ERROR); 1404 if ((error & PCIERRSTAT) == 0) 1405 return; 1406 1407 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1408 PCI_COMMAND_STATUS_REG); 1409 1410 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1411 ahc_name(ahc), 1412 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1413 1414 if (status1 & DPE) { 1415 printf("%s: Data Parity Error Detected during address " 1416 "or write data phase\n", ahc_name(ahc)); 1417 } 1418 if (status1 & SSE) { 1419 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1420 } 1421 if (status1 & RMA) { 1422 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1423 } 1424 if (status1 & RTA) { 1425 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1426 } 1427 if (status1 & STA) { 1428 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1429 } 1430 if (status1 & DPR) { 1431 printf("%s: Data Parity Error has been reported via PERR#\n", 1432 ahc_name(ahc)); 1433 } 1434 1435 /* Clear latched errors. */ 1436 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, 1437 status1); 1438 1439 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1440 printf("%s: Latched PCIERR interrupt with " 1441 "no status bits set\n", ahc_name(ahc)); 1442 } else { 1443 ahc_outb(ahc, CLRINT, CLRPARERR); 1444 } 1445 1446 ahc_unpause(ahc); 1447 } 1448 1449 static int 1450 ahc_aic785X_setup(struct ahc_softc *ahc) 1451 { 1452 uint8_t rev; 1453 1454 ahc->channel = 'A'; 1455 ahc->chip = AHC_AIC7850; 1456 ahc->features = AHC_AIC7850_FE; 1457 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1458 rev = PCI_REVISION(ahc->bd->class); 1459 if (rev >= 1) 1460 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1461 return (0); 1462 } 1463 1464 static int 1465 ahc_aic7860_setup(struct ahc_softc *ahc) 1466 { 1467 uint8_t rev; 1468 1469 ahc->channel = 'A'; 1470 ahc->chip = AHC_AIC7860; 1471 ahc->features = AHC_AIC7860_FE; 1472 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1473 rev = PCI_REVISION(ahc->bd->class); 1474 if (rev >= 1) 1475 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1476 return (0); 1477 } 1478 1479 static int 1480 ahc_apa1480_setup(struct ahc_softc *ahc) 1481 { 1482 int error; 1483 1484 error = ahc_aic7860_setup(ahc); 1485 if (error != 0) 1486 return (error); 1487 ahc->features |= AHC_REMOVABLE; 1488 return (0); 1489 } 1490 1491 static int 1492 ahc_aic7870_setup(struct ahc_softc *ahc) 1493 { 1494 1495 ahc->channel = 'A'; 1496 ahc->chip = AHC_AIC7870; 1497 ahc->features = AHC_AIC7870_FE; 1498 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1499 return (0); 1500 } 1501 1502 static int 1503 ahc_aha394X_setup(struct ahc_softc *ahc) 1504 { 1505 int error; 1506 1507 error = ahc_aic7870_setup(ahc); 1508 if (error == 0) 1509 error = ahc_aha394XX_setup(ahc); 1510 return (error); 1511 } 1512 1513 static int 1514 ahc_aha398X_setup(struct ahc_softc *ahc) 1515 { 1516 int error; 1517 1518 error = ahc_aic7870_setup(ahc); 1519 if (error == 0) 1520 error = ahc_aha398XX_setup(ahc); 1521 return (error); 1522 } 1523 1524 static int 1525 ahc_aha494X_setup(struct ahc_softc *ahc) 1526 { 1527 int error; 1528 1529 error = ahc_aic7870_setup(ahc); 1530 if (error == 0) 1531 error = ahc_aha494XX_setup(ahc); 1532 return (error); 1533 } 1534 1535 static int 1536 ahc_aic7880_setup(struct ahc_softc *ahc) 1537 { 1538 uint8_t rev; 1539 1540 ahc->channel = 'A'; 1541 ahc->chip = AHC_AIC7880; 1542 ahc->features = AHC_AIC7880_FE; 1543 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1544 rev = PCI_REVISION(ahc->bd->class); 1545 if (rev >= 1) { 1546 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1547 } else { 1548 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1549 } 1550 return (0); 1551 } 1552 1553 static int 1554 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1555 { 1556 1557 ahc->flags |= AHC_INT50_SPEEDFLEX; 1558 return (ahc_aic7880_setup(ahc)); 1559 } 1560 1561 static int 1562 ahc_aha394XU_setup(struct ahc_softc *ahc) 1563 { 1564 int error; 1565 1566 error = ahc_aic7880_setup(ahc); 1567 if (error == 0) 1568 error = ahc_aha394XX_setup(ahc); 1569 return (error); 1570 } 1571 1572 static int 1573 ahc_aha398XU_setup(struct ahc_softc *ahc) 1574 { 1575 int error; 1576 1577 error = ahc_aic7880_setup(ahc); 1578 if (error == 0) 1579 error = ahc_aha398XX_setup(ahc); 1580 return (error); 1581 } 1582 1583 static int 1584 ahc_aic7890_setup(struct ahc_softc *ahc) 1585 { 1586 uint8_t rev; 1587 1588 ahc->channel = 'A'; 1589 ahc->chip = AHC_AIC7890; 1590 ahc->features = AHC_AIC7890_FE; 1591 ahc->flags |= AHC_NEWEEPROM_FMT; 1592 rev = PCI_REVISION(ahc->bd->class); 1593 if (rev == 0) 1594 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1595 return (0); 1596 } 1597 1598 static int 1599 ahc_aic7892_setup(struct ahc_softc *ahc) 1600 { 1601 1602 ahc->channel = 'A'; 1603 ahc->chip = AHC_AIC7892; 1604 ahc->features = AHC_AIC7892_FE; 1605 ahc->flags |= AHC_NEWEEPROM_FMT; 1606 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1607 return (0); 1608 } 1609 1610 static int 1611 ahc_aic7895_setup(struct ahc_softc *ahc) 1612 { 1613 uint8_t rev; 1614 1615 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1616 /* 1617 * The 'C' revision of the aic7895 has a few additional features. 1618 */ 1619 rev = PCI_REVISION(ahc->bd->class); 1620 if (rev >= 4) { 1621 ahc->chip = AHC_AIC7895C; 1622 ahc->features = AHC_AIC7895C_FE; 1623 } else { 1624 u_int command; 1625 1626 ahc->chip = AHC_AIC7895; 1627 ahc->features = AHC_AIC7895_FE; 1628 1629 /* 1630 * The BIOS disables the use of MWI transactions 1631 * since it does not have the MWI bug work around 1632 * we have. Disabling MWI reduces performance, so 1633 * turn it on again. 1634 */ 1635 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1636 PCI_COMMAND_STATUS_REG); 1637 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1638 pci_conf_write(ahc->bd->pc, ahc->bd->tag, 1639 PCI_COMMAND_STATUS_REG, command); 1640 ahc->bugs |= AHC_PCI_MWI_BUG; 1641 } 1642 /* 1643 * XXX Does CACHETHEN really not work??? What about PCI retry? 1644 * on C level chips. Need to test, but for now, play it safe. 1645 */ 1646 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1647 | AHC_CACHETHEN_BUG; 1648 1649 #if 0 1650 uint32_t devconfig; 1651 1652 /* 1653 * Cachesize must also be zero due to stray DAC 1654 * problem when sitting behind some bridges. 1655 */ 1656 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1657 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1658 devconfig |= MRDCEN; 1659 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1660 #endif 1661 ahc->flags |= AHC_NEWEEPROM_FMT; 1662 return (0); 1663 } 1664 1665 static int 1666 ahc_aic7896_setup(struct ahc_softc *ahc) 1667 { 1668 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1669 ahc->chip = AHC_AIC7896; 1670 ahc->features = AHC_AIC7896_FE; 1671 ahc->flags |= AHC_NEWEEPROM_FMT; 1672 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1673 return (0); 1674 } 1675 1676 static int 1677 ahc_aic7899_setup(struct ahc_softc *ahc) 1678 { 1679 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1680 ahc->chip = AHC_AIC7899; 1681 ahc->features = AHC_AIC7899_FE; 1682 ahc->flags |= AHC_NEWEEPROM_FMT; 1683 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1684 return (0); 1685 } 1686 1687 static int 1688 ahc_aha29160C_setup(struct ahc_softc *ahc) 1689 { 1690 int error; 1691 1692 error = ahc_aic7899_setup(ahc); 1693 if (error != 0) 1694 return (error); 1695 ahc->features |= AHC_REMOVABLE; 1696 return (0); 1697 } 1698 1699 static int 1700 ahc_raid_setup(struct ahc_softc *ahc) 1701 { 1702 printf("RAID functionality unsupported\n"); 1703 return (ENXIO); 1704 } 1705 1706 static int 1707 ahc_aha394XX_setup(struct ahc_softc *ahc) 1708 { 1709 1710 switch (ahc->bd->dev) { 1711 case AHC_394X_SLOT_CHANNEL_A: 1712 ahc->channel = 'A'; 1713 break; 1714 case AHC_394X_SLOT_CHANNEL_B: 1715 ahc->channel = 'B'; 1716 break; 1717 default: 1718 printf("adapter at unexpected slot %d\n" 1719 "unable to map to a channel\n", 1720 ahc->bd->dev); 1721 ahc->channel = 'A'; 1722 } 1723 return (0); 1724 } 1725 1726 static int 1727 ahc_aha398XX_setup(struct ahc_softc *ahc) 1728 { 1729 1730 switch (ahc->bd->dev) { 1731 case AHC_398X_SLOT_CHANNEL_A: 1732 ahc->channel = 'A'; 1733 break; 1734 case AHC_398X_SLOT_CHANNEL_B: 1735 ahc->channel = 'B'; 1736 break; 1737 case AHC_398X_SLOT_CHANNEL_C: 1738 ahc->channel = 'C'; 1739 break; 1740 default: 1741 printf("adapter at unexpected slot %d\n" 1742 "unable to map to a channel\n", 1743 ahc->bd->dev); 1744 ahc->channel = 'A'; 1745 break; 1746 } 1747 ahc->flags |= AHC_LARGE_SEEPROM; 1748 return (0); 1749 } 1750 1751 static int 1752 ahc_aha494XX_setup(struct ahc_softc *ahc) 1753 { 1754 1755 switch (ahc->bd->dev) { 1756 case AHC_494X_SLOT_CHANNEL_A: 1757 ahc->channel = 'A'; 1758 break; 1759 case AHC_494X_SLOT_CHANNEL_B: 1760 ahc->channel = 'B'; 1761 break; 1762 case AHC_494X_SLOT_CHANNEL_C: 1763 ahc->channel = 'C'; 1764 break; 1765 case AHC_494X_SLOT_CHANNEL_D: 1766 ahc->channel = 'D'; 1767 break; 1768 default: 1769 printf("adapter at unexpected slot %d\n" 1770 "unable to map to a channel\n", 1771 ahc->bd->dev); 1772 ahc->channel = 'A'; 1773 } 1774 ahc->flags |= AHC_LARGE_SEEPROM; 1775 return (0); 1776 }
Cache object: 5f68ed12a7e8db44b26ae72a18193737
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