Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/amrreg.h
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1 /* $NetBSD: amrreg.h,v 1.2 2003/05/04 16:15:36 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amrreg.h,v 1.2 2000/08/30 07:52:40 msmith Exp 66 */ 67 68 #ifndef _PCI_AMRREG_H_ 69 #define _PCI_AMRREG_H_ 70 71 #ifdef AMR_CRASH_ME 72 #define AMR_MAX_CMDS 255 /* ident = 0 not allowed */ 73 #else 74 #define AMR_MAX_CMDS 120 75 #endif 76 #define AMR_MAXLD 40 77 78 #define AMR_MAX_CMDS_PU 63 79 80 #define AMR_MAX_SEGS 26 81 #define AMR_MAX_CHANNEL 3 82 #define AMR_MAX_TARGET 15 83 #define AMR_MAX_LUN 7 84 85 #define AMR_MAX_CDB_LEN 0x0a 86 #define AMR_MAX_REQ_SENSE_LEN 0x20 87 88 #define AMR_SECTOR_SIZE 512 89 90 /* Mailbox commands.*/ 91 #define AMR_CMD_LREAD 0x01 92 #define AMR_CMD_LWRITE 0x02 93 #define AMR_CMD_PASS 0x03 94 #define AMR_CMD_EXT_ENQUIRY 0x04 95 #define AMR_CMD_ENQUIRY 0x05 96 #define AMR_CMD_FLUSH 0x0a 97 #define AMR_CMD_EXT_ENQUIRY2 0x0c 98 #define AMR_CMD_GET_MACHINEID 0x36 99 #define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 100 #define AMR_CMD_CONFIG 0xa1 101 #define AMR_CONFIG_PRODUCT_INFO 0x0e 102 #define AMR_CONFIG_ENQ3 0x0f 103 #define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 104 #define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 105 #define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 106 107 /* Command completion status. */ 108 #define AMR_STATUS_SUCCESS 0x00 109 #define AMR_STATUS_ABORTED 0x02 110 #define AMR_STATUS_FAILED 0x80 111 112 /* Physical/logical drive states. */ 113 #define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 114 #define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 115 #define AMR_DRV_OFFLINE 0x00 116 #define AMR_DRV_DEGRADED 0x01 117 #define AMR_DRV_OPTIMAL 0x02 118 #define AMR_DRV_ONLINE 0x03 119 #define AMR_DRV_FAILED 0x04 120 #define AMR_DRV_REBUILD 0x05 121 #define AMR_DRV_HOTSPARE 0x06 122 123 /* Logical drive properties. */ 124 #define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 125 #define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 126 #define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 127 #define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 128 129 /* Battery status. */ 130 #define AMR_BATT_MODULE_MISSING 0x01 131 #define AMR_BATT_LOW_VOLTAGE 0x02 132 #define AMR_BATT_TEMP_HIGH 0x04 133 #define AMR_BATT_PACK_MISSING 0x08 134 #define AMR_BATT_CHARGE_MASK 0x30 135 #define AMR_BATT_CHARGE_DONE 0x00 136 #define AMR_BATT_CHARGE_INPROG 0x10 137 #define AMR_BATT_CHARGE_FAIL 0x20 138 #define AMR_BATT_CYCLES_EXCEEDED 0x40 139 140 /* 141 * 8LD firmware interface. 142 */ 143 144 /* Array constraints. */ 145 #define AMR_8LD_MAXDRIVES 8 146 #define AMR_8LD_MAXCHAN 5 147 #define AMR_8LD_MAXTARG 15 148 #define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 149 150 /* Adapter information. */ 151 struct amr_adapter_info { 152 u_int8_t aa_maxio; 153 u_int8_t aa_rebuild_rate; 154 u_int8_t aa_maxtargchan; 155 u_int8_t aa_channels; 156 u_int8_t aa_firmware[4]; 157 u_int16_t aa_flashage; 158 u_int8_t aa_chipsetvalue; 159 u_int8_t aa_memorysize; 160 u_int8_t aa_cacheflush; 161 u_int8_t aa_bios[4]; 162 u_int8_t aa_boardtype; 163 u_int8_t aa_scsisensealert; 164 u_int8_t aa_writeconfigcount; 165 u_int8_t aa_driveinsertioncount; 166 u_int8_t aa_inserteddrive; 167 u_int8_t aa_batterystatus; 168 u_int8_t aa_res1; 169 } __attribute__ ((__packed__)); 170 171 /* Logical drive information. */ 172 struct amr_logdrive_info { 173 u_int8_t al_numdrives; 174 u_int8_t al_res1[3]; 175 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 176 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 177 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 178 } __attribute__ ((__packed__)); 179 180 /* Physical drive information. */ 181 struct amr_physdrive_info { 182 /* Low nybble is current state, high nybble is previous state. */ 183 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; 184 u_int8_t ap_predictivefailure; 185 } __attribute__ ((__packed__)); 186 187 /* 188 * Enquiry response structure for AMR_CMD_ENQUIRY (e), AMR_CMD_EXT_ENQUIRY (x) 189 * and AMR_CMD_EXT_ENQUIRY2 (2). 190 */ 191 struct amr_enquiry { 192 struct amr_adapter_info ae_adapter; /* e x 2 */ 193 struct amr_logdrive_info ae_ldrv; /* e x 2 */ 194 struct amr_physdrive_info ae_pdrv; /* e x 2 */ 195 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES]; /* x 2 */ 196 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* x 2 */ 197 u_int32_t ae_extlen; /* 2 */ 198 u_int16_t ae_subsystem; /* 2 */ 199 u_int16_t ae_subvendor; /* 2 */ 200 u_int32_t ae_signature; /* 2 */ 201 #define AMR_SIG_431 0xfffe0001 202 #define AMR_SIG_438 0xfffd0002 203 #define AMR_SIG_762 0xfffc0003 204 #define AMR_SIG_T5 0xfffb0004 205 #define AMR_SIG_466 0xfffa0005 206 #define AMR_SIG_467 0xfff90006 207 #define AMR_SIG_T7 0xfff80007 208 #define AMR_SIG_490 0xfff70008 209 u_int8_t res2[844]; /* 2 */ 210 } __attribute__ ((__packed__)); 211 212 /* 213 * 40LD firmware interface. 214 */ 215 216 /* Array constraints. */ 217 #define AMR_40LD_MAXDRIVES 40 218 #define AMR_40LD_MAXCHAN 16 219 #define AMR_40LD_MAXTARG 16 220 #define AMR_40LD_MAXPHYSDRIVES 256 221 222 /* Product information structure. */ 223 struct amr_prodinfo { 224 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 225 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 226 * logical drives, 0x20 maximum stripes and 0x08 227 * maximum spans */ 228 u_int8_t ap_firmware[16]; /* printable identifiers */ 229 u_int8_t ap_bios[16]; 230 u_int8_t ap_product[80]; 231 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 232 u_int8_t ap_nschan; /* number of SCSI channels present */ 233 u_int8_t ap_fcloops; /* number of fibre loops present */ 234 u_int8_t ap_memtype; /* memory type */ 235 u_int32_t ap_signature; 236 u_int16_t ap_memsize; /* onboard memory in MB */ 237 u_int16_t ap_subsystem; /* subsystem identifier */ 238 u_int16_t ap_subvendor; /* subsystem vendor ID */ 239 u_int8_t ap_numnotifyctr; /* number of notify counters */ 240 } __attribute__ ((__packed__)); 241 242 /* Notify structure. */ 243 struct amr_notify { 244 u_int32_t an_globalcounter; /* change counter */ 245 246 u_int8_t an_paramcounter; /* parameter change counter */ 247 u_int8_t an_paramid; 248 #define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 249 #define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 250 #define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 251 #define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 252 #define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 253 u_int16_t an_paramval; 254 255 u_int8_t an_writeconfigcounter; /* write config occurred */ 256 u_int8_t res1[3]; 257 258 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 259 u_int8_t an_ldrvopid; 260 u_int8_t an_ldrvopcmd; 261 #define AMR_LDRVOP_CHECK 0x01 262 #define AMR_LDRVOP_INIT 0x02 263 #define AMR_LDRVOP_REBUILD 0x03 264 u_int8_t an_ldrvopstatus; 265 #define AMR_LDRVOP_SUCCESS 0x00 266 #define AMR_LDRVOP_FAILED 0x01 267 #define AMR_LDRVOP_ABORTED 0x02 268 #define AMR_LDRVOP_CORRECTED 0x03 269 #define AMR_LDRVOP_STARTED 0x04 270 271 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 272 u_int8_t an_ldrvstateid; 273 u_int8_t an_ldrvstatenew; 274 u_int8_t an_ldrvstateold; 275 276 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 277 u_int8_t an_pdrvstateid; 278 u_int8_t an_pdrvstatenew; 279 u_int8_t an_pdrvstateold; 280 281 u_int8_t an_pdrvfmtcounter; 282 u_int8_t an_pdrvfmtid; 283 u_int8_t an_pdrvfmtval; 284 #define AMR_FORMAT_START 0x01 285 #define AMR_FORMAT_COMPLETE 0x02 286 u_int8_t res2; 287 288 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 289 u_int8_t an_targxferid; 290 u_int8_t an_targxferval; 291 u_int8_t res3; 292 293 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 294 u_int8_t an_fcloopidpdrvid; 295 u_int8_t an_fcloopid0; 296 u_int8_t an_fcloopid1; 297 298 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 299 u_int8_t an_fcloopstate0; 300 u_int8_t an_fcloopstate1; 301 u_int8_t res4; 302 } __attribute__ ((__packed__)); 303 304 /* Enquiry3 structure. */ 305 struct amr_enquiry3 { 306 u_int32_t ae_datasize; /* valid data size in this structure */ 307 union { /* event notify structure */ 308 struct amr_notify n; 309 u_int8_t pad[0x80]; 310 } ae_notify; 311 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 312 u_int8_t ae_cacheflush; /* flush interval in seconds */ 313 u_int8_t ae_sensealert; 314 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 315 u_int8_t ae_batterystatus; 316 u_int8_t ae_numldrives; 317 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 318 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 319 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 320 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 321 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */ 322 u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES]; 323 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 324 325 u_int8_t res1[263]; /* pad to 1024 bytes */ 326 } __attribute__ ((__packed__)); 327 328 /* 329 * Mailbox and command structures. 330 */ 331 332 struct amr_mailbox_cmd { 333 u_int8_t mb_command; 334 u_int8_t mb_ident; 335 u_int16_t mb_blkcount; 336 u_int32_t mb_lba; 337 u_int32_t mb_physaddr; 338 u_int8_t mb_drive; 339 u_int8_t mb_nsgelem; 340 u_int8_t res1; 341 u_int8_t mb_busy; 342 } __attribute__ ((__packed__)); 343 344 struct amr_mailbox_resp { 345 u_int8_t mb_nstatus; 346 u_int8_t mb_status; 347 u_int8_t mb_completed[46]; 348 } __attribute__ ((__packed__)); 349 350 struct amr_mailbox { 351 u_int32_t mb_res1[3]; 352 u_int32_t mb_segment; 353 struct amr_mailbox_cmd mb_cmd; 354 struct amr_mailbox_resp mb_resp; 355 u_int8_t mb_poll; 356 u_int8_t mb_ack; 357 u_int8_t res2[62]; /* Pad to 128+16 bytes. */ 358 } __attribute__ ((__packed__)); 359 360 struct amr_mailbox_ioctl { 361 u_int8_t mb_command; 362 u_int8_t mb_ident; 363 u_int8_t mb_channel; 364 u_int8_t mb_param; 365 u_int8_t mb_pad[4]; 366 u_int32_t mb_physaddr; 367 u_int8_t mb_drive; 368 u_int8_t mb_nsgelem; 369 u_int8_t res1; 370 u_int8_t mb_busy; 371 u_int8_t mb_nstatus; 372 u_int8_t mb_completed[46]; 373 u_int8_t mb_poll; 374 u_int8_t mb_ack; 375 u_int8_t res4[16]; 376 } __attribute__ ((__packed__)); 377 378 struct amr_sgentry { 379 u_int32_t sge_addr; 380 u_int32_t sge_count; 381 } __attribute__ ((__packed__)); 382 383 struct amr_passthrough { 384 u_int8_t ap_timeout:3; 385 u_int8_t ap_ars:1; 386 u_int8_t ap_dummy:3; 387 u_int8_t ap_islogical:1; 388 u_int8_t ap_logical_drive_no; 389 u_int8_t ap_channel; 390 u_int8_t ap_scsi_id; 391 u_int8_t ap_queue_tag; 392 u_int8_t ap_queue_action; 393 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 394 u_int8_t ap_cdb_length; 395 u_int8_t ap_request_sense_length; 396 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 397 u_int8_t ap_no_sg_elements; 398 u_int8_t ap_scsi_status; 399 u_int32_t ap_data_transfer_address; 400 u_int32_t ap_data_transfer_length; 401 } __attribute__ ((__packed__)); 402 403 /* 404 * "Quartz" i960 PCI bridge interface. 405 */ 406 407 #define AMR_QUARTZ_SIG_REG 0xa0 408 #define AMR_QUARTZ_SIG0 0xcccc 409 #define AMR_QUARTZ_SIG1 0x3344 410 411 /* Doorbell registers. */ 412 #define AMR_QREG_IDB 0x20 413 #define AMR_QREG_ODB 0x2c 414 415 #define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 416 #define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 417 #define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 418 419 /* 420 * Old-style ("standard") ASIC bridge interface. 421 */ 422 423 /* I/O registers. */ 424 #define AMR_SREG_CMD 0x10 /* Command/ack register (w) */ 425 #define AMR_SREG_MBOX_BUSY 0x10 /* Mailbox status (r) */ 426 #define AMR_SREG_TOGL 0x11 /* Interrupt enable */ 427 #define AMR_SREG_MBOX 0x14 /* Mailbox physical address */ 428 #define AMR_SREG_MBOX_ENABLE 0x18 /* Atomic mailbox address enable */ 429 #define AMR_SREG_INTR 0x1a /* Interrupt status */ 430 431 /* I/O magic numbers. */ 432 #define AMR_SCMD_POST 0x10 /* in SCMD to initiate action on mailbox */ 433 #define AMR_SCMD_ACKINTR 0x08 /* in SCMD to ack mailbox retrieved */ 434 #define AMR_STOGL_ENABLE 0xc0 /* in STOGL */ 435 #define AMR_SINTR_VALID 0x40 /* in SINTR */ 436 #define AMR_SMBOX_BUSY_FLAG 0x10 /* in SMBOX_BUSY */ 437 #define AMR_SMBOX_ENABLE_ADDR 0x00 /* in SMBOX_ENABLE */ 438 439 #endif /* !_PCI_AMRREG_H_ */
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