Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/btvmeireg.h
Version:
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1 /* $NetBSD: btvmeireg.h,v 1.4 2004/02/24 15:16:05 wiz Exp $ */ 2 3 #ifndef _bit3reg_h_ 4 #define _bit3reg_h_ 5 6 #ifdef _KERNEL 7 8 #define BIT3_LSR_BITS "\2\1CABLE\2LRCERR\3ITO\6INTPR\7RBERR\10PARERR" 9 10 /* following is from: 11 ** Filename: btpciio.h 12 ** 13 ** Purpose: Bit 3 400-809 PCI Applications Toolkit 14 ** Adaptor Node Register Include File. 15 */ 16 17 /****************************************************************************** 18 ** 19 ** Mapping Register Defines 20 ** 21 ******************************************************************************/ 22 23 #define MR_PCI_VME 0x0 /* PCI to VME Map RAM base offset */ 24 #define MR_PCI_VME_SIZE 0x8000 /* PCI to VME Map RAM size (bytes) */ 25 26 #define MR_VME_PCI 0x8000 /* VME to PCI Map RAM base offset */ 27 #define MR_VME_PCI_SIZE 0x4000 /* VME to PCI Map RAM size (bytes) */ 28 29 #define MR_DMA_PCI 0xC000 /* DMA to PCI Map RAM base offset */ 30 #define MR_DMA_PCI_SIZE 0x4000 /* DMA to PCI Map RAM size (bytes) */ 31 32 #define MR_BYTE_SWAP (1<<3) /* r/w, Byte swap bytes */ 33 #define MR_WORD_SWAP (1<<2) /* r/w, Swap words */ 34 #define MR_WBYTE_SWAP (1<<1) /* r/w, Byte Swap non-bytes */ 35 #define MR_RAM_INVALID (1<<0) /* r/w, Map register is invalid */ 36 37 #define MR_ADDR_MASK 0xFFFFF000UL /* Mask for map address bits A31-A12 */ 38 #define MR_REM_BUS_MASK 0x00000FFFUL /* Mask for remote address bits A11-A0 */ 39 40 #define MR_AMOD_MASK 0x00000FC0UL /* Mask for address modifier bits */ 41 /* AM5-AM0 for register bits A11-A6 */ 42 #define MR_AMOD_SHIFT 6 /* Shift value for AMOD bits AM5-AM0 */ 43 44 #define MR_FC_MASK 0x30 /* Mask for Mapping RAM Function Codes */ 45 #define MR_FC_RBIO 0x10 /* Remote Bus I/O Mapping function code */ 46 #define MR_FC_RRAM 0x20 /* Remote RAM Mapping function code */ 47 #define MR_FC_DPRAM 0x30 /* Dual Port RAM Mapping function code */ 48 49 50 51 /****************************************************************************** 52 ** 53 ** Local Adaptor Node Registers 54 ** 55 ******************************************************************************* 56 ** 57 ** Local Command Register (Read/Write, 8 Bits) 58 ** 59 ******************************************************************************* 60 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 61 ** +C_STAT |+CLR_PR |+SND_PT | | | | | 62 ******************************************************************************/ 63 64 #define LOC_CMD1 (0x00) /* Local Command Register */ 65 66 #define LC1_CLR_ERROR (1<<7) /* w, Clear status error bits (1 Shot) */ 67 #define LC1_CLR_PR_INT (1<<6) /* w, Clear PR (PS) Interrupt (1 Shot) */ 68 #define LC1_SND_PT_INT (1<<5) /* r/w, Set PT Interrupt */ 69 70 /****************************************************************************** 71 ** 72 ** Local Interrupt Control Register (Read/Write, 8 Bits) 73 ** 74 ******************************************************************************* 75 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 76 ** +INT_ACT | +INT_EN |+ERR_INT | 0 | 0 | +CINT2 | +CINT1 | +CINT0 77 ******************************************************************************/ 78 79 #define LOC_INT_CTRL (0x01) /* Local Interrupt Control Register */ 80 81 #define LIC_INT_PENDING (1<<7) /* r , Adaptor asserting INT on PCI bus */ 82 #define LIC_INT_ENABLE (1<<6) /* r/w, Normal (PR & CINT) INT Enable */ 83 #define LIC_ERR_INT_ENABLE (1<<5) /* r/w, Error Interrupt Enable */ 84 85 #define LIC_PT_CINT_SEL2 (1<<2) /* r/w, PT CINT Line Selection Bit 2 */ 86 #define LIC_PT_CINT_SEL1 (1<<1) /* r/w, PT CINT Line Selection Bit 1 */ 87 #define LIC_PT_CINT_SEL0 (1<<0) /* r/w, PT CINT Line Selection Bit 0 */ 88 89 90 /****************************************************************************** 91 ** 92 ** Local Status Register (Read Only, 8 Bits) 93 ** 94 ******************************************************************************* 95 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 96 ** +PARITY |+REMBUS |+PR_INT |+CARD_RDY| 0 |+TIMEOUT|+LRC_ERR|+NOCONNECT 97 ******************************************************************************/ 98 99 #define LOC_STATUS (0x02) /* Local Status Register */ 100 101 #define LSR_PARITY_ERR (1<<7) /* Interface Parity Error PCI->REM. */ 102 #define LSR_REMBUS_ERR (1<<6) /* BERR from VME on PCI->REM. xfer */ 103 #define LSR_PR_STATUS (1<<5) /* PR interrupt received from REMOTE */ 104 #define LSR_TIMEOUT_ERR (1<<2) /* Interface Timeout error PCI->REM */ 105 #define LSR_LRC_ERR (1<<1) /* LRC error (DMA master only) */ 106 #define LSR_NO_CONNECT (1<<0) /* REM. bus power or I/O cable is off */ 107 108 #define LSR_ERROR_MASK (LSR_PARITY_ERR|LSR_REMBUS_ERR|LSR_TIMEOUT_ERR|LSR_LRC_ERR) 109 #define LSR_CERROR_MASK (LSR_NO_CONNECT|LSR_ERROR_MASK) 110 111 112 /****************************************************************************** 113 ** 114 ** Local Interrupt Status Register (Read Only) 115 ** 116 ******************************************************************************* 117 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 118 ** +CINT7 | +CINT6 | +CINT5 | +CINT4 | +CINT3 | +CINT2 | +CINT1 | +CINT0 119 ******************************************************************************/ 120 121 #define LOC_INT_STATUS (0x03) /* Local Interrupt Status Register */ 122 123 #define LIS_CINT7 (1<<7) /* Cable Interrupt 7 - CINT7 */ 124 #define LIS_CINT6 (1<<6) /* Cable Interrupt 6 - CINT6 */ 125 #define LIS_CINT5 (1<<5) /* Cable Interrupt 5 - CINT5 */ 126 #define LIS_CINT4 (1<<4) /* Cable Interrupt 4 - CINT4 */ 127 #define LIS_CINT3 (1<<3) /* Cable Interrupt 3 - CINT3 */ 128 #define LIS_CINT2 (1<<2) /* Cable Interrupt 2 - CINT2 */ 129 #define LIS_CINT1 (1<<1) /* Cable Interrupt 1 - CINT1 */ 130 131 #define LIS_CINT_MASK (LIS_CINT1 | LIS_CINT2 | LIS_CINT3 | LIS_CINT4 | LIS_CINT5 | LIS_CINT6 | LIS_CINT7 ) 132 133 134 135 /****************************************************************************** 136 ** 137 ** Remote Adaptor Registers 138 ** 139 ******************************************************************************* 140 ** 141 ** Remote Command Register 1 (Write Only, 8 Bits) 142 ** 143 ******************************************************************************* 144 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 145 ** +RESET |+CLR_PT | +SND_PR |+LOCKBUS| +PGMODE| +IACK2 | +IACK1 | +IACK0|VME 146 ** " | " | " | " | " |+IOPGSEL|+PRMOD1 |+PRMOD0|Q-bus 147 ** " | " | " | " | " |+IOPGSEL| 0 | 0 |MBus1 148 ******************************************************************************/ 149 150 #define REM_CMD1 (0x08) /* Remote Command Register 1 */ 151 152 #define RC1_RESET_REM (1<<7) /* Reset remote bus - ONE SHOT */ 153 #define RC1_CLR_PT_INT (1<<6) /* PT (PM) interrupt - FROM REMOTE */ 154 #define RC1_SND_PR_INT (1<<5) /* PR (PS) interrupt - TO REMOTE */ 155 #define RC1_LOCK_REM_BUS (1<<4) /* Lock remote bus - FOR RMW ONLY */ 156 #define RC1_PG_SEL (1<<3) /* Enable page mode access */ 157 158 #define RC1_INT_ACK_A3 (1<<2) /* IACK Read Mode Address Bit 2 */ 159 #define RC1_INT_ACK_A2 (1<<1) /* IACK Read Mode Address Bit 1 */ 160 #define RC1_INT_ACK_A1 (1<<0) /* IACK Read Mode Address Bit 0 */ 161 162 #define RC1_IACK_MASK (0x07) /* IACK read level select mask */ 163 164 165 /***************************************************************************** 166 ** 167 ** Remote Status Register (Read Only, 8 Bits) 168 ** 169 ****************************************************************************** 170 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 171 ** +RRESET | IACK_1 | +PRSET | +LKNSET| +PGREG |IACK_2|+PTSET|IACK_0|VME 172 ** 0 | 0 | +PRSET | +LKNSET| +PGMOD | 0 |+PTSET| 0 |A24,Q,MB1 173 *****************************************************************************/ 174 175 #define REM_STATUS (0x08) /* Remote Status Register */ 176 177 #define RSR_PR_STATUS (1<<5) /* PR Interrupt is set */ 178 #define RSR_NOT_LOCK_STATUS (1<<4) /* Remote bus is *NOT* locked */ 179 #define RSR_PG_STATUS (1<<3) /* Page mode access is Enabled */ 180 #define RSR_PT_STATUS (1<<1) /* PT interrupt is set */ 181 182 /* The following bits apply to A32 VMEbus products ONLY */ 183 #define RSR_WAS_RESET (1<<7) /* Remote bus was reset */ 184 #define RSR_IACK2 (1<<2) /* IACK Read Mode Address Bit 2 */ 185 #define RSR_IACK1 (1<<6) /* IACK Read Mode Address Bit 1 */ 186 #define RSR_IACK0 (1<<0) /* IACK Read Mode Address Bit 0 */ 187 188 189 /****************************************************************************** 190 ** 191 ** Remote Command Register 2 (Read/Write, 8 Bits) 192 ** THIS REGISTER DOES NOT APPLY TO A24 VMEbus 193 ** 194 ******************************************************************************* 195 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 196 ** +DMA_PAUS | +AMOD_SEL | +DMA_BLK | +INT_DIS | PGSZ3 | PGSZ2 | PGSZ1 | PGSZ0 197 ******************************************************************************/ 198 199 #define REM_CMD2 (0x09) /* Remote Command Register 2 */ 200 201 /* The following bits apply to A32 DMA VMEbus products only */ 202 #define RC2_DMA_PAUSE (1<<7) /* DMA remote pause after 16 xfers */ 203 #define RC2_REM_AMOD_SEL (1<<6) /* Use remote address modifier reg. */ 204 #define RC2_DMA_BLK_SEL (1<<5) /* Use remote block-mode DMA operatn */ 205 #define RC2_CINT_DISABLE (1<<4) /* Disable passing of rem cable intr */ 206 207 /* The following bits apply to all products */ 208 #define RC2_PG_SIZE_64K (0x00) /* 64K Page Size */ 209 #define RC2_PG_SIZE_128K (0x01) /* 128K Page Size */ 210 #define RC2_PG_SIZE_256K (0x03) /* 256K Page Size */ 211 #define RC2_PG_SIZE_512K (0x07) /* 512K Page Size */ 212 #define RC2_PG_SIZE_1MB (0x0F) /* 1M Page Size */ 213 214 #define RC2_PG_SIZE_MASK (0x0F) /* Page Size select mask */ 215 216 217 /****************************************************************************** 218 ** 219 ** Remote Node Address Page Register (Read/Write, 16 Bits) 220 ** 221 ******************************************************************************/ 222 223 #define REM_PAGE (0x0A) /* Remote Address Page Register */ 224 225 #define REM_PAGE_LO (0x0A) /* Address page byte - A16-A23 */ 226 227 /* The following define applies to A32 VMEbus products only */ 228 #define REM_PAGE_HI (0x0B) /* Address page byte - A24-A31 */ 229 230 #define MIN_PAGE_SHIFT 16 /* 64k is minimum size (shift value) */ 231 #define MAX_PAGE_SHIFT 20 /* 1MB maximum page size (shift value) */ 232 233 #define QBUS_PG_MAX (0x3F) /* Needed for "bt_remid" to identify QBUS */ 234 235 236 /****************************************************************************** 237 ** 238 ** Remote Card ID Register (Read/Write, 8 Bits) 239 ** A32 Products Only 240 ** 241 ******************************************************************************/ 242 243 #define REM_CARD_ID (0x0C) /* Remote Card ID Register */ 244 245 246 /****************************************************************************** 247 ** 248 ** Remote Address Modifier Register (Read/Write, 8 Bits) 249 ** VMEbus Products Only 250 ** 251 ******************************************************************************/ 252 253 #define REM_AMOD (0x0D) /* Remote Address Modifier Register */ 254 255 256 /****************************************************************************** 257 ** 258 ** IACK Read Register (Read Only) 259 ** VMEbus & Q-bus Only 260 ** 261 ******************************************************************************/ 262 263 #define REM_IACK (0x0E) /* IACK Read Register */ 264 265 #define REM_IACK_WORD (0x0E) /* IACK vector-D0-D7(word) */ 266 #define REM_IACK_BYTE (0x0F) /* IACK vector-D0-D7(byte)D8-D15(word) */ 267 268 269 270 /****************************************************************************** 271 ** 272 ** DMA Registers 273 ** 274 ******************************************************************************* 275 ** 276 ** Local DMA Command Register (Read/Write, 8 Bits) 277 ** 278 ******************************************************************************* 279 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 280 ** +LDC_START | +DP_SEL | +WRT_SEL | +D32_SEL | 0 | +INT_EN | +DMA_DN | 0 281 ******************************************************************************/ 282 283 #define LDMA_CMD (0x10) /* Local DMA Command Register */ 284 285 #define LDC_START (1<<7) /* Start DMA */ 286 #define LDC_DP_SEL (1<<6) /* DMA to Dual-Port select */ 287 #define LDC_WRITE_SEL (1<<5) /* DMA transfer direction */ 288 #define LDC_DMA_D32_SEL (1<<4) /* DMA transfer size 16 / 32 bit data */ 289 #define LDC_DMA_INT_ENABLE (1<<2) /* DMA done interrupt enable */ 290 #define LDC_DMA_DONE (1<<1) /* DMA done indicator flag */ 291 #define LDC_DMA_ACTIVE (1<<0) /* DMA in progress indicator flag */ 292 293 294 /****************************************************************************** 295 ** 296 ** Local DMA Remainder Count Register (Read/Write, 8 Bits) 297 ** 298 ******************************************************************************/ 299 300 #define LDMA_RMD_CNT (0x11) /* Local DMA Remainder Count Register */ 301 302 303 /******************************************************************************* 304 ** 305 ** Local DMA Packet Count Register (Read/Write, 16 Bits) 306 ** 307 *******************************************************************************/ 308 309 #define LDMA_PKT_CNT (0x12) /* Local DMA Packet Count Register */ 310 311 #define LDMA_PKT_CNT_LO (0x12) /* Packet Count Byte - D0-D7 */ 312 #define LDMA_PKT_CNT_HI (0x13) /* Packet Count Byte - D8-D15 */ 313 314 #define LDMA_MIN_DMA_PKT_SIZE 4UL /* Minimum DMA Packet Size In Bytes */ 315 #define LDMA_DMA_PKT_SIZE 8UL /* Standard DMA Packet Size Shift Val */ 316 #define LDMA_MAX_XFER_LEN 0xFFFFFFL /* Maximum DMA transfer Size In Bytes */ 317 318 319 /****************************************************************************** 320 ** 321 ** Local DMA Address Registers (Read/Write) 322 ** 323 *******************************************************************************/ 324 #define LDMA_ADDR (0x14) /* Local DMA Address [indexes DMA map space] */ 325 326 #define LDMA_ADDR_LO (0x14) /* Local DMA Address Byte - D0-D7 */ 327 #define LDMA_ADDR_MID (0x15) /* Local DMA Address Byte - D8-D15 */ 328 #define LDMA_ADDR_HI (0x16) /* Local DMA Address Byte - D8-D15 */ 329 330 331 332 /****************************************************************************** 333 ** 334 ** Remote DMA Packet Length Count Register (Read/Write) 335 ** 336 ******************************************************************************/ 337 #define RDMA_LEN_CNT (0x18) /* Remote DMA 1st packet size */ 338 339 340 /****************************************************************************** 341 ** 342 ** Remote DMA Address Register (Read/Write) 343 ** 344 ******************************************************************************/ 345 #define RDMA_ADDR (0x1A) /* Remote DMA Address */ 346 347 #define RDMA_ADDR_HI (0x1A) /* Remote DMA Address (A31-A16) */ 348 #define RDMA_ADDR_LO (0x1C) /* Remote DMA Address (A15-A0) */ 349 350 351 /****************************************************************************** 352 ** 353 ** Remote Slave Status Register (Read Only, 8 Bits) 354 ** 355 ******************************************************************************* 356 ** 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 357 ** +PARITY |+REMBUS |+PR_INT |+CARD_RDY| 0 |+TIMEOUT|+LRC_ERR|+NOCONNECT 358 ******************************************************************************/ 359 360 #define REM_SLAVE_STATUS (0x1F) /* Local Status of remote card */ 361 362 #define RSS_PARITY_ERR (1<<7) /* Interface Parity Error Remote->PCI */ 363 #define RSS_REMBUS_ERR (1<<6) /* Invalid mapping RAM access or a */ 364 /* data parity error occurred */ 365 #define RSS_PR_STATUS (1<<5) /* PR interrupt set on the VME card */ 366 #define RSS_TIMEOUT_ERR (1<<2) /* Interface Timeout error on DMA xfer */ 367 #define RSS_PT_STATUS (1<<1) /* PT interrupt set on the VME card */ 368 #define RSS_NO_CONNECT (1<<0) /* Rem. bus power / I/O cable is off */ 369 370 #define RSS_ERROR_MASK (RSS_PARITY_ERR|RSS_REMBUS_ERR|RSS_TIMEOUT_ERR) 371 #define RSS_CERROR_MASK (RSS_NO_CONNECT|RSS_ERROR_MASK) 372 373 #endif /* KERNEL */ 374 375 #endif
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