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sys/dev/pci/cz.c
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1 /* $NetBSD: cz.c,v 1.29 2003/10/27 07:07:34 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only use RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.29 2003/10/27 07:07:34 chs Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 90 #include <sys/callout.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/czreg.h> 96 97 #include <dev/pci/plx9060reg.h> 98 #include <dev/pci/plx9060var.h> 99 100 #include <dev/microcode/cyclades-z/cyzfirm.h> 101 102 #define CZ_DRIVER_VERSION 0x20000411 103 104 #define CZ_POLL_MS 20 105 106 /* These are the interrupts we always use. */ 107 #define CZ_INTERRUPTS \ 108 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 109 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 110 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 111 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 112 113 /* 114 * cztty_softc: 115 * 116 * Per-channel (TTY) state. 117 */ 118 struct cztty_softc { 119 struct cz_softc *sc_parent; 120 struct tty *sc_tty; 121 122 struct callout sc_diag_ch; 123 124 int sc_channel; /* Also used to flag unattached chan */ 125 #define CZTTY_CHANNEL_DEAD -1 126 127 bus_space_tag_t sc_chan_st; /* channel space tag */ 128 bus_space_handle_t sc_chan_sh; /* channel space handle */ 129 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 130 131 u_int sc_overflows, 132 sc_parity_errors, 133 sc_framing_errors, 134 sc_errors; 135 136 int sc_swflags; 137 138 u_int32_t sc_rs_control_dtr, 139 sc_chanctl_hw_flow, 140 sc_chanctl_comm_baud, 141 sc_chanctl_rs_control, 142 sc_chanctl_comm_data_l, 143 sc_chanctl_comm_parity; 144 }; 145 146 /* 147 * cz_softc: 148 * 149 * Per-board state. 150 */ 151 struct cz_softc { 152 struct device cz_dev; /* generic device info */ 153 struct plx9060_config cz_plx; /* PLX 9060 config info */ 154 bus_space_tag_t cz_win_st; /* window space tag */ 155 bus_space_handle_t cz_win_sh; /* window space handle */ 156 struct callout cz_callout; /* callout for polling-mode */ 157 158 void *cz_ih; /* interrupt handle */ 159 160 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 161 int cz_nchannels; /* number of channels */ 162 int cz_nopenchan; /* number of open channels */ 163 struct cztty_softc *cz_ports; /* our array of ports */ 164 165 bus_addr_t cz_fwctl; /* offset of firmware control */ 166 }; 167 168 int cz_match(struct device *, struct cfdata *, void *); 169 void cz_attach(struct device *, struct device *, void *); 170 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 171 172 CFATTACH_DECL(cz, sizeof(struct cz_softc), 173 cz_match, cz_attach, NULL, NULL); 174 175 void cz_reset_board(struct cz_softc *); 176 int cz_load_firmware(struct cz_softc *); 177 178 int cz_intr(void *); 179 void cz_poll(void *); 180 int cztty_transmit(struct cztty_softc *, struct tty *); 181 int cztty_receive(struct cztty_softc *, struct tty *); 182 183 struct cztty_softc * cztty_getttysoftc(dev_t dev); 184 int cztty_attached_ttys; 185 int cz_timeout_ticks; 186 187 void czttystart(struct tty *tp); 188 int czttyparam(struct tty *tp, struct termios *t); 189 void cztty_shutdown(struct cztty_softc *sc); 190 void cztty_modem(struct cztty_softc *sc, int onoff); 191 void cztty_break(struct cztty_softc *sc, int onoff); 192 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 193 int cztty_to_tiocm(struct cztty_softc *sc); 194 void cztty_diag(void *arg); 195 196 extern struct cfdriver cz_cd; 197 198 dev_type_open(czttyopen); 199 dev_type_close(czttyclose); 200 dev_type_read(czttyread); 201 dev_type_write(czttywrite); 202 dev_type_ioctl(czttyioctl); 203 dev_type_stop(czttystop); 204 dev_type_tty(czttytty); 205 dev_type_poll(czttypoll); 206 207 const struct cdevsw cz_cdevsw = { 208 czttyopen, czttyclose, czttyread, czttywrite, czttyioctl, 209 czttystop, czttytty, czttypoll, nommap, ttykqfilter, D_TTY 210 }; 211 212 /* Macros to clear/set/test flags. */ 213 #define SET(t, f) (t) |= (f) 214 #define CLR(t, f) (t) &= ~(f) 215 #define ISSET(t, f) ((t) & (f)) 216 217 /* 218 * Macros to read and write the PLX. 219 */ 220 #define CZ_PLX_READ(cz, reg) \ 221 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 222 #define CZ_PLX_WRITE(cz, reg, val) \ 223 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 224 (reg), (val)) 225 226 /* 227 * Macros to read and write the FPGA. We must already be in the FPGA 228 * window for this. 229 */ 230 #define CZ_FPGA_READ(cz, reg) \ 231 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 232 #define CZ_FPGA_WRITE(cz, reg, val) \ 233 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 234 235 /* 236 * Macros to read and write the firmware control structures in board RAM. 237 */ 238 #define CZ_FWCTL_READ(cz, off) \ 239 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 240 (cz)->cz_fwctl + (off)) 241 242 #define CZ_FWCTL_WRITE(cz, off, val) \ 243 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 244 (cz)->cz_fwctl + (off), (val)) 245 246 /* 247 * Convenience macros for cztty routines. PLX window MUST be to RAM. 248 */ 249 #define CZTTY_CHAN_READ(sc, off) \ 250 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 251 252 #define CZTTY_CHAN_WRITE(sc, off, val) \ 253 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 254 (off), (val)) 255 256 #define CZTTY_BUF_READ(sc, off) \ 257 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 258 259 #define CZTTY_BUF_WRITE(sc, off, val) \ 260 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 261 (off), (val)) 262 263 /* 264 * Convenience macros. 265 */ 266 #define CZ_WIN_RAM(cz) \ 267 do { \ 268 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 269 delay(100); \ 270 } while (0) 271 272 #define CZ_WIN_FPGA(cz) \ 273 do { \ 274 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 275 delay(100); \ 276 } while (0) 277 278 /***************************************************************************** 279 * Cyclades-Z controller code starts here... 280 *****************************************************************************/ 281 282 /* 283 * cz_match: 284 * 285 * Determine if the given PCI device is a Cyclades-Z board. 286 */ 287 int 288 cz_match(struct device *parent, 289 struct cfdata *match, 290 void *aux) 291 { 292 struct pci_attach_args *pa = aux; 293 294 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 295 switch (PCI_PRODUCT(pa->pa_id)) { 296 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 297 return (1); 298 } 299 } 300 301 return (0); 302 } 303 304 /* 305 * cz_attach: 306 * 307 * A Cyclades-Z board was found; attach it. 308 */ 309 void 310 cz_attach(struct device *parent, 311 struct device *self, 312 void *aux) 313 { 314 struct cz_softc *cz = (void *) self; 315 struct pci_attach_args *pa = aux; 316 pci_intr_handle_t ih; 317 const char *intrstr = NULL; 318 struct cztty_softc *sc; 319 struct tty *tp; 320 int i; 321 322 aprint_naive(": Multi-port serial controller\n"); 323 aprint_normal(": Cyclades-Z multiport serial\n"); 324 325 cz->cz_plx.plx_pc = pa->pa_pc; 326 cz->cz_plx.plx_tag = pa->pa_tag; 327 328 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 329 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 330 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 331 aprint_error("%s: unable to map PLX registers\n", 332 cz->cz_dev.dv_xname); 333 return; 334 } 335 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 336 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 337 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 338 aprint_error("%s: unable to map device window\n", 339 cz->cz_dev.dv_xname); 340 return; 341 } 342 343 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 344 cz->cz_nopenchan = 0; 345 346 /* 347 * Make sure that the board is completely stopped. 348 */ 349 CZ_WIN_FPGA(cz); 350 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 351 352 /* 353 * Load the board's firmware. 354 */ 355 if (cz_load_firmware(cz) != 0) 356 return; 357 358 /* 359 * Now that we're ready to roll, map and establish the interrupt 360 * handler. 361 */ 362 if (pci_intr_map(pa, &ih) != 0) { 363 /* 364 * The common case is for Cyclades-Z boards to run 365 * in polling mode, and thus not have an interrupt 366 * mapped for them. Don't bother reporting that 367 * the interrupt is not mappable, since this isn't 368 * really an error. 369 */ 370 cz->cz_ih = NULL; 371 goto polling_mode; 372 } else { 373 intrstr = pci_intr_string(pa->pa_pc, ih); 374 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 375 cz_intr, cz); 376 } 377 if (cz->cz_ih == NULL) { 378 aprint_error("%s: unable to establish interrupt", 379 cz->cz_dev.dv_xname); 380 if (intrstr != NULL) 381 aprint_normal(" at %s", intrstr); 382 aprint_normal("\n"); 383 /* We will fall-back on polling mode. */ 384 } else 385 aprint_normal("%s: interrupting at %s\n", 386 cz->cz_dev.dv_xname, intrstr); 387 388 polling_mode: 389 if (cz->cz_ih == NULL) { 390 callout_init(&cz->cz_callout); 391 if (cz_timeout_ticks == 0) 392 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 393 aprint_normal("%s: polling mode, %d ms interval (%d tick%s)\n", 394 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 395 cz_timeout_ticks == 1 ? "" : "s"); 396 } 397 398 /* 399 * Allocate sufficient pointers for the children and 400 * attach them. Set all ports to a reasonable initial 401 * configuration while we're at it: 402 * 403 * disabled 404 * 8N1 405 * default baud rate 406 * hardware flow control. 407 */ 408 CZ_WIN_RAM(cz); 409 410 if (cz->cz_nchannels == 0) { 411 /* No channels? No more work to do! */ 412 return; 413 } 414 415 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 416 M_DEVBUF, M_WAITOK|M_ZERO); 417 cztty_attached_ttys += cz->cz_nchannels; 418 419 for (i = 0; i < cz->cz_nchannels; i++) { 420 sc = &cz->cz_ports[i]; 421 422 sc->sc_channel = i; 423 sc->sc_chan_st = cz->cz_win_st; 424 sc->sc_parent = cz; 425 426 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 427 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 428 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 429 aprint_error( 430 "%s: unable to subregion channel %d control\n", 431 cz->cz_dev.dv_xname, i); 432 sc->sc_channel = CZTTY_CHANNEL_DEAD; 433 continue; 434 } 435 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 436 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 437 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 438 aprint_error( 439 "%s: unable to subregion channel %d buffer\n", 440 cz->cz_dev.dv_xname, i); 441 sc->sc_channel = CZTTY_CHANNEL_DEAD; 442 continue; 443 } 444 445 callout_init(&sc->sc_diag_ch); 446 447 tp = ttymalloc(); 448 tp->t_dev = makedev(cdevsw_lookup_major(&cz_cdevsw), 449 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 450 tp->t_oproc = czttystart; 451 tp->t_param = czttyparam; 452 tty_attach(tp); 453 454 sc->sc_tty = tp; 455 456 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 457 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 458 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 459 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 460 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 461 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 462 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 463 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 464 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 465 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 466 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 467 } 468 } 469 470 /* 471 * cz_reset_board: 472 * 473 * Reset the board via the PLX. 474 */ 475 void 476 cz_reset_board(struct cz_softc *cz) 477 { 478 u_int32_t reg; 479 480 reg = CZ_PLX_READ(cz, PLX_CONTROL); 481 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 482 delay(1000); 483 484 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 485 delay(1000); 486 487 /* Now reload the PLX from its EEPROM. */ 488 reg = CZ_PLX_READ(cz, PLX_CONTROL); 489 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 490 delay(1000); 491 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 492 } 493 494 /* 495 * cz_load_firmware: 496 * 497 * Load the ZFIRM firmware into the board's RAM and start it 498 * running. 499 */ 500 int 501 cz_load_firmware(struct cz_softc *cz) 502 { 503 struct zfirm_header *zfh; 504 struct zfirm_config *zfc; 505 struct zfirm_block *zfb, *zblocks; 506 const u_int8_t *cp; 507 const char *board; 508 u_int32_t fid; 509 int i, j, nconfigs, nblocks, nbytes; 510 511 zfh = (struct zfirm_header *) cycladesz_firmware; 512 513 /* Find the config header. */ 514 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 515 aprint_error("%s: bad ZFIRM config offset: 0x%x\n", 516 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 517 return (EIO); 518 } 519 zfc = (struct zfirm_config *)(cycladesz_firmware + 520 le32toh(zfh->zfh_configoff)); 521 nconfigs = le32toh(zfh->zfh_nconfig); 522 523 /* Locate the correct configuration for our board. */ 524 for (i = 0; i < nconfigs; i++, zfc++) { 525 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 526 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 527 break; 528 } 529 if (i == nconfigs) { 530 aprint_error("%s: unable to locate config header\n", 531 cz->cz_dev.dv_xname); 532 return (EIO); 533 } 534 535 nblocks = le32toh(zfc->zfc_nblocks); 536 zblocks = (struct zfirm_block *)(cycladesz_firmware + 537 le32toh(zfh->zfh_blockoff)); 538 539 /* 540 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 541 * necessary. 542 */ 543 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 544 #if 0 545 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 546 #endif 547 ) { 548 #ifdef CZ_DEBUG 549 aprint_debug("%s: Loading FPGA...", cz->cz_dev.dv_xname); 550 #endif 551 CZ_WIN_FPGA(cz); 552 for (i = 0; i < nblocks; i++) { 553 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 554 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 555 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 556 nbytes = le32toh(zfb->zfb_size); 557 cp = &cycladesz_firmware[ 558 le32toh(zfb->zfb_fileoff)]; 559 for (j = 0; j < nbytes; j++, cp++) { 560 bus_space_write_1(cz->cz_win_st, 561 cz->cz_win_sh, 0, *cp); 562 /* FPGA needs 30-100us to settle. */ 563 delay(10); 564 } 565 } 566 } 567 #ifdef CZ_DEBUG 568 aprint_debug("done\n"); 569 #endif 570 } 571 572 /* Now load the firmware. */ 573 CZ_WIN_RAM(cz); 574 575 for (i = 0; i < nblocks; i++) { 576 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 577 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 578 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 579 const u_int32_t *lp; 580 u_int32_t ro = le32toh(zfb->zfb_ramoff); 581 nbytes = le32toh(zfb->zfb_size); 582 lp = (const u_int32_t *) 583 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 584 for (j = 0; j < nbytes; j += 4, lp++) { 585 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 586 ro + j, le32toh(*lp)); 587 delay(10); 588 } 589 } 590 } 591 592 /* Now restart the MIPS. */ 593 CZ_WIN_FPGA(cz); 594 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 595 596 /* Wait for the MIPS to start, then report the results. */ 597 CZ_WIN_RAM(cz); 598 599 #ifdef CZ_DEBUG 600 aprint_debug("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 601 #endif 602 for (i = 0; i < 100; i++) { 603 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 604 ZFIRM_SIG_OFF); 605 if (fid == ZFIRM_SIG) { 606 /* MIPS has booted. */ 607 break; 608 } else if (fid == ZFIRM_HLT) { 609 /* 610 * The MIPS has halted, usually due to a power 611 * shortage on the expansion module. 612 */ 613 aprint_error("%s: MIPS halted; possible power supply " 614 "problem\n", cz->cz_dev.dv_xname); 615 return (EIO); 616 } else { 617 #ifdef CZ_DEBUG 618 if ((i % 8) == 0) 619 aprint_debug("."); 620 #endif 621 delay(250000); 622 } 623 } 624 #ifdef CZ_DEBUG 625 aprint_debug("\n"); 626 #endif 627 if (i == 100) { 628 CZ_WIN_FPGA(cz); 629 aprint_error( 630 "%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 631 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 632 aprint_error("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 633 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 634 CZ_FPGA_READ(cz, FPGA_VERSION)); 635 return (EIO); 636 } 637 638 /* 639 * Locate the firmware control structures. 640 */ 641 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 642 ZFIRM_CTRLADDR_OFF); 643 #ifdef CZ_DEBUG 644 aprint_debug("%s: FWCTL structure at offset 0x%08lx\n", 645 cz->cz_dev.dv_xname, cz->cz_fwctl); 646 #endif 647 648 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 649 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 650 651 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 652 653 switch (cz->cz_mailbox0) { 654 case MAILBOX0_8Zo_V1: 655 board = "Cyclades-8Zo ver. 1"; 656 break; 657 658 case MAILBOX0_8Zo_V2: 659 board = "Cyclades-8Zo ver. 2"; 660 break; 661 662 case MAILBOX0_Ze_V1: 663 board = "Cyclades-Ze"; 664 break; 665 666 default: 667 board = "unknown Cyclades Z-series"; 668 break; 669 } 670 671 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 672 aprint_normal("%s: %s, ", cz->cz_dev.dv_xname, board); 673 if (cz->cz_nchannels == 0) 674 aprint_normal("no channels attached, "); 675 else 676 aprint_normal("%d channels (ttyCZ%04d..ttyCZ%04d), ", 677 cz->cz_nchannels, cztty_attached_ttys, 678 cztty_attached_ttys + (cz->cz_nchannels - 1)); 679 aprint_normal("firmware %x.%x.%x\n", 680 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 681 682 return (0); 683 } 684 685 /* 686 * cz_poll: 687 * 688 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 689 * ms. 690 */ 691 void 692 cz_poll(void *arg) 693 { 694 int s = spltty(); 695 struct cz_softc *cz = arg; 696 697 cz_intr(cz); 698 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 699 700 splx(s); 701 } 702 703 /* 704 * cz_intr: 705 * 706 * Interrupt service routine. 707 * 708 * We either are receiving an interrupt directly from the board, or we are 709 * in polling mode and it's time to poll. 710 */ 711 int 712 cz_intr(void *arg) 713 { 714 int rval = 0; 715 u_int command, channel, param; 716 struct cz_softc *cz = arg; 717 struct cztty_softc *sc; 718 struct tty *tp; 719 720 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 721 rval = 1; 722 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 723 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 724 725 /* now clear this interrupt, posslibly enabling another */ 726 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 727 728 if (cz->cz_ports == NULL) { 729 #ifdef CZ_DEBUG 730 printf("%s: interrupt on channel %d, but no channels\n", 731 cz->cz_dev.dv_xname, channel); 732 #endif 733 continue; 734 } 735 736 sc = &cz->cz_ports[channel]; 737 738 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 739 break; 740 741 tp = sc->sc_tty; 742 743 switch (command) { 744 case C_CM_TXFEMPTY: /* transmit cases */ 745 case C_CM_TXBEMPTY: 746 case C_CM_TXLOWWM: 747 case C_CM_INTBACK: 748 if (!ISSET(tp->t_state, TS_ISOPEN)) { 749 #ifdef CZ_DEBUG 750 printf("%s: tx intr on closed channel %d\n", 751 cz->cz_dev.dv_xname, channel); 752 #endif 753 break; 754 } 755 756 if (cztty_transmit(sc, tp)) { 757 /* 758 * Do wakeup stuff here. 759 */ 760 ttwakeup(tp); 761 wakeup(tp); 762 } 763 break; 764 765 case C_CM_RXNNDT: /* receive cases */ 766 case C_CM_RXHIWM: 767 case C_CM_INTBACK2: /* from restart ?? */ 768 #if 0 769 case C_CM_ICHAR: 770 #endif 771 if (!ISSET(tp->t_state, TS_ISOPEN)) { 772 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 773 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 774 break; 775 } 776 777 if (cztty_receive(sc, tp)) { 778 /* 779 * Do wakeup stuff here. 780 */ 781 ttwakeup(tp); 782 wakeup(tp); 783 } 784 break; 785 786 case C_CM_MDCD: 787 if (!ISSET(tp->t_state, TS_ISOPEN)) 788 break; 789 790 (void) (*tp->t_linesw->l_modem)(tp, 791 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 792 CHNCTL_RS_STATUS))); 793 break; 794 795 case C_CM_MDSR: 796 case C_CM_MRI: 797 case C_CM_MCTS: 798 case C_CM_MRTS: 799 break; 800 801 case C_CM_IOCTLW: 802 break; 803 804 case C_CM_PR_ERROR: 805 sc->sc_parity_errors++; 806 goto error_common; 807 808 case C_CM_FR_ERROR: 809 sc->sc_framing_errors++; 810 goto error_common; 811 812 case C_CM_OVR_ERROR: 813 sc->sc_overflows++; 814 error_common: 815 if (sc->sc_errors++ == 0) 816 callout_reset(&sc->sc_diag_ch, 60 * hz, 817 cztty_diag, sc); 818 break; 819 820 case C_CM_RXBRK: 821 if (!ISSET(tp->t_state, TS_ISOPEN)) 822 break; 823 824 /* 825 * A break is a \000 character with TTY_FE error 826 * flags set. So TTY_FE by itself works. 827 */ 828 (*tp->t_linesw->l_rint)(TTY_FE, tp); 829 ttwakeup(tp); 830 wakeup(tp); 831 break; 832 833 default: 834 #ifdef CZ_DEBUG 835 printf("%s: channel %d: Unknown interrupt 0x%x\n", 836 cz->cz_dev.dv_xname, sc->sc_channel, command); 837 #endif 838 break; 839 } 840 } 841 842 return (rval); 843 } 844 845 /* 846 * cz_wait_pci_doorbell: 847 * 848 * Wait for the pci doorbell to be clear - wait for pending 849 * activity to drain. 850 */ 851 int 852 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 853 { 854 int error; 855 856 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 857 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 858 if ((error != 0) && (error != EWOULDBLOCK)) 859 return (error); 860 } 861 return (0); 862 } 863 864 /***************************************************************************** 865 * Cyclades-Z TTY code starts here... 866 *****************************************************************************/ 867 868 #define CZTTYDIALOUT_MASK 0x80000 869 870 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 871 #define CZTTY_CZ(sc) ((sc)->sc_parent) 872 873 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 874 875 struct cztty_softc * 876 cztty_getttysoftc(dev_t dev) 877 { 878 int i, j, k = 0, u = minor(dev) & ~CZTTYDIALOUT_MASK; 879 struct cz_softc *cz = NULL; 880 881 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 882 k = j; 883 cz = device_lookup(&cz_cd, i); 884 if (cz == NULL) 885 continue; 886 if (cz->cz_ports == NULL) 887 continue; 888 j += cz->cz_nchannels; 889 if (j > u) 890 break; 891 } 892 893 if (i >= cz_cd.cd_ndevs) 894 return (NULL); 895 else 896 return (&cz->cz_ports[u - k]); 897 } 898 899 /* 900 * czttytty: 901 * 902 * Return a pointer to our tty. 903 */ 904 struct tty * 905 czttytty(dev_t dev) 906 { 907 struct cztty_softc *sc = CZTTY_SOFTC(dev); 908 909 #ifdef DIAGNOSTIC 910 if (sc == NULL) 911 panic("czttytty"); 912 #endif 913 914 return (sc->sc_tty); 915 } 916 917 /* 918 * cztty_shutdown: 919 * 920 * Shut down a port. 921 */ 922 void 923 cztty_shutdown(struct cztty_softc *sc) 924 { 925 struct cz_softc *cz = CZTTY_CZ(sc); 926 struct tty *tp = sc->sc_tty; 927 int s; 928 929 s = spltty(); 930 931 /* Clear any break condition set with TIOCSBRK. */ 932 cztty_break(sc, 0); 933 934 /* 935 * Hang up if necessary. Wait a bit, so the other side has time to 936 * notice even if we immediately open the port again. 937 */ 938 if (ISSET(tp->t_cflag, HUPCL)) { 939 cztty_modem(sc, 0); 940 (void) tsleep(tp, TTIPRI, ttclos, hz); 941 } 942 943 /* Disable the channel. */ 944 cz_wait_pci_doorbell(cz, "czdis"); 945 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 946 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 947 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 948 949 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 950 #ifdef CZ_DEBUG 951 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 952 #endif 953 callout_stop(&cz->cz_callout); 954 } 955 956 splx(s); 957 } 958 959 /* 960 * czttyopen: 961 * 962 * Open a Cyclades-Z serial port. 963 */ 964 int 965 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 966 { 967 struct cztty_softc *sc = CZTTY_SOFTC(dev); 968 struct cz_softc *cz; 969 struct tty *tp; 970 int s, error; 971 972 if (sc == NULL) 973 return (ENXIO); 974 975 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 976 return (ENXIO); 977 978 cz = CZTTY_CZ(sc); 979 tp = sc->sc_tty; 980 981 if (ISSET(tp->t_state, TS_ISOPEN) && 982 ISSET(tp->t_state, TS_XCLUDE) && 983 p->p_ucred->cr_uid != 0) 984 return (EBUSY); 985 986 s = spltty(); 987 988 /* 989 * Do the following iff this is a first open. 990 */ 991 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 992 struct termios t; 993 994 tp->t_dev = dev; 995 996 /* If we're turning things on, enable interrupts */ 997 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 998 #ifdef CZ_DEBUG 999 printf("%s: Enabling polling.\n", 1000 cz->cz_dev.dv_xname); 1001 #endif 1002 callout_reset(&cz->cz_callout, cz_timeout_ticks, 1003 cz_poll, cz); 1004 } 1005 1006 /* 1007 * Enable the channel. Don't actually ring the 1008 * doorbell here; czttyparam() will do it for us. 1009 */ 1010 cz_wait_pci_doorbell(cz, "czopen"); 1011 1012 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1013 1014 /* 1015 * Initialize the termios status to the defaults. Add in the 1016 * sticky bits from TIOCSFLAGS. 1017 */ 1018 t.c_ispeed = 0; 1019 t.c_ospeed = TTYDEF_SPEED; 1020 t.c_cflag = TTYDEF_CFLAG; 1021 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1022 SET(t.c_cflag, CLOCAL); 1023 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1024 SET(t.c_cflag, CRTSCTS); 1025 1026 /* 1027 * Reset the input and output rings. Do this before 1028 * we call czttyparam(), as that function enables 1029 * the channel. 1030 */ 1031 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1032 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1033 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1034 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1035 1036 /* Make sure czttyparam() will see changes. */ 1037 tp->t_ospeed = 0; 1038 (void) czttyparam(tp, &t); 1039 tp->t_iflag = TTYDEF_IFLAG; 1040 tp->t_oflag = TTYDEF_OFLAG; 1041 tp->t_lflag = TTYDEF_LFLAG; 1042 ttychars(tp); 1043 ttsetwater(tp); 1044 1045 /* 1046 * Turn on DTR. We must always do this, even if carrier is not 1047 * present, because otherwise we'd have to use TIOCSDTR 1048 * immediately after setting CLOCAL, which applications do not 1049 * expect. We always assert DTR while the device is open 1050 * unless explicitly requested to deassert it. 1051 */ 1052 cztty_modem(sc, 1); 1053 } 1054 1055 splx(s); 1056 1057 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1058 if (error) 1059 goto bad; 1060 1061 error = (*tp->t_linesw->l_open)(dev, tp); 1062 if (error) 1063 goto bad; 1064 1065 return (0); 1066 1067 bad: 1068 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1069 /* 1070 * We failed to open the device, and nobody else had it opened. 1071 * Clean up the state as appropriate. 1072 */ 1073 cztty_shutdown(sc); 1074 } 1075 1076 return (error); 1077 } 1078 1079 /* 1080 * czttyclose: 1081 * 1082 * Close a Cyclades-Z serial port. 1083 */ 1084 int 1085 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1086 { 1087 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1088 struct tty *tp = sc->sc_tty; 1089 1090 /* XXX This is for cons.c. */ 1091 if (!ISSET(tp->t_state, TS_ISOPEN)) 1092 return (0); 1093 1094 (*tp->t_linesw->l_close)(tp, flags); 1095 ttyclose(tp); 1096 1097 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1098 /* 1099 * Although we got a last close, the device may still be in 1100 * use; e.g. if this was the dialout node, and there are still 1101 * processes waiting for carrier on the non-dialout node. 1102 */ 1103 cztty_shutdown(sc); 1104 } 1105 1106 return (0); 1107 } 1108 1109 /* 1110 * czttyread: 1111 * 1112 * Read from a Cyclades-Z serial port. 1113 */ 1114 int 1115 czttyread(dev_t dev, struct uio *uio, int flags) 1116 { 1117 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1118 struct tty *tp = sc->sc_tty; 1119 1120 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1121 } 1122 1123 /* 1124 * czttywrite: 1125 * 1126 * Write to a Cyclades-Z serial port. 1127 */ 1128 int 1129 czttywrite(dev_t dev, struct uio *uio, int flags) 1130 { 1131 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1132 struct tty *tp = sc->sc_tty; 1133 1134 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1135 } 1136 1137 /* 1138 * czttypoll: 1139 * 1140 * Poll a Cyclades-Z serial port. 1141 */ 1142 int 1143 czttypoll(dev, events, p) 1144 dev_t dev; 1145 int events; 1146 struct proc *p; 1147 { 1148 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1149 struct tty *tp = sc->sc_tty; 1150 1151 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1152 } 1153 1154 /* 1155 * czttyioctl: 1156 * 1157 * Perform a control operation on a Cyclades-Z serial port. 1158 */ 1159 int 1160 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1161 { 1162 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1163 struct tty *tp = sc->sc_tty; 1164 int s, error; 1165 1166 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 1167 if (error != EPASSTHROUGH) 1168 return (error); 1169 1170 error = ttioctl(tp, cmd, data, flag, p); 1171 if (error != EPASSTHROUGH) 1172 return (error); 1173 1174 error = 0; 1175 1176 s = spltty(); 1177 1178 switch (cmd) { 1179 case TIOCSBRK: 1180 cztty_break(sc, 1); 1181 break; 1182 1183 case TIOCCBRK: 1184 cztty_break(sc, 0); 1185 break; 1186 1187 case TIOCGFLAGS: 1188 *(int *)data = sc->sc_swflags; 1189 break; 1190 1191 case TIOCSFLAGS: 1192 error = suser(p->p_ucred, &p->p_acflag); 1193 if (error) 1194 break; 1195 sc->sc_swflags = *(int *)data; 1196 break; 1197 1198 case TIOCSDTR: 1199 cztty_modem(sc, 1); 1200 break; 1201 1202 case TIOCCDTR: 1203 cztty_modem(sc, 0); 1204 break; 1205 1206 case TIOCMSET: 1207 case TIOCMBIS: 1208 case TIOCMBIC: 1209 tiocm_to_cztty(sc, cmd, *(int *)data); 1210 break; 1211 1212 case TIOCMGET: 1213 *(int *)data = cztty_to_tiocm(sc); 1214 break; 1215 1216 default: 1217 error = EPASSTHROUGH; 1218 break; 1219 } 1220 1221 splx(s); 1222 1223 return (error); 1224 } 1225 1226 /* 1227 * cztty_break: 1228 * 1229 * Set or clear BREAK on a port. 1230 */ 1231 void 1232 cztty_break(struct cztty_softc *sc, int onoff) 1233 { 1234 struct cz_softc *cz = CZTTY_CZ(sc); 1235 1236 cz_wait_pci_doorbell(cz, "czbreak"); 1237 1238 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1239 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1240 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1241 } 1242 1243 /* 1244 * cztty_modem: 1245 * 1246 * Set or clear DTR on a port. 1247 */ 1248 void 1249 cztty_modem(struct cztty_softc *sc, int onoff) 1250 { 1251 struct cz_softc *cz = CZTTY_CZ(sc); 1252 1253 if (sc->sc_rs_control_dtr == 0) 1254 return; 1255 1256 cz_wait_pci_doorbell(cz, "czmod"); 1257 1258 if (onoff) 1259 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1260 else 1261 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1262 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1263 1264 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1265 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1266 } 1267 1268 /* 1269 * tiocm_to_cztty: 1270 * 1271 * Process TIOCM* ioctls. 1272 */ 1273 void 1274 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1275 { 1276 struct cz_softc *cz = CZTTY_CZ(sc); 1277 u_int32_t czttybits; 1278 1279 czttybits = 0; 1280 if (ISSET(ttybits, TIOCM_DTR)) 1281 SET(czttybits, C_RS_DTR); 1282 if (ISSET(ttybits, TIOCM_RTS)) 1283 SET(czttybits, C_RS_RTS); 1284 1285 cz_wait_pci_doorbell(cz, "cztiocm"); 1286 1287 switch (how) { 1288 case TIOCMBIC: 1289 CLR(sc->sc_chanctl_rs_control, czttybits); 1290 break; 1291 1292 case TIOCMBIS: 1293 SET(sc->sc_chanctl_rs_control, czttybits); 1294 break; 1295 1296 case TIOCMSET: 1297 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1298 SET(sc->sc_chanctl_rs_control, czttybits); 1299 break; 1300 } 1301 1302 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1303 1304 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1305 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1306 } 1307 1308 /* 1309 * cztty_to_tiocm: 1310 * 1311 * Process the TIOCMGET ioctl. 1312 */ 1313 int 1314 cztty_to_tiocm(struct cztty_softc *sc) 1315 { 1316 struct cz_softc *cz = CZTTY_CZ(sc); 1317 u_int32_t rs_status, op_mode; 1318 int ttybits = 0; 1319 1320 cz_wait_pci_doorbell(cz, "cztty"); 1321 1322 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1323 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1324 1325 if (ISSET(rs_status, C_RS_RTS)) 1326 SET(ttybits, TIOCM_RTS); 1327 if (ISSET(rs_status, C_RS_CTS)) 1328 SET(ttybits, TIOCM_CTS); 1329 if (ISSET(rs_status, C_RS_DCD)) 1330 SET(ttybits, TIOCM_CAR); 1331 if (ISSET(rs_status, C_RS_DTR)) 1332 SET(ttybits, TIOCM_DTR); 1333 if (ISSET(rs_status, C_RS_RI)) 1334 SET(ttybits, TIOCM_RNG); 1335 if (ISSET(rs_status, C_RS_DSR)) 1336 SET(ttybits, TIOCM_DSR); 1337 1338 if (ISSET(op_mode, C_CH_ENABLE)) 1339 SET(ttybits, TIOCM_LE); 1340 1341 return (ttybits); 1342 } 1343 1344 /* 1345 * czttyparam: 1346 * 1347 * Set Cyclades-Z serial port parameters from termios. 1348 * 1349 * XXX Should just copy the whole termios after making 1350 * XXX sure all the changes could be done. 1351 */ 1352 int 1353 czttyparam(struct tty *tp, struct termios *t) 1354 { 1355 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1356 struct cz_softc *cz = CZTTY_CZ(sc); 1357 u_int32_t rs_status; 1358 int ospeed, cflag; 1359 1360 ospeed = t->c_ospeed; 1361 cflag = t->c_cflag; 1362 1363 /* Check requested parameters. */ 1364 if (ospeed < 0) 1365 return (EINVAL); 1366 if (t->c_ispeed && t->c_ispeed != ospeed) 1367 return (EINVAL); 1368 1369 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1370 SET(cflag, CLOCAL); 1371 CLR(cflag, HUPCL); 1372 } 1373 1374 /* 1375 * If there were no changes, don't do anything. This avoids dropping 1376 * input and improves performance when all we did was frob things like 1377 * VMIN and VTIME. 1378 */ 1379 if (tp->t_ospeed == ospeed && 1380 tp->t_cflag == cflag) 1381 return (0); 1382 1383 /* Data bits. */ 1384 sc->sc_chanctl_comm_data_l = 0; 1385 switch (t->c_cflag & CSIZE) { 1386 case CS5: 1387 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1388 break; 1389 1390 case CS6: 1391 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1392 break; 1393 1394 case CS7: 1395 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1396 break; 1397 1398 case CS8: 1399 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1400 break; 1401 } 1402 1403 /* Stop bits. */ 1404 if (t->c_cflag & CSTOPB) { 1405 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1406 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1407 else 1408 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1409 } else 1410 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1411 1412 /* Parity. */ 1413 if (t->c_cflag & PARENB) { 1414 if (t->c_cflag & PARODD) 1415 sc->sc_chanctl_comm_parity = C_PR_ODD; 1416 else 1417 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1418 } else 1419 sc->sc_chanctl_comm_parity = C_PR_NONE; 1420 1421 /* 1422 * Initialize flow control pins depending on the current flow control 1423 * mode. 1424 */ 1425 if (ISSET(t->c_cflag, CRTSCTS)) { 1426 sc->sc_rs_control_dtr = C_RS_DTR; 1427 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1428 } else if (ISSET(t->c_cflag, MDMBUF)) { 1429 sc->sc_rs_control_dtr = 0; 1430 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1431 } else { 1432 /* 1433 * If no flow control, then always set RTS. This will make 1434 * the other side happy if it mistakenly thinks we're doing 1435 * RTS/CTS flow control. 1436 */ 1437 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1438 sc->sc_chanctl_hw_flow = 0; 1439 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1440 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1441 else 1442 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1443 } 1444 1445 /* Baud rate. */ 1446 sc->sc_chanctl_comm_baud = ospeed; 1447 1448 /* Copy to tty. */ 1449 tp->t_ispeed = 0; 1450 tp->t_ospeed = t->c_ospeed; 1451 tp->t_cflag = t->c_cflag; 1452 1453 /* 1454 * Now load the channel control structure. 1455 */ 1456 1457 cz_wait_pci_doorbell(cz, "czparam"); 1458 1459 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1460 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1461 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1462 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1463 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1464 1465 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1466 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1467 1468 cz_wait_pci_doorbell(cz, "czparam"); 1469 1470 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1471 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1472 1473 cz_wait_pci_doorbell(cz, "czparam"); 1474 1475 /* 1476 * Update the tty layer's idea of the carrier bit, in case we changed 1477 * CLOCAL. We don't hang up here; we only do that by explicit 1478 * request. 1479 */ 1480 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1481 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1482 1483 return (0); 1484 } 1485 1486 /* 1487 * czttystart: 1488 * 1489 * Start or restart transmission. 1490 */ 1491 void 1492 czttystart(struct tty *tp) 1493 { 1494 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1495 int s; 1496 1497 s = spltty(); 1498 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1499 goto out; 1500 1501 if (tp->t_outq.c_cc <= tp->t_lowat) { 1502 if (ISSET(tp->t_state, TS_ASLEEP)) { 1503 CLR(tp->t_state, TS_ASLEEP); 1504 wakeup(&tp->t_outq); 1505 } 1506 selwakeup(&tp->t_wsel); 1507 if (tp->t_outq.c_cc == 0) 1508 goto out; 1509 } 1510 1511 cztty_transmit(sc, tp); 1512 out: 1513 splx(s); 1514 } 1515 1516 /* 1517 * czttystop: 1518 * 1519 * Stop output, e.g., for ^S or output flush. 1520 */ 1521 void 1522 czttystop(struct tty *tp, int flag) 1523 { 1524 1525 /* 1526 * XXX We don't do anything here, yet. Mostly, I don't know 1527 * XXX exactly how this should be implemented on this device. 1528 * XXX We've given a big chunk of data to the MIPS already, 1529 * XXX and I don't know how we request the MIPS to stop sending 1530 * XXX the data. So, punt for now. --thorpej 1531 */ 1532 } 1533 1534 /* 1535 * cztty_diag: 1536 * 1537 * Issue a scheduled diagnostic message. 1538 */ 1539 void 1540 cztty_diag(void *arg) 1541 { 1542 struct cztty_softc *sc = arg; 1543 struct cz_softc *cz = CZTTY_CZ(sc); 1544 u_int overflows, parity_errors, framing_errors; 1545 int s; 1546 1547 s = spltty(); 1548 1549 overflows = sc->sc_overflows; 1550 sc->sc_overflows = 0; 1551 1552 parity_errors = sc->sc_parity_errors; 1553 sc->sc_parity_errors = 0; 1554 1555 framing_errors = sc->sc_framing_errors; 1556 sc->sc_framing_errors = 0; 1557 1558 sc->sc_errors = 0; 1559 1560 splx(s); 1561 1562 log(LOG_WARNING, 1563 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1564 cz->cz_dev.dv_xname, sc->sc_channel, 1565 overflows, overflows == 1 ? "" : "s", 1566 parity_errors, 1567 framing_errors, framing_errors == 1 ? "" : "s"); 1568 } 1569 1570 /* 1571 * tx and rx ring buffer size macros: 1572 * 1573 * The transmitter and receiver both use ring buffers. For each one, there 1574 * is a get (consumer) and a put (producer) offset. The get value is the 1575 * next byte to be read from the ring, and the put is the next one to be 1576 * put into the ring. get == put means the ring is empty. 1577 * 1578 * For each ring, the firmware controls one of (get, put) and this driver 1579 * controls the other. For transmission, this driver updates put to point 1580 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1581 * for receive, the driver controls put, and this driver controls get. 1582 */ 1583 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1584 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1585 1586 /* 1587 * cztty_transmit() 1588 * 1589 * Look at the tty for this port and start sending. 1590 */ 1591 int 1592 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1593 { 1594 struct cz_softc *cz = CZTTY_CZ(sc); 1595 u_int move, get, put, size, address; 1596 #ifdef HOSTRAMCODE 1597 int error, done = 0; 1598 #else 1599 int done = 0; 1600 #endif 1601 1602 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1603 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1604 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1605 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1606 1607 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1608 #ifdef HOSTRAMCODE 1609 if (0) { 1610 move = min(tp->t_outq.c_cc, move); 1611 error = q_to_b(&tp->t_outq, 0, move); 1612 if (error != move) { 1613 printf("%s: channel %d: error moving to " 1614 "transmit buf\n", cz->cz_dev.dv_xname, 1615 sc->sc_channel); 1616 move = error; 1617 } 1618 } else { 1619 #endif 1620 move = min(ndqb(&tp->t_outq, 0), move); 1621 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1622 address + put, tp->t_outq.c_cf, move); 1623 ndflush(&tp->t_outq, move); 1624 #ifdef HOSTRAMCODE 1625 } 1626 #endif 1627 1628 put = ((put + move) % size); 1629 done = 1; 1630 } 1631 if (done) { 1632 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1633 } 1634 return (done); 1635 } 1636 1637 int 1638 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1639 { 1640 struct cz_softc *cz = CZTTY_CZ(sc); 1641 u_int get, put, size, address; 1642 int done = 0, ch; 1643 1644 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1645 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1646 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1647 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1648 1649 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1650 #ifdef HOSTRAMCODE 1651 if (hostram) 1652 ch = ((char *)fifoaddr)[get]; 1653 } else { 1654 #endif 1655 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1656 address + get); 1657 #ifdef HOSTRAMCODE 1658 } 1659 #endif 1660 (*tp->t_linesw->l_rint)(ch, tp); 1661 get = (get + 1) % size; 1662 done = 1; 1663 } 1664 if (done) { 1665 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1666 } 1667 return (done); 1668 }
Cache object: b78312b2babc4261fd4df84d2dab974a
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