Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/eapreg.h
Version:
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1 /* $NetBSD: eapreg.h,v 1.7 2003/12/04 13:57:31 keihan Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson <augustss@NetBSD.org> and Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * ES1370/ES1371/ES1373 registers 41 */ 42 43 #define EAP_ICSC 0x00 /* interrupt / chip select control */ 44 #define EAP_SERR_DISABLE 0x00000001 45 #define EAP_CDC_EN 0x00000002 46 #define EAP_JYSTK_EN 0x00000004 47 #define EAP_UART_EN 0x00000008 48 #define EAP_ADC_EN 0x00000010 49 #define EAP_DAC2_EN 0x00000020 50 #define EAP_DAC1_EN 0x00000040 51 #define EAP_BREQ 0x00000080 52 #define EAP_XTCL0 0x00000100 53 #define EAP_M_CB 0x00000200 54 #define EAP_CCB_INTRM 0x00000400 55 #define EAP_DAC_SYNC 0x00000800 56 #define EAP_WTSRSEL 0x00003000 57 #define EAP_WTSRSEL_5 0x00000000 58 #define EAP_WTSRSEL_11 0x00001000 59 #define EAP_WTSRSEL_22 0x00002000 60 #define EAP_WTSRSEL_44 0x00003000 61 #define EAP_M_SBB 0x00004000 62 #define E1371_SYNC_RES 0x00004000 63 #define EAP_MSFMTSEL 0x00008000 64 #define EAP_DAC_EN(i) (EAP_DAC2_EN << (i)) 65 #define EAP_SET_PCLKDIV(n) (((n)&0x1fff)<<16) 66 #define EAP_GET_PCLKDIV(n) (((n)>>16)&0x1fff) 67 #define EAP_PCLKBITS 0x1fff0000 68 #define EAP_XTCL1 0x40000000 69 #define EAP_ADC_STOP 0x80000000 70 71 #define EAP_ICSS 0x04 /* interrupt / chip select status */ 72 /* on the 5880 control / status */ 73 #define EAP_I_ADC 0x00000001 74 #define EAP_I_DAC2 0x00000002 75 #define EAP_I_DAC1 0x00000004 76 #define EAP_I_UART 0x00000008 77 #define EAP_I_MCCB 0x00000010 78 #define EAP_VC 0x00000060 79 #define EAP_CWRIP 0x00000100 80 #define EAP_CBUSY 0x00000200 81 #define EAP_CSTAT 0x00000400 82 #define EAP_CT5880_AC97_RESET 0x20000000 83 #define EAP_INTR 0x80000000 84 85 #define EAP_UART_DATA 0x08 86 #define EAP_UART_STATUS 0x09 87 #define EAP_US_RXRDY 0x01 88 #define EAP_US_TXRDY 0x02 89 #define EAP_US_TXINT 0x04 90 #define EAP_US_RXINT 0x80 91 #define EAP_UART_CONTROL 0x09 92 #define EAP_UC_CNTRL 0x03 93 #define EAP_UC_TXINTEN 0x20 94 #define EAP_UC_RXINTEN 0x80 95 #define EAP_MEMPAGE 0x0c 96 #define EAP_CODEC 0x10 97 #define EAP_SET_CODEC(a,d) (((a)<<8) | (d)) 98 99 /* 100 * ES1371/ES1373 registers 101 */ 102 103 #define E1371_CODEC 0x14 104 #define E1371_CODEC_VALID 0x80000000 105 #define E1371_CODEC_WIP 0x40000000 106 #define E1371_CODEC_READ 0x00800000 107 #define E1371_SET_CODEC(a,d) (((a)<<16) | (d)) 108 109 #define E1371_SRC 0x10 110 #define E1371_SRC_RAMWE 0x01000000 111 #define E1371_SRC_RBUSY 0x00800000 112 #define E1371_SRC_DISABLE 0x00400000 113 #define E1371_SRC_DISP1 0x00200000 114 #define E1371_SRC_DISP2 0x00100000 115 #define E1371_SRC_DISREC 0x00080000 116 #define E1371_SRC_DATAMASK 0x0000ffff 117 #define E1371_SRC_ADDR(a) ((a)<<25) 118 #define E1371_SRC_DATA(d) ((d) & E1371_SRC_DATAMASK) 119 #define E1371_SRC_CTLMASK (E1371_SRC_DISABLE | E1371_SRC_DISP1 | \ 120 E1371_SRC_DISP2 | E1371_SRC_DISREC) 121 #define E1371_SRC_STATE_MASK 0x00870000 122 #define E1371_SRC_STATE_OK 0x00010000 123 124 #define E1371_LEGACY 0x18 125 126 /* 127 * ES1371/ES1373 sample rate converter registers 128 */ 129 130 #define ESRC_ADC 0x78 131 #define ESRC_DAC1 0x70 132 #define ESRC_DAC2 0x74 133 #define ESRC_ADC_VOLL 0x6c 134 #define ESRC_ADC_VOLR 0x6d 135 #define ESRC_DAC1_VOLL 0x7c 136 #define ESRC_DAC1_VOLR 0x7d 137 #define ESRC_DAC2_VOLL 0x7e 138 #define ESRC_DAC2_VOLR 0x7f 139 #define ESRC_TRUNC_N 0x00 140 #define ESRC_IREGS 0x01 141 #define ESRC_ACF 0x02 142 #define ESRC_VFF 0x03 143 #define ESRC_SET_TRUNC(n) ((n)<<9) 144 #define ESRC_SET_N(n) ((n)<<4) 145 #define ESRC_SMF 0x8000 146 #define ESRC_SET_VFI(n) ((n)<<10) 147 #define ESRC_SET_ACI(n) (n) 148 #define ESRC_SET_ADC_VOL(n) ((n)<<8) 149 #define ESRC_SET_DAC_VOLI(n) ((n)<<12) 150 #define ESRC_SET_DAC_VOLF(n) (n) 151 #define SRC_MAGIC ((1<15)|(1<<13)|(1<<11)|(1<<9)) 152 153 #define EAP_SIC 0x20 154 #define EAP_P1_S_MB 0x00000001 155 #define EAP_P1_S_EB 0x00000002 156 #define EAP_P2_S_MB 0x00000004 157 #define EAP_P2_S_EB 0x00000008 158 #define EAP_R1_S_MB 0x00000010 159 #define EAP_R1_S_EB 0x00000020 160 #define EAP_P2_DAC_SEN 0x00000040 161 #define EAP_P1_SCT_RLD 0x00000080 162 #define EAP_P1_INTR_EN 0x00000100 163 #define EAP_P2_INTR_EN 0x00000200 164 #define EAP_R1_INTR_EN 0x00000400 165 #define EAP_P1_PAUSE 0x00000800 166 #define EAP_P2_PAUSE 0x00001000 167 #define EAP_P1_LOOP_SEL 0x00002000 168 #define EAP_P2_LOOP_SEL 0x00004000 169 #define EAP_R1_LOOP_SEL 0x00008000 170 #define EAP_S_EB(i) (EAP_P2_S_EB >> 2*(i)) 171 #define EAP_S_MB(i) (EAP_P2_S_MB >> 2*(i)) 172 #define EAP_P_INTR_EN(i) (EAP_P2_INTR_EN >> (i)) 173 #define EAP_SET_P2_ST_INC(i) ((i) << 16) 174 #define EAP_SET_P2_END_INC(i) ((i) << 19) 175 #define EAP_INC_BITS 0x003f0000 176 177 #define EAP_DAC1_CSR 0x24 178 #define EAP_DAC2_CSR 0x28 179 #define EAP_ADC_CSR 0x2c 180 #define EAP_GET_CURRSAMP(r) ((r) >> 16) 181 182 #define EAP_DAC_PAGE 0xc 183 #define EAP_ADC_PAGE 0xd 184 #define EAP_UART_PAGE1 0xe 185 #define EAP_UART_PAGE2 0xf 186 187 #define EAP_DAC1_ADDR 0x30 188 #define EAP_DAC1_SIZE 0x34 189 #define EAP_DAC2_ADDR 0x38 190 #define EAP_DAC2_SIZE 0x3c 191 #define EAP_ADC_ADDR 0x30 192 #define EAP_ADC_SIZE 0x34 193 #define EAP_SET_SIZE(c,s) (((c)<<16) | (s)) 194 195 #define EAP_READ_TIMEOUT 5000 196 #define EAP_WRITE_TIMEOUT 5000 197 198 199 #define EAP_XTAL_FREQ 1411200 /* 22.5792 / 16 MHz */ 200 201 /* AK4531 registers */ 202 #define AK_MASTER_L 0x00 203 #define AK_MASTER_R 0x01 204 #define AK_VOICE_L 0x02 205 #define AK_VOICE_R 0x03 206 #define AK_FM_L 0x04 207 #define AK_FM_R 0x05 208 #define AK_CD_L 0x06 209 #define AK_CD_R 0x07 210 #define AK_LINE_L 0x08 211 #define AK_LINE_R 0x09 212 #define AK_AUX_L 0x0a 213 #define AK_AUX_R 0x0b 214 #define AK_MONO1 0x0c 215 #define AK_MONO2 0x0d 216 #define AK_MIC 0x0e 217 #define AK_MONO 0x0f 218 #define AK_OUT_MIXER1 0x10 219 #define AK_M_FM_L 0x40 220 #define AK_M_FM_R 0x20 221 #define AK_M_LINE_L 0x10 222 #define AK_M_LINE_R 0x08 223 #define AK_M_CD_L 0x04 224 #define AK_M_CD_R 0x02 225 #define AK_M_MIC 0x01 226 #define AK_OUT_MIXER2 0x11 227 #define AK_M_AUX_L 0x20 228 #define AK_M_AUX_R 0x10 229 #define AK_M_VOICE_L 0x08 230 #define AK_M_VOICE_R 0x04 231 #define AK_M_MONO2 0x02 232 #define AK_M_MONO1 0x01 233 #define AK_IN_MIXER1_L 0x12 234 #define AK_IN_MIXER1_R 0x13 235 #define AK_IN_MIXER2_L 0x14 236 #define AK_IN_MIXER2_R 0x15 237 #define AK_M_TMIC 0x80 238 #define AK_M_TMONO1 0x40 239 #define AK_M_TMONO2 0x20 240 #define AK_M2_AUX_L 0x10 241 #define AK_M2_AUX_R 0x08 242 #define AK_M_VOICE 0x04 243 #define AK_M2_MONO2 0x02 244 #define AK_M2_MONO1 0x01 245 #define AK_RESET 0x16 246 #define AK_PD 0x02 247 #define AK_NRST 0x01 248 #define AK_CS 0x17 249 #define AK_ADSEL 0x18 250 #define AK_MGAIN 0x19 251 #define AK_NPORTS 0x20 252 253 /* Not sensical for AC97? */ 254 #define VOL_TO_ATT5(v) (0x1f - ((v) >> 3)) 255 #define VOL_TO_GAIN5(v) VOL_TO_ATT5(v) 256 #define ATT5_TO_VOL(v) ((0x1f - (v)) << 3) 257 #define GAIN5_TO_VOL(v) ATT5_TO_VOL(v) 258 #define VOL_0DB 200 259 260 /* Futzable parms */ 261 #define EAP_MASTER_VOL 0 262 #define EAP_VOICE_VOL 1 263 #define EAP_FM_VOL 2 264 #define EAP_VIDEO_VOL 2 /* ES1371 */ 265 #define EAP_CD_VOL 3 266 #define EAP_LINE_VOL 4 267 #define EAP_AUX_VOL 5 268 #define EAP_MIC_VOL 6 269 #define EAP_RECORD_SOURCE 7 270 #define EAP_OUTPUT_SELECT 8 271 #define EAP_MIC_PREAMP 9 272 #define EAP_OUTPUT_CLASS 10 273 #define EAP_RECORD_CLASS 11 274 #define EAP_INPUT_CLASS 12 275 276 #define MIDI_BUSY_WAIT 100 277 #define MIDI_BUSY_DELAY 100 /* Delay when UART is busy */ 278 279 #define EAP_EV1938_A 0x00 280 #define EAP_CT5880_C 0x02 281 #define EAP_CT5880_D 0x03 282 #define EAP_CT5880_E 0x04 283 #define EAP_ES1373_A 0x04 284 #define EAP_ES1373_B 0x06 285 #define EAP_CT5880_A 0x07 286 #define EAP_ES1373_8 0x08 287 #define EAP_ES1371_B 0x09
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