1 /* $NetBSD: emuxkireg.h,v 1.4 2004/02/24 15:12:52 wiz Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Yannick Montulet.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef _DEV_PCI_EMUXKIREG_H_
40 #define _DEV_PCI_EMUXKIREG_H_
41
42 /*
43 * Register values for Creative EMU10000. The register values have been
44 * taken from GPLed SBLive! header file published by Creative. The comments
45 * have been stripped to avoid GPL pollution in kernel. The Creative version
46 * including comments is available in Linux 2.4.* kernel as file
47 * drivers/sound/emu10k1/8010.h
48 */
49
50
51 #define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg))
52
53 #define EMU_PTR 0x00
54 #define EMU_PTR_CHNO_MASK 0x0000003f
55 #define EMU_PTR_ADDR_MASK 0x07ff0000
56
57 #define EMU_DATA 0x04
58
59 #define EMU_IPR 0x08
60 #define EMU_IPR_RATETRCHANGE 0x01000000
61 #define EMU_IPR_FXDSP 0x00800000
62 #define EMU_IPR_FORCEINT 0x00400000
63 #define EMU_PCIERROR 0x00200000
64 #define EMU_IPR_VOLINCR 0x00100000
65 #define EMU_IPR_VOLDECR 0x00080000
66 #define EMU_IPR_MUTE 0x00040000
67 #define EMU_IPR_MICBUFFULL 0x00020000
68 #define EMU_IPR_MICBUFHALFFULL 0x00010000
69 #define EMU_IPR_ADCBUFFULL 0x00008000
70 #define EMU_IPR_ADCBUFHALFFULL 0x00004000
71 #define EMU_IPR_EFXBUFFULL 0x00002000
72 #define EMU_IPR_EFXBUFHALFFULL 0x00001000
73 #define EMU_IPR_GPSPDIFSTCHANGE 0x00000800
74 #define EMU_IPR_CDROMSTCHANGE 0x00000400
75 #define EMU_IPR_INTERVALTIMER 0x00000200
76 #define EMU_IPR_MIDITRANSBUFE 0x00000100
77 #define EMU_IPR_MIDIRECVBUFE 0x00000080
78 #define EMU_IPR_CHANNELLOOP 0x00000040
79 #define EMU_IPR_CHNOMASK 0x0000003f
80
81 #define EMU_INTE 0x0c
82
83 #define EMU_INTE_VSB_MASK 0xc0000000
84 #define EMU_INTE_VSB_220 0x00000000
85 #define EMU_INTE_VSB_240 0x40000000
86 #define EMU_INTE_VSB_260 0x80000000
87 #define EMU_INTE_VSB_280 0xc0000000
88
89 #define EMU_INTE_VMPU_MASK 0x30000000
90 #define EMU_INTE_VMPU_300 0x00000000
91 #define EMU_INTE_VMPU_310 0x10000000
92 #define EMU_INTE_VMPU_320 0x20000000
93 #define EMU_INTE_VMPU_330 0x30000000
94 #define EMU_INTE_MDMAENABLE 0x08000000
95 #define EMU_INTE_SDMAENABLE 0x04000000
96 #define EMU_INTE_MPICENABLE 0x02000000
97 #define EMU_INTE_SPICENABLE 0x01000000
98 #define EMU_INTE_VSBENABLE 0x00800000
99 #define EMU_INTE_ADLIBENABLE 0x00400000
100 #define EMU_INTE_MPUENABLE 0x00200000
101 #define EMU_INTE_FORCEINT 0x00100000
102 #define EMU_INTE_MRHANDENABLE 0x00080000
103 #define EMU_INTE_SAMPLERATER 0x00002000
104 #define EMU_INTE_FXDSPENABLE 0x00001000
105 #define EMU_INTE_PCIERRENABLE 0x00000800
106 #define EMU_INTE_VOLINCRENABLE 0x00000400
107 #define EMU_INTE_VOLDECRENABLE 0x00000200
108 #define EMU_INTE_MUTEENABLE 0x00000100
109 #define EMU_INTE_MICBUFENABLE 0x00000080
110 #define EMU_INTE_ADCBUFENABLE 0x00000040
111 #define EMU_INTE_EFXBUFENABLE 0x00000020
112 #define EMU_INTE_GPSPDIFENABLE 0x00000010
113 #define EMU_INTE_CDSPDIFENABLE 0x00000008
114 #define EMU_INTE_INTERTIMERENB 0x00000004
115 #define EMU_INTE_MIDITXENABLE 0x00000002
116 #define EMU_INTE_MIDIRXENABLE 0x00000001
117
118 #define EMU_WC 0x10
119 #define EMU_WC_SAMPLECOUNTER_MASK 0x03FFFFC0
120 #define EMU_WC_SAMPLECOUNTER EMU_MKSUBREG(20, 6, EMU_WC)
121 #define EMU_WC_CURRENTCHANNEL 0x0000003F
122
123 #define EMU_HCFG 0x14
124 #define EMU_HCFG_LEGACYFUNC_MASK 0xe0000000
125 #define EMU_HCFG_LEGACYFUNC_MPU 0x00000000
126 #define EMU_HCFG_LEGACYFUNC_SB 0x40000000
127 #define EMU_HCFG_LEGACYFUNC_AD 0x60000000
128 #define EMU_HCFG_LEGACYFUNC_MPIC 0x80000000
129 #define EMU_HCFG_LEGACYFUNC_MDMA 0xa0000000
130 #define EMU_HCFG_LEGACYFUNC_SPCI 0xc0000000
131 #define EMU_HCFG_LEGACYFUNC_SDMA 0xe0000000
132 #define EMU_HCFG_IOCAPTUREADDR 0x1f000000
133 #define EMU_HCFG_LEGACYWRITE 0x00800000
134 #define EMU_HCFG_LEGACYWORD 0x00400000
135 #define EMU_HCFG_LEGACYINT 0x00200000
136
137 #define EMU_HCFG_CODECFMT_MASK 0x00070000
138 #define EMU_HCFG_CODECFMT_AC97 0x00000000
139 #define EMU_HCFG_CODECFMT_I2S 0x00010000
140 #define EMU_HCFG_GPINPUT0 0x00004000
141 #define EMU_HCFG_GPINPUT1 0x00002000
142 #define EMU_HCFG_GPOUTPUT_MASK 0x00001c00
143 #define EMU_HCFG_JOYENABLE 0x00000200
144 #define EMU_HCFG_PHASETRACKENABLE 0x00000100
145 #define EMU_HCFG_AC3ENABLE_MASK 0x000000e0
146 #define EMU_HCFG_AC3ENABLE_ZVIDEO 0x00000080
147 #define EMU_HCFG_AC3ENABLE_CDSPDIF 0x00000040
148 #define EMU_HCFG_AC3ENABLE_GPSPDIF 0x00000020
149 #define EMU_HCFG_AUTOMUTE 0x00000010
150 #define EMU_HCFG_LOCKSOUNDCACHE 0x00000008
151 #define EMU_HCFG_LOCKTANKCACHE_MASK 0x00000004
152 #define EMU_HCFG_LOCKTANKCACHE EMU_MKSUBREG(1, 2, EMU_HCFG)
153 #define EMU_HCFG_MUTEBUTTONENABLE 0x00000002
154 #define EMU_HCFG_AUDIOENABLE 0x00000001
155
156 #define EMU_MUDATA 0x18
157 #define EMU_MUCMD 0x19
158 #define EMU_MUCMD_RESET 0xff
159 #define EMU_MUCMD_ENTERUARTMODE 0x3f
160
161 #define EMU_MUSTAT EMU_MUCMD
162 #define EMU_MUSTAT_IRDYN 0x80
163 #define EMU_MUSTAT_ORDYN 0x40
164
165 #define EMU_TIMER 0x1a
166 #define EMU_TIMER_RATE_MASK 0x000003ff
167 #define EMU_TIMER_RATE EMU_MKSUBREG(10, 0, EMU_TIMER)
168
169 #define EMU_AC97DATA 0x1c
170 #define EMU_AC97ADDR 0x1e
171 #define EMU_AC97ADDR_RDY 0x80
172 #define EMU_AC97ADDR_ADDR 0x7f
173
174 /* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
175
176 #define EMU_CHAN_CPF 0x00
177
178 #define EMU_CHAN_CPF_PITCH_MASK 0xffff0000
179 #define EMU_CHAN_CPF_PITCH EMU_MKSUBREG(16, 16, EMU_CHAN_CPF)
180 #define EMU_CHAN_CPF_STEREO_MASK 0x00008000
181 #define EMU_CHAN_CPF_STEREO EMU_MKSUBREG(1, 15, EMU_CHAN_CPF)
182 #define EMU_CHAN_CPF_STOP_MASK 0x00004000
183 #define EMU_CHAN_CPF_FRACADDRESS_MASK 0x00003fff
184
185
186 #define EMU_CHAN_PTRX 0x01
187 #define EMU_CHAN_PTRX_PITCHTARGET_MASK 0xffff0000
188 #define EMU_CHAN_PTRX_PITCHTARGET EMU_MKSUBREG(16, 16, EMU_CHAN_PTRX)
189 #define EMU_CHAN_PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00
190 #define EMU_CHAN_PTRX_FXSENDAMOUNT_A EMU_MKSUBREG(8, 8, EMU_CHAN_PTRX)
191 #define EMU_CHAN_PTRX_FXSENDAMOUNT_B_MASK 0x000000ff
192 #define EMU_CHAN_PTRX_FXSENDAMOUNT_B EMU_MKSUBREG(8, 0, EMU_CHAN_PTRX)
193
194 #define EMU_CHAN_CVCF 0x02
195 #define EMU_CHAN_CVCF_CURRVOL_MASK 0xffff0000
196 #define EMU_CHAN_CVCF_CURRVOL EMU_MKSUBREG(16, 16, EMU_CHAN_CVCF)
197 #define EMU_CHAN_CVCF_CURRFILTER_MASK 0x0000ffff
198 #define EMU_CHAN_CVCF_CURRFILTER EMU_MKSUBREG(16, 0, EMU_CHAN_CVCF)
199
200 #define EMU_CHAN_VTFT 0x03
201 #define EMU_CHAN_VTFT_VOLUMETARGET_MASK 0xffff0000
202 #define EMU_CHAN_VTFT_VOLUMETARGET EMU_MKSUBREG(16, 16, EMU_CHAN_VTFT)
203 #define EMU_CHAN_VTFT_FILTERTARGET_MASK 0x0000ffff
204 #define EMU_CHAN_VTFT_FILTERTARGET EMU_MKSUBREG(16, 0, EMU_CHAN_VTFT)
205
206 #define EMU_CHAN_Z1 0x05
207 #define EMU_CHAN_Z2 0x04
208
209 #define EMU_CHAN_PSST 0x06
210 #define EMU_CHAN_PSST_FXSENDAMOUNT_C_MASK 0xff000000
211 #define EMU_CHAN_PSST_FXSENDAMOUNT_C EMU_MKSUBREG(8, 24, EMU_CHAN_PSST)
212 #define EMU_CHAN_PSST_LOOPSTARTADDR_MASK 0x00ffffff
213 #define EMU_CHAN_PSST_LOOPSTARTADDR EMU_MKSUBREG(24, 0, EMU_CHAN_PSST)
214
215 #define EMU_CHAN_DSL 0x07
216 #define EMU_CHAN_DSL_FXSENDAMOUNT_D_MASK 0xff000000
217 #define EMU_CHAN_DSL_FXSENDAMOUNT_D EMU_MKSUBREG(8, 24, EMU_CHAN_DSL)
218 #define EMU_CHAN_DSL_LOOPENDADDR_MASK 0x00ffffff
219 #define EMU_CHAN_DSL_LOOPENDADDR EMU_MKSUBREG(24, 0, EMU_CHAN_DSL)
220
221 #define EMU_CHAN_CCCA 0x08
222 #define EMU_CHAN_CCCA_RESONANCE 0xf0000000
223 #define EMU_CHAN_CCCA_INTERPROMMASK 0x0e000000
224 #define EMU_CHAN_CCCA_INTERPROM_0 0x00000000
225 #define EMU_CHAN_CCCA_INTERPROM_1 0x02000000
226 #define EMU_CHAN_CCCA_INTERPROM_2 0x04000000
227 #define EMU_CHAN_CCCA_INTERPROM_3 0x06000000
228 #define EMU_CHAN_CCCA_INTERPROM_4 0x08000000
229 #define EMU_CHAN_CCCA_INTERPROM_5 0x0a000000
230 #define EMU_CHAN_CCCA_INTERPROM_6 0x0c000000
231 #define EMU_CHAN_CCCA_INTERPROM_7 0x0e000000
232 #define EMU_CHAN_CCCA_8BITSELECT 0x01000000
233 #define EMU_CHAN_CCCA_CURRADDR_MASK 0x00ffffff
234 #define EMU_CHAN_CCCA_CURRADDR EMU_MKSUBREG(24, 0, EMU_CHAN_CCCA)
235
236 #define EMU_CHAN_CCR 0x09
237 #define EMU_CHAN_CCR_CACHEINVALIDSIZE_MASK 0xfe000000
238 #define EMU_CHAN_CCR_CACHEINVALIDSIZE EMU_MKSUBREG(7, 25, EMU_CHAN_CCR)
239 #define EMU_CHAN_CCR_CACHELOOPFLAG 0x01000000
240 #define EMU_CHAN_CCR_INTERLEAVEDSAMPLES 0x00800000
241 #define EMU_CHAN_CCR_WORDSIZEDSAMPLES 0x00400000
242 #define EMU_CHAN_CCR_READADDRESS_MASK 0x003f0000
243 #define EMU_CHAN_CCR_READADDRESS EMU_MKSUBREG(6, 16, EMU_CHAN_CCR)
244 #define EMU_CHAN_CCR_LOOPINVALSIZE 0x0000fe00
245 #define EMU_CHAN_CCR_LOOPFLAG 0x00000100
246 #define EMU_CHAN_CCR_CACHELOOPADDRHI 0x000000ff
247
248 #define EMU_CHAN_CLP 0x0a
249 #define EMU_CHAN_CLP_CACHELOOPADDR 0x0000ffff
250
251 #define EMU_CHAN_FXRT 0x0b
252 #define EMU_CHAN_FXRT_CHANNELA 0x000f0000
253 #define EMU_CHAN_FXRT_CHANNELB 0x00f00000
254 #define EMU_CHAN_FXRT_CHANNELC 0x0f000000
255 #define EMU_CHAN_FXRT_CHANNELD 0xf0000000
256
257 #define EMU_CHAN_MAPA 0x0c
258 #define EMU_CHAN_MAPB 0x0d
259
260 #define EMU_CHAN_MAP_PTE_MASK 0xffffe000
261 #define EMU_CHAN_MAP_PTI_MASK 0x00001fff
262
263
264 #define EMU_CHAN_ENVVOL 0x10
265 #define EMU_CHAN_ENVVOL_MASK 0x0000ffff
266
267
268 #define EMU_CHAN_ATKHLDV 0x11
269 #define EMU_CHAN_ATKHLDV_PHASE0 0x00008000
270 #define EMU_CHAN_ATKHLDV_HOLDTIME_MASK 0x00007f00
271 #define EMU_CHAN_ATKHLDV_ATTACKTIME_MASK 0x0000007f
272
273
274 #define EMU_CHAN_DCYSUSV 0x12
275 #define EMU_CHAN_DCYSUSV_PHASE1_MASK 0x00008000
276 #define EMU_CHAN_DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00
277 #define EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK 0x00000080
278 #define EMU_CHAN_DCYSUSV_DECAYTIME_MASK 0x0000007f
279
280
281 #define EMU_CHAN_LFOVAL1 0x13
282 #define EMU_CHAN_LFOVAL_MASK 0x0000ffff
283
284 #define EMU_CHAN_ENVVAL 0x14
285 #define EMU_CHAN_ENVVAL_MASK 0x0000ffff
286
287 #define EMU_CHAN_ATKHLDM 0x15
288 #define EMU_CHAN_ATKHLDM_PHASE0 0x00008000
289 #define EMU_CHAN_ATKHLDM_HOLDTIME 0x00007f00
290 #define EMU_CHAN_ATKHLDM_ATTACKTIME 0x0000007f
291
292 #define EMU_CHAN_DCYSUSM 0x16
293 #define EMU_CHAN_DCYSUSM_PHASE1_MASK 0x00008000
294 #define EMU_CHAN_DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00
295 #define EMU_CHAN_DCYSUSM_DECAYTIME_MASK 0x0000007f
296
297 #define EMU_CHAN_LFOVAL2 0x17
298 #define EMU_CHAN_LFOVAL2_MASK 0x0000ffff
299
300 #define EMU_CHAN_IP 0x18
301 #define EMU_CHAN_IP_MASK 0x0000ffff
302 #define EMU_CHAN_IP_UNITY 0x0000e000
303
304 #define EMU_CHAN_IFATN 0x19
305 #define EMU_CHAN_IFATN_FILTERCUTOFF_MASK 0x0000ff00
306 #define EMU_CHAN_IFATN_FILTERCUTOFF EMU_MKSUBREG(8, 8, EMU_CHAN_IFATN)
307 #define EMU_CHAN_IFATN_ATTENUATION_MASK 0x000000ff
308 #define EMU_CHAN_IFATN_ATTENUATION EMU_MKSUBREG(8, 0, EMU_CHAN_IFATN)
309
310 #define EMU_CHAN_PEFE 0x1a
311 #define EMU_CHAN_PEFE_PITCHAMOUNT_MASK 0x0000ff00
312 #define EMU_CHAN_PEFE_PITCHAMOUNT EMU_MKSUBREG(8, 8, EMU_CHAN_PEFE)
313 #define EMU_CHAN_PEFE_FILTERAMOUNT_MASK 0x000000ff
314 #define EMU_CHAN_PEFE_FILTERAMOUNT EMU_MKSUBREG(8, 0, EMU_CHAN_PEFE)
315
316 #define EMU_CHAN_FMMOD 0x1b
317 #define EMU_CHAN_FMMOD_MODVIBRATO 0x0000ff00
318 #define EMU_CHAN_FMMOD_MOFILTER 0x000000ff
319
320 #define EMU_CHAN_TREMFRQ 0x1c
321 #define EMU_CHAN_TREMFRQ_DEPTH 0x0000ff00
322
323 #define EMU_CHAN_FM2FRQ2 0x1d
324 #define EMU_CHAN_FM2FRQ2_DEPTH 0x0000ff00
325 #define EMU_CHAN_FM2FRQ2_FREQUENCY 0x000000ff
326
327 #define EMU_CHAN_TEMPENV 0x1e
328 #define EMU_CHAN_TEMPENV_MASK 0x0000ffff
329
330 #define EMU_CHAN_CD0 0x20
331 #define EMU_CHAN_CD1 0x21
332 #define EMU_CHAN_CD2 0x22
333 #define EMU_CHAN_CD3 0x23
334 #define EMU_CHAN_CD4 0x24
335 #define EMU_CHAN_CD5 0x25
336 #define EMU_CHAN_CD6 0x26
337 #define EMU_CHAN_CD7 0x27
338 #define EMU_CHAN_CD8 0x28
339 #define EMU_CHAN_CD9 0x29
340 #define EMU_CHAN_CDA 0x2a
341 #define EMU_CHAN_CDB 0x2b
342 #define EMU_CHAN_CDC 0x2c
343 #define EMU_CHAN_CDD 0x2d
344 #define EMU_CHAN_CDE 0x2e
345 #define EMU_CHAN_CDF 0x2f
346
347 /* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
348
349 #define EMU_PTB 0x40
350 #define EMU_PTB_MASK 0xfffff000
351
352 #define EMU_TCB 0x41
353 #define EMU_TCB_MASK 0xfffff000
354
355 #define EMU_ADCCR 0x42
356 #define EMU_ADCCR_RCHANENABLE 0x00000010
357 #define EMU_ADCCR_LCHANENABLE 0x00000008
358 #define EMU_ADCCR_SAMPLERATE_MASK 0x00000007
359 #define EMU_ADCCR_SAMPLERATE_48 0x00000000
360 #define EMU_ADCCR_SAMPLERATE_44 0x00000001
361 #define EMU_ADCCR_SAMPLERATE_32 0x00000002
362 #define EMU_ADCCR_SAMPLERATE_24 0x00000003
363 #define EMU_ADCCR_SAMPLERATE_22 0x00000004
364 #define EMU_ADCCR_SAMPLERATE_16 0x00000005
365 #define EMU_ADCCR_SAMPLERATE_11 0x00000006
366 #define EMU_ADCCR_SAMPLERATE_8 0x00000007
367
368 #define EMU_FXWC 0x43
369 #define EMU_TCBS 0x44
370 #define EMU_TCBS_MASK 0x00000007
371 #define EMU_TCBS_BUFFSIZE_16K 0x00000000
372 #define EMU_TCBS_BUFFSIZE_32K 0x00000001
373 #define EMU_TCBS_BUFFSIZE_64K 0x00000002
374 #define EMU_TCBS_BUFFSIZE_128K 0x00000003
375 #define EMU_TCBS_BUFFSIZE_256K 0x00000004
376 #define EMU_TCBS_BUFFSIZE_512K 0x00000005
377 #define EMU_TCBS_BUFFSIZE_1024K 0x00000006
378 #define EMU_TCBS_BUFFSIZE_2048K 0x00000007
379
380 #define EMU_MICBA 0x45
381 #define EMU_ADCBA 0x46
382 #define EMU_FXBA 0x47
383 #define EMU_RECBA_MASK 0xfffff000
384
385 #define EMU_MICBS 0x49
386 #define EMU_ADCBS 0x4a
387 #define EMU_FXBS 0x4b
388 #define EMU_RECBS_BUFSIZE_NONE 0x00000000
389 #define EMU_RECBS_BUFSIZE_384 0x00000001
390 #define EMU_RECBS_BUFSIZE_448 0x00000002
391 #define EMU_RECBS_BUFSIZE_512 0x00000003
392 #define EMU_RECBS_BUFSIZE_640 0x00000004
393 #define EMU_RECBS_BUFSIZE_768 0x00000005
394 #define EMU_RECBS_BUFSIZE_896 0x00000006
395 #define EMU_RECBS_BUFSIZE_1024 0x00000007
396 #define EMU_RECBS_BUFSIZE_1280 0x00000008
397 #define EMU_RECBS_BUFSIZE_1536 0x00000009
398 #define EMU_RECBS_BUFSIZE_1792 0x0000000a
399 #define EMU_RECBS_BUFSIZE_2048 0x0000000b
400 #define EMU_RECBS_BUFSIZE_2560 0x0000000c
401 #define EMU_RECBS_BUFSIZE_3072 0x0000000d
402 #define EMU_RECBS_BUFSIZE_3584 0x0000000e
403 #define EMU_RECBS_BUFSIZE_4096 0x0000000f
404 #define EMU_RECBS_BUFSIZE_5120 0x00000010
405 #define EMU_RECBS_BUFSIZE_6144 0x00000011
406 #define EMU_RECBS_BUFSIZE_7168 0x00000012
407 #define EMU_RECBS_BUFSIZE_8192 0x00000013
408 #define EMU_RECBS_BUFSIZE_10240 0x00000014
409 #define EMU_RECBS_BUFSIZE_12288 0x00000015
410 #define EMU_RECBS_BUFSIZE_14366 0x00000016
411 #define EMU_RECBS_BUFSIZE_16384 0x00000017
412 #define EMU_RECBS_BUFSIZE_20480 0x00000018
413 #define EMU_RECBS_BUFSIZE_24576 0x00000019
414 #define EMU_RECBS_BUFSIZE_28672 0x0000001a
415 #define EMU_RECBS_BUFSIZE_32768 0x0000001b
416 #define EMU_RECBS_BUFSIZE_40960 0x0000001c
417 #define EMU_RECBS_BUFSIZE_49152 0x0000001d
418 #define EMU_RECBS_BUFSIZE_57344 0x0000001e
419 #define EMU_RECBS_BUFSIZE_65536 0x0000001f
420
421 #define EMU_CDCS 0x50
422 #define EMU_GPSCS 0x51
423
424 #define EMU_DBG 0x52
425 #define EMU_DBG_ZC 0x80000000
426 #define EMU_DBG_SATURATION_OCCURRED 0x02000000
427 #define EMU_DBG_SATURATION_ADDR 0x01ff0000
428 #define EMU_DBG_SINGLE_STEP 0x00008000
429 #define EMU_DBG_STEP 0x00004000
430 #define EMU_DBG_CONDITION_CODE 0x00003e00
431 #define EMU_DBG_SINGLE_STEP_ADDR 0x000001ff
432 #define EMU_REG53 0x53
433
434 #define EMU_SPCS0 0x54
435 #define EMU_SPCS1 0x55
436 #define EMU_SPCS2 0x56
437 #define EMU_SPCS_CLKACCYMASK 0x30000000
438 #define EMU_SPCS_CLKACCY_1000PPM 0x00000000
439 #define EMU_SPCS_CLKACCY_50PPM 0x10000000
440 #define EMU_SPCS_CLKACCY_VARIABLE 0x20000000
441 #define EMU_SPCS_SAMPLERATEMASK 0x0f000000
442 #define EMU_SPCS_SAMPLERATE_44 0x00000000
443 #define EMU_SPCS_SAMPLERATE_48 0x02000000
444 #define EMU_SPCS_SAMPLERATE_32 0x03000000
445 #define EMU_SPCS_CHANNELNUMMASK 0x00f00000
446 #define EMU_SPCS_CHANNELNUM_UNSPEC 0x00000000
447 #define EMU_SPCS_CHANNELNUM_LEFT 0x00100000
448 #define EMU_SPCS_CHANNELNUM_RIGHT 0x00200000
449 #define EMU_SPCS_SOURCENUMMASK 0x000f0000
450 #define EMU_SPCS_SOURCENUM_UNSPEC 0x00000000
451 #define EMU_SPCS_GENERATIONSTATUS 0x00008000
452 #define EMU_SPCS_CATEGORYCODEMASK 0x00007f00
453 #define EMU_SPCS_MODEMASK 0x000000c0
454 #define EMU_SPCS_EMPHASISMASK 0x00000038
455 #define EMU_SPCS_EMPHASIS_NONE 0x00000000
456 #define EMU_SPCS_EMPHASIS_50_15 0x00000008
457 #define EMU_SPCS_COPYRIGHT 0x00000004
458 #define EMU_SPCS_NOTAUDIODATA 0x00000002
459 #define EMU_SPCS_PROFESSIONAL 0x00000001
460
461 #define EMU_CLIEL 0x58
462 #define EMU_CLIEH 0x59
463 #define EMU_CLIPL 0x5a
464 #define EMU_CLIPH 0x5b
465 #define EMU_SOLEL 0x5c
466 #define EMU_SOLEH 0x5d
467
468 #define EMU_SPBYPASS 0x5e
469 #define EMU_SPBYPASS_ENABLE 0x00000001
470
471 #define EMU_CDSRCS 0x60
472 #define EMU_GPSRCS 0x61
473 #define EMU_ZVSRCS 0x62
474 #define EMU_SRCS_SPDIFLOCKED 0x02000000
475 #define EMU_SRCS_RATELOCKED 0x01000000
476 #define EMU_SRCS_ESTSAMPLERATE 0x0007ffff
477
478 #define EMU_MICIDX 0x63
479 #define EMU_ADCIDX 0x64
480 #define EMU_FXIDX 0x65
481 #define EMU_RECIDX_MASK 0x0000ffff
482 #define EMU_RECIDX(idxreg) (0x10000000|(idxreg))
483 /*
484 #define EMU_MICIDX_IDX 0x10000063
485 #define EMU_ADCIDX_IDX 0x10000064
486 #define EMU_FXIDX_IDX 0x10000065
487 */
488
489 #define EMU_FXGPREGBASE 0x100
490
491 #define EMU_TANKMEMDATAREGBASE 0x200
492 #define EMU_TANKMEMDATAREG_MASK 0x000fffff
493
494 #define EMU_TANKMEMADDRREGBASE 0x300
495 #define EMU_TANKMEMADDRREG_ADDR_MASK 0x000fffff
496 #define EMU_TANKMEMADDRREG_CLEAR 0x00800000
497 #define EMU_TANKMEMADDRREG_ALIGN 0x00400000
498 #define EMU_TANKMEMADDRREG_WRITE 0x00200000
499 #define EMU_TANKMEMADDRREG_READ 0x00100000
500
501 #define EMU_MICROCODEBASE 0x400
502 #define EMU_DSP_LOWORD_OPX_MASK 0x000ffc00
503 #define EMU_DSP_LOWORD_OPY_MASK 0x000003ff
504 #define EMU_DSP_HIWORD_OPCODE_MASK 0x00f00000
505 #define EMU_DSP_HIWORD_RESULT_MASK 0x000ffc00
506 #define EMU_DSP_HIWORD_OPA_MASK 0x000003ff
507
508 #define EMU_DSP_OP_MACS 0x0
509 #define EMU_DSP_OP_MACS1 0x1
510 #define EMU_DSP_OP_MACW 0x2
511 #define EMU_DSP_OP_MACW1 0x3
512 #define EMU_DSP_OP_MACINTS 0x4
513 #define EMU_DSP_OP_MACINTW 0x5
514 #define EMU_DSP_OP_ACC3 0x6
515 #define EMU_DSP_OP_MACMV 0x7
516 #define EMU_DSP_OP_ANDXOR 0x8
517 #define EMU_DSP_OP_TSTNEG 0x9
518 #define EMU_DSP_OP_LIMIT 0xA
519 #define EMU_DSP_OP_LIMIT1 0xB
520 #define EMU_DSP_OP_LOG 0xC
521 #define EMU_DSP_OP_EXP 0xD
522 #define EMU_DSP_OP_INTERP 0xE
523 #define EMU_DSP_OP_SKIP 0xF
524
525
526 #define EMU_DSP_FX(num) (num)
527
528 #define EMU_DSP_IOL(base, num) (base + (num << 1))
529 #define EMU_DSP_IOR(base, num) (EMU_DSP_IOL(base, num) + 1)
530
531 #define EMU_DSP_INL_BASE 0x010
532 #define EMU_DSP_INL(num) (EMU_DSP_IOL(EMU_DSP_INL_BASE, num))
533 #define EMU_DSP_INR(num) (EMU_DSP_IOR(EMU_DSP_INL_BASE, num))
534 #define EMU_DSP_IN_AC97 0
535 #define EMU_DSP_IN_CDSPDIF 1
536 #define EMU_DSP_IN_ZOOM 2
537 #define EMU_DSP_IN_TOSOPT 3
538 #define EMU_DSP_IN_LVDLM1 4
539 #define EMU_DSP_IN_LVDCOS 5
540 #define EMU_DSP_IN_LVDLM2 6
541 #define EMU_DSP_IN_UNKNOWN 7
542
543 #define EMU_DSP_OUTL_BASE 0x020
544 #define EMU_DSP_OUTL(num) (EMU_DSP_IOL(EMU_DSP_OUTL_BASE, num))
545 #define EMU_DSP_OUTR(num) (EMU_DSP_IOR(EMU_DSP_OUTL_BASE, num))
546 #define EMU_DSP_OUT_AC97 0
547 #define EMU_DSP_OUT_TOSOPT 1
548 #define EMU_DSP_OUT_UNKNOWN 2
549 #define EMU_DSP_OUT_HEAD 3
550 #define EMU_DSP_OUT_RCHAN 4
551 #define EMU_DSP_OUT_ADC 5
552 #define EMU_DSP_OUTL_MIC 6
553
554 #define EMU_DSP_CST_BASE 0x40
555 #define EMU_DSP_CST(num) (EMU_DSP_CST_BASE + num)
556 /*
557 00 = 0x00000000
558 01 = 0x00000001
559 02 = 0x00000002
560 03 = 0x00000003
561 04 = 0x00000004
562 05 = 0x00000008
563 06 = 0x00000010
564 07 = 0x00000020
565 08 = 0x00000100
566 09 = 0x00010000
567 0A = 0x00080000
568 0B = 0x10000000
569 0C = 0x20000000
570 0D = 0x40000000
571 0E = 0x80000000
572 0F = 0x7FFFFFFF
573 10 = 0xFFFFFFFF
574 11 = 0xFFFFFFFE
575 12 = 0xC0000000
576 13 = 0x4F1BBCDC
577 14 = 0x5A7EF9DB
578 15 = 0x00100000
579 */
580
581 #define EMU_DSP_HWR_ACC 0x056
582 #define EMU_DSP_HWR_CCR 0x057
583 #define EMU_DSP_HWR_CCR_S 0x04
584 #define EMU_DSP_HWR_CCR_Z 0x03
585 #define EMU_DSP_HWR_CCR_M 0x02
586 #define EMU_DSP_HWR_CCR_N 0x01
587 #define EMU_DSP_HWR_CCR_B 0x00
588 #define EMU_DSP_HWR_NOISE0 0x058
589 #define EMU_DSP_HWR_NOISE1 0x059
590 #define EMU_DSP_HWR_INTR 0x05A
591 #define EMU_DSP_HWR_DBAC 0x05B
592
593 #define EMU_DSP_GPR(num) (EMU_FXGPREGBASE + num)
594
595 #endif /* _DEV_PCI_EMUXKIREG_H_ */
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