1 /* $NetBSD: fwohci_pci.c,v 1.18 2003/01/31 00:07:42 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: fwohci_pci.c,v 1.18 2003/01/31 00:07:42 thorpej Exp $");
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/socket.h>
45 #include <sys/device.h>
46 #include <sys/select.h>
47
48 #include <machine/bus.h>
49 #include <machine/intr.h>
50
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/ieee1394/ieee1394reg.h>
54 #include <dev/ieee1394/ieee1394var.h>
55 #include <dev/ieee1394/fwohcireg.h>
56 #include <dev/ieee1394/fwohcivar.h>
57
58 struct fwohci_pci_softc {
59 struct fwohci_softc psc_sc;
60 pci_chipset_tag_t psc_pc;
61 void *psc_ih;
62 };
63
64 static int fwohci_pci_match __P((struct device *, struct cfdata *, void *));
65 static void fwohci_pci_attach __P((struct device *, struct device *, void *));
66
67 CFATTACH_DECL(fwohci_pci, sizeof(struct fwohci_pci_softc),
68 fwohci_pci_match, fwohci_pci_attach, NULL, NULL);
69
70 static int
71 fwohci_pci_match(struct device *parent, struct cfdata *match, void *aux)
72 {
73 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
74
75 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
76 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_FIREWIRE &&
77 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI)
78 return 1;
79
80 return 0;
81 }
82
83 static void
84 fwohci_pci_attach(struct device *parent, struct device *self, void *aux)
85 {
86 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
87 struct fwohci_pci_softc *psc = (struct fwohci_pci_softc *) self;
88 char devinfo[256];
89 char const *intrstr;
90 pci_intr_handle_t ih;
91 u_int32_t csr;
92
93 aprint_naive(": IEEE 1394 Controller\n");
94
95 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
96 aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
97 PCI_REVISION(pa->pa_class));
98
99 psc->psc_sc.sc_dmat = pa->pa_dmat;
100 psc->psc_pc = pa->pa_pc;
101
102 /* Map I/O registers */
103 if (pci_mapreg_map(pa, PCI_OHCI_MAP_REGISTER, PCI_MAPREG_TYPE_MEM, 0,
104 &psc->psc_sc.sc_memt, &psc->psc_sc.sc_memh,
105 NULL, &psc->psc_sc.sc_memsize)) {
106 aprint_error("%s: can't map OHCI register space\n",
107 self->dv_xname);
108 return;
109 }
110
111 /* Disable interrupts, so we don't get any spurious ones. */
112 OHCI_CSR_WRITE(&psc->psc_sc, OHCI_REG_IntMaskClear,
113 OHCI_Int_MasterEnable);
114
115 /* Enable the device. */
116 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
117 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
118 csr | PCI_COMMAND_MASTER_ENABLE);
119
120 #if BYTE_ORDER == BIG_ENDIAN
121 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_OHCI_CONTROL_REGISTER);
122 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_OHCI_CONTROL_REGISTER,
123 csr | PCI_GLOBAL_SWAP_BE);
124 #endif
125
126 /* Map and establish the interrupt. */
127 if (pci_intr_map(pa, &ih)) {
128 aprint_error("%s: couldn't map interrupt\n", self->dv_xname);
129 return;
130 }
131 intrstr = pci_intr_string(pa->pa_pc, ih);
132 psc->psc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, fwohci_intr,
133 &psc->psc_sc);
134 if (psc->psc_ih == NULL) {
135 aprint_error("%s: couldn't establish interrupt",
136 self->dv_xname);
137 if (intrstr != NULL)
138 aprint_normal(" at %s", intrstr);
139 aprint_normal("\n");
140 return;
141 }
142 aprint_normal("%s: interrupting at %s\n", self->dv_xname, intrstr);
143
144 if (fwohci_init(&psc->psc_sc, pci_intr_evcnt(pa->pa_pc, ih)) != 0) {
145 pci_intr_disestablish(pa->pa_pc, psc->psc_ih);
146 bus_space_unmap(psc->psc_sc.sc_memt, psc->psc_sc.sc_memh,
147 psc->psc_sc.sc_memsize);
148 }
149 }
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