Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/hostb_pci.c
Version:
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1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/9.0/sys/dev/pci/hostb_pci.c 219902 2011-03-23 13:10:15Z jhb $"); 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcireg.h> 37 38 /* 39 * Provide a device to "eat" the host->pci bridge devices that show up 40 * on PCI busses and stop them showing up twice on the probes. This also 41 * stops them showing up as 'none' in pciconf -l. If the host bridge 42 * provides an AGP capability then we create a child agp device for the 43 * agp GART driver to attach to. 44 */ 45 static int 46 pci_hostb_probe(device_t dev) 47 { 48 u_int32_t id; 49 50 id = pci_get_devid(dev); 51 52 switch (id) { 53 54 /* VIA VT82C596 Power Managment Function */ 55 case 0x30501106: 56 return (ENXIO); 57 58 default: 59 break; 60 } 61 62 if (pci_get_class(dev) == PCIC_BRIDGE && 63 pci_get_subclass(dev) == PCIS_BRIDGE_HOST) { 64 device_set_desc(dev, "Host to PCI bridge"); 65 device_quiet(dev); 66 return (-10000); 67 } 68 return (ENXIO); 69 } 70 71 static int 72 pci_hostb_attach(device_t dev) 73 { 74 75 bus_generic_probe(dev); 76 77 /* 78 * If AGP capabilities are present on this device, then create 79 * an AGP child. 80 */ 81 if (pci_find_cap(dev, PCIY_AGP, NULL) == 0) 82 device_add_child(dev, "agp", -1); 83 bus_generic_attach(dev); 84 return (0); 85 } 86 87 /* Bus interface. */ 88 89 static int 90 pci_hostb_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 91 { 92 93 return (BUS_READ_IVAR(device_get_parent(dev), dev, which, result)); 94 } 95 96 static int 97 pci_hostb_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 98 { 99 100 return (EINVAL); 101 } 102 103 static struct resource * 104 pci_hostb_alloc_resource(device_t dev, device_t child, int type, int *rid, 105 u_long start, u_long end, u_long count, u_int flags) 106 { 107 108 return (bus_alloc_resource(dev, type, rid, start, end, count, flags)); 109 } 110 111 static int 112 pci_hostb_release_resource(device_t dev, device_t child, int type, int rid, 113 struct resource *r) 114 { 115 116 return (bus_release_resource(dev, type, rid, r)); 117 } 118 119 /* PCI interface. */ 120 121 static uint32_t 122 pci_hostb_read_config(device_t dev, device_t child, int reg, int width) 123 { 124 125 return (pci_read_config(dev, reg, width)); 126 } 127 128 static void 129 pci_hostb_write_config(device_t dev, device_t child, int reg, 130 uint32_t val, int width) 131 { 132 133 pci_write_config(dev, reg, val, width); 134 } 135 136 static int 137 pci_hostb_enable_busmaster(device_t dev, device_t child) 138 { 139 140 device_printf(dev, "child %s requested pci_enable_busmaster\n", 141 device_get_nameunit(child)); 142 return (pci_enable_busmaster(dev)); 143 } 144 145 static int 146 pci_hostb_disable_busmaster(device_t dev, device_t child) 147 { 148 149 device_printf(dev, "child %s requested pci_disable_busmaster\n", 150 device_get_nameunit(child)); 151 return (pci_disable_busmaster(dev)); 152 } 153 154 static int 155 pci_hostb_enable_io(device_t dev, device_t child, int space) 156 { 157 158 device_printf(dev, "child %s requested pci_enable_io\n", 159 device_get_nameunit(child)); 160 return (pci_enable_io(dev, space)); 161 } 162 163 static int 164 pci_hostb_disable_io(device_t dev, device_t child, int space) 165 { 166 167 device_printf(dev, "child %s requested pci_disable_io\n", 168 device_get_nameunit(child)); 169 return (pci_disable_io(dev, space)); 170 } 171 172 static int 173 pci_hostb_set_powerstate(device_t dev, device_t child, int state) 174 { 175 176 device_printf(dev, "child %s requested pci_set_powerstate\n", 177 device_get_nameunit(child)); 178 return (pci_set_powerstate(dev, state)); 179 } 180 181 static int 182 pci_hostb_get_powerstate(device_t dev, device_t child) 183 { 184 185 device_printf(dev, "child %s requested pci_get_powerstate\n", 186 device_get_nameunit(child)); 187 return (pci_get_powerstate(dev)); 188 } 189 190 static int 191 pci_hostb_assign_interrupt(device_t dev, device_t child) 192 { 193 194 device_printf(dev, "child %s requested pci_assign_interrupt\n", 195 device_get_nameunit(child)); 196 return (PCI_ASSIGN_INTERRUPT(device_get_parent(dev), dev)); 197 } 198 199 static int 200 pci_hostb_find_extcap(device_t dev, device_t child, int capability, 201 int *capreg) 202 { 203 204 return (pci_find_extcap(dev, capability, capreg)); 205 } 206 207 static device_method_t pci_hostb_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, pci_hostb_probe), 210 DEVMETHOD(device_attach, pci_hostb_attach), 211 DEVMETHOD(device_shutdown, bus_generic_shutdown), 212 DEVMETHOD(device_suspend, bus_generic_suspend), 213 DEVMETHOD(device_resume, bus_generic_resume), 214 215 /* Bus interface */ 216 DEVMETHOD(bus_read_ivar, pci_hostb_read_ivar), 217 DEVMETHOD(bus_write_ivar, pci_hostb_write_ivar), 218 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 219 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 220 221 DEVMETHOD(bus_alloc_resource, pci_hostb_alloc_resource), 222 DEVMETHOD(bus_release_resource, pci_hostb_release_resource), 223 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 224 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 225 226 /* PCI interface */ 227 DEVMETHOD(pci_read_config, pci_hostb_read_config), 228 DEVMETHOD(pci_write_config, pci_hostb_write_config), 229 DEVMETHOD(pci_enable_busmaster, pci_hostb_enable_busmaster), 230 DEVMETHOD(pci_disable_busmaster, pci_hostb_disable_busmaster), 231 DEVMETHOD(pci_enable_io, pci_hostb_enable_io), 232 DEVMETHOD(pci_disable_io, pci_hostb_disable_io), 233 DEVMETHOD(pci_get_powerstate, pci_hostb_get_powerstate), 234 DEVMETHOD(pci_set_powerstate, pci_hostb_set_powerstate), 235 DEVMETHOD(pci_assign_interrupt, pci_hostb_assign_interrupt), 236 DEVMETHOD(pci_find_extcap, pci_hostb_find_extcap), 237 238 { 0, 0 } 239 }; 240 241 static driver_t pci_hostb_driver = { 242 "hostb", 243 pci_hostb_methods, 244 1, 245 }; 246 247 static devclass_t pci_hostb_devclass; 248 249 DRIVER_MODULE(hostb, pci, pci_hostb_driver, pci_hostb_devclass, 0, 0);
Cache object: 3d148c52e3e5af5179e77f617fcfa5a1
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