1 /* $NetBSD: if_atw_pci.c,v 1.6 2004/02/17 21:20:55 dyoung Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center; Charles M. Hannum; and David Young.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * PCI bus front-end for the ADMtek ADM8211 802.11 MAC/BBP chip.
42 *
43 * Derived from the ``Tulip'' PCI bus front-end.
44 */
45
46 #include <sys/cdefs.h>
47 __KERNEL_RCSID(0, "$NetBSD: if_atw_pci.c,v 1.6 2004/02/17 21:20:55 dyoung Exp $");
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/mbuf.h>
52 #include <sys/malloc.h>
53 #include <sys/kernel.h>
54 #include <sys/socket.h>
55 #include <sys/ioctl.h>
56 #include <sys/errno.h>
57 #include <sys/device.h>
58
59 #include <machine/endian.h>
60
61 #include <net/if.h>
62 #include <net/if_dl.h>
63 #include <net/if_media.h>
64 #include <net/if_ether.h>
65
66 #include <net80211/ieee80211_compat.h>
67 #include <net80211/ieee80211_radiotap.h>
68 #include <net80211/ieee80211_var.h>
69
70 #include <machine/bus.h>
71 #include <machine/intr.h>
72
73 #include <dev/ic/atwreg.h>
74 #include <dev/ic/rf3000reg.h>
75 #include <dev/ic/si4136reg.h>
76 #include <dev/ic/atwvar.h>
77
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcidevs.h>
81
82 /*
83 * PCI configuration space registers used by the ADM8211.
84 */
85 #define ATW_PCI_IOBA 0x10 /* i/o mapped base */
86 #define ATW_PCI_MMBA 0x14 /* memory mapped base */
87
88 struct atw_pci_softc {
89 struct atw_softc psc_atw; /* real ADM8211 softc */
90
91 pci_intr_handle_t psc_ih; /* interrupt handle */
92 void *psc_intrcookie;
93
94 pci_chipset_tag_t psc_pc; /* our PCI chipset */
95 pcitag_t psc_pcitag; /* our PCI tag */
96 };
97
98 int atw_pci_match(struct device *, struct cfdata *, void *);
99 void atw_pci_attach(struct device *, struct device *, void *);
100
101 CFATTACH_DECL(atw_pci, sizeof(struct atw_pci_softc),
102 atw_pci_match, atw_pci_attach, NULL, NULL);
103
104 const struct atw_pci_product {
105 u_int32_t app_vendor; /* PCI vendor ID */
106 u_int32_t app_product; /* PCI product ID */
107 const char *app_product_name;
108 } atw_pci_products[] = {
109 { PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_ADM8211,
110 "ADMtek ADM8211 802.11 MAC/BBP" },
111
112 { 0, 0, NULL },
113 };
114
115 const struct atw_pci_product *atw_pci_lookup(const struct pci_attach_args *);
116
117 const struct atw_pci_product *
118 atw_pci_lookup(const struct pci_attach_args *pa)
119 {
120 const struct atw_pci_product *app;
121
122 for (app = atw_pci_products;
123 app->app_product_name != NULL;
124 app++) {
125 if (PCI_VENDOR(pa->pa_id) == app->app_vendor &&
126 PCI_PRODUCT(pa->pa_id) == app->app_product)
127 return (app);
128 }
129 return (NULL);
130 }
131
132 int
133 atw_pci_match(struct device *parent, struct cfdata *match, void *aux)
134 {
135 struct pci_attach_args *pa = aux;
136
137 if (atw_pci_lookup(pa) != NULL)
138 return (1);
139
140 return (0);
141 }
142
143 static int
144 atw_pci_enable(struct atw_softc *sc)
145 {
146 struct atw_pci_softc *psc = (void *)sc;
147
148 /* Establish the interrupt. */
149 psc->psc_intrcookie = pci_intr_establish(psc->psc_pc, psc->psc_ih,
150 IPL_NET, atw_intr, sc);
151 if (psc->psc_intrcookie == NULL) {
152 printf("%s: unable to establish interrupt\n",
153 sc->sc_dev.dv_xname);
154 return (1);
155 }
156
157 return (0);
158 }
159
160 static void
161 atw_pci_disable(struct atw_softc *sc)
162 {
163 struct atw_pci_softc *psc = (void *)sc;
164
165 /* Unhook the interrupt handler. */
166 pci_intr_disestablish(psc->psc_pc, psc->psc_intrcookie);
167 psc->psc_intrcookie = NULL;
168 }
169
170 void
171 atw_pci_attach(struct device *parent, struct device *self, void *aux)
172 {
173 struct atw_pci_softc *psc = (void *) self;
174 struct atw_softc *sc = &psc->psc_atw;
175 struct pci_attach_args *pa = aux;
176 pci_chipset_tag_t pc = pa->pa_pc;
177 const char *intrstr = NULL;
178 bus_space_tag_t iot, memt;
179 bus_space_handle_t ioh, memh;
180 int ioh_valid, memh_valid;
181 const struct atw_pci_product *app;
182 pcireg_t reg;
183 int pmreg, rev;
184
185 psc->psc_pc = pa->pa_pc;
186 psc->psc_pcitag = pa->pa_tag;
187
188 app = atw_pci_lookup(pa);
189 if (app == NULL) {
190 printf("\n");
191 panic("atw_pci_attach: impossible");
192 }
193
194 /*
195 * No power management hooks.
196 * XXX Maybe we should add some!
197 */
198 sc->sc_flags |= ATWF_ENABLED;
199
200 /*
201 * Get revision info, and set some chip-specific variables.
202 */
203 rev = PCI_REVISION(pa->pa_class);
204 printf(": %s, pass %d.%d\n", app->app_product_name,
205 (rev >> 4) & 0xf, rev & 0xf);
206
207 /*
208 * Check to see if the device is in power-save mode, and
209 * being it out if necessary.
210 *
211 * XXX This code comes almost verbatim from if_tlp_pci.c. I do
212 * not understand it. Tulip clears the "sleep mode" bit in the
213 * CFDA register, first. There is an equivalent (?) register at the
214 * same place in the ADM8211, but the docs do not assign its bits
215 * any meanings. -dcy
216 */
217 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
218 reg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR);
219 switch (reg & PCI_PMCSR_STATE_MASK) {
220 case PCI_PMCSR_STATE_D1:
221 case PCI_PMCSR_STATE_D2:
222 printf(": waking up from power state D%d\n%s",
223 reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname);
224 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
225 (reg & ~PCI_PMCSR_STATE_MASK) |
226 PCI_PMCSR_STATE_D0);
227 break;
228 case PCI_PMCSR_STATE_D3:
229 /*
230 * The card has lost all configuration data in
231 * this state, so punt.
232 */
233 printf(": unable to wake up from power state D3, "
234 "reboot required.\n");
235 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
236 (reg & ~PCI_PMCSR_STATE_MASK) |
237 PCI_PMCSR_STATE_D0);
238 return;
239 }
240 }
241
242 /*
243 * Map the device.
244 */
245 ioh_valid = (pci_mapreg_map(pa, ATW_PCI_IOBA,
246 PCI_MAPREG_TYPE_IO, 0,
247 &iot, &ioh, NULL, NULL) == 0);
248 memh_valid = (pci_mapreg_map(pa, ATW_PCI_MMBA,
249 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
250 &memt, &memh, NULL, NULL) == 0);
251
252 if (memh_valid) {
253 sc->sc_st = memt;
254 sc->sc_sh = memh;
255 } else if (ioh_valid) {
256 sc->sc_st = iot;
257 sc->sc_sh = ioh;
258 } else {
259 printf(": unable to map device registers\n");
260 return;
261 }
262
263 sc->sc_dmat = pa->pa_dmat;
264
265 /*
266 * Make sure bus mastering is enabled.
267 */
268 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
269 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
270 PCI_COMMAND_MASTER_ENABLE);
271
272 /*
273 * Get the cacheline size.
274 */
275 sc->sc_cacheline = PCI_CACHELINE(pci_conf_read(pc, pa->pa_tag,
276 PCI_BHLC_REG));
277
278 /*
279 * Get PCI data moving command info.
280 */
281 if (pa->pa_flags & PCI_FLAGS_MRL_OKAY) /* read line */
282 sc->sc_flags |= ATWF_MRL;
283 if (pa->pa_flags & PCI_FLAGS_MRM_OKAY) /* read multiple */
284 sc->sc_flags |= ATWF_MRM;
285 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) /* write invalidate */
286 sc->sc_flags |= ATWF_MWI;
287
288 /*
289 * Map and establish our interrupt.
290 */
291 if (pci_intr_map(pa, &psc->psc_ih)) {
292 printf("%s: unable to map interrupt\n",
293 sc->sc_dev.dv_xname);
294 return;
295 }
296 intrstr = pci_intr_string(pc, psc->psc_ih);
297 psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET,
298 atw_intr, sc);
299 if (psc->psc_intrcookie == NULL) {
300 printf("%s: unable to establish interrupt",
301 sc->sc_dev.dv_xname);
302 if (intrstr != NULL)
303 printf(" at %s", intrstr);
304 printf("\n");
305 return;
306 }
307
308 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
309
310 sc->sc_enable = atw_pci_enable;
311 sc->sc_disable = atw_pci_disable;
312
313 /*
314 * Finish off the attach.
315 */
316 atw_attach(sc);
317 }
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