if_epic_pci.c

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    1 /*      $NetBSD: if_epic_pci.c,v 1.26 2003/01/31 00:07:42 thorpej Exp $ */
    2 
    3 /*-
    4  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
    9  * NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 /*
   41  * PCI bus front-end for the Standard Microsystems Corp. 83C170
   42  * Ethernet PCI Integrated Controller (EPIC/100) driver.
   43  */
   44 
   45 #include <sys/cdefs.h>
   46 __KERNEL_RCSID(0, "$NetBSD: if_epic_pci.c,v 1.26 2003/01/31 00:07:42 thorpej Exp $");
   47 
   48 #include <sys/param.h>
   49 #include <sys/systm.h> 
   50 #include <sys/mbuf.h>   
   51 #include <sys/malloc.h>
   52 #include <sys/kernel.h>
   53 #include <sys/socket.h>
   54 #include <sys/ioctl.h>
   55 #include <sys/errno.h>
   56 #include <sys/device.h>
   57  
   58 #include <net/if.h>
   59 #include <net/if_dl.h>
   60 #include <net/if_media.h>
   61 #include <net/if_ether.h>
   62 
   63 #include <machine/bus.h>
   64 #include <machine/intr.h>
   65 
   66 #include <dev/mii/miivar.h>
   67 
   68 #include <dev/ic/smc83c170reg.h>
   69 #include <dev/ic/smc83c170var.h>
   70 
   71 #include <dev/pci/pcivar.h>
   72 #include <dev/pci/pcireg.h>
   73 #include <dev/pci/pcidevs.h>
   74 
   75 /*
   76  * PCI configuration space registers used by the EPIC.
   77  */
   78 #define EPIC_PCI_IOBA           0x10    /* i/o mapped base */
   79 #define EPIC_PCI_MMBA           0x14    /* memory mapped base */
   80 
   81 struct epic_pci_softc {
   82         struct epic_softc sc_epic;      /* real EPIC softc */
   83 
   84         /* PCI-specific goo. */
   85         void    *sc_ih;                 /* interrupt handle */
   86 };
   87 
   88 int     epic_pci_match(struct device *, struct cfdata *, void *);
   89 void    epic_pci_attach(struct device *, struct device *, void *);
   90 
   91 CFATTACH_DECL(epic_pci, sizeof(struct epic_pci_softc),
   92     epic_pci_match, epic_pci_attach, NULL, NULL);
   93 
   94 const struct epic_pci_product {
   95         u_int32_t       epp_prodid;     /* PCI product ID */
   96         const char      *epp_name;      /* device name */
   97 } epic_pci_products[] = {
   98         { PCI_PRODUCT_SMC_83C170,       "SMC 83c170 Fast Ethernet" },
   99         { PCI_PRODUCT_SMC_83C175,       "SMC 83c175 Fast Ethernet" },
  100         { 0,                            NULL },
  101 };
  102 
  103 const struct epic_pci_product *epic_pci_lookup(const struct pci_attach_args *);
  104 
  105 const struct epic_pci_product *
  106 epic_pci_lookup(pa)
  107         const struct pci_attach_args *pa;
  108 {
  109         const struct epic_pci_product *epp;
  110 
  111         if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SMC)
  112                 return (NULL);
  113 
  114         for (epp = epic_pci_products; epp->epp_name != NULL; epp++)
  115                 if (PCI_PRODUCT(pa->pa_id) == epp->epp_prodid)
  116                         return (epp);
  117 
  118         return (NULL);
  119 }
  120 
  121 const struct epic_pci_subsys_info {
  122         pcireg_t subsysid;
  123         int flags;
  124 } epic_pci_subsys_info[] = {
  125         { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa015), /* SMC9432BTX */
  126           EPIC_HAS_BNC },
  127         { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa024), /* SMC9432BTX1 */
  128           EPIC_HAS_BNC },
  129         { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa016), /* SMC9432FTX */
  130           EPIC_HAS_MII_FIBER | EPIC_DUPLEXLED_ON_694 },
  131         { 0xffffffff,
  132           0 }
  133 };
  134 
  135 const struct epic_pci_subsys_info *
  136   epic_pci_subsys_lookup(const struct pci_attach_args *);
  137 
  138 const struct epic_pci_subsys_info *
  139 epic_pci_subsys_lookup(pa)
  140         const struct pci_attach_args *pa;
  141 {
  142         pci_chipset_tag_t pc = pa->pa_pc;
  143         pcireg_t reg;
  144         const struct epic_pci_subsys_info *esp;
  145 
  146         reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
  147 
  148         for (esp = epic_pci_subsys_info; esp->subsysid != 0xffffffff; esp++)
  149                 if (esp->subsysid == reg)
  150                         return (esp);
  151 
  152         return (NULL);
  153 }
  154 
  155 int
  156 epic_pci_match(parent, match, aux)
  157         struct device *parent;
  158         struct cfdata *match;
  159         void *aux;
  160 {
  161         struct pci_attach_args *pa = aux;
  162 
  163         if (epic_pci_lookup(pa) != NULL)
  164                 return (1);
  165 
  166         return (0);
  167 }
  168 
  169 void
  170 epic_pci_attach(parent, self, aux)
  171         struct device *parent, *self;
  172         void *aux;
  173 {
  174         struct epic_pci_softc *psc = (struct epic_pci_softc *)self;
  175         struct epic_softc *sc = &psc->sc_epic;
  176         struct pci_attach_args *pa = aux;
  177         pci_chipset_tag_t pc = pa->pa_pc;
  178         pci_intr_handle_t ih;
  179         const char *intrstr = NULL;
  180         const struct epic_pci_product *epp;
  181         const struct epic_pci_subsys_info *esp;
  182         bus_space_tag_t iot, memt;
  183         bus_space_handle_t ioh, memh;
  184         pcireg_t reg;
  185         int pmreg, ioh_valid, memh_valid;
  186 
  187         aprint_naive(": Ethernet controller\n");
  188 
  189         epp = epic_pci_lookup(pa);
  190         if (epp == NULL) {
  191                 printf("\n");
  192                 panic("epic_pci_attach: impossible");
  193         }
  194 
  195         aprint_normal(": %s, rev. %d\n", epp->epp_name,
  196             PCI_REVISION(pa->pa_class));
  197 
  198         if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
  199                 reg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR);
  200                 switch (reg & PCI_PMCSR_STATE_MASK) {
  201                 case PCI_PMCSR_STATE_D1:
  202                 case PCI_PMCSR_STATE_D2:
  203                         aprint_normal("%s: waking up from power state D%d\n",
  204                             sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK);
  205                         pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
  206                             (reg & ~PCI_PMCSR_STATE_MASK) |
  207                             PCI_PMCSR_STATE_D0);
  208                         break;
  209                 case PCI_PMCSR_STATE_D3:
  210                         /*
  211                          * IO and MEM are disabled. We can't enable
  212                          * the card because the BARs might be invalid.
  213                          */
  214                         aprint_error(
  215                             "%s: unable to wake up from power state D3, "
  216                             "reboot required.\n", sc->sc_dev.dv_xname);
  217                         pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
  218                             (reg & ~PCI_PMCSR_STATE_MASK) |
  219                             PCI_PMCSR_STATE_D0);
  220                         return;
  221                 }
  222         }
  223 
  224         /*
  225          * Map the device.
  226          */
  227         ioh_valid = (pci_mapreg_map(pa, EPIC_PCI_IOBA,
  228             PCI_MAPREG_TYPE_IO, 0,
  229             &iot, &ioh, NULL, NULL) == 0);
  230         memh_valid = (pci_mapreg_map(pa, EPIC_PCI_MMBA,
  231             PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
  232             &memt, &memh, NULL, NULL) == 0);
  233 
  234         if (memh_valid) {
  235                 sc->sc_st = memt;
  236                 sc->sc_sh = memh;
  237         } else if (ioh_valid) {
  238                 sc->sc_st = iot;
  239                 sc->sc_sh = ioh;
  240         } else {
  241                 aprint_error("%s: unable to map device registers\n",
  242                     sc->sc_dev.dv_xname);
  243                 return;
  244         }
  245 
  246         sc->sc_dmat = pa->pa_dmat;
  247 
  248         /* Make sure bus mastering is enabled. */
  249         pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
  250             pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
  251             PCI_COMMAND_MASTER_ENABLE);
  252 
  253         /*
  254          * Map and establish our interrupt.
  255          */
  256         if (pci_intr_map(pa, &ih)) {
  257                 aprint_error("%s: unable to map interrupt\n",
  258                     sc->sc_dev.dv_xname);
  259                 return;
  260         }
  261         intrstr = pci_intr_string(pc, ih); 
  262         psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, epic_intr, sc);
  263         if (psc->sc_ih == NULL) {
  264                 aprint_error("%s: unable to establish interrupt",
  265                     sc->sc_dev.dv_xname);
  266                 if (intrstr != NULL)
  267                         aprint_normal(" at %s", intrstr);
  268                 aprint_normal("\n");
  269                 return;
  270         }
  271         aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
  272 
  273         esp = epic_pci_subsys_lookup(pa);
  274         if (esp)
  275                 sc->sc_hwflags = esp->flags;
  276 
  277         /*
  278          * Finish off the attach.
  279          */
  280         epic_attach(sc);
  281 }
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FreeBSD/Linux Kernel Cross Reference sys/dev/pci/if_epic_pci.c

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sys/dev/pci/if_epic_pci.c
