1 /* $NetBSD: if_fxp_pci.c,v 1.37.2.1 2004/04/28 07:06:49 tron Exp $ */
2
3 /*-
4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * PCI bus front-end for the Intel i82557 fast Ethernet controller
42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards.
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.37.2.1 2004/04/28 07:06:49 tron Exp $");
47
48 #include "rnd.h"
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/mbuf.h>
53 #include <sys/malloc.h>
54 #include <sys/kernel.h>
55 #include <sys/socket.h>
56 #include <sys/ioctl.h>
57 #include <sys/errno.h>
58 #include <sys/device.h>
59
60 #if NRND > 0
61 #include <sys/rnd.h>
62 #endif
63
64 #include <machine/endian.h>
65
66 #include <net/if.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_ether.h>
70
71 #include <machine/bus.h>
72 #include <machine/intr.h>
73
74 #include <dev/mii/miivar.h>
75
76 #include <dev/ic/i82557reg.h>
77 #include <dev/ic/i82557var.h>
78
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcireg.h>
81 #include <dev/pci/pcidevs.h>
82
83 struct fxp_pci_softc {
84 struct fxp_softc psc_fxp;
85
86 pci_chipset_tag_t psc_pc; /* pci chipset tag */
87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */
88 pcitag_t psc_tag; /* pci register tag */
89 void *psc_powerhook; /* power hook */
90
91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */
92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */
93 };
94
95 int fxp_pci_match __P((struct device *, struct cfdata *, void *));
96 void fxp_pci_attach __P((struct device *, struct device *, void *));
97
98 int fxp_pci_enable __P((struct fxp_softc *));
99 void fxp_pci_disable __P((struct fxp_softc *));
100
101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc));
102 static void fxp_pci_power __P((int why, void *arg));
103
104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc),
105 fxp_pci_match, fxp_pci_attach, NULL, NULL);
106
107 static const struct fxp_pci_product {
108 u_int32_t fpp_prodid; /* PCI product ID */
109 const char *fpp_name; /* device name */
110 } fxp_pci_products[] = {
111 { PCI_PRODUCT_INTEL_82557,
112 "Intel i82557 Ethernet" },
113 { PCI_PRODUCT_INTEL_82559ER,
114 "Intel i82559ER Ethernet" },
115 { PCI_PRODUCT_INTEL_IN_BUSINESS,
116 "Intel InBusiness Ethernet" },
117 { PCI_PRODUCT_INTEL_82801BA_LAN,
118 "Intel i82562 Ethernet" },
119 { PCI_PRODUCT_INTEL_82801E_LAN_1,
120 "Intel i82559 Ethernet" },
121 { PCI_PRODUCT_INTEL_82801E_LAN_2,
122 "Intel i82559 Ethernet" },
123 { PCI_PRODUCT_INTEL_PRO_100_VE_0,
124 "Intel PRO/100 VE Network Controller" },
125 { PCI_PRODUCT_INTEL_PRO_100_VE_1,
126 "Intel PRO/100 VE Network Controller" },
127 { PCI_PRODUCT_INTEL_PRO_100_VE_2,
128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" },
129 { PCI_PRODUCT_INTEL_PRO_100_VE_3,
130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" },
131 { PCI_PRODUCT_INTEL_PRO_100_VE_4,
132 "Intel PRO/100 VE (MOB) Network Controller" },
133 { PCI_PRODUCT_INTEL_PRO_100_VM_0,
134 "Intel PRO/100 VM Network Controller" },
135 { PCI_PRODUCT_INTEL_PRO_100_VM_1,
136 "Intel PRO/100 VM Network Controller" },
137 { PCI_PRODUCT_INTEL_PRO_100_VM_2,
138 "Intel PRO/100 VM Network Controller" },
139 { PCI_PRODUCT_INTEL_PRO_100_VM_3,
140 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" },
141 { PCI_PRODUCT_INTEL_PRO_100_VM_4,
142 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" },
143 { PCI_PRODUCT_INTEL_PRO_100_VM_5,
144 "Intel PRO/100 VM (MOB) Network Controller" },
145 { PCI_PRODUCT_INTEL_PRO_100_VM_6,
146 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" },
147 { PCI_PRODUCT_INTEL_PRO_100_M,
148 "Intel PRO/100 M Network Controller" },
149 { PCI_PRODUCT_INTEL_82801EB_LAN,
150 "Intel 82801EB/ER (ICH5) Network Controller" },
151 { 0,
152 NULL },
153 };
154
155 static const struct fxp_pci_product *
156 fxp_pci_lookup(const struct pci_attach_args *pa)
157 {
158 const struct fxp_pci_product *fpp;
159
160 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
161 return (NULL);
162
163 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++)
164 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid)
165 return (fpp);
166
167 return (NULL);
168 }
169
170 int
171 fxp_pci_match(parent, match, aux)
172 struct device *parent;
173 struct cfdata *match;
174 void *aux;
175 {
176 struct pci_attach_args *pa = aux;
177
178 if (fxp_pci_lookup(pa) != NULL)
179 return (1);
180
181 return (0);
182 }
183
184 /*
185 * Restore PCI configuration registers that may have been clobbered.
186 * This is necessary due to bugs on the Sony VAIO Z505-series on-board
187 * ethernet, after an APM suspend/resume, as well as after an ACPI
188 * D3->D0 transition. We call this function from a power hook after
189 * APM resume events, as well as after the ACPI D3->D0 transition.
190 */
191 static void
192 fxp_pci_confreg_restore(psc)
193 struct fxp_pci_softc *psc;
194 {
195 pcireg_t reg;
196
197 #if 0
198 /*
199 * Check to see if the command register is blank -- if so, then
200 * we'll assume that all the clobberable-registers have been
201 * clobbered.
202 */
203
204 /*
205 * In general, the above metric is accurate. Unfortunately,
206 * it is inaccurate across a hibernation. Ideally APM/ACPI
207 * code should take note of hibernation events and execute
208 * a hibernation wakeup hook, but at present a hibernation wake
209 * is indistinguishable from a suspend wake.
210 */
211
212 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag,
213 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0)
214 return;
215 #else
216 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG);
217 #endif
218
219 pci_conf_write(psc->psc_pc, psc->psc_tag,
220 PCI_COMMAND_STATUS_REG,
221 (reg & 0xffff0000) |
222 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff));
223 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG,
224 psc->psc_regs[PCI_BHLC_REG>>2]);
225 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0,
226 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]);
227 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4,
228 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]);
229 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8,
230 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]);
231 }
232
233
234 /*
235 * Power handler routine. Called when the system is transitioning into/out
236 * of power save modes. We restore the (bashed) PCI configuration registers
237 * on a resume.
238 */
239 static void
240 fxp_pci_power(why, arg)
241 int why;
242 void *arg;
243 {
244 struct fxp_pci_softc *psc = arg;
245
246 if (why == PWR_RESUME)
247 fxp_pci_confreg_restore(psc);
248 }
249
250 void
251 fxp_pci_attach(parent, self, aux)
252 struct device *parent, *self;
253 void *aux;
254 {
255 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self;
256 struct fxp_softc *sc = (struct fxp_softc *)self;
257 struct pci_attach_args *pa = aux;
258 pci_chipset_tag_t pc = pa->pa_pc;
259 pci_intr_handle_t ih;
260 const struct fxp_pci_product *fpp;
261 const char *intrstr = NULL;
262 bus_space_tag_t iot, memt;
263 bus_space_handle_t ioh, memh;
264 int ioh_valid, memh_valid;
265 bus_addr_t addr;
266 bus_size_t size;
267 int flags;
268 int pci_pwrmgmt_cap_reg;
269
270 aprint_naive(": Ethernet controller\n");
271
272 /*
273 * Map control/status registers.
274 */
275 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA,
276 PCI_MAPREG_TYPE_IO, 0,
277 &iot, &ioh, NULL, NULL) == 0);
278
279 /*
280 * Version 2.1 of the PCI spec, page 196, "Address Maps":
281 *
282 * Prefetchable
283 *
284 * Set to one if there are no side effects on reads, the
285 * device returns all bytes regardless of the byte enables,
286 * and host bridges can merge processor writes into this
287 * range without causing errors. Bit must be set to zero
288 * otherwise.
289 *
290 * The 82557 incorrectly sets the "prefetchable" bit, resulting
291 * in errors on systems which will do merged reads and writes.
292 * These errors manifest themselves as all-bits-set when reading
293 * from the EEPROM or other < 4 byte registers.
294 *
295 * We must work around this problem by always forcing the mapping
296 * for memory space to be uncacheable. On systems which cannot
297 * create an uncacheable mapping (because the firmware mapped it
298 * into only cacheable/prefetchable space due to the "prefetchable"
299 * bit), we can fall back onto i/o mapped access.
300 */
301 memh_valid = 0;
302 memt = pa->pa_memt;
303 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) &&
304 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA,
305 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT,
306 &addr, &size, &flags) == 0) {
307 flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
308 if (bus_space_map(memt, addr, size, flags, &memh) == 0)
309 memh_valid = 1;
310 }
311
312 if (memh_valid) {
313 sc->sc_st = memt;
314 sc->sc_sh = memh;
315 } else if (ioh_valid) {
316 sc->sc_st = iot;
317 sc->sc_sh = ioh;
318 } else {
319 aprint_error(": unable to map device registers\n");
320 return;
321 }
322
323 sc->sc_dmat = pa->pa_dmat;
324
325 fpp = fxp_pci_lookup(pa);
326 if (fpp == NULL) {
327 printf("\n");
328 panic("fxp_pci_attach: impossible");
329 }
330
331 sc->sc_rev = PCI_REVISION(pa->pa_class);
332
333 switch (fpp->fpp_prodid) {
334 case PCI_PRODUCT_INTEL_82557:
335 case PCI_PRODUCT_INTEL_82559ER:
336 case PCI_PRODUCT_INTEL_IN_BUSINESS:
337 {
338 const char *chipname = NULL;
339
340 if (sc->sc_rev >= FXP_REV_82558_A4) {
341 chipname = "i82558 Ethernet";
342 /*
343 * Enable the MWI command for memory writes.
344 */
345 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY)
346 sc->sc_flags |= FXPF_MWI;
347 }
348 if (sc->sc_rev >= FXP_REV_82559_A0)
349 chipname = "i82559 Ethernet";
350 if (sc->sc_rev >= FXP_REV_82559S_A)
351 chipname = "i82559S Ethernet";
352 if (sc->sc_rev >= FXP_REV_82550)
353 chipname = "i82550 Ethernet";
354
355 /*
356 * Mark all i82559 and i82550 revisions as having
357 * the "resume bug". See i82557.c for details.
358 */
359 if (sc->sc_rev >= FXP_REV_82559_A0)
360 sc->sc_flags |= FXPF_HAS_RESUME_BUG;
361
362 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname :
363 fpp->fpp_name, sc->sc_rev);
364 break;
365 }
366
367 case PCI_PRODUCT_INTEL_82801BA_LAN:
368 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev);
369
370 /*
371 * The 82801BA Ethernet has a bug which requires us to send a
372 * NOP before a CU_RESUME if we're in 10baseT mode.
373 */
374 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN)
375 sc->sc_flags |= FXPF_HAS_RESUME_BUG;
376 break;
377
378 case PCI_PRODUCT_INTEL_PRO_100_VE_0:
379 case PCI_PRODUCT_INTEL_PRO_100_VE_1:
380 case PCI_PRODUCT_INTEL_PRO_100_VM_0:
381 case PCI_PRODUCT_INTEL_PRO_100_VM_1:
382 case PCI_PRODUCT_INTEL_82562EH_HPNA_0:
383 case PCI_PRODUCT_INTEL_82562EH_HPNA_1:
384 case PCI_PRODUCT_INTEL_82562EH_HPNA_2:
385 case PCI_PRODUCT_INTEL_PRO_100_VM_2:
386 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev);
387
388 /*
389 * ICH3 chips apparently have problems with the enhanced
390 * features, so just treat them as an i82557. It also
391 * has the resume bug that the ICH2 has.
392 */
393 sc->sc_rev = 1;
394 sc->sc_flags |= FXPF_HAS_RESUME_BUG;
395 break;
396 case PCI_PRODUCT_INTEL_82801E_LAN_1:
397 case PCI_PRODUCT_INTEL_82801E_LAN_2:
398 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev);
399
400 /*
401 * XXX We have to read the C-ICH's developer's manual
402 * in detail
403 */
404 break;
405 case PCI_PRODUCT_INTEL_PRO_100_VE_2:
406 case PCI_PRODUCT_INTEL_PRO_100_VE_3:
407 case PCI_PRODUCT_INTEL_PRO_100_VE_4:
408 case PCI_PRODUCT_INTEL_PRO_100_VM_3:
409 case PCI_PRODUCT_INTEL_PRO_100_VM_4:
410 case PCI_PRODUCT_INTEL_PRO_100_VM_5:
411 case PCI_PRODUCT_INTEL_PRO_100_VM_6:
412 case PCI_PRODUCT_INTEL_82801EB_LAN:
413 default:
414 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev);
415
416 /*
417 * No particular quirks.
418 */
419 break;
420 }
421
422 /* Make sure bus-mastering is enabled. */
423 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
424 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
425 PCI_COMMAND_MASTER_ENABLE);
426
427 /*
428 * Under some circumstances (such as APM suspend/resume
429 * cycles, and across ACPI power state changes), the
430 * i82257-family can lose the contents of critical PCI
431 * configuration registers, causing the card to be
432 * non-responsive and useless. This occurs on the Sony VAIO
433 * Z505-series, among others. Preserve them here so they can
434 * be later restored (by fxp_pci_confreg_restore()).
435 */
436 psc->psc_pc = pc;
437 psc->psc_tag = pa->pa_tag;
438 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] =
439 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
440 psc->psc_regs[PCI_BHLC_REG>>2] =
441 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG);
442 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] =
443 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0);
444 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] =
445 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4);
446 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] =
447 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8);
448
449 /*
450 * Work around BIOS ACPI bugs where the chip is inadvertantly
451 * left in ACPI D3 (lowest power state). First confirm the device
452 * supports ACPI power management, then move it to the D0 (fully
453 * functional) state if it is not already there.
454 */
455 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT,
456 &pci_pwrmgmt_cap_reg, 0)) {
457 pcireg_t reg;
458
459 sc->sc_enable = fxp_pci_enable;
460 sc->sc_disable = fxp_pci_disable;
461
462 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR;
463 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg);
464 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) |
465 PCI_PMCSR_STATE_D0;
466 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0)
467 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg,
468 psc->psc_pwrmgmt_csr);
469 }
470 /* Restore PCI configuration registers. */
471 fxp_pci_confreg_restore(psc);
472
473 sc->sc_enabled = 1;
474
475 /*
476 * Map and establish our interrupt.
477 */
478 if (pci_intr_map(pa, &ih)) {
479 aprint_error("%s: couldn't map interrupt\n",
480 sc->sc_dev.dv_xname);
481 return;
482 }
483 intrstr = pci_intr_string(pc, ih);
484 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc);
485 if (sc->sc_ih == NULL) {
486 aprint_error("%s: couldn't establish interrupt",
487 sc->sc_dev.dv_xname);
488 if (intrstr != NULL)
489 aprint_normal(" at %s", intrstr);
490 aprint_normal("\n");
491 return;
492 }
493 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
494
495 /* Finish off the attach. */
496 fxp_attach(sc);
497 if (sc->sc_disable != NULL)
498 fxp_disable(sc);
499
500 /* Add a suspend hook to restore PCI config state */
501 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc);
502 if (psc->psc_powerhook == NULL)
503 aprint_error(
504 "%s: WARNING: unable to establish pci power hook\n",
505 sc->sc_dev.dv_xname);
506 }
507
508 int
509 fxp_pci_enable(struct fxp_softc *sc)
510 {
511 struct fxp_pci_softc *psc = (void *) sc;
512
513 #if 0
514 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname);
515 #endif
516
517 /* Bring the device into D0 power state. */
518 pci_conf_write(psc->psc_pc, psc->psc_tag,
519 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr);
520
521 /* Now restore the configuration registers. */
522 fxp_pci_confreg_restore(psc);
523
524 return (0);
525 }
526
527 void
528 fxp_pci_disable(struct fxp_softc *sc)
529 {
530 struct fxp_pci_softc *psc = (void *) sc;
531
532 /*
533 * for some 82558_A4 and 82558_B0, entering D3 state makes
534 * media detection disordered.
535 */
536 if (sc->sc_rev <= FXP_REV_82558_B0)
537 return;
538
539 #if 0
540 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname);
541 #endif
542
543 /* Put the device into D3 state. */
544 pci_conf_write(psc->psc_pc, psc->psc_tag,
545 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr &
546 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3);
547 }
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