The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/if_sipreg.h

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    1 /*      $NetBSD: if_sipreg.h,v 1.13 2003/12/03 21:58:49 cube Exp $      */
    2 
    3 /*-
    4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the NetBSD
   21  *      Foundation, Inc. and its contributors.
   22  * 4. Neither the name of The NetBSD Foundation nor the names of its
   23  *    contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   36  * POSSIBILITY OF SUCH DAMAGE.
   37  */
   38 
   39 /*-
   40  * Copyright (c) 1999 Network Computer, Inc.
   41  * All rights reserved.
   42  *
   43  * Redistribution and use in source and binary forms, with or without
   44  * modification, are permitted provided that the following conditions
   45  * are met:
   46  * 1. Redistributions of source code must retain the above copyright
   47  *    notice, this list of conditions and the following disclaimer.
   48  * 2. Redistributions in binary form must reproduce the above copyright
   49  *    notice, this list of conditions and the following disclaimer in the
   50  *    documentation and/or other materials provided with the distribution.
   51  * 3. Neither the name of Network Computer, Inc. nor the names of its
   52  *    contributors may be used to endorse or promote products derived
   53  *    from this software without specific prior written permission.
   54  *
   55  * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS
   56  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   57  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   58  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   59  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   60  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   61  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   62  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   63  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   64  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   65  * POSSIBILITY OF SUCH DAMAGE.
   66  */
   67 
   68 #ifndef _DEV_PCI_IF_SIPREG_H_
   69 #define _DEV_PCI_IF_SIPREG_H_
   70 
   71 /*
   72  * Register description for the Silicon Integrated Systems SiS 900,
   73  * SiS 7016, National Semiconductor DP83815 10/100, and National
   74  * Semiconduction DP83820 10/100/1000 PCI Ethernet controller.
   75  *
   76  * Written by Jason R. Thorpe for Network Computer, Inc.
   77  */
   78 
   79 /*
   80  * Transmit FIFO size.  Used to compute the transmit drain threshold.
   81  *
   82  * The transmit FIFO is arranged as a 512 32-bit memory array.
   83  */
   84 #define SIP_TXFIFO_SIZE (512 * 4)
   85 
   86 /*
   87  * The SiS900 uses a single descriptor format for both transmit
   88  * and receive descriptor chains.
   89  *
   90  * Note the DP83820 can use 64-bit DMA addresses for link and bufptr.
   91  * However, we do not yet support that.
   92  *
   93  * For transmit, buffers need not be aligned.  For receive, buffers
   94  * must be aligned to 4-byte (8-byte on DP83820) boundaries.
   95  */
   96 struct sip_desc {
   97 #ifdef DP83820
   98         u_int32_t       sipd_link;      /* link to next descriptor */
   99         u_int32_t       sipd_bufptr;    /* pointer to DMA segment */
  100         u_int32_t       sipd_cmdsts;    /* command/status word */
  101         u_int32_t       sipd_extsts;    /* extended status */
  102 #else
  103         u_int32_t       sipd_link;      /* link to next descriptor */
  104         u_int32_t       sipd_cmdsts;    /* command/status word */
  105         u_int32_t       sipd_bufptr;    /* pointer to DMA segment */
  106 #endif /* DP83820 */
  107 };
  108 
  109 /*
  110  * CMDSTS bits common to transmit and receive.
  111  */
  112 #define CMDSTS_OWN      0x80000000      /* owned by consumer */
  113 #define CMDSTS_MORE     0x40000000      /* more descriptors */
  114 #define CMDSTS_INTR     0x20000000      /* interrupt when ownership changes */
  115 #define CMDSTS_SUPCRC   0x10000000      /* suppress CRC */
  116 #define CMDSTS_OK       0x08000000      /* packet ok */
  117 #ifdef DP83820
  118 #define CMDSTS_SIZE_MASK 0x0000ffff     /* packet size */
  119 #else
  120 #define CMDSTS_SIZE_MASK 0x000007ff     /* packet size */
  121 #endif /* DP83820 */
  122 
  123 #define CMDSTS_SIZE(x)  ((x) & CMDSTS_SIZE_MASK)
  124 
  125 /*
  126  * CMDSTS bits for transmit.
  127  */
  128 #define CMDSTS_Tx_TXA   0x04000000      /* transmit abort */
  129 #define CMDSTS_Tx_TFU   0x02000000      /* transmit FIFO underrun */
  130 #define CMDSTS_Tx_CRS   0x01000000      /* carrier sense lost */
  131 #define CMDSTS_Tx_TD    0x00800000      /* transmit deferred */
  132 #define CMDSTS_Tx_ED    0x00400000      /* excessive deferral */
  133 #define CMDSTS_Tx_OWC   0x00200000      /* out of window collision */
  134 #define CMDSTS_Tx_EC    0x00100000      /* excessive collisions */
  135 #define CMDSTS_Tx_CCNT  0x000f0000      /* collision count */
  136 
  137 #define CMDSTS_COLLISIONS(x)    (((x) & CMDSTS_Tx_CCNT) >> 16)
  138 
  139 /*
  140  * CMDSTS bits for receive.
  141  */
  142 #define CMDSTS_Rx_RXA   0x04000000      /* receive abort */
  143 #define CMDSTS_Rx_RXO   0x02000000      /* receive overrun */
  144 #define CMDSTS_Rx_DEST  0x01800000      /* destination class */
  145 #define CMDSTS_Rx_LONG  0x00400000      /* packet too long */
  146 #define CMDSTS_Rx_RUNT  0x00200000      /* runt packet */
  147 #define CMDSTS_Rx_ISE   0x00100000      /* invalid symbol error */
  148 #define CMDSTS_Rx_CRCE  0x00080000      /* CRC error */
  149 #define CMDSTS_Rx_FAE   0x00040000      /* frame alignment error */
  150 #define CMDSTS_Rx_LBP   0x00020000      /* loopback packet */
  151 #ifdef DP83820
  152 #define CMDSTS_Rx_IRL   0x00010000      /* in-range length error */
  153 #else
  154 #define CMDSTS_Rx_COL   0x00010000      /* collision activity */
  155 #endif /* DP83820 */
  156 
  157 #define CMDSTS_Rx_DEST_REJ 0x00000000   /* packet rejected */
  158 #define CMDSTS_Rx_DEST_STA 0x00800000   /* matched station address */
  159 #define CMDSTS_Rx_DEST_MUL 0x01000000   /* multicast address */
  160 #define CMDSTS_Rx_DEST_BRD 0x01800000   /* broadcast address */
  161 
  162 #ifdef DP83820
  163 /*
  164  * EXTSTS bits.
  165  */
  166 #define EXTSTS_Rx_UDPERR 0x00400000     /* UDP checksum error */
  167 #define EXTSTS_UDPPKT    0x00200000     /* perform UDP checksum */
  168 #define EXTSTS_Rx_TCPERR 0x00100000     /* TCP checksum error */
  169 #define EXTSTS_TCPPKT    0x00080000     /* perform TCP checksum */
  170 #define EXTSTS_Rx_IPERR  0x00040000     /* IP header checksum error */
  171 #define EXTSTS_IPPKT     0x00020000     /* perform IP header checksum */
  172 #define EXTSTS_VPKT      0x00010000     /* insert VLAN tag */
  173 #define EXTSTS_VTCI      0x0000ffff     /* VLAN tag control information */
  174 #endif /* DP83820 */
  175 
  176 /*
  177  * PCI Configuration space registers.
  178  */
  179 #define SIP_PCI_CFGIOA  (PCI_MAPREG_START + 0x00)
  180 
  181 #define SIP_PCI_CFGMA   (PCI_MAPREG_START + 0x04)
  182 
  183 #ifdef DP83820
  184 #define SIP_PCI_CFGMA1  (PCI_MAPREG_START + 0x08)
  185 #endif /* DP83820 */
  186 
  187 #define SIP_PCI_CFGEROMA 0x30           /* expansion ROM address */
  188 
  189 #define SIP_PCI_CFGPMC   0x40           /* power management cap. */
  190 
  191 #define SIP_PCI_CFGPMCSR 0x44           /* power management ctl. */
  192 
  193 /*
  194  * MAC Operation Registers
  195  */
  196 #define SIP_CR          0x00    /* command register */
  197 #ifdef DP83820
  198 #define CR_RXPRI3       0x00010000      /* Rx priority queue select */
  199 #define CR_RXPRI2       0x00008000      /* Rx priority queue select */
  200 #define CR_RXPRI1       0x00004000      /* Rx priority queue select */
  201 #define CR_RXPRI0       0x00002000      /* Rx priority queue select */
  202 #define CR_TXPRI3       0x00001000      /* Tx priority queue select */
  203 #define CR_TXPRI2       0x00000800      /* Tx priority queue select */
  204 #define CR_TXPRI1       0x00000400      /* Tx priority queue select */
  205 #define CR_TXPRI0       0x00000200      /* Tx priority queue select */
  206 #endif /* DP83820 */
  207 #define CR_RLD          0x00000400      /* reload from NVRAM */
  208 #define CR_RST          0x00000100      /* software reset */
  209 #define CR_SWI          0x00000080      /* software interrupt */
  210 #define CR_RXR          0x00000020      /* receiver reset */
  211 #define CR_TXR          0x00000010      /* transmit reset */
  212 #define CR_RXD          0x00000008      /* receiver disable */
  213 #define CR_RXE          0x00000004      /* receiver enable */
  214 #define CR_TXD          0x00000002      /* transmit disable */
  215 #define CR_TXE          0x00000001      /* transmit enable */
  216 
  217 #define SIP_CFG         0x04    /* configuration register */
  218 #define CFG_LNKSTS      0x80000000      /* link status (83815) */
  219 #ifdef DP83820
  220 #define CFG_SPEED1000   0x40000000      /* 1000Mb/s input pin */
  221 #define CFG_SPEED100    0x20000000      /* 100Mb/s input pin */
  222 #define CFG_DUPSTS      0x10000000      /* full-duplex status */
  223 #define CFG_TBI_EN      0x01000000      /* ten-bit interface enable */
  224 #define CFG_MODE_1000   0x00400000      /* 1000Mb/s mode enable */
  225 #define CFG_PINT_DUP    0x00100000      /* interrupt on PHY DUP change */
  226 #define CFG_PINT_LNK    0x00080000      /* interrupt on PHY LNK change */
  227 #define CFG_PINT_SPD    0x00040000      /* interrupt on PHY SPD change */
  228 #define CFG_TMRTEST     0x00020000      /* timer test mode */
  229 #define CFG_MRM_DIS     0x00010000      /* MRM disable */
  230 #define CFG_MWI_DIS     0x00008000      /* MWI disable */
  231 #define CFG_T64ADDR     0x00004000      /* target 64-bit addressing enable */
  232 #define CFG_PCI64_DET   0x00002000      /* 64-bit PCI bus detected */
  233 #define CFG_DATA64_EN   0x00001000      /* 64-bit data enable */
  234 #define CFG_M64ADDR     0x00000800      /* master 64-bit addressing enable */
  235 #else
  236 #define CFG_SPEED100    0x40000000      /* 100Mb/s (83815) */
  237 #define CFG_FDUP        0x20000000      /* full duplex (83815) */
  238 #define CFG_POL         0x10000000      /* 10Mb/s polarity (83815) */
  239 #define CFG_ANEG_DN     0x08000000      /* autonegotiation done (83815) */
  240 #define CFG_PHY_CFG     0x00fc0000      /* PHY configuration (83815) */
  241 #define CFG_PINT_ACEN   0x00020000      /* PHY interrupt auto clear (83815) */
  242 #define CFG_PAUSE_ADV   0x00010000      /* pause advertise (83815) */
  243 #define CFG_ANEG_SEL    0x0000e000      /* autonegotiation select (83815) */
  244 #endif /* DP83820 */
  245 #define CFG_PHY_RST     0x00000400      /* PHY reset (83815) */
  246 #define CFG_PHY_DIS     0x00000200      /* PHY disable (83815) */
  247 #ifdef DP83820
  248 #define CFG_EXTSTS_EN   0x00000100      /* extended status enable */
  249 #else
  250 #define CFG_EUPHCOMP    0x00000100      /* 83810 descriptor compat (83815) */
  251 #endif /* DP83820 */
  252 #define CFG_EDBMASTEN   0x00002000      /* 635,900B ?? from linux driver */
  253 #define CFG_RNDCNT      0x00000400      /* 635,900B ?? from linux driver */
  254 #define CFG_FAIRBO      0x00000200      /* 635,900B ?? from linux driver */
  255 #define CFG_REQALG      0x00000080      /* PCI bus request alg. */
  256 #define CFG_SB          0x00000040      /* single backoff */
  257 #define CFG_POW         0x00000020      /* program out of window timer */
  258 #define CFG_EXD         0x00000010      /* excessive defferal timer disable */
  259 #define CFG_PESEL       0x00000008      /* parity error detection action */
  260 #ifdef DP83820
  261 #define CFG_BROM_DIS    0x00000004      /* boot ROM disable */
  262 #define CFG_EXT_125     0x00000002      /* external 125MHz reference select */
  263 #endif /* DP83820 */
  264 #define CFG_BEM         0x00000001      /* big-endian mode */
  265 
  266 #define SIP_EROMAR      0x08    /* EEPROM access register */
  267 #ifndef DP83820
  268 #define EROMAR_REQ      0x00000400      /* SiS 96x specific */
  269 #define EROMAR_DONE     0x00000200      /* SiS 96x specific */
  270 #define EROMAR_GNT      0x00000100      /* SiS 96x specific */
  271 #endif /* DP83820 */
  272 #define EROMAR_MDC      0x00000040      /* MII clock */
  273 #define EROMAR_MDDIR    0x00000020      /* MII direction (1 == MAC->PHY) */
  274 #define EROMAR_MDIO     0x00000010      /* MII data */
  275 #define EROMAR_EECS     0x00000008      /* chip select */
  276 #define EROMAR_EESK     0x00000004      /* clock */
  277 #define EROMAR_EEDO     0x00000002      /* data out */
  278 #define EROMAR_EEDI     0x00000001      /* data in */
  279 
  280 #define SIP_PTSCR       0x0c    /* PCI test control register */
  281 #ifdef DP83820
  282 #define PTSCR_RBIST_RST     0x00002000  /* SRAM BIST reset */
  283 #define PTSCR_RBIST_EN      0x00000400  /* SRAM BIST enable */
  284 #define PTSCR_RBIST_DONE    0x00000200  /* SRAM BIST done */
  285 #define PTSCR_RBIST_RX1FAIL 0x00000100  /* Rx status FIFO BIST fail */
  286 #define PTSCR_RBIST_RX0FAIL 0x00000080  /* Rx data FIFO BIST fail */
  287 #define PTSCR_RBIST_TX0FAIL 0x00000020  /* Tx data FIFO BIST fail */
  288 #define PTSCR_RBIST_HFFAIL  0x00000010  /* hash filter BIST fail */
  289 #define PTSCR_RBIST_RXFAIL  0x00000008  /* Rx filter BIST failed */
  290 #define PTSCR_EELOAD_EN     0x00000004  /* EEPROM load initiate */
  291 #define PTSCR_EEBIST_EN     0x00000002  /* EEPROM BIST enable */
  292 #define PTSCR_EEBIST_FAIL   0x00000001  /* EEPROM BIST failed */
  293 #else
  294 #define PTSCR_DIS_TEST  0x40000000      /* discard timer test mode */
  295 #define PTSCR_EROM_TACC 0x0f000000      /* boot rom access time */
  296 #define PTSCR_TRRAMADR  0x001ff000      /* TX/RX RAM address */
  297 #define PTSCR_BMTEN     0x00000200      /* bus master test enable */
  298 #define PTSCR_RRTMEN    0x00000080      /* receive RAM test mode enable */
  299 #define PTSCR_TRTMEN    0x00000040      /* transmit RAM test mode enable */
  300 #define PTSCR_SRTMEN    0x00000020      /* status RAM test mode enable */
  301 #define PTSCR_SRAMADR   0x0000001f      /* status RAM address */
  302 #endif /* DP83820 */
  303 
  304 #define SIP_ISR         0x10    /* interrupt status register */
  305 #ifdef DP83820
  306 #define ISR_TXDESC3     0x40000000      /* Tx queue 3 */
  307 #define ISR_TXDESC2     0x20000000      /* Tx queue 2 */
  308 #define ISR_TXDESC1     0x10000000      /* Tx queue 1 */
  309 #define ISR_TXDESC0     0x08000000      /* Tx queue 0 */
  310 #define ISR_RXDESC3     0x04000000      /* Rx queue 3 */
  311 #define ISR_RXDESC2     0x02000000      /* Rx queue 2 */
  312 #define ISR_RXDESC1     0x01000000      /* Rx queue 1 */
  313 #define ISR_RXDESC0     0x00800000      /* Rx queue 0 */
  314 #define ISR_TXRCMP      0x00400000      /* transmit reset complete */
  315 #define ISR_RXRCMP      0x00200000      /* receive reset complete */
  316 #define ISR_DPERR       0x00100000      /* detected parity error */
  317 #define ISR_SSERR       0x00080000      /* signalled system error */
  318 #define ISR_RMABT       0x00040000      /* received master abort */
  319 #define ISR_RTABT       0x00020000      /* received target abort */
  320 #else
  321 #define ISR_WAKEEVT     0x10000000      /* wake up event */
  322 #define ISR_PAUSE_END   0x08000000      /* end of transmission pause */
  323 #define ISR_PAUSE_ST    0x04000000      /* start of transmission pause */
  324 #define ISR_TXRCMP      0x02000000      /* transmit reset complete */
  325 #define ISR_RXRCMP      0x01000000      /* receive reset complete */
  326 #define ISR_DPERR       0x00800000      /* detected parity error */
  327 #define ISR_SSERR       0x00400000      /* signalled system error */
  328 #define ISR_RMABT       0x00200000      /* received master abort */
  329 #define ISR_RTABT       0x00100000      /* received target abort */
  330 #endif /* DP83820 */
  331 #define ISR_RXSOVR      0x00010000      /* Rx status FIFO overrun */
  332 #define ISR_HIBERR      0x00008000      /* high bits error set */
  333 #ifdef DP83820
  334 #define ISR_PHY         0x00004000      /* PHY interrupt */
  335 #define ISR_PME         0x00002000      /* power management event */
  336 #endif /* DP83820 */
  337 #define ISR_SWI         0x00001000      /* software interrupt */
  338 #ifdef DP83820
  339 #define ISR_MIB         0x00000800      /* MIB service */
  340 #endif /* DP83820 */
  341 #define ISR_TXURN       0x00000400      /* Tx underrun */
  342 #define ISR_TXIDLE      0x00000200      /* Tx idle */
  343 #define ISR_TXERR       0x00000100      /* Tx error */
  344 #define ISR_TXDESC      0x00000080      /* Tx descriptor interrupt */
  345 #define ISR_TXOK        0x00000040      /* Tx okay */
  346 #define ISR_RXORN       0x00000020      /* Rx overrun */
  347 #define ISR_RXIDLE      0x00000010      /* Rx idle */
  348 #define ISR_RXEARLY     0x00000008      /* Rx early */
  349 #define ISR_RXERR       0x00000004      /* Rx error */
  350 #define ISR_RXDESC      0x00000002      /* Rx descriptor interrupt */
  351 #define ISR_RXOK        0x00000001      /* Rx okay */
  352 
  353 #define SIP_IMR         0x14    /* interrupt mask register */
  354 /* See bits in SIP_ISR */
  355 
  356 #define SIP_IER         0x18    /* interrupt enable register */
  357 #define IER_IE          0x00000001      /* master interrupt enable */
  358 
  359 #ifdef DP83820
  360 #define SIP_IHR         0x1c    /* interrupt hold-off register */
  361 #define IHR_IHCTL       0x00000100      /* interrupt hold-off control */
  362 #define IHR_IH          0x000000ff      /* interrupt hold-off timer (100us) */
  363 #else
  364 #define SIP_ENPHY       0x1c    /* enhanced PHY access register */
  365 #define ENPHY_PHYDATA   0xffff0000      /* PHY data */
  366 #define ENPHY_DATA_SHIFT 16
  367 #define ENPHY_PHYADDR   0x0000f800      /* PHY number (7016 only) */
  368 #define ENPHY_PHYADDR_SHIFT 11
  369 #define ENPHY_REGADDR   0x000007c0      /* PHY register */
  370 #define ENPHY_REGADDR_SHIFT 6
  371 #define ENPHY_RWCMD     0x00000020      /* 1 == read, 0 == write */
  372 #define ENPHY_ACCESS    0x00000010      /* PHY access enable */
  373 #endif /* DP83820 */
  374 
  375 #define SIP_TXDP        0x20    /* transmit descriptor pointer reg */
  376 
  377 #ifdef DP83820
  378 #define SIP_TXDP_HI     0x24    /* transmit descriptor pointer (high) reg */
  379 #endif /* DP83820 */
  380 
  381 #ifdef DP83820
  382 #define SIP_TXCFG       0x28    /* transmit configuration register */
  383 #else
  384 #define SIP_TXCFG       0x24    /* transmit configuration register */
  385 #endif /* DP83820 */
  386 #define TXCFG_CSI       0x80000000      /* carrier sense ignore */
  387 #define TXCFG_HBI       0x40000000      /* heartbeat ignore */
  388 #define TXCFG_MLB       0x20000000      /* MAC loopback */
  389 #define TXCFG_ATP       0x10000000      /* automatic transmit padding */
  390 #ifdef DP83820
  391 #define TXCFG_ECRETRY   0x008000000     /* excessive collision retry enable */
  392 #define TXCFG_MXDMA      0x00700000     /* max DMA burst size */
  393 #define TXCFG_MXDMA_1024 0x00000000     /*    1024 bytes */
  394 #define TXCFG_MXDMA_8    0x00100000     /*       8 bytes */
  395 #define TXCFG_MXDMA_16   0x00200000     /*      16 bytes */
  396 #define TXCFG_MXDMA_32   0x00300000     /*      32 bytes */
  397 #define TXCFG_MXDMA_64   0x00400000     /*      64 bytes */
  398 #define TXCFG_MXDMA_128  0x00500000     /*     128 bytes */
  399 #define TXCFG_MXDMA_256  0x00600000     /*     256 bytes */
  400 #define TXCFG_MXDMA_512  0x00700000     /*     512 bytes */
  401 #define TXCFG_BRST_DIS  0x00080000      /* 1000Mb/s burst disable */
  402 #define TXCFG_FLTH      0x0000ff00      /* Fx fill threshold */
  403 #define TXCFG_FLTH_SHIFT 8
  404 #define TXCFG_DRTH      0x000000ff      /* Tx drain threshold */
  405 #else
  406 #define TXCFG_MXDMA     0x00700000      /* max DMA burst size */
  407 #define TXCFG_MXDMA_512 0x00000000      /*     512 bytes */
  408 #define TXCFG_MXDMA_4   0x00100000      /*       4 bytes */
  409 #define TXCFG_MXDMA_8   0x00200000      /*       8 bytes */
  410 #define TXCFG_MXDMA_16  0x00300000      /*      16 bytes */
  411 #define TXCFG_MXDMA_32  0x00400000      /*      32 bytes */
  412 #define TXCFG_MXDMA_64  0x00500000      /*      64 bytes */
  413 #define TXCFG_MXDMA_128 0x00600000      /*     128 bytes */
  414 #define TXCFG_MXDMA_256 0x00700000      /*     256 bytes */
  415 #define TXCFG_FLTH      0x00003f00      /* Tx fill threshold */
  416 #define TXCFG_FLTH_SHIFT 8
  417 #define TXCFG_DRTH      0x0000003f      /* Tx drain threshold */
  418 #endif /* DP83820 */
  419 
  420 #ifdef DP83820
  421 #define SIP_GPIOR       0x2c    /* general purpose i/o register */
  422 #define GPIOR_GP5_IN    0x00004000      /* GP 5 in */
  423 #define GPIOR_GP4_IN    0x00002000      /* GP 4 in */
  424 #define GPIOR_GP3_IN    0x00001000      /* GP 3 in */
  425 #define GPIOR_GP2_IN    0x00000800      /* GP 2 in */
  426 #define GPIOR_GP1_IN    0x00000400      /* GP 1 in */
  427 #define GPIOR_GP5_OE    0x00000200      /* GP 5 out enable */
  428 #define GPIOR_GP4_OE    0x00000100      /* GP 4 out enable */
  429 #define GPIOR_GP3_OE    0x00000080      /* GP 3 out enable */
  430 #define GPIOR_GP2_OE    0x00000040      /* GP 2 out enable */
  431 #define GPIOR_GP1_OE    0x00000020      /* GP 1 out enable */
  432 #define GPIOR_GP5_OUT   0x00000010      /* GP 5 out */
  433 #define GPIOR_GP4_OUT   0x00000008      /* GP 4 out */
  434 #define GPIOR_GP3_OUT   0x00000004      /* GP 3 out */
  435 #define GPIOR_GP2_OUT   0x00000002      /* GP 2 out */
  436 #define GPIOR_GP1_OUT   0x00000001      /* GP 1 out */
  437 #endif /* DP83820 */
  438 
  439 #define SIP_RXDP        0x30    /* receive descriptor pointer reg */
  440 
  441 #ifdef DP83820
  442 #define SIP_RXDP_HI     0x34    /* receive descriptor pointer (high) reg */
  443 #endif /* DP83820 */
  444 
  445 #ifdef DP83820
  446 #define SIP_RXCFG       0x38    /* receive configuration register */
  447 #else
  448 #define SIP_RXCFG       0x34    /* receive configuration register */
  449 #endif
  450 #define RXCFG_AEP       0x80000000      /* accept error packets */
  451 #define RXCFG_ARP       0x40000000      /* accept runt packets */
  452 #ifdef DP83820
  453 #define RXCFG_STRIPCRC  0x20000000      /* strip CRC */
  454 #endif /* DP83820 */
  455 #define RXCFG_ATX       0x10000000      /* accept transmit packets */
  456 #define RXCFG_ALP       0x08000000      /* accept long packets */
  457 #ifdef DP83820
  458 #define RXCFG_AIRL      0x04000000      /* accept in-range length err packets */
  459 #define RXCFG_MXDMA      0x00700000     /* max DMA burst size */
  460 #define RXCFG_MXDMA_1024 0x00000000     /*    1024 bytes */
  461 #define RXCFG_MXDMA_8    0x00100000     /*       8 bytes */
  462 #define RXCFG_MXDMA_16   0x00200000     /*      16 bytes */
  463 #define RXCFG_MXDMA_32   0x00300000     /*      32 bytes */
  464 #define RXCFG_MXDMA_64   0x00400000     /*      64 bytes */
  465 #define RXCFG_MXDMA_128  0x00500000     /*     128 bytes */
  466 #define RXCFG_MXDMA_256  0x00600000     /*     256 bytes */
  467 #define RXCFG_MXDMA_512  0x00700000     /*     512 bytes */
  468 #else
  469 #define RXCFG_MXDMA     0x00700000      /* max DMA burst size */
  470 #define RXCFG_MXDMA_512 0x00000000      /*     512 bytes */
  471 #define RXCFG_MXDMA_4   0x00100000      /*       4 bytes */
  472 #define RXCFG_MXDMA_8   0x00200000      /*       8 bytes */
  473 #define RXCFG_MXDMA_16  0x00300000      /*      16 bytes */
  474 #define RXCFG_MXDMA_32  0x00400000      /*      32 bytes */
  475 #define RXCFG_MXDMA_64  0x00500000      /*      64 bytes */
  476 #define RXCFG_MXDMA_128 0x00600000      /*     128 bytes */
  477 #define RXCFG_MXDMA_256 0x00700000      /*     256 bytes */
  478 #endif /* DP83820 */
  479 #define RXCFG_DRTH      0x0000003e
  480 #define RXCFG_DRTH_SHIFT 1
  481 
  482 #ifdef DP83820
  483 #define SIP_PQCR        0x3c    /* priority queueing control register */
  484 #define PQCR_RXPQ_4     0x0000000c      /* 4 Rx queues */
  485 #define PQCR_RXPQ_3     0x00000008      /* 3 Rx queues */
  486 #define PQCR_RXPQ_2     0x00000004      /* 2 Rx queues */
  487 #define PQCR_TXFAIR     0x00000002      /* Tx fairness enable */
  488 #define PQCR_TXPQEN     0x00000001      /* Tx priority queueing enable */
  489 #else
  490 #define SIP_FLOWCTL     0x38    /* flow control register */
  491 #define FLOWCTL_PAUSE   0x00000002      /* PAUSE flag */
  492 #define FLOWCTL_FLOWEN  0x00000001      /* enable flow control */
  493 
  494 #define SIP_NS_CCSR     0x3c    /* CLKRUN control/status register (83815) */
  495 #define CCSR_PMESTS     0x00008000      /* PME status */
  496 #define CCSR_PMEEN      0x00000100      /* PME enable */
  497 #define CCSR_CLKRUN_EN  0x00000001      /* clkrun enable */
  498 #endif /* DP83820 */
  499 
  500 #define SIP_NS_WCSR     0x40    /* WoL control/status register (83815) */
  501 
  502 #define SIP_NS_PCR      0x44    /* pause control/status register (83815) */
  503 
  504 #define SIP_RFCR        0x48    /* receive filter control register */
  505 #define RFCR_RFEN       0x80000000      /* Rx filter enable */
  506 #define RFCR_AAB        0x40000000      /* accept all broadcast */
  507 #define RFCR_AAM        0x20000000      /* accept all multicast */
  508 #define RFCR_AAP        0x10000000      /* accept all physical */
  509 #define RFCR_APM        0x08000000      /* accept perfect match (83815) */
  510 #define RFCR_APAT       0x07800000      /* accept pattern match (83815) */
  511 #define RFCR_AARP       0x00400000      /* accept ARP (83815) */
  512 #define RFCR_MHEN       0x00200000      /* multicast hash enable (83815) */
  513 #define RFCR_UHEN       0x00100000      /* unicast hash enable (83815) */
  514 #define RFCR_ULM        0x00080000      /* U/L bit mask (83815) */
  515 #define RFCR_NS_RFADDR  0x000003ff      /* Rx filter ext reg address (83815) */
  516 #define RFCR_RFADDR     0x000f0000      /* Rx filter address */
  517 #define RFCR_RFADDR_NODE0 0x00000000    /* node address 1, 0 */
  518 #define RFCR_RFADDR_NODE2 0x00010000    /* node address 3, 2 */
  519 #define RFCR_RFADDR_NODE4 0x00020000    /* node address 5, 4 */
  520 #define RFCR_RFADDR_MC0   0x00040000    /* multicast hash word 0 */
  521 #define RFCR_RFADDR_MC1   0x00050000    /* multicast hash word 1 */
  522 #define RFCR_RFADDR_MC2   0x00060000    /* multicast hash word 2 */
  523 #define RFCR_RFADDR_MC3   0x00070000    /* multicast hash word 3 */
  524 #define RFCR_RFADDR_MC4   0x00080000    /* multicast hash word 4 */
  525 #define RFCR_RFADDR_MC5   0x00090000    /* multicast hash word 5 */
  526 #define RFCR_RFADDR_MC6   0x000a0000    /* multicast hash word 6 */
  527 #define RFCR_RFADDR_MC7   0x000b0000    /* multicast hash word 7 */
  528 /* For SiS900B and 635/735 only */
  529 #define RFCR_RFADDR_MC8   0x000c0000    /* multicast hash word 8 */
  530 #define RFCR_RFADDR_MC9   0x000d0000    /* multicast hash word 9 */
  531 #define RFCR_RFADDR_MC10  0x000e0000    /* multicast hash word 10 */
  532 #define RFCR_RFADDR_MC11  0x000f0000    /* multicast hash word 11 */
  533 #define RFCR_RFADDR_MC12  0x00100000    /* multicast hash word 12 */
  534 #define RFCR_RFADDR_MC13  0x00110000    /* multicast hash word 13 */
  535 #define RFCR_RFADDR_MC14  0x00120000    /* multicast hash word 14 */
  536 #define RFCR_RFADDR_MC15  0x00130000    /* multicast hash word 15 */
  537 
  538 #define RFCR_NS_RFADDR_PMATCH0  0x0000  /* perfect match octets 1-0 */
  539 #define RFCR_NS_RFADDR_PMATCH2  0x0002  /* perfect match octets 3-2 */
  540 #define RFCR_NS_RFADDR_PMATCH4  0x0004  /* perfect match octets 5-4 */
  541 #define RFCR_NS_RFADDR_PCOUNT   0x0006  /* pattern count */
  542 #ifdef DP83820
  543 #define RFCR_NS_RFADDR_PCOUNT2  0x0008  /* pattern count 2, 3 */
  544 #define RFCR_NS_RFADDR_SOPAS0   0x000a  /* SecureOn 0, 1 */
  545 #define RFCR_NS_RFADDR_SOPAS2   0x000c  /* SecureOn 2, 3 */
  546 #define RFCR_NS_RFADDR_SOPAS4   0x000e  /* SecureOn 4, 5 */
  547 #define RFCR_NS_RFADDR_FILTMEM  0x0100  /* hash memory */
  548 #define RFCR_NS_RFADDR_PATMEM   0x0200  /* pattern memory */
  549 #else
  550 #define RFCR_NS_RFADDR_FILTMEM  0x0200  /* filter memory (hash/pattern) */
  551 #endif /* DP83820 */
  552 
  553 #define SIP_RFDR        0x4c    /* receive filter data register */
  554 #define RFDR_BMASK      0x00030000      /* byte mask (83815) */
  555 #define RFDR_DATA       0x0000ffff      /* data bits */
  556 
  557 #define SIP_NS_BRAR     0x50    /* boot rom address (83815) */
  558 #define BRAR_AUTOINC    0x80000000      /* autoincrement */
  559 #define BRAR_ADDR       0x0000ffff      /* address */
  560 
  561 #define SIP_NS_BRDR     0x54    /* boot rom data (83815) */
  562 
  563 #define SIP_NS_SRR      0x58    /* silicon revision register (83815) */
  564 #ifdef DP83820
  565 #define SRR_REV_B       0x00000103
  566 #else
  567 #define SRR_REV_A       0x00000101
  568 #define SRR_REV_B_1     0x00000200
  569 #define SRR_REV_B_2     0x00000201
  570 #define SRR_REV_B_3     0x00000203
  571 #define SRR_REV_C_1     0x00000300
  572 #define SRR_REV_C_2     0x00000302
  573 #endif /* DP83820 */
  574 
  575 #define SIP_NS_MIBC     0x5c    /* mib control register (83815) */
  576 #define MIBC_MIBS       0x00000008      /* mib counter strobe */
  577 #define MIBC_ACLR       0x00000004      /* clear all counters */
  578 #define MIBC_FRZ        0x00000002      /* freeze all counters */
  579 #define MIBC_WRN        0x00000001      /* warning test indicator */
  580 
  581 #define SIP_NS_MIB(mibreg)      /* mib data registers (83815) */        \
  582         (0x60 + (mibreg))
  583 #define MIB_RXErroredPkts       0x00
  584 #define MIB_RXFCSErrors         0x04
  585 #define MIB_RXMsdPktErrors      0x08
  586 #define MIB_RXFAErrors          0x0c
  587 #define MIB_RXSymbolErrors      0x10
  588 #define MIB_RXFrameTooLong      0x14
  589 #ifdef DP83820
  590 #define MIB_RXIRLErrors         0x18
  591 #define MIB_RXBadOpcodes        0x1c
  592 #define MIB_RXPauseFrames       0x20
  593 #define MIB_TXPauseFrames       0x24
  594 #define MIB_TXSQEErrors         0x28
  595 #else
  596 #define MIB_RXTXSQEErrors       0x18
  597 #endif /* DP83820 */
  598 
  599 #ifndef DP83820
  600 #define SIP_NS_PHY(miireg)      /* PHY registers (83815) */             \
  601         (0x80 + ((miireg) << 2))
  602 #endif
  603 
  604 #ifdef DP83820
  605 #define SIP_TXDP1       0xa0    /* transmit descriptor pointer (pri 1) */
  606 
  607 #define SIP_TXDP2       0xa4    /* transmit descriptor pointer (pri 2) */
  608 
  609 #define SIP_TXDP3       0xa8    /* transmit descriptor pointer (pri 3) */
  610 
  611 #define SIP_RXDP1       0xb0    /* receive descriptor pointer (pri 1) */
  612 
  613 #define SIP_RXDP2       0xb4    /* receive descriptor pointer (pri 2) */
  614 
  615 #define SIP_RXDP3       0xb8    /* receive descriptor pointer (pri 3) */
  616 
  617 #define SIP_VRCR        0xbc    /* VLAN/IP receive control register */
  618 #define VRCR_RUDPE      0x00000080      /* reject UDP checksum errors */
  619 #define VRCR_RTCPE      0x00000040      /* reject TCP checksum errors */
  620 #define VRCR_RIPE       0x00000020      /* reject IP checksum errors */
  621 #define VRCR_IPEN       0x00000010      /* IP checksum enable */
  622 #define VRCR_DUTF       0x00000008      /* discard untagged frames */
  623 #define VRCR_DVTF       0x00000004      /* discard VLAN tagged frames */
  624 #define VRCR_VTREN      0x00000002      /* VLAN tag removal enable */
  625 #define VRCR_VTDEN      0x00000001      /* VLAN tag detection enable */
  626 
  627 #define SIP_VTCR        0xc0    /* VLAN/IP transmit control register */
  628 #define VTCR_PPCHK      0x00000008      /* per-packet checksum generation */
  629 #define VTCR_GCHK       0x00000004      /* global checksum generation */
  630 #define VTCR_VPPTI      0x00000002      /* VLAN per-packet tag insertion */
  631 #define VTCR_VGTI       0x00000001      /* VLAN global tag insertion */
  632 
  633 #define SIP_VDR         0xc4    /* VLAN data register */
  634 #define VDR_VTCI        0xffff0000      /* VLAN tag control information */
  635 #define VDR_VTYPE       0x0000ffff      /* VLAN type field */
  636 
  637 #define SIP_NS_CCSR     0xcc    /* CLKRUN control/status register (83815) */
  638 #define CCSR_PMESTS     0x00008000      /* PME status */
  639 #define CCSR_PMEEN      0x00000100      /* PME enable */
  640 #define CCSR_CLKRUN_EN  0x00000001      /* clkrun enable */
  641 
  642 #define SIP_TBICR       0xe0    /* TBI control register */
  643 #define TBICR_MR_LOOPBACK   0x00004000  /* TBI PCS loopback enable */
  644 #define TBICR_MR_AN_ENABLE  0x00001000  /* TBI autonegotiation enable */
  645 #define TBICR_MR_RESTART_AN 0x00000200  /* restart TBI autoneogtiation */
  646 
  647 #define SIP_TBISR       0xe4    /* TBI status register */
  648 #define TBISR_MR_LINK_STATUS 0x00000020 /* TBI link status */
  649 #define TBISR_MR_AN_COMPLETE 0x00000004 /* TBI autonegotiation complete */
  650 
  651 #define SIP_TANAR       0xe8    /* TBI autoneg adv. register */
  652 #define TANAR_NP        0x00008000      /* next page exchange required */
  653 #define TANAR_RF2       0x00002000      /* remote fault 2 */
  654 #define TANAR_RF1       0x00001000      /* remote fault 1 */
  655 #define TANAR_PS2       0x00000100      /* pause encoding 2 */
  656 #define TANAR_PS1       0x00000080      /* pause encoding 1 */
  657 #define TANAR_HALF_DUP  0x00000040      /* adv. half duplex */
  658 #define TANAR_FULL_DUP  0x00000020      /* adv. full duplex */
  659 
  660 #define SIP_TANLPAR     0xec    /* TBI autoneg link partner ability register */
  661         /* See TANAR bits */
  662 
  663 #define SIP_TANER       0xf0    /* TBI autoneg expansion register */
  664 #define TANER_NPA       0x00000004      /* we support next page function */
  665 #define TANER_PR        0x00000002      /* page received from link partner */
  666 
  667 #define SIP_TESR        0xf4    /* TBI extended status register */
  668 #define TESR_1000FDX    0x00008000      /* we support 1000base FDX */
  669 #define TESR_1000HDX    0x00004000      /* we support 1000base HDX */
  670 #else
  671 #define SIP_PMCTL       0xb0    /* power management control register */
  672 #define PMCTL_GATECLK   0x80000000      /* gate dual clock enable */
  673 #define PMCTL_WAKEALL   0x40000000      /* wake on all Rx OK */
  674 #define PMCTL_FRM3ACS   0x04000000      /* 3rd wake-up frame access */
  675 #define PMCTL_FRM2ACS   0x02000000      /* 2nd wake-up frame access */
  676 #define PMCTL_FRM1ACS   0x01000000      /* 1st wake-up frame access */
  677 #define PMCTL_FRM3EN    0x00400000      /* 3rd wake-up frame match enable */
  678 #define PMCTL_FRM2EN    0x00200000      /* 2nd wake-up frame match enable */
  679 #define PMCTL_FRM1EN    0x00100000      /* 1st wake-up frame match enable */
  680 #define PMCTL_ALGORITHM 0x00000800      /* Magic Packet match algorithm */
  681 #define PMCTL_MAGICPKT  0x00000400      /* Magic Packet match enable */
  682 #define PMCTL_LINKON    0x00000002      /* link on monitor enable */
  683 #define PMCTL_LINKLOSS  0x00000001      /* link loss monitor enable */
  684 
  685 #define SIP_PMEVT       0xb4    /* power management wake-up evnt reg */
  686 #define PMEVT_ALLFRMMAT 0x40000000      /* receive packet ok */
  687 #define PMEVT_FRM3MAT   0x04000000      /* match 3rd wake-up frame */
  688 #define PMEVT_FRM2MAT   0x02000000      /* match 2nd wake-up frame */
  689 #define PMEVT_FRM1MAT   0x01000000      /* match 1st wake-up frame */
  690 #define PMEVT_MAGICPKT  0x00000400      /* Magic Packet */
  691 #define PMEVT_ONEVT     0x00000002      /* link on event */
  692 #define PMEVT_LOSSEVT   0x00000001      /* link loss event */
  693 
  694 #define SIP_WAKECRC     0xbc    /* wake-up frame CRC register */
  695 
  696 #define SIP_WAKEMASK0   0xc0    /* wake-up frame mask registers */
  697 #define SIP_WAKEMASK1   0xc4
  698 #define SIP_WAKEMASK2   0xc8
  699 #define SIP_WAKEMASK3   0xcc
  700 #define SIP_WAKEMASK4   0xe0
  701 #define SIP_WAKEMASK5   0xe4
  702 #define SIP_WAKEMASK6   0xe8
  703 #define SIP_WAKEMASK7   0xec
  704 #endif /* DP83820 */
  705 
  706 /*
  707  * Revision codes for the SiS 630 chipset built-in Ethernet.
  708  */
  709 #define SIS_REV_900B    0x03
  710 #define SIS_REV_630E    0x81
  711 #define SIS_REV_630S    0x82
  712 #define SIS_REV_630EA1  0x83
  713 #define SIS_REV_630ET   0x84
  714 #define SIS_REV_635     0x90    /* same for 735 (745?) */
  715 #define SIS_REV_960     0x91
  716 
  717 /*
  718  * MII operations for recent SiS chipsets
  719  */
  720 #define SIS_MII_STARTDELIM      0x01
  721 #define SIS_MII_READOP          0x02
  722 #define SIS_MII_WRITEOP         0x01
  723 #define SIS_MII_TURNAROUND      0x02
  724 
  725 /*
  726  * Serial EEPROM opcodes, including the start bit.
  727  */
  728 #define SIP_EEPROM_OPC_ERASE    0x04
  729 #define SIP_EEPROM_OPC_WRITE    0x05
  730 #define SIP_EEPROM_OPC_READ     0x06
  731 
  732 /*
  733  * Serial EEPROM address map (byte address) for the SiS900.
  734  */
  735 #define SIP_EEPROM_SIGNATURE    0x00    /* SiS 900 signature */
  736 #define SIP_EEPROM_MASK         0x02    /* `enable' mask */
  737 #define SIP_EEPROM_VENDOR_ID    0x04    /* PCI vendor ID */
  738 #define SIP_EEPROM_DEVICE_ID    0x06    /* PCI device ID */
  739 #define SIP_EEPROM_SUBVENDOR_ID 0x08    /* PCI subvendor ID */
  740 #define SIP_EEPROM_SUBSYSTEM_ID 0x0a    /* PCI subsystem ID */
  741 #define SIP_EEPROM_PMC          0x0c    /* PCI power management capabilities */
  742 #define SIP_EEPROM_reserved     0x0e    /* reserved */
  743 #define SIP_EEPROM_ETHERNET_ID0 0x10    /* Ethernet address 0, 1 */
  744 #define SIP_EEPROM_ETHERNET_ID1 0x12    /* Ethernet address 2, 3 */
  745 #define SIP_EEPROM_ETHERNET_ID2 0x14    /* Ethernet address 4, 5 */
  746 #define SIP_EEPROM_CHECKSUM     0x16    /* checksum */
  747 
  748 /*
  749  * Serial EEPROM data (byte addresses) for the DP83815.
  750  */
  751 #define SIP_DP83815_EEPROM_CHECKSUM     0x16    /* checksum */
  752 #define SIP_DP83815_EEPROM_LENGTH       0x18    /* length of EEPROM data */
  753 
  754 /*
  755  * Serial EEPROM data (byte addresses) for the DP83820.
  756  */
  757 #define SIP_DP83820_EEPROM_SUBSYSTEM_ID 0x00    /* PCI subsystem ID */
  758 #define SIP_DP83820_EEPROM_SUBVENDOR_ID 0x02    /* PCI subvendor ID */
  759 #define SIP_DP83820_EEPROM_CFGINT       0x04    /* PCI INT [31:16] */
  760 #define SIP_DP83820_EEPROM_CONFIG0      0x06    /* configuration word 0 */
  761 #define SIP_DP83820_EEPROM_CONFIG1      0x08    /* configuration word 1 */
  762 #define SIP_DP83820_EEPROM_CONFIG2      0x0a    /* configuration word 2 */
  763 #define SIP_DP83820_EEPROM_CONFIG3      0x0c    /* configuration word 3 */
  764 #define SIP_DP83820_EEPROM_SOPAS0       0x0e    /* SecureOn [47:32] */
  765 #define SIP_DP83820_EEPROM_SOPAS1       0x10    /* SecureOn [31:16] */
  766 #define SIP_DP83820_EEPROM_SOPAS2       0x12    /* SecureOn [15:0] */
  767 #define SIP_DP83820_EEPROM_PMATCH0      0x14    /* MAC [47:32] */
  768 #define SIP_DP83820_EEPROM_PMATCH1      0x16    /* MAC [31:16] */
  769 #define SIP_DP83820_EEPROM_PMATCH2      0x18    /* MAC [15:0] */
  770 #define SIP_DP83820_EEPROM_CHECKSUM     0x1a    /* checksum */
  771 #define SIP_DP83820_EEPROM_LENGTH       0x1c    /* length of EEPROM data */
  772 
  773 #define DP83820_CONFIG2_CFG_EXT_125     (1U << 0)
  774 #define DP83820_CONFIG2_CFG_M64ADDR     (1U << 1)
  775 #define DP83820_CONFIG2_CFG_DATA64_EN   (1U << 2)
  776 #define DP83820_CONFIG2_CFG_T64ADDR     (1U << 3)
  777 #define DP83820_CONFIG2_CFG_MWI_DIS     (1U << 4)
  778 #define DP83820_CONFIG2_CFG_MRM_DIS     (1U << 5)
  779 #define DP83820_CONFIG2_CFG_MODE_1000   (1U << 7)
  780 #define DP83820_CONFIG2_CFG_TBI_EN      (1U << 9)
  781 
  782 #endif /* _DEV_PCI_IF_SIPREG_H_ */

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