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sys/dev/pci/if_ste.c
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1 /* $NetBSD: if_ste.c,v 1.17.4.1 2004/07/23 22:57:25 he Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. ST-201 10/100 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.17.4.1 2004/07/23 22:57:25 he Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stereg.h> 84 85 /* 86 * Transmit descriptor list size. 87 */ 88 #define STE_NTXDESC 256 89 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 90 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 91 92 /* 93 * Receive descriptor list size. 94 */ 95 #define STE_NRXDESC 128 96 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 97 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 98 99 /* 100 * Control structures are DMA'd to the ST-201 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct ste_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct ste_tfd scd_txdescs[STE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 114 }; 115 116 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 117 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 118 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct ste_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct ste_softc { 132 struct device sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 void *sc_sdhook; /* shutdown hook */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 struct callout sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 152 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct ste_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 int sc_txpending; /* number of Tx requests pending */ 162 int sc_txdirty; /* first dirty Tx descriptor */ 163 int sc_txlast; /* last used Tx descriptor */ 164 165 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 166 167 int sc_txthresh; /* Tx threshold */ 168 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 169 uint16_t sc_IntEnable; /* prototype IntEnable register */ 170 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 171 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 172 }; 173 174 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 175 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 176 177 #define STE_CDTXSYNC(sc, x, ops) \ 178 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 179 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 180 181 #define STE_CDRXSYNC(sc, x, ops) \ 182 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 183 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 184 185 #define STE_INIT_RXDESC(sc, x) \ 186 do { \ 187 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 188 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 189 struct mbuf *__m = __ds->ds_mbuf; \ 190 \ 191 /* \ 192 * Note: We scoot the packet forward 2 bytes in the buffer \ 193 * so that the payload after the Ethernet header is aligned \ 194 * to a 4-byte boundary. \ 195 */ \ 196 __m->m_data = __m->m_ext.ext_buf + 2; \ 197 __rfd->rfd_frag.frag_addr = \ 198 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 199 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 200 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 201 __rfd->rfd_status = 0; \ 202 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 203 } while (/*CONSTCOND*/0) 204 205 #define STE_TIMEOUT 1000 206 207 void ste_start(struct ifnet *); 208 void ste_watchdog(struct ifnet *); 209 int ste_ioctl(struct ifnet *, u_long, caddr_t); 210 int ste_init(struct ifnet *); 211 void ste_stop(struct ifnet *, int); 212 213 void ste_shutdown(void *); 214 215 void ste_reset(struct ste_softc *, u_int32_t); 216 void ste_setthresh(struct ste_softc *); 217 void ste_txrestart(struct ste_softc *, u_int8_t); 218 void ste_rxdrain(struct ste_softc *); 219 int ste_add_rxbuf(struct ste_softc *, int); 220 void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 221 void ste_tick(void *); 222 223 void ste_stats_update(struct ste_softc *); 224 225 void ste_set_filter(struct ste_softc *); 226 227 int ste_intr(void *); 228 void ste_txintr(struct ste_softc *); 229 void ste_rxintr(struct ste_softc *); 230 231 int ste_mii_readreg(struct device *, int, int); 232 void ste_mii_writereg(struct device *, int, int, int); 233 void ste_mii_statchg(struct device *); 234 235 int ste_mediachange(struct ifnet *); 236 void ste_mediastatus(struct ifnet *, struct ifmediareq *); 237 238 int ste_match(struct device *, struct cfdata *, void *); 239 void ste_attach(struct device *, struct device *, void *); 240 241 int ste_copy_small = 0; 242 243 CFATTACH_DECL(ste, sizeof(struct ste_softc), 244 ste_match, ste_attach, NULL, NULL); 245 246 uint32_t ste_mii_bitbang_read(struct device *); 247 void ste_mii_bitbang_write(struct device *, uint32_t); 248 249 const struct mii_bitbang_ops ste_mii_bitbang_ops = { 250 ste_mii_bitbang_read, 251 ste_mii_bitbang_write, 252 { 253 PC_MgmtData, /* MII_BIT_MDO */ 254 PC_MgmtData, /* MII_BIT_MDI */ 255 PC_MgmtClk, /* MII_BIT_MDC */ 256 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 257 0, /* MII_BIT_DIR_PHY_HOST */ 258 } 259 }; 260 261 /* 262 * Devices supported by this driver. 263 */ 264 const struct ste_product { 265 pci_vendor_id_t ste_vendor; 266 pci_product_id_t ste_product; 267 const char *ste_name; 268 } ste_products[] = { 269 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 270 "Sundance ST-201 10/100 Ethernet" }, 271 272 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 273 "D-Link DL-1002 10/100 Ethernet" }, 274 275 { 0, 0, 276 NULL }, 277 }; 278 279 static const struct ste_product * 280 ste_lookup(const struct pci_attach_args *pa) 281 { 282 const struct ste_product *sp; 283 284 for (sp = ste_products; sp->ste_name != NULL; sp++) { 285 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 286 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 287 return (sp); 288 } 289 return (NULL); 290 } 291 292 int 293 ste_match(struct device *parent, struct cfdata *cf, void *aux) 294 { 295 struct pci_attach_args *pa = aux; 296 297 if (ste_lookup(pa) != NULL) 298 return (1); 299 300 return (0); 301 } 302 303 void 304 ste_attach(struct device *parent, struct device *self, void *aux) 305 { 306 struct ste_softc *sc = (struct ste_softc *) self; 307 struct pci_attach_args *pa = aux; 308 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 309 pci_chipset_tag_t pc = pa->pa_pc; 310 pci_intr_handle_t ih; 311 const char *intrstr = NULL; 312 bus_space_tag_t iot, memt; 313 bus_space_handle_t ioh, memh; 314 bus_dma_segment_t seg; 315 int ioh_valid, memh_valid; 316 int i, rseg, error; 317 const struct ste_product *sp; 318 pcireg_t pmode; 319 uint8_t enaddr[ETHER_ADDR_LEN]; 320 uint16_t myea[ETHER_ADDR_LEN / 2]; 321 int pmreg; 322 323 callout_init(&sc->sc_tick_ch); 324 325 sp = ste_lookup(pa); 326 if (sp == NULL) { 327 printf("\n"); 328 panic("ste_attach: impossible"); 329 } 330 331 printf(": %s\n", sp->ste_name); 332 333 /* 334 * Map the device. 335 */ 336 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 337 PCI_MAPREG_TYPE_IO, 0, 338 &iot, &ioh, NULL, NULL) == 0); 339 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 340 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 341 &memt, &memh, NULL, NULL) == 0); 342 343 if (memh_valid) { 344 sc->sc_st = memt; 345 sc->sc_sh = memh; 346 } else if (ioh_valid) { 347 sc->sc_st = iot; 348 sc->sc_sh = ioh; 349 } else { 350 printf("%s: unable to map device registers\n", 351 sc->sc_dev.dv_xname); 352 return; 353 } 354 355 sc->sc_dmat = pa->pa_dmat; 356 357 /* Enable bus mastering. */ 358 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 359 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 360 PCI_COMMAND_MASTER_ENABLE); 361 362 /* Get it out of power save mode if needed. */ 363 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 364 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 365 PCI_PMCSR_STATE_MASK; 366 if (pmode == PCI_PMCSR_STATE_D3) { 367 /* 368 * The card has lost all configuration data in 369 * this state, so punt. 370 */ 371 printf("%s: unable to wake up from power state D3\n", 372 sc->sc_dev.dv_xname); 373 return; 374 } 375 if (pmode != PCI_PMCSR_STATE_D0) { 376 printf("%s: waking up from power state D%d\n", 377 sc->sc_dev.dv_xname, pmode); 378 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 379 PCI_PMCSR_STATE_D0); 380 } 381 } 382 383 /* 384 * Map and establish our interrupt. 385 */ 386 if (pci_intr_map(pa, &ih)) { 387 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 388 return; 389 } 390 intrstr = pci_intr_string(pc, ih); 391 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ste_intr, sc); 392 if (sc->sc_ih == NULL) { 393 printf("%s: unable to establish interrupt", 394 sc->sc_dev.dv_xname); 395 if (intrstr != NULL) 396 printf(" at %s", intrstr); 397 printf("\n"); 398 return; 399 } 400 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 401 402 /* 403 * Allocate the control data structures, and create and load the 404 * DMA map for it. 405 */ 406 if ((error = bus_dmamem_alloc(sc->sc_dmat, 407 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 408 0)) != 0) { 409 printf("%s: unable to allocate control data, error = %d\n", 410 sc->sc_dev.dv_xname, error); 411 goto fail_0; 412 } 413 414 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 415 sizeof(struct ste_control_data), (caddr_t *)&sc->sc_control_data, 416 BUS_DMA_COHERENT)) != 0) { 417 printf("%s: unable to map control data, error = %d\n", 418 sc->sc_dev.dv_xname, error); 419 goto fail_1; 420 } 421 422 if ((error = bus_dmamap_create(sc->sc_dmat, 423 sizeof(struct ste_control_data), 1, 424 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 425 printf("%s: unable to create control data DMA map, " 426 "error = %d\n", sc->sc_dev.dv_xname, error); 427 goto fail_2; 428 } 429 430 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 431 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 432 0)) != 0) { 433 printf("%s: unable to load control data DMA map, error = %d\n", 434 sc->sc_dev.dv_xname, error); 435 goto fail_3; 436 } 437 438 /* 439 * Create the transmit buffer DMA maps. 440 */ 441 for (i = 0; i < STE_NTXDESC; i++) { 442 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 443 STE_NTXFRAGS, MCLBYTES, 0, 0, 444 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 445 printf("%s: unable to create tx DMA map %d, " 446 "error = %d\n", sc->sc_dev.dv_xname, i, error); 447 goto fail_4; 448 } 449 } 450 451 /* 452 * Create the receive buffer DMA maps. 453 */ 454 for (i = 0; i < STE_NRXDESC; i++) { 455 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 456 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 457 printf("%s: unable to create rx DMA map %d, " 458 "error = %d\n", sc->sc_dev.dv_xname, i, error); 459 goto fail_5; 460 } 461 sc->sc_rxsoft[i].ds_mbuf = NULL; 462 } 463 464 /* 465 * Reset the chip to a known state. 466 */ 467 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 468 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 469 470 /* 471 * Read the Ethernet address from the EEPROM. 472 */ 473 for (i = 0; i < 3; i++) { 474 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 475 myea[i] = le16toh(myea[i]); 476 } 477 memcpy(enaddr, myea, sizeof(enaddr)); 478 479 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 480 ether_sprintf(enaddr)); 481 482 /* 483 * Initialize our media structures and probe the MII. 484 */ 485 sc->sc_mii.mii_ifp = ifp; 486 sc->sc_mii.mii_readreg = ste_mii_readreg; 487 sc->sc_mii.mii_writereg = ste_mii_writereg; 488 sc->sc_mii.mii_statchg = ste_mii_statchg; 489 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ste_mediachange, 490 ste_mediastatus); 491 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 492 MII_OFFSET_ANY, 0); 493 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 495 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 496 } else 497 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 498 499 ifp = &sc->sc_ethercom.ec_if; 500 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 501 ifp->if_softc = sc; 502 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 503 ifp->if_ioctl = ste_ioctl; 504 ifp->if_start = ste_start; 505 ifp->if_watchdog = ste_watchdog; 506 ifp->if_init = ste_init; 507 ifp->if_stop = ste_stop; 508 IFQ_SET_READY(&ifp->if_snd); 509 510 /* 511 * Default the transmit threshold to 128 bytes. 512 */ 513 sc->sc_txthresh = 128; 514 515 /* 516 * Disable MWI if the PCI layer tells us to. 517 */ 518 sc->sc_DMACtrl = 0; 519 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 520 sc->sc_DMACtrl |= DC_MWIDisable; 521 522 /* 523 * We can support 802.1Q VLAN-sized frames. 524 */ 525 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 526 527 /* 528 * Attach the interface. 529 */ 530 if_attach(ifp); 531 ether_ifattach(ifp, enaddr); 532 533 /* 534 * Make sure the interface is shutdown during reboot. 535 */ 536 sc->sc_sdhook = shutdownhook_establish(ste_shutdown, sc); 537 if (sc->sc_sdhook == NULL) 538 printf("%s: WARNING: unable to establish shutdown hook\n", 539 sc->sc_dev.dv_xname); 540 return; 541 542 /* 543 * Free any resources we've allocated during the failed attach 544 * attempt. Do this in reverse order and fall through. 545 */ 546 fail_5: 547 for (i = 0; i < STE_NRXDESC; i++) { 548 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 549 bus_dmamap_destroy(sc->sc_dmat, 550 sc->sc_rxsoft[i].ds_dmamap); 551 } 552 fail_4: 553 for (i = 0; i < STE_NTXDESC; i++) { 554 if (sc->sc_txsoft[i].ds_dmamap != NULL) 555 bus_dmamap_destroy(sc->sc_dmat, 556 sc->sc_txsoft[i].ds_dmamap); 557 } 558 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 559 fail_3: 560 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 561 fail_2: 562 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 563 sizeof(struct ste_control_data)); 564 fail_1: 565 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 566 fail_0: 567 return; 568 } 569 570 /* 571 * ste_shutdown: 572 * 573 * Make sure the interface is stopped at reboot time. 574 */ 575 void 576 ste_shutdown(void *arg) 577 { 578 struct ste_softc *sc = arg; 579 580 ste_stop(&sc->sc_ethercom.ec_if, 1); 581 } 582 583 static void 584 ste_dmahalt_wait(struct ste_softc *sc) 585 { 586 int i; 587 588 for (i = 0; i < STE_TIMEOUT; i++) { 589 delay(2); 590 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 591 DC_DMAHaltBusy) == 0) 592 break; 593 } 594 595 if (i == STE_TIMEOUT) 596 printf("%s: DMA halt timed out\n", sc->sc_dev.dv_xname); 597 } 598 599 /* 600 * ste_start: [ifnet interface function] 601 * 602 * Start packet transmission on the interface. 603 */ 604 void 605 ste_start(struct ifnet *ifp) 606 { 607 struct ste_softc *sc = ifp->if_softc; 608 struct mbuf *m0, *m; 609 struct ste_descsoft *ds; 610 struct ste_tfd *tfd; 611 bus_dmamap_t dmamap; 612 int error, olasttx, nexttx, opending, seg, totlen; 613 614 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 615 return; 616 617 /* 618 * Remember the previous number of pending transmissions 619 * and the current last descriptor in the list. 620 */ 621 opending = sc->sc_txpending; 622 olasttx = sc->sc_txlast; 623 624 /* 625 * Loop through the send queue, setting up transmit descriptors 626 * until we drain the queue, or use up all available transmit 627 * descriptors. 628 */ 629 while (sc->sc_txpending < STE_NTXDESC) { 630 /* 631 * Grab a packet off the queue. 632 */ 633 IFQ_POLL(&ifp->if_snd, m0); 634 if (m0 == NULL) 635 break; 636 m = NULL; 637 638 /* 639 * Get the last and next available transmit descriptor. 640 */ 641 nexttx = STE_NEXTTX(sc->sc_txlast); 642 tfd = &sc->sc_txdescs[nexttx]; 643 ds = &sc->sc_txsoft[nexttx]; 644 645 dmamap = ds->ds_dmamap; 646 647 /* 648 * Load the DMA map. If this fails, the packet either 649 * didn't fit in the alloted number of segments, or we 650 * were short on resources. In this case, we'll copy 651 * and try again. 652 */ 653 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 654 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 655 MGETHDR(m, M_DONTWAIT, MT_DATA); 656 if (m == NULL) { 657 printf("%s: unable to allocate Tx mbuf\n", 658 sc->sc_dev.dv_xname); 659 break; 660 } 661 if (m0->m_pkthdr.len > MHLEN) { 662 MCLGET(m, M_DONTWAIT); 663 if ((m->m_flags & M_EXT) == 0) { 664 printf("%s: unable to allocate Tx " 665 "cluster\n", sc->sc_dev.dv_xname); 666 m_freem(m); 667 break; 668 } 669 } 670 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 671 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 672 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 673 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 674 if (error) { 675 printf("%s: unable to load Tx buffer, " 676 "error = %d\n", sc->sc_dev.dv_xname, error); 677 break; 678 } 679 } 680 681 IFQ_DEQUEUE(&ifp->if_snd, m0); 682 if (m != NULL) { 683 m_freem(m0); 684 m0 = m; 685 } 686 687 /* 688 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 689 */ 690 691 /* Sync the DMA map. */ 692 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 693 BUS_DMASYNC_PREWRITE); 694 695 /* Initialize the fragment list. */ 696 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 697 tfd->tfd_frags[seg].frag_addr = 698 htole32(dmamap->dm_segs[seg].ds_addr); 699 tfd->tfd_frags[seg].frag_len = 700 htole32(dmamap->dm_segs[seg].ds_len); 701 totlen += dmamap->dm_segs[seg].ds_len; 702 } 703 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 704 705 /* Initialize the descriptor. */ 706 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 707 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 708 709 /* Sync the descriptor. */ 710 STE_CDTXSYNC(sc, nexttx, 711 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 712 713 /* 714 * Store a pointer to the packet so we can free it later, 715 * and remember what txdirty will be once the packet is 716 * done. 717 */ 718 ds->ds_mbuf = m0; 719 720 /* Advance the tx pointer. */ 721 sc->sc_txpending++; 722 sc->sc_txlast = nexttx; 723 724 #if NBPFILTER > 0 725 /* 726 * Pass the packet to any BPF listeners. 727 */ 728 if (ifp->if_bpf) 729 bpf_mtap(ifp->if_bpf, m0); 730 #endif /* NBPFILTER > 0 */ 731 } 732 733 if (sc->sc_txpending == STE_NTXDESC) { 734 /* No more slots left; notify upper layer. */ 735 ifp->if_flags |= IFF_OACTIVE; 736 } 737 738 if (sc->sc_txpending != opending) { 739 /* 740 * We enqueued packets. If the transmitter was idle, 741 * reset the txdirty pointer. 742 */ 743 if (opending == 0) 744 sc->sc_txdirty = STE_NEXTTX(olasttx); 745 746 /* 747 * Cause a descriptor interrupt to happen on the 748 * last packet we enqueued, and also cause the 749 * DMA engine to wait after is has finished processing 750 * it. 751 */ 752 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 753 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 754 htole32(TFD_TxDMAIndicate); 755 STE_CDTXSYNC(sc, sc->sc_txlast, 756 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 757 758 /* 759 * Link up the new chain of descriptors to the 760 * last. 761 */ 762 sc->sc_txdescs[olasttx].tfd_next = 763 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 764 STE_CDTXSYNC(sc, olasttx, 765 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 766 767 /* 768 * Kick the transmit DMA logic. Note that since we're 769 * using auto-polling, reading the Tx desc pointer will 770 * give it the nudge it needs to get going. 771 */ 772 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 773 STE_TxDMAListPtr) == 0) { 774 bus_space_write_4(sc->sc_st, sc->sc_sh, 775 STE_DMACtrl, DC_TxDMAHalt); 776 ste_dmahalt_wait(sc); 777 bus_space_write_4(sc->sc_st, sc->sc_sh, 778 STE_TxDMAListPtr, 779 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 780 bus_space_write_4(sc->sc_st, sc->sc_sh, 781 STE_DMACtrl, DC_TxDMAResume); 782 } 783 784 /* Set a watchdog timer in case the chip flakes out. */ 785 ifp->if_timer = 5; 786 } 787 } 788 789 /* 790 * ste_watchdog: [ifnet interface function] 791 * 792 * Watchdog timer handler. 793 */ 794 void 795 ste_watchdog(struct ifnet *ifp) 796 { 797 struct ste_softc *sc = ifp->if_softc; 798 799 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 800 ifp->if_oerrors++; 801 802 (void) ste_init(ifp); 803 804 /* Try to get more packets going. */ 805 ste_start(ifp); 806 } 807 808 /* 809 * ste_ioctl: [ifnet interface function] 810 * 811 * Handle control requests from the operator. 812 */ 813 int 814 ste_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 815 { 816 struct ste_softc *sc = ifp->if_softc; 817 struct ifreq *ifr = (struct ifreq *)data; 818 int s, error; 819 820 s = splnet(); 821 822 switch (cmd) { 823 case SIOCSIFMEDIA: 824 case SIOCGIFMEDIA: 825 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 826 break; 827 828 default: 829 error = ether_ioctl(ifp, cmd, data); 830 if (error == ENETRESET) { 831 /* 832 * Multicast list has changed; set the hardware filter 833 * accordingly. 834 */ 835 ste_set_filter(sc); 836 error = 0; 837 } 838 break; 839 } 840 841 /* Try to get more packets going. */ 842 ste_start(ifp); 843 844 splx(s); 845 return (error); 846 } 847 848 /* 849 * ste_intr: 850 * 851 * Interrupt service routine. 852 */ 853 int 854 ste_intr(void *arg) 855 { 856 struct ste_softc *sc = arg; 857 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 858 uint16_t isr; 859 uint8_t txstat; 860 int wantinit; 861 862 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 863 IS_InterruptStatus) == 0) 864 return (0); 865 866 for (wantinit = 0; wantinit == 0;) { 867 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 868 if ((isr & sc->sc_IntEnable) == 0) 869 break; 870 871 /* Receive interrupts. */ 872 if (isr & IE_RxDMAComplete) 873 ste_rxintr(sc); 874 875 /* Transmit interrupts. */ 876 if (isr & (IE_TxDMAComplete|IE_TxComplete)) 877 ste_txintr(sc); 878 879 /* Statistics overflow. */ 880 if (isr & IE_UpdateStats) 881 ste_stats_update(sc); 882 883 /* Transmission errors. */ 884 if (isr & IE_TxComplete) { 885 for (;;) { 886 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 887 STE_TxStatus); 888 if ((txstat & TS_TxComplete) == 0) 889 break; 890 if (txstat & TS_TxUnderrun) { 891 sc->sc_txthresh += 32; 892 if (sc->sc_txthresh > 0x1ffc) 893 sc->sc_txthresh = 0x1ffc; 894 printf("%s: transmit underrun, new " 895 "threshold: %d bytes\n", 896 sc->sc_dev.dv_xname, 897 sc->sc_txthresh); 898 ste_reset(sc, AC_TxReset | AC_DMA | 899 AC_FIFO | AC_Network); 900 ste_setthresh(sc); 901 bus_space_write_1(sc->sc_st, sc->sc_sh, 902 STE_TxDMAPollPeriod, 127); 903 ste_txrestart(sc, 904 bus_space_read_1(sc->sc_st, 905 sc->sc_sh, STE_TxFrameId)); 906 } 907 if (txstat & TS_TxReleaseError) { 908 printf("%s: Tx FIFO release error\n", 909 sc->sc_dev.dv_xname); 910 wantinit = 1; 911 } 912 if (txstat & TS_MaxCollisions) { 913 printf("%s: excessive collisions\n", 914 sc->sc_dev.dv_xname); 915 wantinit = 1; 916 } 917 if (txstat & TS_TxStatusOverflow) { 918 printf("%s: status overflow\n", 919 sc->sc_dev.dv_xname); 920 wantinit = 1; 921 } 922 bus_space_write_2(sc->sc_st, sc->sc_sh, 923 STE_TxStatus, 0); 924 } 925 } 926 927 /* Host interface errors. */ 928 if (isr & IE_HostError) { 929 printf("%s: Host interface error\n", 930 sc->sc_dev.dv_xname); 931 wantinit = 1; 932 } 933 } 934 935 if (wantinit) 936 ste_init(ifp); 937 938 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 939 sc->sc_IntEnable); 940 941 /* Try to get more packets going. */ 942 ste_start(ifp); 943 944 return (1); 945 } 946 947 /* 948 * ste_txintr: 949 * 950 * Helper; handle transmit interrupts. 951 */ 952 void 953 ste_txintr(struct ste_softc *sc) 954 { 955 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 956 struct ste_descsoft *ds; 957 uint32_t control; 958 int i; 959 960 ifp->if_flags &= ~IFF_OACTIVE; 961 962 /* 963 * Go through our Tx list and free mbufs for those 964 * frames which have been transmitted. 965 */ 966 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 967 i = STE_NEXTTX(i), sc->sc_txpending--) { 968 ds = &sc->sc_txsoft[i]; 969 970 STE_CDTXSYNC(sc, i, 971 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 972 973 control = le32toh(sc->sc_txdescs[i].tfd_control); 974 if ((control & TFD_TxDMAComplete) == 0) 975 break; 976 977 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 978 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 979 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 980 m_freem(ds->ds_mbuf); 981 ds->ds_mbuf = NULL; 982 } 983 984 /* Update the dirty transmit buffer pointer. */ 985 sc->sc_txdirty = i; 986 987 /* 988 * If there are no more pending transmissions, cancel the watchdog 989 * timer. 990 */ 991 if (sc->sc_txpending == 0) 992 ifp->if_timer = 0; 993 } 994 995 /* 996 * ste_rxintr: 997 * 998 * Helper; handle receive interrupts. 999 */ 1000 void 1001 ste_rxintr(struct ste_softc *sc) 1002 { 1003 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1004 struct ste_descsoft *ds; 1005 struct mbuf *m; 1006 uint32_t status; 1007 int i, len; 1008 1009 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 1010 ds = &sc->sc_rxsoft[i]; 1011 1012 STE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1013 1014 status = le32toh(sc->sc_rxdescs[i].rfd_status); 1015 1016 if ((status & RFD_RxDMAComplete) == 0) 1017 break; 1018 1019 /* 1020 * If the packet had an error, simply recycle the 1021 * buffer. Note, we count the error later in the 1022 * periodic stats update. 1023 */ 1024 if (status & RFD_RxFrameError) { 1025 STE_INIT_RXDESC(sc, i); 1026 continue; 1027 } 1028 1029 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1030 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1031 1032 /* 1033 * No errors; receive the packet. Note, we have 1034 * configured the chip to not include the CRC at 1035 * the end of the packet. 1036 */ 1037 len = RFD_RxDMAFrameLen(status); 1038 1039 /* 1040 * If the packet is small enough to fit in a 1041 * single header mbuf, allocate one and copy 1042 * the data into it. This greatly reduces 1043 * memory consumption when we receive lots 1044 * of small packets. 1045 * 1046 * Otherwise, we add a new buffer to the receive 1047 * chain. If this fails, we drop the packet and 1048 * recycle the old buffer. 1049 */ 1050 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1051 MGETHDR(m, M_DONTWAIT, MT_DATA); 1052 if (m == NULL) 1053 goto dropit; 1054 m->m_data += 2; 1055 memcpy(mtod(m, caddr_t), 1056 mtod(ds->ds_mbuf, caddr_t), len); 1057 STE_INIT_RXDESC(sc, i); 1058 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1059 ds->ds_dmamap->dm_mapsize, 1060 BUS_DMASYNC_PREREAD); 1061 } else { 1062 m = ds->ds_mbuf; 1063 if (ste_add_rxbuf(sc, i) != 0) { 1064 dropit: 1065 ifp->if_ierrors++; 1066 STE_INIT_RXDESC(sc, i); 1067 bus_dmamap_sync(sc->sc_dmat, 1068 ds->ds_dmamap, 0, 1069 ds->ds_dmamap->dm_mapsize, 1070 BUS_DMASYNC_PREREAD); 1071 continue; 1072 } 1073 } 1074 1075 m->m_pkthdr.rcvif = ifp; 1076 m->m_pkthdr.len = m->m_len = len; 1077 1078 #if NBPFILTER > 0 1079 /* 1080 * Pass this up to any BPF listeners, but only 1081 * pass if up the stack if it's for us. 1082 */ 1083 if (ifp->if_bpf) 1084 bpf_mtap(ifp->if_bpf, m); 1085 #endif /* NBPFILTER > 0 */ 1086 1087 /* Pass it on. */ 1088 (*ifp->if_input)(ifp, m); 1089 } 1090 1091 /* Update the receive pointer. */ 1092 sc->sc_rxptr = i; 1093 } 1094 1095 /* 1096 * ste_tick: 1097 * 1098 * One second timer, used to tick the MII. 1099 */ 1100 void 1101 ste_tick(void *arg) 1102 { 1103 struct ste_softc *sc = arg; 1104 int s; 1105 1106 s = splnet(); 1107 mii_tick(&sc->sc_mii); 1108 ste_stats_update(sc); 1109 splx(s); 1110 1111 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1112 } 1113 1114 /* 1115 * ste_stats_update: 1116 * 1117 * Read the ST-201 statistics counters. 1118 */ 1119 void 1120 ste_stats_update(struct ste_softc *sc) 1121 { 1122 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1123 bus_space_tag_t st = sc->sc_st; 1124 bus_space_handle_t sh = sc->sc_sh; 1125 1126 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1127 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1128 1129 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1130 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1131 1132 ifp->if_opackets += 1133 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK); 1134 ifp->if_ipackets += 1135 (u_int) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1136 1137 ifp->if_collisions += 1138 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1139 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1140 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames); 1141 1142 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1143 1144 ifp->if_ierrors += 1145 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors); 1146 1147 ifp->if_oerrors += 1148 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1149 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1150 bus_space_read_1(st, sh, STE_CarrierSenseErrors); 1151 1152 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1153 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1154 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1155 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1156 } 1157 1158 /* 1159 * ste_reset: 1160 * 1161 * Perform a soft reset on the ST-201. 1162 */ 1163 void 1164 ste_reset(struct ste_softc *sc, u_int32_t rstbits) 1165 { 1166 uint32_t ac; 1167 int i; 1168 1169 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1170 1171 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1172 1173 delay(50000); 1174 1175 for (i = 0; i < STE_TIMEOUT; i++) { 1176 delay(1000); 1177 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1178 AC_ResetBusy) == 0) 1179 break; 1180 } 1181 1182 if (i == STE_TIMEOUT) 1183 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1184 1185 delay(1000); 1186 } 1187 1188 /* 1189 * ste_setthresh: 1190 * 1191 * set the various transmit threshold registers 1192 */ 1193 void 1194 ste_setthresh(struct ste_softc *sc) 1195 { 1196 /* set the TX threhold */ 1197 bus_space_write_2(sc->sc_st, sc->sc_sh, 1198 STE_TxStartThresh, sc->sc_txthresh); 1199 /* Urgent threshold: set to sc_txthresh / 2 */ 1200 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1201 sc->sc_txthresh >> 6); 1202 /* Burst threshold: use default value (256 bytes) */ 1203 } 1204 1205 /* 1206 * restart TX at the given frame ID in the transmitter ring 1207 */ 1208 1209 void 1210 ste_txrestart(struct ste_softc *sc, u_int8_t id) 1211 { 1212 u_int32_t control; 1213 1214 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1215 control = le32toh(sc->sc_txdescs[id].tfd_control); 1216 control &= ~TFD_TxDMAComplete; 1217 sc->sc_txdescs[id].tfd_control = htole32(control); 1218 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1219 1220 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1221 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1222 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1223 ste_dmahalt_wait(sc); 1224 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1225 STE_CDTXADDR(sc, id)); 1226 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1227 } 1228 1229 /* 1230 * ste_init: [ ifnet interface function ] 1231 * 1232 * Initialize the interface. Must be called at splnet(). 1233 */ 1234 int 1235 ste_init(struct ifnet *ifp) 1236 { 1237 struct ste_softc *sc = ifp->if_softc; 1238 bus_space_tag_t st = sc->sc_st; 1239 bus_space_handle_t sh = sc->sc_sh; 1240 struct ste_descsoft *ds; 1241 int i, error = 0; 1242 1243 /* 1244 * Cancel any pending I/O. 1245 */ 1246 ste_stop(ifp, 0); 1247 1248 /* 1249 * Reset the chip to a known state. 1250 */ 1251 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1252 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1253 1254 /* 1255 * Initialize the transmit descriptor ring. 1256 */ 1257 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1258 sc->sc_txpending = 0; 1259 sc->sc_txdirty = 0; 1260 sc->sc_txlast = STE_NTXDESC - 1; 1261 1262 /* 1263 * Initialize the receive descriptor and receive job 1264 * descriptor rings. 1265 */ 1266 for (i = 0; i < STE_NRXDESC; i++) { 1267 ds = &sc->sc_rxsoft[i]; 1268 if (ds->ds_mbuf == NULL) { 1269 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1270 printf("%s: unable to allocate or map rx " 1271 "buffer %d, error = %d\n", 1272 sc->sc_dev.dv_xname, i, error); 1273 /* 1274 * XXX Should attempt to run with fewer receive 1275 * XXX buffers instead of just failing. 1276 */ 1277 ste_rxdrain(sc); 1278 goto out; 1279 } 1280 } else 1281 STE_INIT_RXDESC(sc, i); 1282 } 1283 sc->sc_rxptr = 0; 1284 1285 /* Set the station address. */ 1286 for (i = 0; i < ETHER_ADDR_LEN; i++) 1287 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1288 LLADDR(ifp->if_sadl)[i]); 1289 1290 /* Set up the receive filter. */ 1291 ste_set_filter(sc); 1292 1293 /* 1294 * Give the receive ring to the chip. 1295 */ 1296 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1297 STE_CDRXADDR(sc, sc->sc_rxptr)); 1298 1299 /* 1300 * We defer giving the transmit ring to the chip until we 1301 * transmit the first packet. 1302 */ 1303 1304 /* 1305 * Initialize the Tx auto-poll period. It's OK to make this number 1306 * large (127 is the max) -- we explicitly kick the transmit engine 1307 * when there's actually a packet. We are using auto-polling only 1308 * to make the interface to the transmit engine not suck. 1309 */ 1310 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1311 1312 /* ..and the Rx auto-poll period. */ 1313 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1314 1315 /* Initialize the Tx start threshold. */ 1316 ste_setthresh(sc); 1317 1318 /* Set the FIFO release threshold to 512 bytes. */ 1319 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1320 1321 /* Set maximum packet size for VLAN. */ 1322 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1323 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1324 else 1325 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1326 1327 /* 1328 * Initialize the interrupt mask. 1329 */ 1330 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1331 IE_TxDMAComplete | IE_RxDMAComplete; 1332 1333 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1334 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1335 1336 /* 1337 * Start the receive DMA engine. 1338 */ 1339 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1340 1341 /* 1342 * Initialize MacCtrl0 -- do it before setting the media, 1343 * as setting the media will actually program the register. 1344 */ 1345 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1346 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1347 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1348 1349 /* 1350 * Set the current media. 1351 */ 1352 mii_mediachg(&sc->sc_mii); 1353 1354 /* 1355 * Start the MAC. 1356 */ 1357 bus_space_write_2(st, sh, STE_MacCtrl1, 1358 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1359 1360 /* 1361 * Start the one second MII clock. 1362 */ 1363 callout_reset(&sc->sc_tick_ch, hz, ste_tick, sc); 1364 1365 /* 1366 * ...all done! 1367 */ 1368 ifp->if_flags |= IFF_RUNNING; 1369 ifp->if_flags &= ~IFF_OACTIVE; 1370 1371 out: 1372 if (error) 1373 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1374 return (error); 1375 } 1376 1377 /* 1378 * ste_drain: 1379 * 1380 * Drain the receive queue. 1381 */ 1382 void 1383 ste_rxdrain(struct ste_softc *sc) 1384 { 1385 struct ste_descsoft *ds; 1386 int i; 1387 1388 for (i = 0; i < STE_NRXDESC; i++) { 1389 ds = &sc->sc_rxsoft[i]; 1390 if (ds->ds_mbuf != NULL) { 1391 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1392 m_freem(ds->ds_mbuf); 1393 ds->ds_mbuf = NULL; 1394 } 1395 } 1396 } 1397 1398 /* 1399 * ste_stop: [ ifnet interface function ] 1400 * 1401 * Stop transmission on the interface. 1402 */ 1403 void 1404 ste_stop(struct ifnet *ifp, int disable) 1405 { 1406 struct ste_softc *sc = ifp->if_softc; 1407 struct ste_descsoft *ds; 1408 int i; 1409 1410 /* 1411 * Stop the one second clock. 1412 */ 1413 callout_stop(&sc->sc_tick_ch); 1414 1415 /* Down the MII. */ 1416 mii_down(&sc->sc_mii); 1417 1418 /* 1419 * Disable interrupts. 1420 */ 1421 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1422 1423 /* 1424 * Stop receiver, transmitter, and stats update. 1425 */ 1426 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1427 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1428 1429 /* 1430 * Stop the transmit and receive DMA. 1431 */ 1432 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1433 DC_RxDMAHalt | DC_TxDMAHalt); 1434 ste_dmahalt_wait(sc); 1435 1436 /* 1437 * Release any queued transmit buffers. 1438 */ 1439 for (i = 0; i < STE_NTXDESC; i++) { 1440 ds = &sc->sc_txsoft[i]; 1441 if (ds->ds_mbuf != NULL) { 1442 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1443 m_freem(ds->ds_mbuf); 1444 ds->ds_mbuf = NULL; 1445 } 1446 } 1447 1448 if (disable) 1449 ste_rxdrain(sc); 1450 1451 /* 1452 * Mark the interface down and cancel the watchdog timer. 1453 */ 1454 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1455 ifp->if_timer = 0; 1456 } 1457 1458 static int 1459 ste_eeprom_wait(struct ste_softc *sc) 1460 { 1461 int i; 1462 1463 for (i = 0; i < STE_TIMEOUT; i++) { 1464 delay(1000); 1465 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1466 EC_EepromBusy) == 0) 1467 return (0); 1468 } 1469 return (1); 1470 } 1471 1472 /* 1473 * ste_read_eeprom: 1474 * 1475 * Read data from the serial EEPROM. 1476 */ 1477 void 1478 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1479 { 1480 1481 if (ste_eeprom_wait(sc)) 1482 printf("%s: EEPROM failed to come ready\n", 1483 sc->sc_dev.dv_xname); 1484 1485 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1486 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1487 if (ste_eeprom_wait(sc)) 1488 printf("%s: EEPROM read timed out\n", 1489 sc->sc_dev.dv_xname); 1490 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1491 } 1492 1493 /* 1494 * ste_add_rxbuf: 1495 * 1496 * Add a receive buffer to the indicated descriptor. 1497 */ 1498 int 1499 ste_add_rxbuf(struct ste_softc *sc, int idx) 1500 { 1501 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1502 struct mbuf *m; 1503 int error; 1504 1505 MGETHDR(m, M_DONTWAIT, MT_DATA); 1506 if (m == NULL) 1507 return (ENOBUFS); 1508 1509 MCLGET(m, M_DONTWAIT); 1510 if ((m->m_flags & M_EXT) == 0) { 1511 m_freem(m); 1512 return (ENOBUFS); 1513 } 1514 1515 if (ds->ds_mbuf != NULL) 1516 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1517 1518 ds->ds_mbuf = m; 1519 1520 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1521 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1522 BUS_DMA_READ|BUS_DMA_NOWAIT); 1523 if (error) { 1524 printf("%s: can't load rx DMA map %d, error = %d\n", 1525 sc->sc_dev.dv_xname, idx, error); 1526 panic("ste_add_rxbuf"); /* XXX */ 1527 } 1528 1529 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1530 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1531 1532 STE_INIT_RXDESC(sc, idx); 1533 1534 return (0); 1535 } 1536 1537 /* 1538 * ste_set_filter: 1539 * 1540 * Set up the receive filter. 1541 */ 1542 void 1543 ste_set_filter(struct ste_softc *sc) 1544 { 1545 struct ethercom *ec = &sc->sc_ethercom; 1546 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1547 struct ether_multi *enm; 1548 struct ether_multistep step; 1549 uint32_t crc; 1550 uint16_t mchash[4]; 1551 1552 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1553 if (ifp->if_flags & IFF_BROADCAST) 1554 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1555 1556 if (ifp->if_flags & IFF_PROMISC) { 1557 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1558 goto allmulti; 1559 } 1560 1561 /* 1562 * Set up the multicast address filter by passing all multicast 1563 * addresses through a CRC generator, and then using the low-order 1564 * 6 bits as an index into the 64 bit multicast hash table. The 1565 * high order bits select the register, while the rest of the bits 1566 * select the bit within the register. 1567 */ 1568 1569 memset(mchash, 0, sizeof(mchash)); 1570 1571 ETHER_FIRST_MULTI(step, ec, enm); 1572 if (enm == NULL) 1573 goto done; 1574 1575 while (enm != NULL) { 1576 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1577 /* 1578 * We must listen to a range of multicast addresses. 1579 * For now, just accept all multicasts, rather than 1580 * trying to set only those filter bits needed to match 1581 * the range. (At this time, the only use of address 1582 * ranges is for IP multicast routing, for which the 1583 * range is big enough to require all bits set.) 1584 */ 1585 goto allmulti; 1586 } 1587 1588 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1589 1590 /* Just want the 6 least significant bits. */ 1591 crc &= 0x3f; 1592 1593 /* Set the corresponding bit in the hash table. */ 1594 mchash[crc >> 4] |= 1 << (crc & 0xf); 1595 1596 ETHER_NEXT_MULTI(step, enm); 1597 } 1598 1599 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1600 1601 ifp->if_flags &= ~IFF_ALLMULTI; 1602 goto done; 1603 1604 allmulti: 1605 ifp->if_flags |= IFF_ALLMULTI; 1606 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1607 1608 done: 1609 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1610 /* 1611 * Program the multicast hash table. 1612 */ 1613 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1614 mchash[0]); 1615 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1616 mchash[1]); 1617 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1618 mchash[2]); 1619 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1620 mchash[3]); 1621 } 1622 1623 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1624 sc->sc_ReceiveMode); 1625 } 1626 1627 /* 1628 * ste_mii_readreg: [mii interface function] 1629 * 1630 * Read a PHY register on the MII of the ST-201. 1631 */ 1632 int 1633 ste_mii_readreg(struct device *self, int phy, int reg) 1634 { 1635 1636 return (mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg)); 1637 } 1638 1639 /* 1640 * ste_mii_writereg: [mii interface function] 1641 * 1642 * Write a PHY register on the MII of the ST-201. 1643 */ 1644 void 1645 ste_mii_writereg(struct device *self, int phy, int reg, int val) 1646 { 1647 1648 mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1649 } 1650 1651 /* 1652 * ste_mii_statchg: [mii interface function] 1653 * 1654 * Callback from MII layer when media changes. 1655 */ 1656 void 1657 ste_mii_statchg(struct device *self) 1658 { 1659 struct ste_softc *sc = (struct ste_softc *) self; 1660 1661 if (sc->sc_mii.mii_media_active & IFM_FDX) 1662 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1663 else 1664 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1665 1666 /* XXX 802.1x flow-control? */ 1667 1668 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1669 } 1670 1671 /* 1672 * ste_mii_bitbang_read: [mii bit-bang interface function] 1673 * 1674 * Read the MII serial port for the MII bit-bang module. 1675 */ 1676 uint32_t 1677 ste_mii_bitbang_read(struct device *self) 1678 { 1679 struct ste_softc *sc = (void *) self; 1680 1681 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1682 } 1683 1684 /* 1685 * ste_mii_bitbang_write: [mii big-bang interface function] 1686 * 1687 * Write the MII serial port for the MII bit-bang module. 1688 */ 1689 void 1690 ste_mii_bitbang_write(struct device *self, uint32_t val) 1691 { 1692 struct ste_softc *sc = (void *) self; 1693 1694 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1695 } 1696 1697 /* 1698 * ste_mediastatus: [ifmedia interface function] 1699 * 1700 * Get the current interface media status. 1701 */ 1702 void 1703 ste_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1704 { 1705 struct ste_softc *sc = ifp->if_softc; 1706 1707 mii_pollstat(&sc->sc_mii); 1708 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1709 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1710 } 1711 1712 /* 1713 * ste_mediachange: [ifmedia interface function] 1714 * 1715 * Set hardware to newly-selected media. 1716 */ 1717 int 1718 ste_mediachange(struct ifnet *ifp) 1719 { 1720 struct ste_softc *sc = ifp->if_softc; 1721 1722 if (ifp->if_flags & IFF_UP) 1723 mii_mediachg(&sc->sc_mii); 1724 return (0); 1725 }
Cache object: 9d9ef5882b35df0a5e221603a81f12ca
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