The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/if_stge.c

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    1 /*      $NetBSD: if_stge.c,v 1.19 2003/03/01 19:49:45 mjacob Exp $      */
    2 
    3 /*-
    4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the NetBSD
   21  *      Foundation, Inc. and its contributors.
   22  * 4. Neither the name of The NetBSD Foundation nor the names of its
   23  *    contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   36  * POSSIBILITY OF SUCH DAMAGE.
   37  */
   38 
   39 /*
   40  * Device driver for the Sundance Tech. TC9021 10/100/1000
   41  * Ethernet controller.
   42  */
   43 
   44 #include <sys/cdefs.h>
   45 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.19 2003/03/01 19:49:45 mjacob Exp $");
   46 
   47 #include "bpfilter.h"
   48 
   49 #include <sys/param.h>
   50 #include <sys/systm.h>
   51 #include <sys/callout.h>
   52 #include <sys/mbuf.h>
   53 #include <sys/malloc.h>
   54 #include <sys/kernel.h>
   55 #include <sys/socket.h>
   56 #include <sys/ioctl.h>
   57 #include <sys/errno.h>
   58 #include <sys/device.h>
   59 #include <sys/queue.h>
   60 
   61 #include <uvm/uvm_extern.h>             /* for PAGE_SIZE */
   62 
   63 #include <net/if.h>
   64 #include <net/if_dl.h>
   65 #include <net/if_media.h>
   66 #include <net/if_ether.h>
   67 
   68 #if NBPFILTER > 0
   69 #include <net/bpf.h>
   70 #endif
   71 
   72 #include <machine/bus.h>
   73 #include <machine/intr.h>
   74 
   75 #include <dev/mii/mii.h>
   76 #include <dev/mii/miivar.h>
   77 #include <dev/mii/mii_bitbang.h>
   78 
   79 #include <dev/pci/pcireg.h>
   80 #include <dev/pci/pcivar.h>
   81 #include <dev/pci/pcidevs.h>
   82 
   83 #include <dev/pci/if_stgereg.h>
   84 
   85 /* #define      STGE_CU_BUG                     1 */
   86 #define STGE_VLAN_UNTAG                 1
   87 /* #define      STGE_VLAN_CFI           1 */
   88 
   89 /*
   90  * Transmit descriptor list size.
   91  */
   92 #define STGE_NTXDESC            256
   93 #define STGE_NTXDESC_MASK       (STGE_NTXDESC - 1)
   94 #define STGE_NEXTTX(x)          (((x) + 1) & STGE_NTXDESC_MASK)
   95 
   96 /*
   97  * Receive descriptor list size.
   98  */
   99 #define STGE_NRXDESC            256
  100 #define STGE_NRXDESC_MASK       (STGE_NRXDESC - 1)
  101 #define STGE_NEXTRX(x)          (((x) + 1) & STGE_NRXDESC_MASK)
  102 
  103 /*
  104  * Only interrupt every N frames.  Must be a power-of-two.
  105  */
  106 #define STGE_TXINTR_SPACING     16
  107 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1)
  108 
  109 /*
  110  * Control structures are DMA'd to the TC9021 chip.  We allocate them in
  111  * a single clump that maps to a single DMA segment to make several things
  112  * easier.
  113  */
  114 struct stge_control_data {
  115         /*
  116          * The transmit descriptors.
  117          */
  118         struct stge_tfd scd_txdescs[STGE_NTXDESC];
  119 
  120         /*
  121          * The receive descriptors.
  122          */
  123         struct stge_rfd scd_rxdescs[STGE_NRXDESC];
  124 };
  125 
  126 #define STGE_CDOFF(x)   offsetof(struct stge_control_data, x)
  127 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)])
  128 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)])
  129 
  130 /*
  131  * Software state for transmit and receive jobs.
  132  */
  133 struct stge_descsoft {
  134         struct mbuf *ds_mbuf;           /* head of our mbuf chain */
  135         bus_dmamap_t ds_dmamap;         /* our DMA map */
  136 };
  137 
  138 /*
  139  * Software state per device.
  140  */
  141 struct stge_softc {
  142         struct device sc_dev;           /* generic device information */
  143         bus_space_tag_t sc_st;          /* bus space tag */
  144         bus_space_handle_t sc_sh;       /* bus space handle */
  145         bus_dma_tag_t sc_dmat;          /* bus DMA tag */
  146         struct ethercom sc_ethercom;    /* ethernet common data */
  147         void *sc_sdhook;                /* shutdown hook */
  148         int sc_rev;                     /* silicon revision */
  149 
  150         void *sc_ih;                    /* interrupt cookie */
  151 
  152         struct mii_data sc_mii;         /* MII/media information */
  153 
  154         struct callout sc_tick_ch;      /* tick callout */
  155 
  156         bus_dmamap_t sc_cddmamap;       /* control data DMA map */
  157 #define sc_cddma        sc_cddmamap->dm_segs[0].ds_addr
  158 
  159         /*
  160          * Software state for transmit and receive descriptors.
  161          */
  162         struct stge_descsoft sc_txsoft[STGE_NTXDESC];
  163         struct stge_descsoft sc_rxsoft[STGE_NRXDESC];
  164 
  165         /*
  166          * Control data structures.
  167          */
  168         struct stge_control_data *sc_control_data;
  169 #define sc_txdescs      sc_control_data->scd_txdescs
  170 #define sc_rxdescs      sc_control_data->scd_rxdescs
  171 
  172 #ifdef STGE_EVENT_COUNTERS
  173         /*
  174          * Event counters.
  175          */
  176         struct evcnt sc_ev_txstall;     /* Tx stalled */
  177         struct evcnt sc_ev_txdmaintr;   /* Tx DMA interrupts */
  178         struct evcnt sc_ev_txindintr;   /* Tx Indicate interrupts */
  179         struct evcnt sc_ev_rxintr;      /* Rx interrupts */
  180 
  181         struct evcnt sc_ev_txseg1;      /* Tx packets w/ 1 segment */
  182         struct evcnt sc_ev_txseg2;      /* Tx packets w/ 2 segments */
  183         struct evcnt sc_ev_txseg3;      /* Tx packets w/ 3 segments */
  184         struct evcnt sc_ev_txseg4;      /* Tx packets w/ 4 segments */
  185         struct evcnt sc_ev_txseg5;      /* Tx packets w/ 5 segments */
  186         struct evcnt sc_ev_txsegmore;   /* Tx packets w/ more than 5 segments */
  187         struct evcnt sc_ev_txcopy;      /* Tx packets that we had to copy */
  188 
  189         struct evcnt sc_ev_rxipsum;     /* IP checksums checked in-bound */
  190         struct evcnt sc_ev_rxtcpsum;    /* TCP checksums checked in-bound */
  191         struct evcnt sc_ev_rxudpsum;    /* UDP checksums checked in-bound */
  192 
  193         struct evcnt sc_ev_txipsum;     /* IP checksums comp. out-bound */
  194         struct evcnt sc_ev_txtcpsum;    /* TCP checksums comp. out-bound */
  195         struct evcnt sc_ev_txudpsum;    /* UDP checksums comp. out-bound */
  196 #endif /* STGE_EVENT_COUNTERS */
  197 
  198         int     sc_txpending;           /* number of Tx requests pending */
  199         int     sc_txdirty;             /* first dirty Tx descriptor */
  200         int     sc_txlast;              /* last used Tx descriptor */
  201 
  202         int     sc_rxptr;               /* next ready Rx descriptor/descsoft */
  203         int     sc_rxdiscard;
  204         int     sc_rxlen;
  205         struct mbuf *sc_rxhead;
  206         struct mbuf *sc_rxtail;
  207         struct mbuf **sc_rxtailp;
  208 
  209         int     sc_txthresh;            /* Tx threshold */
  210         int     sc_usefiber;            /* if we're fiber */
  211         uint32_t sc_DMACtrl;            /* prototype DMACtrl register */
  212         uint32_t sc_MACCtrl;            /* prototype MacCtrl register */
  213         uint16_t sc_IntEnable;          /* prototype IntEnable register */
  214         uint16_t sc_ReceiveMode;        /* prototype ReceiveMode register */
  215         uint8_t sc_PhyCtrl;             /* prototype PhyCtrl register */
  216 };
  217 
  218 #define STGE_RXCHAIN_RESET(sc)                                          \
  219 do {                                                                    \
  220         (sc)->sc_rxtailp = &(sc)->sc_rxhead;                            \
  221         *(sc)->sc_rxtailp = NULL;                                       \
  222         (sc)->sc_rxlen = 0;                                             \
  223 } while (/*CONSTCOND*/0)
  224 
  225 #define STGE_RXCHAIN_LINK(sc, m)                                        \
  226 do {                                                                    \
  227         *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);                      \
  228         (sc)->sc_rxtailp = &(m)->m_next;                                \
  229 } while (/*CONSTCOND*/0)
  230 
  231 #ifdef STGE_EVENT_COUNTERS
  232 #define STGE_EVCNT_INCR(ev)     (ev)->ev_count++
  233 #else
  234 #define STGE_EVCNT_INCR(ev)     /* nothing */
  235 #endif
  236 
  237 #define STGE_CDTXADDR(sc, x)    ((sc)->sc_cddma + STGE_CDTXOFF((x)))
  238 #define STGE_CDRXADDR(sc, x)    ((sc)->sc_cddma + STGE_CDRXOFF((x)))
  239 
  240 #define STGE_CDTXSYNC(sc, x, ops)                                       \
  241         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  242             STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops))
  243 
  244 #define STGE_CDRXSYNC(sc, x, ops)                                       \
  245         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  246             STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops))
  247 
  248 #define STGE_INIT_RXDESC(sc, x)                                         \
  249 do {                                                                    \
  250         struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)];             \
  251         struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)];                \
  252                                                                         \
  253         /*                                                              \
  254          * Note: We scoot the packet forward 2 bytes in the buffer      \
  255          * so that the payload after the Ethernet header is aligned     \
  256          * to a 4-byte boundary.                                        \
  257          */                                                             \
  258         __rfd->rfd_frag.frag_word0 =                                    \
  259             htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\
  260             FRAG_LEN(MCLBYTES - 2));                                    \
  261         __rfd->rfd_next =                                               \
  262             htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x))));   \
  263         __rfd->rfd_status = 0;                                          \
  264         STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
  265 } while (/*CONSTCOND*/0)
  266 
  267 #define STGE_TIMEOUT 1000
  268 
  269 void    stge_start(struct ifnet *);
  270 void    stge_watchdog(struct ifnet *);
  271 int     stge_ioctl(struct ifnet *, u_long, caddr_t);
  272 int     stge_init(struct ifnet *);
  273 void    stge_stop(struct ifnet *, int);
  274 
  275 void    stge_shutdown(void *);
  276 
  277 void    stge_reset(struct stge_softc *);
  278 void    stge_rxdrain(struct stge_softc *);
  279 int     stge_add_rxbuf(struct stge_softc *, int);
  280 #if 0
  281 void    stge_read_eeprom(struct stge_softc *, int, uint16_t *);
  282 #endif
  283 void    stge_tick(void *);
  284 
  285 void    stge_stats_update(struct stge_softc *);
  286 
  287 void    stge_set_filter(struct stge_softc *);
  288 
  289 int     stge_intr(void *);
  290 void    stge_txintr(struct stge_softc *);
  291 void    stge_rxintr(struct stge_softc *);
  292 
  293 int     stge_mii_readreg(struct device *, int, int);
  294 void    stge_mii_writereg(struct device *, int, int, int);
  295 void    stge_mii_statchg(struct device *);
  296 
  297 int     stge_mediachange(struct ifnet *);
  298 void    stge_mediastatus(struct ifnet *, struct ifmediareq *);
  299 
  300 int     stge_match(struct device *, struct cfdata *, void *);
  301 void    stge_attach(struct device *, struct device *, void *);
  302 
  303 int     stge_copy_small = 0;
  304 
  305 CFATTACH_DECL(stge, sizeof(struct stge_softc),
  306     stge_match, stge_attach, NULL, NULL);
  307 
  308 uint32_t stge_mii_bitbang_read(struct device *);
  309 void    stge_mii_bitbang_write(struct device *, uint32_t);
  310 
  311 const struct mii_bitbang_ops stge_mii_bitbang_ops = {
  312         stge_mii_bitbang_read,
  313         stge_mii_bitbang_write,
  314         {
  315                 PC_MgmtData,            /* MII_BIT_MDO */
  316                 PC_MgmtData,            /* MII_BIT_MDI */
  317                 PC_MgmtClk,             /* MII_BIT_MDC */
  318                 PC_MgmtDir,             /* MII_BIT_DIR_HOST_PHY */
  319                 0,                      /* MII_BIT_DIR_PHY_HOST */
  320         }
  321 };
  322 
  323 /*
  324  * Devices supported by this driver.
  325  */
  326 const struct stge_product {
  327         pci_vendor_id_t         stge_vendor;
  328         pci_product_id_t        stge_product;
  329         const char              *stge_name;
  330 } stge_products[] = {
  331         { PCI_VENDOR_SUNDANCETI,        PCI_PRODUCT_SUNDANCETI_ST2021,
  332           "Sundance ST-2021 Gigabit Ethernet" },
  333 
  334         { PCI_VENDOR_TAMARACK,          PCI_PRODUCT_TAMARACK_TC9021,
  335           "Tamarack TC9021 Gigabit Ethernet" },
  336 
  337         { PCI_VENDOR_TAMARACK,          PCI_PRODUCT_TAMARACK_TC9021_ALT,
  338           "Tamarack TC9021 Gigabit Ethernet" },
  339 
  340         /*
  341          * The Sundance sample boards use the Sundance vendor ID,
  342          * but the Tamarack product ID.
  343          */
  344         { PCI_VENDOR_SUNDANCETI,        PCI_PRODUCT_TAMARACK_TC9021,
  345           "Sundance TC9021 Gigabit Ethernet" },
  346 
  347         { PCI_VENDOR_SUNDANCETI,        PCI_PRODUCT_TAMARACK_TC9021_ALT,
  348           "Sundance TC9021 Gigabit Ethernet" },
  349 
  350         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DL4000,
  351           "D-Link DL-4000 Gigabit Ethernet" },
  352 
  353         { PCI_VENDOR_ANTARES,           PCI_PRODUCT_ANTARES_TC9021,
  354           "Antares Gigabit Ethernet" },
  355 
  356         { 0,                            0,
  357           NULL },
  358 };
  359 
  360 static const struct stge_product *
  361 stge_lookup(const struct pci_attach_args *pa)
  362 {
  363         const struct stge_product *sp;
  364 
  365         for (sp = stge_products; sp->stge_name != NULL; sp++) {
  366                 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor &&
  367                     PCI_PRODUCT(pa->pa_id) == sp->stge_product)
  368                         return (sp);
  369         }
  370         return (NULL);
  371 }
  372 
  373 int
  374 stge_match(struct device *parent, struct cfdata *cf, void *aux)
  375 {
  376         struct pci_attach_args *pa = aux;
  377 
  378         if (stge_lookup(pa) != NULL)
  379                 return (1);
  380 
  381         return (0);
  382 }
  383 
  384 void
  385 stge_attach(struct device *parent, struct device *self, void *aux)
  386 {
  387         struct stge_softc *sc = (struct stge_softc *) self;
  388         struct pci_attach_args *pa = aux;
  389         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
  390         pci_chipset_tag_t pc = pa->pa_pc;
  391         pci_intr_handle_t ih;
  392         const char *intrstr = NULL;
  393         bus_space_tag_t iot, memt;
  394         bus_space_handle_t ioh, memh;
  395         bus_dma_segment_t seg;
  396         int ioh_valid, memh_valid;
  397         int i, rseg, error;
  398         const struct stge_product *sp;
  399         pcireg_t pmode;
  400         uint8_t enaddr[ETHER_ADDR_LEN];
  401         int pmreg;
  402 
  403         callout_init(&sc->sc_tick_ch);
  404 
  405         sp = stge_lookup(pa);
  406         if (sp == NULL) {
  407                 printf("\n");
  408                 panic("ste_attach: impossible");
  409         }
  410 
  411         sc->sc_rev = PCI_REVISION(pa->pa_class);
  412 
  413         printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev);
  414 
  415         /*
  416          * Map the device.
  417          */
  418         ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA,
  419             PCI_MAPREG_TYPE_IO, 0,
  420             &iot, &ioh, NULL, NULL) == 0);
  421         memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA,
  422             PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
  423             &memt, &memh, NULL, NULL) == 0);
  424 
  425         if (memh_valid) {
  426                 sc->sc_st = memt;
  427                 sc->sc_sh = memh;
  428         } else if (ioh_valid) {
  429                 sc->sc_st = iot;
  430                 sc->sc_sh = ioh;
  431         } else {
  432                 printf("%s: unable to map device registers\n",
  433                     sc->sc_dev.dv_xname);
  434                 return;
  435         }
  436 
  437         sc->sc_dmat = pa->pa_dmat;
  438 
  439         /* Enable bus mastering. */
  440         pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
  441             pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
  442             PCI_COMMAND_MASTER_ENABLE);
  443 
  444         /* Get it out of power save mode if needed. */
  445         if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
  446                 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) &
  447                     PCI_PMCSR_STATE_MASK;
  448                 if (pmode == PCI_PMCSR_STATE_D3) {
  449                         /*
  450                          * The card has lost all configuration data in
  451                          * this state, so punt.
  452                          */
  453                         printf("%s: unable to wake up from power state D3\n",
  454                             sc->sc_dev.dv_xname);
  455                         return;
  456                 }
  457                 if (pmode != 0) {
  458                         printf("%s: waking up from power state D%d\n",
  459                             sc->sc_dev.dv_xname, pmode);
  460                         pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
  461                             PCI_PMCSR_STATE_D0);
  462                 }
  463         }
  464 
  465         /*
  466          * Map and establish our interrupt.
  467          */
  468         if (pci_intr_map(pa, &ih)) {
  469                 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname);
  470                 return;
  471         }
  472         intrstr = pci_intr_string(pc, ih);
  473         sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc);
  474         if (sc->sc_ih == NULL) {
  475                 printf("%s: unable to establish interrupt",
  476                     sc->sc_dev.dv_xname);
  477                 if (intrstr != NULL)
  478                         printf(" at %s", intrstr);
  479                 printf("\n");
  480                 return;
  481         }
  482         printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
  483 
  484         /*
  485          * Allocate the control data structures, and create and load the
  486          * DMA map for it.
  487          */
  488         if ((error = bus_dmamem_alloc(sc->sc_dmat,
  489             sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
  490             0)) != 0) {
  491                 printf("%s: unable to allocate control data, error = %d\n",
  492                     sc->sc_dev.dv_xname, error);
  493                 goto fail_0;
  494         }
  495 
  496         if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
  497             sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data,
  498             BUS_DMA_COHERENT)) != 0) {
  499                 printf("%s: unable to map control data, error = %d\n",
  500                     sc->sc_dev.dv_xname, error);
  501                 goto fail_1;
  502         }
  503 
  504         if ((error = bus_dmamap_create(sc->sc_dmat,
  505             sizeof(struct stge_control_data), 1,
  506             sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
  507                 printf("%s: unable to create control data DMA map, "
  508                     "error = %d\n", sc->sc_dev.dv_xname, error);
  509                 goto fail_2;
  510         }
  511 
  512         if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
  513             sc->sc_control_data, sizeof(struct stge_control_data), NULL,
  514             0)) != 0) {
  515                 printf("%s: unable to load control data DMA map, error = %d\n",
  516                     sc->sc_dev.dv_xname, error);
  517                 goto fail_3;
  518         }
  519 
  520         /*
  521          * Create the transmit buffer DMA maps.  Note that rev B.3
  522          * and earlier seem to have a bug regarding multi-fragment
  523          * packets.  We need to limit the number of Tx segments on
  524          * such chips to 1.
  525          */
  526         for (i = 0; i < STGE_NTXDESC; i++) {
  527                 if ((error = bus_dmamap_create(sc->sc_dmat,
  528                     ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0,
  529                     &sc->sc_txsoft[i].ds_dmamap)) != 0) {
  530                         printf("%s: unable to create tx DMA map %d, "
  531                             "error = %d\n", sc->sc_dev.dv_xname, i, error);
  532                         goto fail_4;
  533                 }
  534         }
  535 
  536         /*
  537          * Create the receive buffer DMA maps.
  538          */
  539         for (i = 0; i < STGE_NRXDESC; i++) {
  540                 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
  541                     MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) {
  542                         printf("%s: unable to create rx DMA map %d, "
  543                             "error = %d\n", sc->sc_dev.dv_xname, i, error);
  544                         goto fail_5;
  545                 }
  546                 sc->sc_rxsoft[i].ds_mbuf = NULL;
  547         }
  548 
  549         /*
  550          * Determine if we're copper or fiber.  It affects how we
  551          * reset the card.
  552          */
  553         if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) &
  554             AC_PhyMedia)
  555                 sc->sc_usefiber = 1;
  556         else
  557                 sc->sc_usefiber = 0;
  558 
  559         /*
  560          * Reset the chip to a known state.
  561          */
  562         stge_reset(sc);
  563 
  564         /*
  565          * Reading the station address from the EEPROM doesn't seem
  566          * to work, at least on my sample boards.  Instread, since
  567          * the reset sequence does AutoInit, read it from the station
  568          * address registers.
  569          */
  570         enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh,
  571             STGE_StationAddress0) & 0xff;
  572         enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh,
  573             STGE_StationAddress0) >> 8;
  574         enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh,
  575             STGE_StationAddress1) & 0xff;
  576         enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh,
  577             STGE_StationAddress1) >> 8;
  578         enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh,
  579             STGE_StationAddress2) & 0xff;
  580         enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh,
  581             STGE_StationAddress2) >> 8;
  582 
  583         printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
  584             ether_sprintf(enaddr));
  585 
  586         /*
  587          * Read some important bits from the PhyCtrl register.
  588          */
  589         sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh,
  590             STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
  591 
  592         /*
  593          * Initialize our media structures and probe the MII.
  594          */
  595         sc->sc_mii.mii_ifp = ifp;
  596         sc->sc_mii.mii_readreg = stge_mii_readreg;
  597         sc->sc_mii.mii_writereg = stge_mii_writereg;
  598         sc->sc_mii.mii_statchg = stge_mii_statchg;
  599         ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, stge_mediachange,
  600             stge_mediastatus);
  601         mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
  602             MII_OFFSET_ANY, MIIF_DOPAUSE);
  603         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
  604                 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
  605                 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
  606         } else
  607                 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
  608 
  609         ifp = &sc->sc_ethercom.ec_if;
  610         strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
  611         ifp->if_softc = sc;
  612         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  613         ifp->if_ioctl = stge_ioctl;
  614         ifp->if_start = stge_start;
  615         ifp->if_watchdog = stge_watchdog;
  616         ifp->if_init = stge_init;
  617         ifp->if_stop = stge_stop;
  618         IFQ_SET_READY(&ifp->if_snd);
  619 
  620         /*
  621          * The manual recommends disabling early transmit, so we
  622          * do.  It's disabled anyway, if using IP checksumming,
  623          * since the entire packet must be in the FIFO in order
  624          * for the chip to perform the checksum.
  625          */
  626         sc->sc_txthresh = 0x0fff;
  627 
  628         /*
  629          * Disable MWI if the PCI layer tells us to.
  630          */
  631         sc->sc_DMACtrl = 0;
  632         if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0)
  633                 sc->sc_DMACtrl |= DMAC_MWIDisable;
  634 
  635         /*
  636          * We can support 802.1Q VLAN-sized frames and jumbo
  637          * Ethernet frames.
  638          *
  639          * XXX Figure out how to do hw-assisted VLAN tagging in
  640          * XXX a reasonable way on this chip.
  641          */
  642         sc->sc_ethercom.ec_capabilities |=
  643             ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */
  644             ETHERCAP_VLAN_HWTAGGING;
  645 
  646         /*
  647          * We can do IPv4/TCPv4/UDPv4 checksums in hardware.
  648          */
  649         sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 |
  650             IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
  651 
  652         /*
  653          * Attach the interface.
  654          */
  655         if_attach(ifp);
  656         ether_ifattach(ifp, enaddr);
  657 
  658 #ifdef STGE_EVENT_COUNTERS
  659         /*
  660          * Attach event counters.
  661          */
  662         evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC,
  663             NULL, sc->sc_dev.dv_xname, "txstall");
  664         evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR,
  665             NULL, sc->sc_dev.dv_xname, "txdmaintr");
  666         evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR,
  667             NULL, sc->sc_dev.dv_xname, "txindintr");
  668         evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,        
  669             NULL, sc->sc_dev.dv_xname, "rxintr");
  670 
  671         evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC,       
  672             NULL, sc->sc_dev.dv_xname, "txseg1");                      
  673         evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC,       
  674             NULL, sc->sc_dev.dv_xname, "txseg2");                      
  675         evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC,       
  676             NULL, sc->sc_dev.dv_xname, "txseg3");                      
  677         evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC,       
  678             NULL, sc->sc_dev.dv_xname, "txseg4");                      
  679         evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC,       
  680             NULL, sc->sc_dev.dv_xname, "txseg5");                      
  681         evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC,       
  682             NULL, sc->sc_dev.dv_xname, "txsegmore");                      
  683         evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC,       
  684             NULL, sc->sc_dev.dv_xname, "txcopy");                      
  685 
  686         evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,       
  687             NULL, sc->sc_dev.dv_xname, "rxipsum");                      
  688         evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC,      
  689             NULL, sc->sc_dev.dv_xname, "rxtcpsum");
  690         evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC,      
  691             NULL, sc->sc_dev.dv_xname, "rxudpsum");
  692         evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
  693             NULL, sc->sc_dev.dv_xname, "txipsum");
  694         evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC,
  695             NULL, sc->sc_dev.dv_xname, "txtcpsum");
  696         evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC,
  697             NULL, sc->sc_dev.dv_xname, "txudpsum");
  698 #endif /* STGE_EVENT_COUNTERS */
  699 
  700         /*
  701          * Make sure the interface is shutdown during reboot.
  702          */
  703         sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc);
  704         if (sc->sc_sdhook == NULL)
  705                 printf("%s: WARNING: unable to establish shutdown hook\n",
  706                     sc->sc_dev.dv_xname);
  707         return;
  708 
  709         /*
  710          * Free any resources we've allocated during the failed attach
  711          * attempt.  Do this in reverse order and fall through.
  712          */
  713  fail_5:
  714         for (i = 0; i < STGE_NRXDESC; i++) {
  715                 if (sc->sc_rxsoft[i].ds_dmamap != NULL)
  716                         bus_dmamap_destroy(sc->sc_dmat,
  717                             sc->sc_rxsoft[i].ds_dmamap);
  718         }
  719  fail_4:
  720         for (i = 0; i < STGE_NTXDESC; i++) {
  721                 if (sc->sc_txsoft[i].ds_dmamap != NULL)
  722                         bus_dmamap_destroy(sc->sc_dmat,
  723                             sc->sc_txsoft[i].ds_dmamap);
  724         }
  725         bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
  726  fail_3:
  727         bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
  728  fail_2:
  729         bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
  730             sizeof(struct stge_control_data));
  731  fail_1:
  732         bus_dmamem_free(sc->sc_dmat, &seg, rseg);
  733  fail_0:
  734         return;
  735 }
  736 
  737 /*
  738  * stge_shutdown:
  739  *
  740  *      Make sure the interface is stopped at reboot time.
  741  */
  742 void
  743 stge_shutdown(void *arg)
  744 {
  745         struct stge_softc *sc = arg;
  746 
  747         stge_stop(&sc->sc_ethercom.ec_if, 1);
  748 }
  749 
  750 static void
  751 stge_dma_wait(struct stge_softc *sc)
  752 {
  753         int i;
  754 
  755         for (i = 0; i < STGE_TIMEOUT; i++) {
  756                 delay(2);
  757                 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) &
  758                      DMAC_TxDMAInProg) == 0)
  759                         break;
  760         }
  761 
  762         if (i == STGE_TIMEOUT)
  763                 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname);
  764 }
  765 
  766 /*
  767  * stge_start:          [ifnet interface function]
  768  *
  769  *      Start packet transmission on the interface.
  770  */
  771 void
  772 stge_start(struct ifnet *ifp)
  773 {
  774         struct stge_softc *sc = ifp->if_softc;
  775         struct mbuf *m0;
  776         struct stge_descsoft *ds;
  777         struct stge_tfd *tfd;
  778         bus_dmamap_t dmamap;
  779         int error, firsttx, nexttx, opending, seg, totlen;
  780         uint64_t csum_flags;
  781 
  782         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
  783                 return;
  784 
  785         /*
  786          * Remember the previous number of pending transmissions
  787          * and the first descriptor we will use.
  788          */
  789         opending = sc->sc_txpending;
  790         firsttx = STGE_NEXTTX(sc->sc_txlast);
  791 
  792         /*
  793          * Loop through the send queue, setting up transmit descriptors
  794          * until we drain the queue, or use up all available transmit
  795          * descriptors.
  796          */
  797         for (;;) {
  798                 struct m_tag *mtag;
  799                 uint64_t tfc;
  800 
  801                 /*
  802                  * Grab a packet off the queue.
  803                  */
  804                 IFQ_POLL(&ifp->if_snd, m0);
  805                 if (m0 == NULL)
  806                         break;
  807 
  808                 /*
  809                  * Leave one unused descriptor at the end of the
  810                  * list to prevent wrapping completely around.
  811                  */
  812                 if (sc->sc_txpending == (STGE_NTXDESC - 1)) {
  813                         STGE_EVCNT_INCR(&sc->sc_ev_txstall);
  814                         break;
  815                 }
  816 
  817                 /*
  818                  * See if we have any VLAN stuff.
  819                  */
  820                 mtag = sc->sc_ethercom.ec_nvlans ?
  821                     m_tag_find(m0, PACKET_TAG_VLAN, NULL) : NULL;
  822 
  823                 /*
  824                  * Get the last and next available transmit descriptor.
  825                  */
  826                 nexttx = STGE_NEXTTX(sc->sc_txlast);
  827                 tfd = &sc->sc_txdescs[nexttx];
  828                 ds = &sc->sc_txsoft[nexttx];
  829 
  830                 dmamap = ds->ds_dmamap;
  831 
  832                 /*
  833                  * Load the DMA map.  If this fails, the packet either
  834                  * didn't fit in the alloted number of segments, or we
  835                  * were short on resources.  For the too-may-segments
  836                  * case, we simply report an error and drop the packet,
  837                  * since we can't sanely copy a jumbo packet to a single
  838                  * buffer.
  839                  */
  840                 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
  841                     BUS_DMA_NOWAIT);
  842                 if (error) {
  843                         if (error == EFBIG) {
  844                                 printf("%s: Tx packet consumes too many "
  845                                     "DMA segments, dropping...\n",
  846                                     sc->sc_dev.dv_xname);
  847                                 IFQ_DEQUEUE(&ifp->if_snd, m0);
  848                                 m_freem(m0);
  849                                 continue;
  850                         }
  851                         /*
  852                          * Short on resources, just stop for now.
  853                          */
  854                         break;
  855                 }
  856 
  857                 IFQ_DEQUEUE(&ifp->if_snd, m0);
  858 
  859                 /*
  860                  * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
  861                  */
  862 
  863                 /* Sync the DMA map. */
  864                 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
  865                     BUS_DMASYNC_PREWRITE);
  866 
  867                 /* Initialize the fragment list. */
  868                 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) {
  869                         tfd->tfd_frags[seg].frag_word0 =
  870                             htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) |
  871                             FRAG_LEN(dmamap->dm_segs[seg].ds_len));
  872                         totlen += dmamap->dm_segs[seg].ds_len;
  873                 }
  874 
  875 #ifdef STGE_EVENT_COUNTERS
  876                 switch (dmamap->dm_nsegs) {
  877                 case 1:
  878                         STGE_EVCNT_INCR(&sc->sc_ev_txseg1);
  879                         break;
  880                 case 2:
  881                         STGE_EVCNT_INCR(&sc->sc_ev_txseg2);
  882                         break;
  883                 case 3:
  884                         STGE_EVCNT_INCR(&sc->sc_ev_txseg3);
  885                         break;
  886                 case 4:
  887                         STGE_EVCNT_INCR(&sc->sc_ev_txseg4);
  888                         break;
  889                 case 5:
  890                         STGE_EVCNT_INCR(&sc->sc_ev_txseg5);
  891                         break;
  892                 default:
  893                         STGE_EVCNT_INCR(&sc->sc_ev_txsegmore);
  894                         break;
  895                 }
  896 #endif /* STGE_EVENT_COUNTERS */
  897 
  898                 /*
  899                  * Initialize checksumming flags in the descriptor.
  900                  * Byte-swap constants so the compiler can optimize.
  901                  */
  902                 csum_flags = 0;
  903                 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
  904                         STGE_EVCNT_INCR(&sc->sc_ev_txipsum);
  905                         csum_flags |= htole64(TFD_IPChecksumEnable);
  906                 }
  907 
  908                 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
  909                         STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum);
  910                         csum_flags |= htole64(TFD_TCPChecksumEnable);
  911                 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) {
  912                         STGE_EVCNT_INCR(&sc->sc_ev_txudpsum);
  913                         csum_flags |= htole64(TFD_UDPChecksumEnable);
  914                 }
  915 
  916                 /*
  917                  * Initialize the descriptor and give it to the chip.
  918                  * Check to see if we have a VLAN tag to insert.
  919                  */
  920 
  921                 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) |
  922                     TFD_FragCount(seg) | csum_flags |
  923                     (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ?
  924                         TFD_TxDMAIndicate : 0);
  925                 if (mtag) {
  926 #if     0
  927                         struct ether_header *eh =
  928                             mtod(m0, struct ether_header *);
  929                         u_int16_t etype = ntohs(eh->ether_type);
  930                         printf("%s: xmit (tag %d) etype %x\n",
  931                            ifp->if_xname, *mtod(n, int *), etype);
  932 #endif
  933                         tfc |= TFD_VLANTagInsert |
  934 #ifdef  STGE_VLAN_CFI
  935                             TFD_CFI |
  936 #endif
  937                             TFD_VID((*(u_int *)(mtag + 1)));
  938                 }
  939                 tfd->tfd_control = htole64(tfc);
  940 
  941                 /* Sync the descriptor. */
  942                 STGE_CDTXSYNC(sc, nexttx,
  943                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  944 
  945                 /*
  946                  * Kick the transmit DMA logic.
  947                  */
  948                 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl,
  949                     sc->sc_DMACtrl | DMAC_TxDMAPollNow);
  950 
  951                 /*
  952                  * Store a pointer to the packet so we can free it later.
  953                  */
  954                 ds->ds_mbuf = m0;
  955 
  956                 /* Advance the tx pointer. */
  957                 sc->sc_txpending++;
  958                 sc->sc_txlast = nexttx;
  959 
  960 #if NBPFILTER > 0
  961                 /*
  962                  * Pass the packet to any BPF listeners.
  963                  */
  964                 if (ifp->if_bpf)
  965                         bpf_mtap(ifp->if_bpf, m0);
  966 #endif /* NBPFILTER > 0 */
  967         }
  968 
  969         if (sc->sc_txpending == (STGE_NTXDESC - 1)) {
  970                 /* No more slots left; notify upper layer. */
  971                 ifp->if_flags |= IFF_OACTIVE;
  972         }
  973 
  974         if (sc->sc_txpending != opending) {
  975                 /*
  976                  * We enqueued packets.  If the transmitter was idle,
  977                  * reset the txdirty pointer.
  978                  */
  979                 if (opending == 0)
  980                         sc->sc_txdirty = firsttx;
  981 
  982                 /* Set a watchdog timer in case the chip flakes out. */
  983                 ifp->if_timer = 5;
  984         }
  985 }
  986 
  987 /*
  988  * stge_watchdog:       [ifnet interface function]
  989  *
  990  *      Watchdog timer handler.
  991  */
  992 void
  993 stge_watchdog(struct ifnet *ifp)
  994 {
  995         struct stge_softc *sc = ifp->if_softc;
  996 
  997         /*
  998          * Sweep up first, since we don't interrupt every frame.
  999          */
 1000         stge_txintr(sc);
 1001         if (sc->sc_txpending != 0) {
 1002                 printf("%s: device timeout\n", sc->sc_dev.dv_xname);
 1003                 ifp->if_oerrors++;
 1004 
 1005                 (void) stge_init(ifp);
 1006 
 1007                 /* Try to get more packets going. */
 1008                 stge_start(ifp);
 1009         }
 1010 }
 1011 
 1012 /*
 1013  * stge_ioctl:          [ifnet interface function]
 1014  *
 1015  *      Handle control requests from the operator.
 1016  */
 1017 int
 1018 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 1019 {
 1020         struct stge_softc *sc = ifp->if_softc;
 1021         struct ifreq *ifr = (struct ifreq *)data;
 1022         int s, error;
 1023 
 1024         s = splnet();
 1025 
 1026         switch (cmd) {
 1027         case SIOCSIFMEDIA:
 1028         case SIOCGIFMEDIA:
 1029                 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
 1030                 break;
 1031 
 1032         default:
 1033                 error = ether_ioctl(ifp, cmd, data);
 1034                 if (error == ENETRESET) { 
 1035                         /*
 1036                          * Multicast list has changed; set the hardware filter
 1037                          * accordingly.
 1038                          */
 1039                         stge_set_filter(sc);
 1040                         error = 0;
 1041                 }
 1042                 break;
 1043         }
 1044 
 1045         /* Try to get more packets going. */
 1046         stge_start(ifp);
 1047 
 1048         splx(s);
 1049         return (error);
 1050 }
 1051 
 1052 /*
 1053  * stge_intr:
 1054  *
 1055  *      Interrupt service routine.
 1056  */
 1057 int
 1058 stge_intr(void *arg)
 1059 {
 1060         struct stge_softc *sc = arg;
 1061         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 1062         uint32_t txstat;
 1063         int wantinit;
 1064         uint16_t isr;
 1065 
 1066         if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) &
 1067              IS_InterruptStatus) == 0)
 1068                 return (0);
 1069 
 1070         for (wantinit = 0; wantinit == 0;) {
 1071                 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck);
 1072                 if ((isr & sc->sc_IntEnable) == 0)
 1073                         break;
 1074 
 1075                 /* Host interface errors. */
 1076                 if (isr & IS_HostError) {
 1077                         printf("%s: Host interface error\n",
 1078                             sc->sc_dev.dv_xname);
 1079                         wantinit = 1;
 1080                         continue;
 1081                 }
 1082 
 1083                 /* Receive interrupts. */
 1084                 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) {
 1085                         STGE_EVCNT_INCR(&sc->sc_ev_rxintr);
 1086                         stge_rxintr(sc);
 1087                         if (isr & IS_RFDListEnd) {
 1088                                 printf("%s: receive ring overflow\n",
 1089                                     sc->sc_dev.dv_xname);
 1090                                 /*
 1091                                  * XXX Should try to recover from this
 1092                                  * XXX more gracefully.
 1093                                  */
 1094                                 wantinit = 1;
 1095                         }
 1096                 }
 1097 
 1098                 /* Transmit interrupts. */
 1099                 if (isr & (IS_TxDMAComplete|IS_TxComplete)) {
 1100 #ifdef STGE_EVENT_COUNTERS
 1101                         if (isr & IS_TxDMAComplete)
 1102                                 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr);
 1103 #endif
 1104                         stge_txintr(sc);
 1105                 }
 1106 
 1107                 /* Statistics overflow. */
 1108                 if (isr & IS_UpdateStats)
 1109                         stge_stats_update(sc);
 1110 
 1111                 /* Transmission errors. */
 1112                 if (isr & IS_TxComplete) {
 1113                         STGE_EVCNT_INCR(&sc->sc_ev_txindintr);
 1114                         for (;;) {
 1115                                 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh,
 1116                                     STGE_TxStatus);
 1117                                 if ((txstat & TS_TxComplete) == 0)
 1118                                         break;
 1119                                 if (txstat & TS_TxUnderrun) {
 1120                                         sc->sc_txthresh++;
 1121                                         if (sc->sc_txthresh > 0x0fff)
 1122                                                 sc->sc_txthresh = 0x0fff;
 1123                                         printf("%s: transmit underrun, new "
 1124                                             "threshold: %d bytes\n",
 1125                                             sc->sc_dev.dv_xname,
 1126                                             sc->sc_txthresh << 5);
 1127                                 }
 1128                                 if (txstat & TS_MaxCollisions)
 1129                                         printf("%s: excessive collisions\n",
 1130                                             sc->sc_dev.dv_xname);
 1131                         }
 1132                         wantinit = 1;
 1133                 }
 1134 
 1135         }
 1136 
 1137         if (wantinit)
 1138                 stge_init(ifp);
 1139 
 1140         bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable,
 1141             sc->sc_IntEnable);
 1142 
 1143         /* Try to get more packets going. */
 1144         stge_start(ifp);
 1145 
 1146         return (1);
 1147 }
 1148 
 1149 /*
 1150  * stge_txintr:
 1151  *
 1152  *      Helper; handle transmit interrupts.
 1153  */
 1154 void
 1155 stge_txintr(struct stge_softc *sc)
 1156 {
 1157         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 1158         struct stge_descsoft *ds;
 1159         uint64_t control;
 1160         int i;
 1161 
 1162         ifp->if_flags &= ~IFF_OACTIVE;
 1163 
 1164         /*
 1165          * Go through our Tx list and free mbufs for those
 1166          * frames which have been transmitted.
 1167          */
 1168         for (i = sc->sc_txdirty; sc->sc_txpending != 0;
 1169              i = STGE_NEXTTX(i), sc->sc_txpending--) {
 1170                 ds = &sc->sc_txsoft[i];
 1171 
 1172                 STGE_CDTXSYNC(sc, i,
 1173                     BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 1174 
 1175                 control = le64toh(sc->sc_txdescs[i].tfd_control);
 1176                 if ((control & TFD_TFDDone) == 0)
 1177                         break;
 1178 
 1179                 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
 1180                     0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 1181                 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 1182                 m_freem(ds->ds_mbuf);
 1183                 ds->ds_mbuf = NULL;
 1184         }
 1185 
 1186         /* Update the dirty transmit buffer pointer. */
 1187         sc->sc_txdirty = i;
 1188 
 1189         /*
 1190          * If there are no more pending transmissions, cancel the watchdog
 1191          * timer.
 1192          */
 1193         if (sc->sc_txpending == 0)
 1194                 ifp->if_timer = 0;
 1195 }
 1196 
 1197 /*
 1198  * stge_rxintr:
 1199  *
 1200  *      Helper; handle receive interrupts.
 1201  */
 1202 void
 1203 stge_rxintr(struct stge_softc *sc)
 1204 {
 1205         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 1206         struct stge_descsoft *ds;
 1207         struct mbuf *m, *tailm;
 1208         uint64_t status;
 1209         int i, len;
 1210 
 1211         for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) {
 1212                 ds = &sc->sc_rxsoft[i];
 1213 
 1214                 STGE_CDRXSYNC(sc, i,
 1215                     BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 1216 
 1217                 status = le64toh(sc->sc_rxdescs[i].rfd_status);
 1218 
 1219                 if ((status & RFD_RFDDone) == 0)
 1220                         break;
 1221 
 1222                 if (__predict_false(sc->sc_rxdiscard)) {
 1223                         STGE_INIT_RXDESC(sc, i);
 1224                         if (status & RFD_FrameEnd) {
 1225                                 /* Reset our state. */
 1226                                 sc->sc_rxdiscard = 0;
 1227                         }
 1228                         continue;
 1229                 }
 1230 
 1231                 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 1232                     ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 1233 
 1234                 m = ds->ds_mbuf;
 1235 
 1236                 /*
 1237                  * Add a new receive buffer to the ring.
 1238                  */
 1239                 if (stge_add_rxbuf(sc, i) != 0) {
 1240                         /*
 1241                          * Failed, throw away what we've done so
 1242                          * far, and discard the rest of the packet.
 1243                          */
 1244                         ifp->if_ierrors++;
 1245                         bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 1246                             ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 1247                         STGE_INIT_RXDESC(sc, i);
 1248                         if ((status & RFD_FrameEnd) == 0)
 1249                                 sc->sc_rxdiscard = 1;
 1250                         if (sc->sc_rxhead != NULL)
 1251                                 m_freem(sc->sc_rxhead);
 1252                         STGE_RXCHAIN_RESET(sc);
 1253                         continue;
 1254                 }
 1255 
 1256 #ifdef DIAGNOSTIC
 1257                 if (status & RFD_FrameStart) {
 1258                         KASSERT(sc->sc_rxhead == NULL);
 1259                         KASSERT(sc->sc_rxtailp == &sc->sc_rxhead);
 1260                 }
 1261 #endif
 1262 
 1263                 STGE_RXCHAIN_LINK(sc, m);
 1264 
 1265                 /*
 1266                  * If this is not the end of the packet, keep
 1267                  * looking.
 1268                  */
 1269                 if ((status & RFD_FrameEnd) == 0) {
 1270                         sc->sc_rxlen += m->m_len;
 1271                         continue;
 1272                 }
 1273 
 1274                 /*
 1275                  * Okay, we have the entire packet now...
 1276                  */
 1277                 *sc->sc_rxtailp = NULL;
 1278                 m = sc->sc_rxhead;
 1279                 tailm = sc->sc_rxtail;
 1280 
 1281                 STGE_RXCHAIN_RESET(sc);
 1282 
 1283                 /*
 1284                  * If the packet had an error, drop it.  Note we
 1285                  * count the error later in the periodic stats update.
 1286                  */
 1287                 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
 1288                               RFD_RxAlignmentError | RFD_RxFCSError |
 1289                               RFD_RxLengthError)) {
 1290                         m_freem(m);
 1291                         continue;
 1292                 }
 1293 
 1294                 /*
 1295                  * No errors.
 1296                  *
 1297                  * Note we have configured the chip to not include
 1298                  * the CRC at the end of the packet.
 1299                  */
 1300                 len = RFD_RxDMAFrameLen(status);
 1301                 tailm->m_len = len - sc->sc_rxlen;
 1302 
 1303                 /*
 1304                  * If the packet is small enough to fit in a
 1305                  * single header mbuf, allocate one and copy
 1306                  * the data into it.  This greatly reduces
 1307                  * memory consumption when we receive lots
 1308                  * of small packets.
 1309                  */
 1310                 if (stge_copy_small != 0 && len <= (MHLEN - 2)) {
 1311                         struct mbuf *nm;
 1312                         MGETHDR(nm, M_DONTWAIT, MT_DATA);
 1313                         if (nm == NULL) {
 1314                                 ifp->if_ierrors++;
 1315                                 m_freem(m);
 1316                                 continue;
 1317                         }
 1318                         nm->m_data += 2;
 1319                         nm->m_pkthdr.len = nm->m_len = len;
 1320                         m_copydata(m, 0, len, mtod(nm, caddr_t));
 1321                         m_freem(m);
 1322                         m = nm;
 1323                 }
 1324 
 1325                 /*
 1326                  * Set the incoming checksum information for the packet.
 1327                  */
 1328                 if (status & RFD_IPDetected) {
 1329                         STGE_EVCNT_INCR(&sc->sc_ev_rxipsum);
 1330                         m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
 1331                         if (status & RFD_IPError)
 1332                                 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
 1333                         if (status & RFD_TCPDetected) {
 1334                                 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum);
 1335                                 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
 1336                                 if (status & RFD_TCPError)
 1337                                         m->m_pkthdr.csum_flags |=
 1338                                             M_CSUM_TCP_UDP_BAD;
 1339                         } else if (status & RFD_UDPDetected) {
 1340                                 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum);
 1341                                 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
 1342                                 if (status & RFD_UDPError)
 1343                                         m->m_pkthdr.csum_flags |=
 1344                                             M_CSUM_TCP_UDP_BAD;
 1345                         }
 1346                 }
 1347 
 1348                 m->m_pkthdr.rcvif = ifp;
 1349                 m->m_pkthdr.len = len;
 1350 
 1351 #if NBPFILTER > 0
 1352                 /*
 1353                  * Pass this up to any BPF listeners, but only
 1354                  * pass if up the stack if it's for us.
 1355                  */
 1356                 if (ifp->if_bpf)
 1357                         bpf_mtap(ifp->if_bpf, m);
 1358 #endif /* NBPFILTER > 0 */
 1359 #ifdef  STGE_VLAN_UNTAG
 1360                 /*
 1361                  * Check for VLAN tagged packets
 1362                  */
 1363                 if (status & RFD_VLANDetected) {
 1364                         struct m_tag *mtag =
 1365                             m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT);
 1366                         if (mtag == NULL) {
 1367                                 printf("%s: no mbuf for VLAN tag\n",
 1368                                     ifp->if_xname);
 1369                                 m_freem(m);
 1370                                 continue;
 1371                         }
 1372                         *(u_int *)(mtag + 1) = RFD_TCI(status);
 1373                         m_tag_prepend(m, mtag);
 1374                 }
 1375 #endif
 1376 #if     0
 1377                 if (status & RFD_VLANDetected) {
 1378                         struct ether_header *eh;
 1379                         u_int16_t etype;
 1380 
 1381                         eh = mtod(m, struct ether_header *);
 1382                         etype = ntohs(eh->ether_type);
 1383                         printf("%s: VLANtag detected (TCI %d) etype %x\n",
 1384                             ifp->if_xname, (u_int16_t) RFD_TCI(status),
 1385                             etype);
 1386                 }
 1387 #endif
 1388                 /* Pass it on. */
 1389                 (*ifp->if_input)(ifp, m);
 1390         }
 1391 
 1392         /* Update the receive pointer. */
 1393         sc->sc_rxptr = i;
 1394 }
 1395 
 1396 /*
 1397  * stge_tick:
 1398  *
 1399  *      One second timer, used to tick the MII.
 1400  */
 1401 void
 1402 stge_tick(void *arg)
 1403 {
 1404         struct stge_softc *sc = arg;
 1405         int s;
 1406 
 1407         s = splnet();
 1408         mii_tick(&sc->sc_mii);
 1409         stge_stats_update(sc);
 1410         splx(s);
 1411 
 1412         callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
 1413 }
 1414 
 1415 /*
 1416  * stge_stats_update:
 1417  *
 1418  *      Read the TC9021 statistics counters.
 1419  */
 1420 void
 1421 stge_stats_update(struct stge_softc *sc)
 1422 {
 1423         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 1424         bus_space_tag_t st = sc->sc_st;
 1425         bus_space_handle_t sh = sc->sc_sh;
 1426 
 1427         (void) bus_space_read_4(st, sh, STGE_OctetRcvOk);
 1428 
 1429         ifp->if_ipackets +=
 1430             bus_space_read_4(st, sh, STGE_FramesRcvdOk);
 1431 
 1432         ifp->if_ierrors +=
 1433             (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors);
 1434 
 1435         (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk);
 1436 
 1437         ifp->if_opackets +=
 1438             bus_space_read_4(st, sh, STGE_FramesXmtdOk);
 1439 
 1440         ifp->if_collisions +=
 1441             bus_space_read_4(st, sh, STGE_LateCollisions) +
 1442             bus_space_read_4(st, sh, STGE_MultiColFrames) +
 1443             bus_space_read_4(st, sh, STGE_SingleColFrames);
 1444 
 1445         ifp->if_oerrors +=
 1446             (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) +
 1447             (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal);
 1448 }
 1449 
 1450 /*
 1451  * stge_reset:
 1452  *
 1453  *      Perform a soft reset on the TC9021.
 1454  */
 1455 void
 1456 stge_reset(struct stge_softc *sc)
 1457 {
 1458         uint32_t ac;
 1459         int i;
 1460 
 1461         ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl);
 1462 
 1463         /*
 1464          * Only assert RstOut if we're fiber.  We need GMII clocks
 1465          * to be present in order for the reset to complete on fiber
 1466          * cards.
 1467          */
 1468         bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl,
 1469             ac | AC_GlobalReset | AC_RxReset | AC_TxReset |
 1470             AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
 1471             (sc->sc_usefiber ? AC_RstOut : 0));
 1472 
 1473         delay(50000);
 1474 
 1475         for (i = 0; i < STGE_TIMEOUT; i++) {
 1476                 delay(5000);
 1477                 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) &
 1478                      AC_ResetBusy) == 0)
 1479                         break;
 1480         }
 1481 
 1482         if (i == STGE_TIMEOUT)
 1483                 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
 1484 
 1485         delay(1000);
 1486 }
 1487 
 1488 /*
 1489  * stge_init:           [ ifnet interface function ]
 1490  *
 1491  *      Initialize the interface.  Must be called at splnet().
 1492  */
 1493 int
 1494 stge_init(struct ifnet *ifp)
 1495 {
 1496         struct stge_softc *sc = ifp->if_softc;
 1497         bus_space_tag_t st = sc->sc_st;
 1498         bus_space_handle_t sh = sc->sc_sh;
 1499         struct stge_descsoft *ds;
 1500         int i, error = 0;
 1501 
 1502         /*
 1503          * Cancel any pending I/O.
 1504          */
 1505         stge_stop(ifp, 0);
 1506 
 1507         /*
 1508          * Reset the chip to a known state.
 1509          */
 1510         stge_reset(sc);
 1511 
 1512         /*
 1513          * Initialize the transmit descriptor ring.
 1514          */
 1515         memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
 1516         for (i = 0; i < STGE_NTXDESC; i++) {
 1517                 sc->sc_txdescs[i].tfd_next =
 1518                     (uint64_t) STGE_CDTXADDR(sc, STGE_NEXTTX(i));
 1519                 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone);
 1520         }
 1521         sc->sc_txpending = 0;
 1522         sc->sc_txdirty = 0;
 1523         sc->sc_txlast = STGE_NTXDESC - 1;
 1524 
 1525         /*
 1526          * Initialize the receive descriptor and receive job
 1527          * descriptor rings.
 1528          */
 1529         for (i = 0; i < STGE_NRXDESC; i++) {
 1530                 ds = &sc->sc_rxsoft[i];
 1531                 if (ds->ds_mbuf == NULL) {
 1532                         if ((error = stge_add_rxbuf(sc, i)) != 0) {
 1533                                 printf("%s: unable to allocate or map rx "
 1534                                     "buffer %d, error = %d\n",
 1535                                     sc->sc_dev.dv_xname, i, error);
 1536                                 /*
 1537                                  * XXX Should attempt to run with fewer receive
 1538                                  * XXX buffers instead of just failing.
 1539                                  */
 1540                                 stge_rxdrain(sc);
 1541                                 goto out;
 1542                         }
 1543                 } else
 1544                         STGE_INIT_RXDESC(sc, i);
 1545         }
 1546         sc->sc_rxptr = 0;
 1547         sc->sc_rxdiscard = 0;
 1548         STGE_RXCHAIN_RESET(sc);
 1549 
 1550         /* Set the station address. */
 1551         bus_space_write_2(st, sh, STGE_StationAddress0,
 1552             LLADDR(ifp->if_sadl)[0] | (LLADDR(ifp->if_sadl)[1] << 8));
 1553         bus_space_write_2(st, sh, STGE_StationAddress1,
 1554             LLADDR(ifp->if_sadl)[2] | (LLADDR(ifp->if_sadl)[3] << 8));
 1555         bus_space_write_2(st, sh, STGE_StationAddress2,
 1556             LLADDR(ifp->if_sadl)[4] | (LLADDR(ifp->if_sadl)[5] << 8));
 1557 
 1558         /*
 1559          * Set the statistics masks.  Disable all the RMON stats,
 1560          * and disable selected stats in the non-RMON stats registers.
 1561          */
 1562         bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff);
 1563         bus_space_write_4(st, sh, STGE_StatisticsMask,
 1564             (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
 1565             (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
 1566             (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
 1567             (1U << 21));
 1568 
 1569         /* Set up the receive filter. */
 1570         stge_set_filter(sc);
 1571 
 1572         /*
 1573          * Give the transmit and receive ring to the chip.
 1574          */
 1575         bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */
 1576         bus_space_write_4(st, sh, STGE_TFDListPtrLo,
 1577             STGE_CDTXADDR(sc, sc->sc_txdirty));
 1578 
 1579         bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */
 1580         bus_space_write_4(st, sh, STGE_RFDListPtrLo,
 1581             STGE_CDRXADDR(sc, sc->sc_rxptr));
 1582 
 1583         /*
 1584          * Initialize the Tx auto-poll period.  It's OK to make this number
 1585          * large (255 is the max, but we use 127) -- we explicitly kick the
 1586          * transmit engine when there's actually a packet.
 1587          */
 1588         bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127);
 1589 
 1590         /* ..and the Rx auto-poll period. */
 1591         bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64);
 1592 
 1593         /* Initialize the Tx start threshold. */
 1594         bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh);
 1595 
 1596         /*
 1597          * Initialize the Rx DMA interrupt control register.  We
 1598          * request an interrupt after every incoming packet, but
 1599          * defer it for 32us (64 * 512 ns).  When the number of
 1600          * interrupts pending reaches 8, we stop deferring the
 1601          * interrupt, and signal it immediately.
 1602          */
 1603         bus_space_write_4(st, sh, STGE_RxDMAIntCtrl,
 1604             RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512));
 1605 
 1606         /*
 1607          * Initialize the interrupt mask.
 1608          */
 1609         sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats |
 1610             IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
 1611         bus_space_write_2(st, sh, STGE_IntStatus, 0xffff);
 1612         bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable);
 1613 
 1614         /*
 1615          * Configure the DMA engine.
 1616          * XXX Should auto-tune TxBurstLimit.
 1617          */
 1618         bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl |
 1619             DMAC_TxBurstLimit(3));
 1620 
 1621         /*
 1622          * Send a PAUSE frame when we reach 29,696 bytes in the Rx
 1623          * FIFO, and send an un-PAUSE frame when the FIFO is totally
 1624          * empty again.
 1625          */
 1626         bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16);
 1627         bus_space_write_2(st, sh, STGE_FlowOffThresh, 0);
 1628 
 1629         /*
 1630          * Set the maximum frame size.
 1631          */
 1632         bus_space_write_2(st, sh, STGE_MaxFrameSize,
 1633             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
 1634             ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
 1635              ETHER_VLAN_ENCAP_LEN : 0));
 1636 
 1637         /*
 1638          * Initialize MacCtrl -- do it before setting the media,
 1639          * as setting the media will actually program the register.
 1640          *
 1641          * Note: We have to poke the IFS value before poking
 1642          * anything else.
 1643          */
 1644         sc->sc_MACCtrl = MC_IFSSelect(0);
 1645         bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl);
 1646         sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
 1647 #ifdef  STGE_VLAN_UNTAG
 1648         sc->sc_MACCtrl |= MC_AutoVLANuntagging;
 1649 #endif
 1650 
 1651         if (sc->sc_rev >= 6) {          /* >= B.2 */
 1652                 /* Multi-frag frame bug work-around. */
 1653                 bus_space_write_2(st, sh, STGE_DebugCtrl,
 1654                     bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200);
 1655 
 1656                 /* Tx Poll Now bug work-around. */
 1657                 bus_space_write_2(st, sh, STGE_DebugCtrl,
 1658                     bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010);
 1659         }
 1660 
 1661         /*
 1662          * Set the current media.
 1663          */
 1664         mii_mediachg(&sc->sc_mii);
 1665 
 1666         /*
 1667          * Start the one second MII clock.
 1668          */
 1669         callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
 1670 
 1671         /*
 1672          * ...all done!
 1673          */
 1674         ifp->if_flags |= IFF_RUNNING;
 1675         ifp->if_flags &= ~IFF_OACTIVE;
 1676 
 1677  out:
 1678         if (error)
 1679                 printf("%s: interface not running\n", sc->sc_dev.dv_xname);
 1680         return (error);
 1681 }
 1682 
 1683 /*
 1684  * stge_drain:
 1685  *
 1686  *      Drain the receive queue.
 1687  */
 1688 void
 1689 stge_rxdrain(struct stge_softc *sc)
 1690 {
 1691         struct stge_descsoft *ds;
 1692         int i;
 1693 
 1694         for (i = 0; i < STGE_NRXDESC; i++) {
 1695                 ds = &sc->sc_rxsoft[i];
 1696                 if (ds->ds_mbuf != NULL) {
 1697                         bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 1698                         ds->ds_mbuf->m_next = NULL;
 1699                         m_freem(ds->ds_mbuf);
 1700                         ds->ds_mbuf = NULL;
 1701                 }
 1702         }
 1703 }
 1704 
 1705 /*
 1706  * stge_stop:           [ ifnet interface function ]
 1707  *
 1708  *      Stop transmission on the interface.
 1709  */
 1710 void
 1711 stge_stop(struct ifnet *ifp, int disable)
 1712 {
 1713         struct stge_softc *sc = ifp->if_softc;
 1714         struct stge_descsoft *ds;
 1715         int i;
 1716 
 1717         /*
 1718          * Stop the one second clock.
 1719          */
 1720         callout_stop(&sc->sc_tick_ch);
 1721 
 1722         /* Down the MII. */
 1723         mii_down(&sc->sc_mii);
 1724 
 1725         /*
 1726          * Disable interrupts.
 1727          */
 1728         bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0);
 1729 
 1730         /*
 1731          * Stop receiver, transmitter, and stats update.
 1732          */
 1733         bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl,
 1734             MC_StatisticsDisable | MC_TxDisable | MC_RxDisable);
 1735 
 1736         /*
 1737          * Stop the transmit and receive DMA.
 1738          */
 1739         stge_dma_wait(sc);
 1740         bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0);
 1741         bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0);
 1742         bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0);
 1743         bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0);
 1744 
 1745         /*
 1746          * Release any queued transmit buffers.
 1747          */
 1748         for (i = 0; i < STGE_NTXDESC; i++) {
 1749                 ds = &sc->sc_txsoft[i];
 1750                 if (ds->ds_mbuf != NULL) {
 1751                         bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 1752                         m_freem(ds->ds_mbuf);
 1753                         ds->ds_mbuf = NULL;
 1754                 }
 1755         }
 1756 
 1757         if (disable)
 1758                 stge_rxdrain(sc);
 1759 
 1760         /*
 1761          * Mark the interface down and cancel the watchdog timer.
 1762          */
 1763         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 1764         ifp->if_timer = 0;
 1765 }
 1766 
 1767 #if 0
 1768 static int
 1769 stge_eeprom_wait(struct stge_softc *sc)
 1770 {
 1771         int i;
 1772 
 1773         for (i = 0; i < STGE_TIMEOUT; i++) {
 1774                 delay(1000);
 1775                 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) &
 1776                      EC_EepromBusy) == 0)
 1777                         return (0);
 1778         }
 1779         return (1);
 1780 }
 1781 
 1782 /*
 1783  * stge_read_eeprom:
 1784  *
 1785  *      Read data from the serial EEPROM.
 1786  */
 1787 void
 1788 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
 1789 {
 1790 
 1791         if (stge_eeprom_wait(sc))
 1792                 printf("%s: EEPROM failed to come ready\n",
 1793                     sc->sc_dev.dv_xname);
 1794 
 1795         bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl,
 1796             EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
 1797         if (stge_eeprom_wait(sc))
 1798                 printf("%s: EEPROM read timed out\n",
 1799                     sc->sc_dev.dv_xname);
 1800         *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData);
 1801 }
 1802 #endif /* 0 */
 1803 
 1804 /*
 1805  * stge_add_rxbuf:
 1806  *
 1807  *      Add a receive buffer to the indicated descriptor.
 1808  */
 1809 int
 1810 stge_add_rxbuf(struct stge_softc *sc, int idx)
 1811 {
 1812         struct stge_descsoft *ds = &sc->sc_rxsoft[idx];
 1813         struct mbuf *m;
 1814         int error;
 1815 
 1816         MGETHDR(m, M_DONTWAIT, MT_DATA);
 1817         if (m == NULL)  
 1818                 return (ENOBUFS);
 1819 
 1820         MCLGET(m, M_DONTWAIT);
 1821         if ((m->m_flags & M_EXT) == 0) {
 1822                 m_freem(m);
 1823                 return (ENOBUFS);
 1824         }
 1825 
 1826         m->m_data = m->m_ext.ext_buf + 2;
 1827         m->m_len = MCLBYTES - 2;
 1828 
 1829         if (ds->ds_mbuf != NULL)
 1830                 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 1831 
 1832         ds->ds_mbuf = m;
 1833 
 1834         error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
 1835             m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
 1836         if (error) {
 1837                 printf("%s: can't load rx DMA map %d, error = %d\n",
 1838                     sc->sc_dev.dv_xname, idx, error);
 1839                 panic("stge_add_rxbuf");        /* XXX */
 1840         }
 1841 
 1842         bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 1843             ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 1844 
 1845         STGE_INIT_RXDESC(sc, idx);
 1846 
 1847         return (0);
 1848 }
 1849 
 1850 /*
 1851  * stge_set_filter:
 1852  *
 1853  *      Set up the receive filter.
 1854  */
 1855 void
 1856 stge_set_filter(struct stge_softc *sc)
 1857 {
 1858         struct ethercom *ec = &sc->sc_ethercom;
 1859         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 1860         struct ether_multi *enm;
 1861         struct ether_multistep step;
 1862         uint32_t crc;
 1863         uint32_t mchash[2];
 1864 
 1865         sc->sc_ReceiveMode = RM_ReceiveUnicast;
 1866         if (ifp->if_flags & IFF_BROADCAST)
 1867                 sc->sc_ReceiveMode |= RM_ReceiveBroadcast;
 1868 
 1869 #ifdef  STGE_CU_BUG
 1870         /*
 1871          * Some cards (Sundance TI, copper) only seem to work
 1872          * right now if we put them into promiscuous mode. It
 1873          * probably is the Marvell PHY stuff that isn't quite
 1874          * right.
 1875          */
 1876         ifp->if_flags |= IFF_PROMISC;
 1877 #endif
 1878 
 1879         if (ifp->if_flags & IFF_PROMISC) {
 1880                 sc->sc_ReceiveMode |= RM_ReceiveAllFrames;
 1881                 goto allmulti;
 1882         }
 1883 
 1884         /*
 1885          * Set up the multicast address filter by passing all multicast
 1886          * addresses through a CRC generator, and then using the low-order
 1887          * 6 bits as an index into the 64 bit multicast hash table.  The
 1888          * high order bits select the register, while the rest of the bits
 1889          * select the bit within the register.
 1890          */
 1891 
 1892         memset(mchash, 0, sizeof(mchash));
 1893 
 1894         ETHER_FIRST_MULTI(step, ec, enm);
 1895         if (enm == NULL)
 1896                 goto done;
 1897 
 1898         while (enm != NULL) {
 1899                 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1900                         /*
 1901                          * We must listen to a range of multicast addresses.
 1902                          * For now, just accept all multicasts, rather than
 1903                          * trying to set only those filter bits needed to match
 1904                          * the range.  (At this time, the only use of address
 1905                          * ranges is for IP multicast routing, for which the
 1906                          * range is big enough to require all bits set.)
 1907                          */
 1908                         goto allmulti;
 1909                 }
 1910 
 1911                 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
 1912 
 1913                 /* Just want the 6 least significant bits. */
 1914                 crc &= 0x3f;
 1915 
 1916                 /* Set the corresponding bit in the hash table. */
 1917                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
 1918 
 1919                 ETHER_NEXT_MULTI(step, enm);
 1920         }
 1921 
 1922         sc->sc_ReceiveMode |= RM_ReceiveMulticastHash;
 1923 
 1924         ifp->if_flags &= ~IFF_ALLMULTI;
 1925         goto done;
 1926 
 1927  allmulti:
 1928         ifp->if_flags |= IFF_ALLMULTI;
 1929         sc->sc_ReceiveMode |= RM_ReceiveMulticast;
 1930 
 1931  done:
 1932         if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
 1933                 /*
 1934                  * Program the multicast hash table.
 1935                  */
 1936                 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0,
 1937                     mchash[0]);
 1938                 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1,
 1939                     mchash[1]);
 1940         }
 1941 
 1942         bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode,
 1943             sc->sc_ReceiveMode);
 1944 }
 1945 
 1946 /*
 1947  * stge_mii_readreg:    [mii interface function]
 1948  *
 1949  *      Read a PHY register on the MII of the TC9021.
 1950  */
 1951 int
 1952 stge_mii_readreg(struct device *self, int phy, int reg)
 1953 {
 1954 
 1955         return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg));
 1956 }
 1957 
 1958 /*
 1959  * stge_mii_writereg:   [mii interface function]
 1960  *
 1961  *      Write a PHY register on the MII of the TC9021.
 1962  */
 1963 void
 1964 stge_mii_writereg(struct device *self, int phy, int reg, int val)
 1965 {
 1966 
 1967         mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);
 1968 }
 1969 
 1970 /*
 1971  * stge_mii_statchg:    [mii interface function]
 1972  *
 1973  *      Callback from MII layer when media changes.
 1974  */
 1975 void
 1976 stge_mii_statchg(struct device *self)
 1977 {
 1978         struct stge_softc *sc = (struct stge_softc *) self;
 1979 
 1980         if (sc->sc_mii.mii_media_active & IFM_FDX)
 1981                 sc->sc_MACCtrl |= MC_DuplexSelect;
 1982         else
 1983                 sc->sc_MACCtrl &= ~MC_DuplexSelect;
 1984 
 1985         /* XXX 802.1x flow-control? */
 1986 
 1987         bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl);
 1988 }
 1989 
 1990 /*
 1991  * sste_mii_bitbang_read: [mii bit-bang interface function]
 1992  *
 1993  *      Read the MII serial port for the MII bit-bang module.
 1994  */
 1995 uint32_t
 1996 stge_mii_bitbang_read(struct device *self)
 1997 {
 1998         struct stge_softc *sc = (void *) self;
 1999 
 2000         return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl));
 2001 }
 2002 
 2003 /*
 2004  * stge_mii_bitbang_write: [mii big-bang interface function]
 2005  *
 2006  *      Write the MII serial port for the MII bit-bang module.
 2007  */
 2008 void
 2009 stge_mii_bitbang_write(struct device *self, uint32_t val)
 2010 {
 2011         struct stge_softc *sc = (void *) self;
 2012 
 2013         bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl,
 2014             val | sc->sc_PhyCtrl);
 2015 }
 2016 
 2017 /*
 2018  * stge_mediastatus:    [ifmedia interface function]
 2019  *
 2020  *      Get the current interface media status.
 2021  */
 2022 void
 2023 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 2024 {
 2025         struct stge_softc *sc = ifp->if_softc;
 2026 
 2027         mii_pollstat(&sc->sc_mii);
 2028         ifmr->ifm_status = sc->sc_mii.mii_media_status;
 2029         ifmr->ifm_active = sc->sc_mii.mii_media_active;
 2030 }
 2031 
 2032 /*
 2033  * stge_mediachange:    [ifmedia interface function]
 2034  *
 2035  *      Set hardware to newly-selected media.
 2036  */
 2037 int
 2038 stge_mediachange(struct ifnet *ifp)
 2039 {
 2040         struct stge_softc *sc = ifp->if_softc;
 2041 
 2042         if (ifp->if_flags & IFF_UP)
 2043                 mii_mediachg(&sc->sc_mii);
 2044         return (0);
 2045 }

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