FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/ifpci2.c
1 /* $NetBSD: ifpci2.c,v 1.3 2003/10/28 17:01:19 pooka Exp $ */
2 /*
3 * Copyright (c) 1999 Gary Jennejohn. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 * 4. Altered versions must be plainly marked as such, and must not be
18 * misrepresented as being the original software and/or documentation.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 *---------------------------------------------------------------------------
33 * a lot of code was borrowed from i4b_bchan.c and i4b_hscx.c
34 *---------------------------------------------------------------------------
35 *
36 * Fritz!Card PCI driver
37 * ------------------------------------------------
38 *
39 * $Id: ifpci2.c,v 1.3 2003/10/28 17:01:19 pooka Exp $
40 *
41 * last edit-date: [Fri Jan 5 11:38:58 2001]
42 *
43 *---------------------------------------------------------------------------*/
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: ifpci2.c,v 1.3 2003/10/28 17:01:19 pooka Exp $");
47
48
49 #include <sys/param.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/systm.h>
53 #include <sys/mbuf.h>
54
55 #include <machine/bus.h>
56 #include <sys/device.h>
57
58 #include <sys/socket.h>
59 #include <net/if.h>
60
61 #include <sys/callout.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcidevs.h>
66 #include <netisdn/i4b_debug.h>
67 #include <netisdn/i4b_ioctl.h>
68
69 #include <netisdn/i4b_global.h>
70 #include <netisdn/i4b_l2.h>
71 #include <netisdn/i4b_l1l2.h>
72 #include <netisdn/i4b_trace.h>
73 #include <netisdn/i4b_mbuf.h>
74
75 #include <dev/ic/isic_l1.h>
76 #include <dev/ic/isacsx.h>
77 #include <dev/ic/hscx.h>
78
79 #include <dev/pci/isic_pci.h>
80
81 /* PCI config map to use (only one in this driver) */
82 #define FRITZPCI_PORT0_IO_MAPOFF PCI_MAPREG_START+4
83 #define FRITZPCI_PORT0_MEM_MAPOFF PCI_MAPREG_START
84
85 static isdn_link_t *avma1pp2_ret_linktab(void *token, int channel);
86 static void avma1pp2_set_link(void *token, int channel, const struct isdn_l4_driver_functions *l4_driver, void *l4_driver_softc);
87
88 void n_connect_request(struct call_desc *cd);
89 void n_connect_response(struct call_desc *cd, int response, int cause);
90 void n_disconnect_request(struct call_desc *cd, int cause);
91 void n_alert_request(struct call_desc *cd);
92 void n_mgmt_command(struct isdn_l3_driver *drv, int cmd, void *parm);
93
94 extern const struct isdn_layer1_isdnif_driver isic_std_driver;
95
96 const struct isdn_l3_driver_functions
97 ifpci2_l3_driver = {
98 avma1pp2_ret_linktab,
99 avma1pp2_set_link,
100 n_connect_request,
101 n_connect_response,
102 n_disconnect_request,
103 n_alert_request,
104 NULL,
105 NULL,
106 n_mgmt_command
107 };
108
109 struct ifpci_softc {
110 struct isic_softc sc_isic; /* parent class */
111
112 /* PCI-specific goo */
113 void *sc_ih; /* interrupt handler */
114 bus_addr_t sc_base;
115 bus_size_t sc_size;
116 pci_chipset_tag_t sc_pc;
117 };
118
119 /* prototypes */
120 static void avma1pp2_disable(struct isic_softc *);
121 static int isic_hscx_fifo(l1_bchan_state_t *chan, struct isic_softc *sc);
122
123 static int avma1pp2_intr(void*);
124 static void avma1pp2_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size);
125 static void avma1pp2_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size);
126 static void avma1pp2_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data);
127 static u_int8_t avma1pp2_read_reg(struct isic_softc *sc, int what, bus_size_t offs);
128 static void hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc);
129 static void hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc);
130 static void hscx_write_reg(int chan, u_int val, struct isic_softc *sc);
131 static u_char hscx_read_reg(int chan, struct isic_softc *sc);
132 static u_int hscx_read_reg_int(int chan, struct isic_softc *sc);
133 static void avma1pp2_bchannel_stat(isdn_layer1token, int h_chan, bchan_statistics_t *bsp);
134 static void avma1pp2_map_int(struct ifpci_softc *sc, struct pci_attach_args *pa);
135 static void avma1pp2_bchannel_setup(isdn_layer1token, int h_chan, int bprot, int activate);
136 static void avma1pp2_init_linktab(struct isic_softc *);
137 static int ifpci2_match(struct device *parent, struct cfdata *match, void *aux);
138 static void ifpci2_attach(struct device *parent, struct device *self, void *aux);
139 static int ifpci2_detach(struct device *self, int flags);
140 static int ifpci2_activate(struct device *self, enum devact act);
141
142 CFATTACH_DECL(ifritz, sizeof(struct ifpci_softc),
143 ifpci2_match, ifpci2_attach, ifpci2_detach, ifpci2_activate);
144
145 /*---------------------------------------------------------------------------*
146 * AVM PCI Fritz!Card V. 2 special registers
147 *---------------------------------------------------------------------------*/
148
149 /*
150 * AVM PCI Status Latch 0 read only bits
151 */
152 #define ASL_IRQ_ISAC 0x01 /* ISAC interrupt, active high */
153 #define ASL_IRQ_HSCX 0x02 /* HSX interrupt, active high */
154 #define ASL_IRQ_TIMER 0x04 /* Timer interrupt, active high */
155 #define ASL_IRQ_BCHAN ASL_IRQ_HSCX
156 /* actually active high */
157 #define ASL_IRQ_Pending (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
158
159 /*
160 * AVM PCI Status Latch 0 read only bits
161 */
162 #define ASL_TIMERRESET 0x04
163 #define ASL_ENABLE_INT 0x08
164
165 /*
166 * "HSCX" status bits
167 */
168 #define HSCX_STAT_RME 0x01
169 #define HSCX_STAT_RDO 0x10
170 #define HSCX_STAT_CRCVFRRAB 0x0E
171 #define HSCX_STAT_CRCVFR 0x06
172 #define HSCX_STAT_RML_MASK 0x3f00
173
174 /*
175 * "HSCX" interrupt bits
176 */
177 #define HSCX_INT_XPR 0x80
178 #define HSCX_INT_XDU 0x40
179 #define HSCX_INT_RPR 0x20
180 #define HSCX_INT_MASK 0xE0
181
182 /*
183 * "HSCX" command bits
184 */
185 #define HSCX_CMD_XRS 0x80
186 #define HSCX_CMD_XME 0x01
187 #define HSCX_CMD_RRS 0x20
188 #define HSCX_CMD_XML_MASK 0x3f00
189
190 /* "HSCX" mode bits */
191 #define HSCX_MODE_ITF_FLG 0x01
192 #define HSCX_MODE_TRANS 0x02
193
194 /* offsets to various registers in the ASIC, evidently */
195 #define STAT0_OFFSET 0x02
196
197 #define HSCX_FIFO1 0x10
198 #define HSCX_FIFO2 0x18
199
200 #define HSCX_STAT1 0x14
201 #define HSCX_STAT2 0x1c
202
203 #define ISACSX_INDEX 0x04
204 #define ISACSX_DATA 0x08
205
206 /*
207 * Commands and parameters are sent to the "HSCX" as a long, but the
208 * fields are handled as bytes.
209 *
210 * The long contains:
211 * (prot << 16)|(txl << 8)|cmd
212 *
213 * where:
214 * prot = protocol to use
215 * txl = transmit length
216 * cmd = the command to be executed
217 *
218 * The fields are defined as u_char in struct l1_softc.
219 *
220 * Macro to coalesce the byte fields into a u_int
221 */
222 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
223 | (sc->avma1pp_prot << 16))
224
225 /*
226 * to prevent deactivating the "HSCX" when both channels are active we
227 * define an HSCX_ACTIVE flag which is or'd into the channel's state
228 * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
229 * It is set high to allow room for new flags.
230 */
231 #define HSCX_AVMA1PP_ACTIVE 0x1000
232
233 static int
234 ifpci2_match(struct device *parent, struct cfdata *match, void *aux)
235 {
236 struct pci_attach_args *pa = aux;
237
238 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AVM &&
239 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AVM_FRITZ_PCI_V2_ISDN)
240 return 1;
241 return 0;
242 }
243
244 static void
245 ifpci2_attach(struct device *parent, struct device *self, void *aux)
246 {
247 struct ifpci_softc *psc = (void*)self;
248 struct pci_attach_args *pa = aux;
249 struct isic_softc *sc = &psc->sc_isic;
250 struct isdn_l3_driver *drv;
251 u_int v;
252
253 /* announce */
254 printf(": Fritz!PCI V2 card\n");
255
256 /* initialize sc */
257 callout_init(&sc->sc_T3_callout);
258 callout_init(&sc->sc_T4_callout);
259
260 /* setup io mappings */
261 sc->sc_num_mappings = 1;
262 MALLOC_MAPS(sc);
263 sc->sc_maps[0].size = 0;
264 if (pci_mapreg_map(pa, FRITZPCI_PORT0_IO_MAPOFF, PCI_MAPREG_TYPE_IO, 0,
265 &sc->sc_maps[0].t, &sc->sc_maps[0].h, &psc->sc_base, &psc->sc_size) != 0) {
266 printf("%s: can't map card\n", sc->sc_dev.dv_xname);
267 return;
268 }
269
270 /* setup access routines */
271
272 sc->clearirq = NULL;
273 sc->readreg = avma1pp2_read_reg;
274 sc->writereg = avma1pp2_write_reg;
275
276 sc->readfifo = avma1pp2_read_fifo;
277 sc->writefifo = avma1pp2_write_fifo;
278
279
280 /* setup card type */
281
282 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCIV2;
283
284 /* setup IOM bus type */
285
286 sc->sc_bustyp = BUS_TYPE_IOM2;
287
288 /* this is no IPAC based card */
289 sc->sc_ipac = 0;
290 sc->sc_bfifolen = HSCX_FIFO_LEN;
291
292 /* setup interrupt mapping */
293 avma1pp2_map_int(psc, pa);
294
295 /* init the card */
296
297 v = bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, 0);
298 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, 0);
299 DELAY(SEC_DELAY/20); /* 50 ms */
300 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, 1);
301 DELAY(SEC_DELAY/20); /* 50 ms */
302 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, 0);
303 DELAY(SEC_DELAY/20); /* 50 ms */
304
305 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_TIMERRESET);
306 DELAY(SEC_DELAY/100); /* 10 ms */
307 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_ENABLE_INT);
308 DELAY(SEC_DELAY/100); /* 10 ms */
309
310 /* setup i4b infrastructure (have to roll our own here) */
311
312 /* sc->sc_isac_version = ((ISAC_READ(I_RBCH)) >> 5) & 0x03; */
313 printf("%s: ISACSX %s\n", sc->sc_dev.dv_xname, "PSB3186");
314
315 /* init the ISAC */
316 isic_isacsx_init(sc);
317
318 v = ISAC_READ(I_CIR0); /* Leo: reset generates status change */
319
320 /* init the "HSCX" */
321 avma1pp2_bchannel_setup(sc, HSCX_CH_A, BPROT_NONE, 0);
322
323 avma1pp2_bchannel_setup(sc, HSCX_CH_B, BPROT_NONE, 0);
324
325 /* can't use the normal B-Channel stuff */
326 avma1pp2_init_linktab(sc);
327
328 /* set trace level */
329
330 sc->sc_trace = TRACE_OFF;
331
332 sc->sc_state = ISAC_IDLE;
333
334 sc->sc_ibuf = NULL;
335 sc->sc_ib = NULL;
336 sc->sc_ilen = 0;
337
338 sc->sc_obuf = NULL;
339 sc->sc_op = NULL;
340 sc->sc_ol = 0;
341 sc->sc_freeflag = 0;
342
343 sc->sc_obuf2 = NULL;
344 sc->sc_freeflag2 = 0;
345
346 /* init higher protocol layers */
347 drv = isdn_attach_isdnif(sc->sc_dev.dv_xname,
348 "AVM Fritz!PCI V2", &sc->sc_l2, &ifpci2_l3_driver, NBCH_BRI);
349 sc->sc_l3token = drv;
350 sc->sc_l2.driver = &isic_std_driver;
351 sc->sc_l2.l1_token = sc;
352 sc->sc_l2.drv = drv;
353 isdn_layer2_status_ind(&sc->sc_l2, drv, STI_ATTACH, 1);
354 isdn_isdnif_ready(drv->isdnif);
355 }
356
357 static int
358 ifpci2_detach(self, flags)
359 struct device *self;
360 int flags;
361 {
362 struct ifpci_softc *psc = (struct ifpci_softc *)self;
363
364 bus_space_unmap(psc->sc_isic.sc_maps[0].t, psc->sc_isic.sc_maps[0].h, psc->sc_size);
365 bus_space_free(psc->sc_isic.sc_maps[0].t, psc->sc_isic.sc_maps[0].h, psc->sc_size);
366 pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
367
368 return (0);
369 }
370
371 int
372 ifpci2_activate(self, act)
373 struct device *self;
374 enum devact act;
375 {
376 struct ifpci_softc *psc = (struct ifpci_softc *)self;
377 int error = 0, s;
378
379 s = splnet();
380 switch (act) {
381 case DVACT_ACTIVATE:
382 error = EOPNOTSUPP;
383 break;
384
385 case DVACT_DEACTIVATE:
386 psc->sc_isic.sc_intr_valid = ISIC_INTR_DYING;
387 isdn_layer2_status_ind(&psc->sc_isic.sc_l2, psc->sc_isic.sc_l3token, STI_ATTACH, 0);
388 isdn_detach_isdnif(psc->sc_isic.sc_l3token);
389 psc->sc_isic.sc_l3token = NULL;
390 break;
391 }
392 splx(s);
393 return (error);
394 }
395
396 /*---------------------------------------------------------------------------*
397 * AVM read fifo routines
398 *---------------------------------------------------------------------------*/
399
400 static void
401 avma1pp2_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size)
402 {
403 int i;
404
405 switch (what) {
406 case ISIC_WHAT_ISAC:
407 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_INDEX, 0);
408 /* evidently each byte must be read as a long */
409 for (i = 0; i < size; i++)
410 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_DATA);
411 break;
412 case ISIC_WHAT_HSCXA:
413 hscx_read_fifo(0, buf, size, sc);
414 break;
415 case ISIC_WHAT_HSCXB:
416 hscx_read_fifo(1, buf, size, sc);
417 break;
418 }
419 }
420
421 static void
422 hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc)
423 {
424 u_int32_t *ip;
425 size_t cnt;
426 int dataoff;
427
428 dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
429
430 ip = (u_int32_t *)buf;
431 cnt = 0;
432 /* what if len isn't a multiple of sizeof(int) and buf is */
433 /* too small ???? */
434 while (cnt < len)
435 {
436 *ip++ = bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, dataoff);
437 cnt += 4;
438 }
439 }
440
441 /*---------------------------------------------------------------------------*
442 * AVM write fifo routines
443 *---------------------------------------------------------------------------*/
444
445 static void
446 avma1pp2_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
447 {
448 int i;
449
450 switch (what) {
451 case ISIC_WHAT_ISAC:
452 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_INDEX, 0);
453 /* evidently each byte must be written as a long */
454 for (i = 0; i < size; i++)
455 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_DATA, ((unsigned char *)buf)[i]);
456 break;
457 case ISIC_WHAT_HSCXA:
458 hscx_write_fifo(0, buf, size, sc);
459 break;
460 case ISIC_WHAT_HSCXB:
461 hscx_write_fifo(1, buf, size, sc);
462 break;
463 }
464 }
465
466 static void
467 hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc)
468 {
469 u_int32_t *ip;
470 size_t cnt;
471 int dataoff;
472 l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
473
474 dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
475
476 sc->avma1pp_cmd &= ~HSCX_CMD_XME;
477 sc->avma1pp_txl = 0;
478 if (Bchan->out_mbuf_cur == NULL)
479 {
480 if (Bchan->bprot != BPROT_NONE)
481 sc->avma1pp_cmd |= HSCX_CMD_XME;
482 }
483 if (len != sc->sc_bfifolen)
484 sc->avma1pp_txl = len;
485
486 cnt = 0; /* borrow cnt */
487 AVMA1PPSETCMDLONG(cnt);
488 hscx_write_reg(chan, cnt, sc);
489
490 ip = (u_int32_t *)buf;
491 cnt = 0;
492 while (cnt < len)
493 {
494 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, dataoff, *ip);
495 ip++;
496 cnt += 4;
497 }
498 }
499
500 /*---------------------------------------------------------------------------*
501 * AVM write register routines
502 *---------------------------------------------------------------------------*/
503
504 static void
505 avma1pp2_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data)
506 {
507 switch (what) {
508 case ISIC_WHAT_ISAC:
509 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_INDEX, offs);
510 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_DATA, data);
511 break;
512 case ISIC_WHAT_HSCXA:
513 hscx_write_reg(0, data, sc);
514 break;
515 case ISIC_WHAT_HSCXB:
516 hscx_write_reg(1, data, sc);
517 break;
518 }
519 }
520
521 static void
522 hscx_write_reg(int chan, u_int val, struct isic_softc *sc)
523 {
524 u_int off;
525
526 off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
527 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, off, val);
528 }
529
530 /*---------------------------------------------------------------------------*
531 * AVM read register routines
532 *---------------------------------------------------------------------------*/
533
534 static u_int8_t
535 avma1pp2_read_reg(struct isic_softc *sc, int what, bus_size_t offs)
536 {
537 u_int8_t val;
538
539 switch (what) {
540 case ISIC_WHAT_ISAC:
541 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_INDEX, offs);
542 val = (u_int8_t)bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_DATA);
543 return(val);
544 case ISIC_WHAT_HSCXA:
545 return hscx_read_reg(0, sc);
546 case ISIC_WHAT_HSCXB:
547 return hscx_read_reg(1, sc);
548 }
549 return 0;
550 }
551
552 static u_char
553 hscx_read_reg(int chan, struct isic_softc *sc)
554 {
555 return(hscx_read_reg_int(chan, sc) & 0xff);
556 }
557
558 /*
559 * need to be able to return an int because the RBCH is in the 2nd
560 * byte.
561 */
562 static u_int
563 hscx_read_reg_int(int chan, struct isic_softc *sc)
564 {
565 u_int off;
566
567 off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
568 return(bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, off));
569 }
570
571 /*
572 * this is the real interrupt routine
573 */
574 static void
575 avma1pp2_hscx_intr(int h_chan, u_int stat, struct isic_softc *sc)
576 {
577 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
578 int activity = -1;
579 u_int param = 0;
580
581 NDBGL1(L1_H_IRQ, "%#x", stat);
582
583 if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
584 {
585 chan->stat_XDU++;
586 NDBGL1(L1_H_XFRERR, "xmit data underrun");
587 /* abort the transmission */
588 sc->avma1pp_txl = 0;
589 sc->avma1pp_cmd |= HSCX_CMD_XRS;
590 AVMA1PPSETCMDLONG(param);
591 hscx_write_reg(h_chan, param, sc);
592 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
593 AVMA1PPSETCMDLONG(param);
594 hscx_write_reg(h_chan, param, sc);
595
596 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
597 {
598 i4b_Bfreembuf(chan->out_mbuf_head);
599 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
600 }
601 }
602
603 /*
604 * The following is based on examination of the Linux driver.
605 *
606 * The logic here is different than with a "real" HSCX; all kinds
607 * of information (interrupt/status bits) are in stat.
608 * HSCX_INT_RPR indicates a receive interrupt
609 * HSCX_STAT_RDO indicates an overrun condition, abort -
610 * otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
611 * HSCX_STAT_RME indicates end-of-frame and apparently any
612 * CRC/framing errors are only reported in this state.
613 * if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
614 * CRC/framing error
615 */
616
617 if(stat & HSCX_INT_RPR)
618 {
619 register int fifo_data_len;
620 int error = 0;
621 /* always have to read the FIFO, so use a scratch buffer */
622 u_char scrbuf[HSCX_FIFO_LEN];
623
624 if(stat & HSCX_STAT_RDO)
625 {
626 chan->stat_RDO++;
627 NDBGL1(L1_H_XFRERR, "receive data overflow");
628 error++;
629 }
630
631 /*
632 * check whether we're receiving data for an inactive B-channel
633 * and discard it. This appears to happen for telephony when
634 * both B-channels are active and one is deactivated. Since
635 * it is not really possible to deactivate the channel in that
636 * case (the ASIC seems to deactivate _both_ channels), the
637 * "deactivated" channel keeps receiving data which can lead
638 * to exhaustion of mbufs and a kernel panic.
639 *
640 * This is a hack, but it's the only solution I can think of
641 * without having the documentation for the ASIC.
642 * GJ - 28 Nov 1999
643 */
644 if (chan->state == HSCX_IDLE)
645 {
646 NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
647 error++;
648 }
649
650 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
651
652 if(fifo_data_len == 0)
653 fifo_data_len = sc->sc_bfifolen;
654
655 /* ALWAYS read data from HSCX fifo */
656
657 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
658 chan->rxcount += fifo_data_len;
659
660 /* all error conditions checked, now decide and take action */
661
662 if(error == 0)
663 {
664 if(chan->in_mbuf == NULL)
665 {
666 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
667 panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!");
668 chan->in_cbptr = chan->in_mbuf->m_data;
669 chan->in_len = 0;
670 }
671
672 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
673 {
674 /* OK to copy the data */
675 memcpy(chan->in_cbptr, scrbuf, fifo_data_len);
676 chan->in_cbptr += fifo_data_len;
677 chan->in_len += fifo_data_len;
678
679 /* setup mbuf data length */
680
681 chan->in_mbuf->m_len = chan->in_len;
682 chan->in_mbuf->m_pkthdr.len = chan->in_len;
683
684 if(sc->sc_trace & TRACE_B_RX)
685 {
686 struct i4b_trace_hdr hdr;
687 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
688 hdr.dir = FROM_NT;
689 hdr.count = ++sc->sc_trace_bcount;
690 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
691 }
692
693 if (stat & HSCX_STAT_RME)
694 {
695 if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
696 {
697 (*chan->l4_driver->bch_rx_data_ready)(chan->l4_driver_softc);
698 activity = ACT_RX;
699
700 /* mark buffer ptr as unused */
701
702 chan->in_mbuf = NULL;
703 chan->in_cbptr = NULL;
704 chan->in_len = 0;
705 }
706 else
707 {
708 chan->stat_CRC++;
709 NDBGL1(L1_H_XFRERR, "CRC/RAB");
710 if (chan->in_mbuf != NULL)
711 {
712 i4b_Bfreembuf(chan->in_mbuf);
713 chan->in_mbuf = NULL;
714 chan->in_cbptr = NULL;
715 chan->in_len = 0;
716 }
717 }
718 }
719 } /* END enough space in mbuf */
720 else
721 {
722 if(chan->bprot == BPROT_NONE)
723 {
724 /* setup mbuf data length */
725
726 chan->in_mbuf->m_len = chan->in_len;
727 chan->in_mbuf->m_pkthdr.len = chan->in_len;
728
729 if(sc->sc_trace & TRACE_B_RX)
730 {
731 struct i4b_trace_hdr hdr;
732 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
733 hdr.dir = FROM_NT;
734 hdr.count = ++sc->sc_trace_bcount;
735 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
736 }
737
738 if(!(isdn_bchan_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
739 activity = ACT_RX;
740
741 /* move rx'd data to rx queue */
742
743 if (!(IF_QFULL(&chan->rx_queue)))
744 {
745 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
746 }
747 else
748 {
749 i4b_Bfreembuf(chan->in_mbuf);
750 }
751
752 /* signal upper layer that data are available */
753 (*chan->l4_driver->bch_rx_data_ready)(chan->l4_driver_softc);
754
755 /* alloc new buffer */
756
757 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
758 panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!");
759
760 /* setup new data ptr */
761
762 chan->in_cbptr = chan->in_mbuf->m_data;
763
764 /* OK to copy the data */
765 memcpy(chan->in_cbptr, scrbuf, fifo_data_len);
766
767 chan->in_cbptr += fifo_data_len;
768 chan->in_len = fifo_data_len;
769
770 chan->rxcount += fifo_data_len;
771 }
772 else
773 {
774 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
775 chan->in_cbptr = chan->in_mbuf->m_data;
776 chan->in_len = 0;
777 }
778 }
779 } /* if(error == 0) */
780 else
781 {
782 /* land here for RDO */
783 if (chan->in_mbuf != NULL)
784 {
785 i4b_Bfreembuf(chan->in_mbuf);
786 chan->in_mbuf = NULL;
787 chan->in_cbptr = NULL;
788 chan->in_len = 0;
789 }
790 sc->avma1pp_txl = 0;
791 sc->avma1pp_cmd |= HSCX_CMD_RRS;
792 AVMA1PPSETCMDLONG(param);
793 hscx_write_reg(h_chan, param, sc);
794 sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
795 AVMA1PPSETCMDLONG(param);
796 hscx_write_reg(h_chan, param, sc);
797 }
798 }
799
800
801 /* transmit fifo empty, new data can be written to fifo */
802
803 if(stat & HSCX_INT_XPR)
804 {
805 /*
806 * for a description what is going on here, please have
807 * a look at isic_bchannel_start() in i4b_bchan.c !
808 */
809
810 NDBGL1(L1_H_IRQ, "%s: chan %d - XPR, Tx Fifo Empty!", sc->sc_dev.dv_xname, h_chan);
811
812 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
813 {
814 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
815
816 if(chan->out_mbuf_head == NULL)
817 {
818 chan->state &= ~HSCX_TX_ACTIVE;
819 (*chan->l4_driver->bch_tx_queue_empty)(chan->l4_driver_softc);
820 }
821 else
822 {
823 chan->state |= HSCX_TX_ACTIVE;
824 chan->out_mbuf_cur = chan->out_mbuf_head;
825 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
826 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
827
828 if(sc->sc_trace & TRACE_B_TX)
829 {
830 struct i4b_trace_hdr hdr;
831 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
832 hdr.dir = FROM_TE;
833 hdr.count = ++sc->sc_trace_bcount;
834 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
835 }
836
837 if(chan->bprot == BPROT_NONE)
838 {
839 if(!(isdn_bchan_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
840 activity = ACT_TX;
841 }
842 else
843 {
844 activity = ACT_TX;
845 }
846 }
847 }
848
849 isic_hscx_fifo(chan, sc);
850 }
851
852 /* call timeout handling routine */
853
854 if(activity == ACT_RX || activity == ACT_TX)
855 (*chan->l4_driver->bch_activity)(chan->l4_driver_softc, activity);
856 }
857
858 /*
859 * this is the main routine which checks each channel and then calls
860 * the real interrupt routine as appropriate
861 */
862 static void
863 avma1pp2_hscx_int_handler(struct isic_softc *sc)
864 {
865 u_int stat;
866
867 /* has to be a u_int because the byte count is in the 2nd byte */
868 stat = hscx_read_reg_int(0, sc);
869 if (stat & HSCX_INT_MASK)
870 avma1pp2_hscx_intr(0, stat, sc);
871 stat = hscx_read_reg_int(1, sc);
872 if (stat & HSCX_INT_MASK)
873 avma1pp2_hscx_intr(1, stat, sc);
874 }
875
876 static void
877 avma1pp2_disable(struct isic_softc *sc)
878 {
879 /* could be still be wrong, but seems to prevent hangs */
880 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, 0x00);
881 }
882
883 static int
884 avma1pp2_intr(void * parm)
885 {
886 struct isic_softc *sc = parm;
887 int ret = 0;
888 #define OURS ret = 1
889 u_char stat;
890
891 if (sc->sc_intr_valid != ISIC_INTR_VALID)
892 return 0;
893
894 stat = bus_space_read_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET);
895 NDBGL1(L1_H_IRQ, "stat %x", stat);
896 /* was there an interrupt from this card ? */
897 if ((stat & ASL_IRQ_Pending) == 0)
898 return 0; /* no */
899 /* For slow machines loop as long as an interrupt is active */
900 for (; ((stat & ASL_IRQ_Pending) != 0) ;)
901 {
902 /* interrupts are high active */
903 if (stat & ASL_IRQ_TIMER)
904 NDBGL1(L1_H_IRQ, "timer interrupt ???");
905 if (stat & ASL_IRQ_HSCX)
906 {
907 NDBGL1(L1_H_IRQ, "HSCX");
908 avma1pp2_hscx_int_handler(sc);
909 }
910 if (stat & ASL_IRQ_ISAC)
911 {
912 u_char isacsx_irq_stat;
913
914 NDBGL1(L1_H_IRQ, "ISAC");
915 for(;;)
916 {
917 /* ISTA tells us whether it was a C/I or HDLC int. */
918 isacsx_irq_stat = ISAC_READ(I_ISTA);
919
920 if(isacsx_irq_stat)
921 isic_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
922 else
923 break;
924 }
925
926 /*
927 * XXX: Leo: Note that Linux doesn't do this mask
928 * frobbing...
929 */
930 ISAC_WRITE(I_MASKD, 0xff);
931 ISAC_WRITE(I_MASK, 0xff);
932
933 DELAY(100);
934
935 ISAC_WRITE(I_MASKD, isacsx_imaskd);
936 ISAC_WRITE(I_MASK, isacsx_imask);
937
938 }
939 stat = bus_space_read_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET);
940 NDBGL1(L1_H_IRQ, "stat %x", stat);
941 OURS;
942 }
943 return ret;
944 }
945
946 static void
947 avma1pp2_map_int(struct ifpci_softc *psc, struct pci_attach_args *pa)
948 {
949 struct isic_softc *sc = &psc->sc_isic;
950 pci_chipset_tag_t pc = pa->pa_pc;
951 pci_intr_handle_t ih;
952 const char *intrstr;
953
954 /* Map and establish the interrupt. */
955 if (pci_intr_map(pa, &ih)) {
956 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
957 avma1pp2_disable(sc);
958 return;
959 }
960 psc->sc_pc = pc;
961 intrstr = pci_intr_string(pc, ih);
962 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, avma1pp2_intr, sc);
963 if (psc->sc_ih == NULL) {
964 printf("%s: couldn't establish interrupt",
965 sc->sc_dev.dv_xname);
966 if (intrstr != NULL)
967 printf(" at %s", intrstr);
968 printf("\n");
969 avma1pp2_disable(sc);
970 return;
971 }
972 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
973 }
974
975 static void
976 avma1pp2_hscx_init(struct isic_softc *sc, int h_chan, int activate)
977 {
978 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
979 u_int param = 0;
980
981 NDBGL1(L1_BCHAN, "%s: channel=%d, %s",
982 sc->sc_dev.dv_xname, h_chan, activate ? "activate" : "deactivate");
983 sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
984
985 if (activate == 0)
986 {
987 /* only deactivate if both channels are idle */
988 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
989 sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
990 {
991 return;
992 }
993 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
994 sc->avma1pp_prot = HSCX_MODE_TRANS;
995 AVMA1PPSETCMDLONG(param);
996 hscx_write_reg(h_chan, param, sc);
997 return;
998 }
999 if(chan->bprot == BPROT_RHDLC)
1000 {
1001 NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1002
1003 /* HDLC Frames, transparent mode 0 */
1004 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1005 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1006 AVMA1PPSETCMDLONG(param);
1007 hscx_write_reg(h_chan, param, sc);
1008 sc->avma1pp_cmd = HSCX_CMD_XRS;
1009 AVMA1PPSETCMDLONG(param);
1010 hscx_write_reg(h_chan, param, sc);
1011 sc->avma1pp_cmd = 0;
1012 }
1013 else
1014 {
1015 NDBGL1(L1_BCHAN, "BPROT_NONE??");
1016
1017 /* Raw Telephony, extended transparent mode 1 */
1018 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1019 sc->avma1pp_prot = HSCX_MODE_TRANS;
1020 AVMA1PPSETCMDLONG(param);
1021 hscx_write_reg(h_chan, param, sc);
1022 sc->avma1pp_cmd = HSCX_CMD_XRS;
1023 AVMA1PPSETCMDLONG(param);
1024 hscx_write_reg(h_chan, param, sc);
1025 sc->avma1pp_cmd = 0;
1026 }
1027 }
1028
1029 static void
1030 avma1pp2_bchannel_setup(isdn_layer1token t, int h_chan, int bprot, int activate)
1031 {
1032 struct isic_softc *sc = (struct isic_softc*)t;
1033 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1034
1035 int s = splnet();
1036
1037 if(activate == 0)
1038 {
1039 /* deactivation */
1040 chan->state = HSCX_IDLE;
1041 avma1pp2_hscx_init(sc, h_chan, activate);
1042 }
1043
1044 NDBGL1(L1_BCHAN, "%s: channel=%d, %s",
1045 sc->sc_dev.dv_xname, h_chan, activate ? "activate" : "deactivate");
1046
1047 /* general part */
1048
1049 chan->channel = h_chan; /* B channel */
1050 chan->bprot = bprot; /* B channel protocol */
1051 chan->state = HSCX_IDLE; /* B channel state */
1052
1053 /* receiver part */
1054
1055 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1056
1057 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1058
1059 chan->rxcount = 0; /* reset rx counter */
1060
1061 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1062
1063 chan->in_mbuf = NULL; /* reset mbuf ptr */
1064 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1065 chan->in_len = 0; /* reset mbuf data len */
1066
1067 /* transmitter part */
1068
1069 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1070
1071 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1072
1073 chan->txcount = 0; /* reset tx counter */
1074
1075 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1076
1077 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1078 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1079 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1080 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1081
1082 if(activate != 0)
1083 {
1084 /* activation */
1085 avma1pp2_hscx_init(sc, h_chan, activate);
1086 chan->state |= HSCX_AVMA1PP_ACTIVE;
1087 }
1088
1089 splx(s);
1090 }
1091
1092 static void
1093 avma1pp2_bchannel_start(isdn_layer1token t, int h_chan)
1094 {
1095 struct isic_softc *sc = (struct isic_softc*)t;
1096 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1097 int s;
1098 int activity = -1;
1099
1100 s = splnet(); /* enter critical section */
1101 if(chan->state & HSCX_TX_ACTIVE) /* already running ? */
1102 {
1103 splx(s);
1104 return; /* yes, leave */
1105 }
1106
1107 /* get next mbuf from queue */
1108
1109 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1110
1111 if(chan->out_mbuf_head == NULL) /* queue empty ? */
1112 {
1113 splx(s); /* leave critical section */
1114 return; /* yes, exit */
1115 }
1116
1117 /* init current mbuf values */
1118
1119 chan->out_mbuf_cur = chan->out_mbuf_head;
1120 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1121 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1122
1123 /* activity indicator for timeout handling */
1124
1125 if(chan->bprot == BPROT_NONE)
1126 {
1127 if(!(isdn_bchan_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1128 activity = ACT_TX;
1129 }
1130 else
1131 {
1132 activity = ACT_TX;
1133 }
1134
1135 chan->state |= HSCX_TX_ACTIVE; /* we start transmitting */
1136
1137 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
1138 {
1139 struct i4b_trace_hdr hdr;
1140 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1141 hdr.dir = FROM_TE;
1142 hdr.count = ++sc->sc_trace_bcount;
1143 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1144 }
1145
1146 isic_hscx_fifo(chan, sc);
1147
1148 /* call timeout handling routine */
1149
1150 if(activity == ACT_RX || activity == ACT_TX)
1151 (*chan->l4_driver->bch_activity)(chan->l4_driver_softc, activity);
1152
1153 splx(s);
1154 }
1155
1156 /*---------------------------------------------------------------------------*
1157 * return the address of isic drivers linktab
1158 *---------------------------------------------------------------------------*/
1159 static isdn_link_t *
1160 avma1pp2_ret_linktab(void *token, int channel)
1161 {
1162 struct l2_softc *l2sc = token;
1163 struct isic_softc *sc = l2sc->l1_token;
1164
1165 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1166
1167 return(&chan->isdn_linktab);
1168 }
1169
1170 /*---------------------------------------------------------------------------*
1171 * set the driver linktab in the b channel softc
1172 *---------------------------------------------------------------------------*/
1173 static void
1174 avma1pp2_set_link(void *token, int channel, const struct isdn_l4_driver_functions *l4_driver, void *l4_driver_softc)
1175 {
1176 struct l2_softc *l2sc = token;
1177 struct isic_softc *sc = l2sc->l1_token;
1178 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1179
1180 chan->l4_driver = l4_driver;
1181 chan->l4_driver_softc = l4_driver_softc;
1182 }
1183
1184 static const struct isdn_l4_bchannel_functions
1185 avma1pp2_l4_bchannel_functions = {
1186 avma1pp2_bchannel_setup,
1187 avma1pp2_bchannel_start,
1188 avma1pp2_bchannel_stat
1189 };
1190
1191 /*---------------------------------------------------------------------------*
1192 * initialize our local linktab
1193 *---------------------------------------------------------------------------*/
1194 static void
1195 avma1pp2_init_linktab(struct isic_softc *sc)
1196 {
1197 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1198 isdn_link_t *lt = &chan->isdn_linktab;
1199
1200 /* local setup */
1201 lt->l1token = sc;
1202 lt->channel = HSCX_CH_A;
1203 lt->bchannel_driver = &avma1pp2_l4_bchannel_functions;
1204 lt->tx_queue = &chan->tx_queue;
1205
1206 /* used by non-HDLC data transfers, i.e. telephony drivers */
1207 lt->rx_queue = &chan->rx_queue;
1208
1209 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1210 lt->rx_mbuf = &chan->in_mbuf;
1211
1212 chan = &sc->sc_chan[HSCX_CH_B];
1213 lt = &chan->isdn_linktab;
1214
1215 lt->l1token = sc;
1216 lt->channel = HSCX_CH_B;
1217 lt->bchannel_driver = &avma1pp2_l4_bchannel_functions;
1218 lt->tx_queue = &chan->tx_queue;
1219
1220 /* used by non-HDLC data transfers, i.e. telephony drivers */
1221 lt->rx_queue = &chan->rx_queue;
1222
1223 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1224 lt->rx_mbuf = &chan->in_mbuf;
1225 }
1226
1227 /*
1228 * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1229 */
1230 static void
1231 avma1pp2_bchannel_stat(isdn_layer1token t, int h_chan, bchan_statistics_t *bsp)
1232 {
1233 struct isic_softc *sc = (struct isic_softc*)t;
1234 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1235 int s;
1236
1237 s = splnet();
1238
1239 bsp->outbytes = chan->txcount;
1240 bsp->inbytes = chan->rxcount;
1241
1242 chan->txcount = 0;
1243 chan->rxcount = 0;
1244
1245 splx(s);
1246 }
1247
1248 /*---------------------------------------------------------------------------*
1249 * fill HSCX fifo with data from the current mbuf
1250 * Put this here until it can go into i4b_hscx.c
1251 *---------------------------------------------------------------------------*/
1252 static int
1253 isic_hscx_fifo(l1_bchan_state_t *chan, struct isic_softc *sc)
1254 {
1255 int len;
1256 int nextlen;
1257 int i;
1258 int cmd;
1259 /* using a scratch buffer simplifies writing to the FIFO */
1260 u_char scrbuf[HSCX_FIFO_LEN];
1261
1262 len = 0;
1263 cmd = 0;
1264
1265 /*
1266 * fill the HSCX tx fifo with data from the current mbuf. if
1267 * current mbuf holds less data than HSCX fifo length, try to
1268 * get the next mbuf from (a possible) mbuf chain. if there is
1269 * not enough data in a single mbuf or in a chain, then this
1270 * is the last mbuf and we tell the HSCX that it has to send
1271 * CRC and closing flag
1272 */
1273
1274 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1275 {
1276 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1277
1278 #ifdef NOTDEF
1279 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1280 chan->out_mbuf_head,
1281 chan->out_mbuf_cur,
1282 chan->out_mbuf_cur_ptr,
1283 chan->out_mbuf_cur_len,
1284 len,
1285 nextlen);
1286 #endif
1287
1288 cmd |= HSCX_CMDR_XTF;
1289 /* collect the data in the scratch buffer */
1290 for (i = 0; i < nextlen; i++)
1291 scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1292
1293 len += nextlen;
1294 chan->txcount += nextlen;
1295
1296 chan->out_mbuf_cur_ptr += nextlen;
1297 chan->out_mbuf_cur_len -= nextlen;
1298
1299 if(chan->out_mbuf_cur_len == 0)
1300 {
1301 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1302 {
1303 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1304 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1305
1306 if(sc->sc_trace & TRACE_B_TX)
1307 {
1308 struct i4b_trace_hdr hdr;
1309 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1310 hdr.dir = FROM_TE;
1311 hdr.count = ++sc->sc_trace_bcount;
1312 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1313 }
1314 }
1315 else
1316 {
1317 if (chan->bprot != BPROT_NONE)
1318 cmd |= HSCX_CMDR_XME;
1319 i4b_Bfreembuf(chan->out_mbuf_head);
1320 chan->out_mbuf_head = NULL;
1321 }
1322 }
1323 }
1324 /* write what we have from the scratch buf to the HSCX fifo */
1325 if (len != 0)
1326 HSCX_WRFIFO(chan->channel, scrbuf, len);
1327 return(cmd);
1328 }
Cache object: 68ce6a2ffe2f2cc54b19126c516d026d
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