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sys/dev/pci/isp_pci.c
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1 /* $NetBSD: isp_pci.c,v 1.91 2004/03/10 22:42:47 matt Exp $ */ 2 /* 3 * This driver, which is contained in NetBSD in the files: 4 * 5 * sys/dev/ic/isp.c 6 * sys/dev/ic/isp_inline.h 7 * sys/dev/ic/isp_netbsd.c 8 * sys/dev/ic/isp_netbsd.h 9 * sys/dev/ic/isp_target.c 10 * sys/dev/ic/isp_target.h 11 * sys/dev/ic/isp_tpublic.h 12 * sys/dev/ic/ispmbox.h 13 * sys/dev/ic/ispreg.h 14 * sys/dev/ic/ispvar.h 15 * sys/microcode/isp/asm_sbus.h 16 * sys/microcode/isp/asm_1040.h 17 * sys/microcode/isp/asm_1080.h 18 * sys/microcode/isp/asm_12160.h 19 * sys/microcode/isp/asm_2100.h 20 * sys/microcode/isp/asm_2200.h 21 * sys/pci/isp_pci.c 22 * sys/sbus/isp_sbus.c 23 * 24 * Is being actively maintained by Matthew Jacob (mjacob@NetBSD.org). 25 * This driver also is shared source with FreeBSD, OpenBSD, Linux, Solaris, 26 * Linux versions. This tends to be an interesting maintenance problem. 27 * 28 * Please coordinate with Matthew Jacob on changes you wish to make here. 29 */ 30 /* 31 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 32 */ 33 /* 34 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 35 * All rights reserved. 36 * 37 * Additional Copyright (C) 2000, 2001 by Matthew Jacob 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.91 2004/03/10 22:42:47 matt Exp $"); 61 62 #include <dev/ic/isp_netbsd.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcidevs.h> 66 #include <uvm/uvm_extern.h> 67 #include <sys/reboot.h> 68 69 static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); 70 static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); 71 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 72 static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 73 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); 74 #endif 75 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 76 !defined(ISP_DISABLE_2200_SUPPORT) && \ 77 !defined(ISP_DISABLE_1020_SUPPORT) && \ 78 !defined(ISP_DISABLE_1080_SUPPORT) && \ 79 !defined(ISP_DISABLE_12160_SUPPORT) 80 static int 81 isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 82 #endif 83 #if !defined(ISP_DISABLE_2300_SUPPORT) 84 static int 85 isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); 86 #endif 87 static int isp_pci_mbxdma(struct ispsoftc *); 88 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, 89 u_int16_t *, u_int16_t); 90 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); 91 static void isp_pci_reset1(struct ispsoftc *); 92 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 93 static int isp_pci_intr(void *); 94 95 #if defined(ISP_DISABLE_1020_SUPPORT) 96 #define ISP_1040_RISC_CODE NULL 97 #else 98 #define ISP_1040_RISC_CODE (u_int16_t *) isp_1040_risc_code 99 #include <dev/microcode/isp/asm_1040.h> 100 #endif 101 102 #if defined(ISP_DISABLE_1080_SUPPORT) 103 #define ISP_1080_RISC_CODE NULL 104 #else 105 #define ISP_1080_RISC_CODE (u_int16_t *) isp_1080_risc_code 106 #include <dev/microcode/isp/asm_1080.h> 107 #endif 108 109 #if defined(ISP_DISABLE_12160_SUPPORT) 110 #define ISP_12160_RISC_CODE NULL 111 #else 112 #define ISP_12160_RISC_CODE (u_int16_t *) isp_12160_risc_code 113 #include <dev/microcode/isp/asm_12160.h> 114 #endif 115 116 #if defined(ISP_DISABLE_2100_SUPPORT) 117 #define ISP_2100_RISC_CODE NULL 118 #else 119 #define ISP_2100_RISC_CODE (u_int16_t *) isp_2100_risc_code 120 #include <dev/microcode/isp/asm_2100.h> 121 #endif 122 123 #if defined(ISP_DISABLE_2200_SUPPORT) 124 #define ISP_2200_RISC_CODE NULL 125 #else 126 #define ISP_2200_RISC_CODE (u_int16_t *) isp_2200_risc_code 127 #include <dev/microcode/isp/asm_2200.h> 128 #endif 129 130 #if defined(ISP_DISABLE_2300_SUPPORT) 131 #define ISP_2300_RISC_CODE NULL 132 #else 133 #define ISP_2300_RISC_CODE (u_int16_t *) isp_2300_risc_code 134 #include <dev/microcode/isp/asm_2300.h> 135 #endif 136 137 #ifndef ISP_DISABLE_1020_SUPPORT 138 static struct ispmdvec mdvec = { 139 isp_pci_rd_isr, 140 isp_pci_rd_reg, 141 isp_pci_wr_reg, 142 isp_pci_mbxdma, 143 isp_pci_dmasetup, 144 isp_pci_dmateardown, 145 NULL, 146 isp_pci_reset1, 147 isp_pci_dumpregs, 148 ISP_1040_RISC_CODE, 149 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 150 }; 151 #endif 152 153 #ifndef ISP_DISABLE_1080_SUPPORT 154 static struct ispmdvec mdvec_1080 = { 155 isp_pci_rd_isr, 156 isp_pci_rd_reg_1080, 157 isp_pci_wr_reg_1080, 158 isp_pci_mbxdma, 159 isp_pci_dmasetup, 160 isp_pci_dmateardown, 161 NULL, 162 isp_pci_reset1, 163 isp_pci_dumpregs, 164 ISP_1080_RISC_CODE, 165 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 166 }; 167 #endif 168 169 #ifndef ISP_DISABLE_12160_SUPPORT 170 static struct ispmdvec mdvec_12160 = { 171 isp_pci_rd_isr, 172 isp_pci_rd_reg_1080, 173 isp_pci_wr_reg_1080, 174 isp_pci_mbxdma, 175 isp_pci_dmasetup, 176 isp_pci_dmateardown, 177 NULL, 178 isp_pci_reset1, 179 isp_pci_dumpregs, 180 ISP_12160_RISC_CODE, 181 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 182 }; 183 #endif 184 185 #ifndef ISP_DISABLE_2100_SUPPORT 186 static struct ispmdvec mdvec_2100 = { 187 isp_pci_rd_isr, 188 isp_pci_rd_reg, 189 isp_pci_wr_reg, 190 isp_pci_mbxdma, 191 isp_pci_dmasetup, 192 isp_pci_dmateardown, 193 NULL, 194 isp_pci_reset1, 195 isp_pci_dumpregs, 196 ISP_2100_RISC_CODE 197 }; 198 #endif 199 200 #ifndef ISP_DISABLE_2200_SUPPORT 201 static struct ispmdvec mdvec_2200 = { 202 isp_pci_rd_isr, 203 isp_pci_rd_reg, 204 isp_pci_wr_reg, 205 isp_pci_mbxdma, 206 isp_pci_dmasetup, 207 isp_pci_dmateardown, 208 NULL, 209 isp_pci_reset1, 210 isp_pci_dumpregs, 211 ISP_2200_RISC_CODE 212 }; 213 #endif 214 215 #ifndef ISP_DISABLE_2300_SUPPORT 216 static struct ispmdvec mdvec_2300 = { 217 isp_pci_rd_isr_2300, 218 isp_pci_rd_reg, 219 isp_pci_wr_reg, 220 isp_pci_mbxdma, 221 isp_pci_dmasetup, 222 isp_pci_dmateardown, 223 NULL, 224 isp_pci_reset1, 225 isp_pci_dumpregs, 226 ISP_2300_RISC_CODE 227 }; 228 #endif 229 230 #ifndef PCI_VENDOR_QLOGIC 231 #define PCI_VENDOR_QLOGIC 0x1077 232 #endif 233 234 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 235 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 236 #endif 237 238 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 239 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 240 #endif 241 242 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 243 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 244 #endif 245 246 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 247 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 248 #endif 249 250 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 251 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 252 #endif 253 254 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 255 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 256 #endif 257 258 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 259 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 260 #endif 261 262 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 263 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 264 #endif 265 266 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 267 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 268 #endif 269 270 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 271 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 272 #endif 273 274 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 275 276 #define PCI_QLOGIC_ISP1080 \ 277 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 278 279 #define PCI_QLOGIC_ISP1240 \ 280 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 281 282 #define PCI_QLOGIC_ISP1280 \ 283 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 284 285 #define PCI_QLOGIC_ISP10160 \ 286 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 287 288 #define PCI_QLOGIC_ISP12160 \ 289 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 290 291 #define PCI_QLOGIC_ISP2100 \ 292 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 293 294 #define PCI_QLOGIC_ISP2200 \ 295 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 296 297 #define PCI_QLOGIC_ISP2300 \ 298 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 299 300 #define PCI_QLOGIC_ISP2312 \ 301 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 302 303 #define IO_MAP_REG 0x10 304 #define MEM_MAP_REG 0x14 305 #define PCIR_ROMADDR 0x30 306 307 #define PCI_DFLT_LTNCY 0x40 308 #define PCI_DFLT_LNSZ 0x10 309 310 311 static int isp_pci_probe(struct device *, struct cfdata *, void *); 312 static void isp_pci_attach(struct device *, struct device *, void *); 313 314 struct isp_pcisoftc { 315 struct ispsoftc pci_isp; 316 pci_chipset_tag_t pci_pc; 317 pcitag_t pci_tag; 318 bus_space_tag_t pci_st; 319 bus_space_handle_t pci_sh; 320 bus_dmamap_t *pci_xfer_dmap; 321 void * pci_ih; 322 int16_t pci_poff[_NREG_BLKS]; 323 }; 324 325 CFATTACH_DECL(isp_pci, sizeof (struct isp_pcisoftc), 326 isp_pci_probe, isp_pci_attach, NULL, NULL); 327 328 #ifdef DEBUG 329 const char vstring[] = 330 "Qlogic ISP Driver, NetBSD (pci) Platform Version %d.%d Core Version %d.%d"; 331 #endif 332 333 static int 334 isp_pci_probe(struct device *parent, struct cfdata *match, void *aux) 335 { 336 struct pci_attach_args *pa = aux; 337 switch (pa->pa_id) { 338 #ifndef ISP_DISABLE_1020_SUPPORT 339 case PCI_QLOGIC_ISP: 340 return (1); 341 #endif 342 #ifndef ISP_DISABLE_1080_SUPPORT 343 case PCI_QLOGIC_ISP1080: 344 case PCI_QLOGIC_ISP1240: 345 case PCI_QLOGIC_ISP1280: 346 return (1); 347 #endif 348 #ifndef ISP_DISABLE_12160_SUPPORT 349 case PCI_QLOGIC_ISP10160: 350 case PCI_QLOGIC_ISP12160: 351 return (1); 352 #endif 353 #ifndef ISP_DISABLE_2100_SUPPORT 354 case PCI_QLOGIC_ISP2100: 355 return (1); 356 #endif 357 #ifndef ISP_DISABLE_2200_SUPPORT 358 case PCI_QLOGIC_ISP2200: 359 return (1); 360 #endif 361 #ifndef ISP_DISABLE_2300_SUPPORT 362 case PCI_QLOGIC_ISP2300: 363 case PCI_QLOGIC_ISP2312: 364 return (1); 365 #endif 366 default: 367 return (0); 368 } 369 } 370 371 372 static void 373 isp_pci_attach(struct device *parent, struct device *self, void *aux) 374 { 375 #ifdef DEBUG 376 static char oneshot = 1; 377 #endif 378 static const char nomem[] = "\n%s: no mem for sdparam table\n"; 379 u_int32_t data, rev, linesz = PCI_DFLT_LNSZ; 380 struct pci_attach_args *pa = aux; 381 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self; 382 struct ispsoftc *isp = &pcs->pci_isp; 383 bus_space_tag_t st, iot, memt; 384 bus_space_handle_t sh, ioh, memh; 385 pci_intr_handle_t ih; 386 pcireg_t mem_type; 387 char *dstring; 388 const char *intrstr; 389 int ioh_valid, memh_valid; 390 391 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 392 PCI_MAPREG_TYPE_IO, 0, 393 &iot, &ioh, NULL, NULL) == 0); 394 395 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG); 396 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 397 memh_valid = 0; 398 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT && 399 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) { 400 memh_valid = 0; 401 } else { 402 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0, 403 &memt, &memh, NULL, NULL) == 0); 404 } 405 if (memh_valid) { 406 st = memt; 407 sh = memh; 408 } else if (ioh_valid) { 409 st = iot; 410 sh = ioh; 411 } else { 412 printf(": unable to map device registers\n"); 413 return; 414 } 415 dstring = "\n"; 416 417 pcs->pci_st = st; 418 pcs->pci_sh = sh; 419 pcs->pci_pc = pa->pa_pc; 420 pcs->pci_tag = pa->pa_tag; 421 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 422 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 423 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 424 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 425 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 426 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 427 428 #ifndef ISP_DISABLE_1020_SUPPORT 429 if (pa->pa_id == PCI_QLOGIC_ISP) { 430 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n"; 431 isp->isp_mdvec = &mdvec; 432 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 433 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 434 if (isp->isp_param == NULL) { 435 printf(nomem, isp->isp_name); 436 return; 437 } 438 memset(isp->isp_param, 0, sizeof (sdparam)); 439 } 440 #endif 441 #ifndef ISP_DISABLE_1080_SUPPORT 442 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 443 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 444 isp->isp_mdvec = &mdvec_1080; 445 isp->isp_type = ISP_HA_SCSI_1080; 446 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 447 if (isp->isp_param == NULL) { 448 printf(nomem, isp->isp_name); 449 return; 450 } 451 memset(isp->isp_param, 0, sizeof (sdparam)); 452 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 453 ISP1080_DMA_REGS_OFF; 454 } 455 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 456 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 457 isp->isp_mdvec = &mdvec_1080; 458 isp->isp_type = ISP_HA_SCSI_1240; 459 isp->isp_param = 460 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 461 if (isp->isp_param == NULL) { 462 printf(nomem, isp->isp_name); 463 return; 464 } 465 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 466 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 467 ISP1080_DMA_REGS_OFF; 468 } 469 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 470 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 471 isp->isp_mdvec = &mdvec_1080; 472 isp->isp_type = ISP_HA_SCSI_1280; 473 isp->isp_param = 474 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 475 if (isp->isp_param == NULL) { 476 printf(nomem, isp->isp_name); 477 return; 478 } 479 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 480 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 481 ISP1080_DMA_REGS_OFF; 482 } 483 #endif 484 #ifndef ISP_DISABLE_12160_SUPPORT 485 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 486 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 487 isp->isp_mdvec = &mdvec_12160; 488 isp->isp_type = ISP_HA_SCSI_10160; 489 isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT); 490 if (isp->isp_param == NULL) { 491 printf(nomem, isp->isp_name); 492 return; 493 } 494 memset(isp->isp_param, 0, sizeof (sdparam)); 495 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 496 ISP1080_DMA_REGS_OFF; 497 } 498 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 499 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 500 isp->isp_mdvec = &mdvec_12160; 501 isp->isp_type = ISP_HA_SCSI_12160; 502 isp->isp_param = 503 malloc(2 * sizeof (sdparam), M_DEVBUF, M_NOWAIT); 504 if (isp->isp_param == NULL) { 505 printf(nomem, isp->isp_name); 506 return; 507 } 508 memset(isp->isp_param, 0, 2 * sizeof (sdparam)); 509 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 510 ISP1080_DMA_REGS_OFF; 511 } 512 #endif 513 #ifndef ISP_DISABLE_2100_SUPPORT 514 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 515 dstring = ": QLogic FC-AL HBA\n"; 516 isp->isp_mdvec = &mdvec_2100; 517 isp->isp_type = ISP_HA_FC_2100; 518 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 519 if (isp->isp_param == NULL) { 520 printf(nomem, isp->isp_name); 521 return; 522 } 523 memset(isp->isp_param, 0, sizeof (fcparam)); 524 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 525 PCI_MBOX_REGS2100_OFF; 526 if (rev < 3) { 527 /* 528 * XXX: Need to get the actual revision 529 * XXX: number of the 2100 FB. At any rate, 530 * XXX: lower cache line size for early revision 531 * XXX; boards. 532 */ 533 linesz = 1; 534 } 535 } 536 #endif 537 #ifndef ISP_DISABLE_2200_SUPPORT 538 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 539 dstring = ": QLogic FC-AL and Fabric HBA\n"; 540 isp->isp_mdvec = &mdvec_2200; 541 isp->isp_type = ISP_HA_FC_2200; 542 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 543 if (isp->isp_param == NULL) { 544 printf(nomem, isp->isp_name); 545 return; 546 } 547 memset(isp->isp_param, 0, sizeof (fcparam)); 548 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 549 PCI_MBOX_REGS2100_OFF; 550 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 551 } 552 #endif 553 #ifndef ISP_DISABLE_2300_SUPPORT 554 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 555 pa->pa_id == PCI_QLOGIC_ISP2312) { 556 isp->isp_mdvec = &mdvec_2300; 557 if (pa->pa_id == PCI_QLOGIC_ISP2300) { 558 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 559 isp->isp_type = ISP_HA_FC_2300; 560 } else { 561 dstring = 562 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 563 isp->isp_type = ISP_HA_FC_2312; 564 isp->isp_port = pa->pa_function; 565 } 566 isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT); 567 if (isp->isp_param == NULL) { 568 printf(nomem, isp->isp_name); 569 return; 570 } 571 memset(isp->isp_param, 0, sizeof (fcparam)); 572 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 573 PCI_MBOX_REGS2300_OFF; 574 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 575 } 576 #endif 577 /* 578 * Set up logging levels. 579 */ 580 #ifdef ISP_LOGDEFAULT 581 isp->isp_dblev = ISP_LOGDEFAULT; 582 #else 583 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 584 if (bootverbose) 585 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 586 #ifdef SCSIDEBUG 587 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 588 #endif 589 #endif 590 if (isp->isp_dblev & ISP_LOGCONFIG) { 591 printf("\n"); 592 } else { 593 printf(dstring); 594 } 595 596 #ifdef DEBUG 597 if (oneshot) { 598 oneshot = 0; 599 isp_prt(isp, ISP_LOGCONFIG, vstring, 600 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 601 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 602 } 603 #endif 604 605 isp->isp_dmatag = pa->pa_dmat; 606 isp->isp_revision = rev; 607 608 /* 609 * Make sure that command register set sanely. 610 */ 611 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 612 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 613 614 /* 615 * Not so sure about these- but I think it's important that they get 616 * enabled...... 617 */ 618 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 619 if (IS_2300(isp)) { /* per QLogic errata */ 620 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 621 } 622 if (IS_23XX(isp)) { 623 isp->isp_touched = 1; 624 } 625 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 626 627 /* 628 * Make sure that the latency timer, cache line size, 629 * and ROM is disabled. 630 */ 631 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 632 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 633 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 634 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 635 data |= (linesz << PCI_CACHELINE_SHIFT); 636 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 637 638 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 639 data &= ~1; 640 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 641 642 if (pci_intr_map(pa, &ih)) { 643 printf("%s: couldn't map interrupt\n", isp->isp_name); 644 free(isp->isp_param, M_DEVBUF); 645 return; 646 } 647 intrstr = pci_intr_string(pa->pa_pc, ih); 648 if (intrstr == NULL) 649 intrstr = "<I dunno>"; 650 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 651 isp_pci_intr, isp); 652 if (pcs->pci_ih == NULL) { 653 printf("%s: couldn't establish interrupt at %s\n", 654 isp->isp_name, intrstr); 655 free(isp->isp_param, M_DEVBUF); 656 return; 657 } 658 659 printf("%s: interrupting at %s\n", isp->isp_name, intrstr); 660 661 if (IS_FC(isp)) { 662 DEFAULT_NODEWWN(isp) = 0x400000007F000002ULL; 663 DEFAULT_PORTWWN(isp) = 0x400000007F000002ULL; 664 } 665 666 isp->isp_confopts = self->dv_cfdata->cf_flags; 667 isp->isp_role = ISP_DEFAULT_ROLES; 668 ISP_LOCK(isp); 669 isp->isp_osinfo.no_mbox_ints = 1; 670 isp_reset(isp); 671 if (isp->isp_state != ISP_RESETSTATE) { 672 ISP_UNLOCK(isp); 673 free(isp->isp_param, M_DEVBUF); 674 return; 675 } 676 ENABLE_INTS(isp); 677 isp_init(isp); 678 if (isp->isp_state != ISP_INITSTATE) { 679 isp_uninit(isp); 680 ISP_UNLOCK(isp); 681 free(isp->isp_param, M_DEVBUF); 682 return; 683 } 684 /* 685 * Do platform attach. 686 */ 687 ISP_UNLOCK(isp); 688 isp_attach(isp); 689 if (isp->isp_state != ISP_RUNSTATE) { 690 ISP_LOCK(isp); 691 isp_uninit(isp); 692 free(isp->isp_param, M_DEVBUF); 693 ISP_UNLOCK(isp); 694 } 695 } 696 697 #define IspVirt2Off(a, x) \ 698 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 699 _BLK_REG_SHFT] + ((x) & 0xff)) 700 701 #define BXR2(pcs, off) \ 702 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 703 #define BXW2(pcs, off, v) \ 704 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 705 706 707 static INLINE int 708 isp_pci_rd_debounced(struct ispsoftc *isp, int off, u_int16_t *rp) 709 { 710 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 711 u_int16_t val0, val1; 712 int i = 0; 713 714 do { 715 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 716 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 717 } while (val0 != val1 && ++i < 1000); 718 if (val0 != val1) { 719 return (1); 720 } 721 *rp = val0; 722 return (0); 723 } 724 725 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 726 !defined(ISP_DISABLE_2200_SUPPORT) && \ 727 !defined(ISP_DISABLE_1020_SUPPORT) && \ 728 !defined(ISP_DISABLE_1080_SUPPORT) && \ 729 !defined(ISP_DISABLE_12160_SUPPORT) 730 static int 731 isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, 732 u_int16_t *semap, u_int16_t *mbp) 733 { 734 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 735 u_int16_t isr, sema; 736 737 if (IS_2100(isp)) { 738 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 739 return (0); 740 } 741 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 742 return (0); 743 } 744 } else { 745 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 746 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 747 } 748 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 749 isr &= INT_PENDING_MASK(isp); 750 sema &= BIU_SEMA_LOCK; 751 if (isr == 0 && sema == 0) { 752 return (0); 753 } 754 *isrp = isr; 755 if ((*semap = sema) != 0) { 756 if (IS_2100(isp)) { 757 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 758 return (0); 759 } 760 } else { 761 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 762 } 763 } 764 return (1); 765 } 766 #endif 767 768 #ifndef ISP_DISABLE_2300_SUPPORT 769 static int 770 isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, 771 u_int16_t *semap, u_int16_t *mbox0p) 772 { 773 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 774 u_int32_t r2hisr; 775 776 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 777 *isrp = 0; 778 return (0); 779 } 780 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 781 IspVirt2Off(pcs, BIU_R2HSTSLO)); 782 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 783 if ((r2hisr & BIU_R2HST_INTR) == 0) { 784 *isrp = 0; 785 return (0); 786 } 787 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 788 case ISPR2HST_ROM_MBX_OK: 789 case ISPR2HST_ROM_MBX_FAIL: 790 case ISPR2HST_MBX_OK: 791 case ISPR2HST_MBX_FAIL: 792 case ISPR2HST_ASYNC_EVENT: 793 *isrp = r2hisr & 0xffff; 794 *mbox0p = (r2hisr >> 16); 795 *semap = 1; 796 return (1); 797 case ISPR2HST_RIO_16: 798 *isrp = r2hisr & 0xffff; 799 *mbox0p = ASYNC_RIO1; 800 *semap = 1; 801 return (1); 802 case ISPR2HST_FPOST: 803 *isrp = r2hisr & 0xffff; 804 *mbox0p = ASYNC_CMD_CMPLT; 805 *semap = 1; 806 return (1); 807 case ISPR2HST_FPOST_CTIO: 808 *isrp = r2hisr & 0xffff; 809 *mbox0p = ASYNC_CTIO_DONE; 810 *semap = 1; 811 return (1); 812 case ISPR2HST_RSPQ_UPDATE: 813 *isrp = r2hisr & 0xffff; 814 *mbox0p = 0; 815 *semap = 0; 816 return (1); 817 default: 818 return (0); 819 } 820 } 821 #endif 822 823 static u_int16_t 824 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 825 { 826 u_int16_t rv; 827 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 828 int oldconf = 0; 829 830 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 831 /* 832 * We will assume that someone has paused the RISC processor. 833 */ 834 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 835 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 836 oldconf | BIU_PCI_CONF1_SXP); 837 } 838 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 839 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 840 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 841 } 842 return (rv); 843 } 844 845 static void 846 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) 847 { 848 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 849 int oldconf = 0; 850 851 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 852 /* 853 * We will assume that someone has paused the RISC processor. 854 */ 855 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 856 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 857 oldconf | BIU_PCI_CONF1_SXP); 858 } 859 BXW2(pcs, IspVirt2Off(isp, regoff), val); 860 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 861 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 862 } 863 } 864 865 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 866 static u_int16_t 867 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 868 { 869 u_int16_t rv, oc = 0; 870 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 871 872 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 873 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 874 u_int16_t tc; 875 /* 876 * We will assume that someone has paused the RISC processor. 877 */ 878 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 879 tc = oc & ~BIU_PCI1080_CONF1_DMA; 880 if (regoff & SXP_BANK1_SELECT) 881 tc |= BIU_PCI1080_CONF1_SXP1; 882 else 883 tc |= BIU_PCI1080_CONF1_SXP0; 884 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 885 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 886 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 887 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 888 oc | BIU_PCI1080_CONF1_DMA); 889 } 890 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 891 if (oc) { 892 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 893 } 894 return (rv); 895 } 896 897 static void 898 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) 899 { 900 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 901 int oc = 0; 902 903 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 904 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 905 u_int16_t tc; 906 /* 907 * We will assume that someone has paused the RISC processor. 908 */ 909 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 910 tc = oc & ~BIU_PCI1080_CONF1_DMA; 911 if (regoff & SXP_BANK1_SELECT) 912 tc |= BIU_PCI1080_CONF1_SXP1; 913 else 914 tc |= BIU_PCI1080_CONF1_SXP0; 915 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 916 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 917 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 918 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 919 oc | BIU_PCI1080_CONF1_DMA); 920 } 921 BXW2(pcs, IspVirt2Off(isp, regoff), val); 922 if (oc) { 923 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 924 } 925 } 926 #endif 927 928 static int 929 isp_pci_mbxdma(struct ispsoftc *isp) 930 { 931 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 932 bus_dma_tag_t dmat = isp->isp_dmatag; 933 bus_dma_segment_t sg; 934 bus_size_t len; 935 fcparam *fcp; 936 int rs, i; 937 938 if (isp->isp_rquest_dma) /* been here before? */ 939 return (0); 940 941 len = isp->isp_maxcmds * sizeof (XS_T *); 942 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK); 943 if (isp->isp_xflist == NULL) { 944 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 945 return (1); 946 } 947 memset(isp->isp_xflist, 0, len); 948 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 949 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 950 if (pcs->pci_xfer_dmap == NULL) { 951 free(isp->isp_xflist, M_DEVBUF); 952 isp->isp_xflist = NULL; 953 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array"); 954 return (1); 955 } 956 for (i = 0; i < isp->isp_maxcmds; i++) { 957 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 958 MAXPHYS, 0, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 959 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps"); 960 break; 961 } 962 } 963 if (i < isp->isp_maxcmds) { 964 while (--i >= 0) { 965 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 966 } 967 free(isp->isp_xflist, M_DEVBUF); 968 free(pcs->pci_xfer_dmap, M_DEVBUF); 969 isp->isp_xflist = NULL; 970 pcs->pci_xfer_dmap = NULL; 971 return (1); 972 } 973 974 /* 975 * Allocate and map the request queue. 976 */ 977 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 978 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 979 BUS_DMA_NOWAIT) || 980 bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 981 (caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 982 goto dmafail; 983 } 984 985 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 986 &isp->isp_rqdmap) || bus_dmamap_load(dmat, isp->isp_rqdmap, 987 (caddr_t)isp->isp_rquest, len, NULL, 988 BUS_DMA_NOWAIT)) { 989 goto dmafail; 990 } 991 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 992 993 /* 994 * Allocate and map the result queue. 995 */ 996 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 997 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 998 BUS_DMA_NOWAIT) || 999 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&isp->isp_result, 1000 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1001 goto dmafail; 1002 } 1003 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1004 &isp->isp_rsdmap) || bus_dmamap_load(isp->isp_dmatag, 1005 isp->isp_rsdmap, (caddr_t)isp->isp_result, len, NULL, 1006 BUS_DMA_NOWAIT)) { 1007 goto dmafail; 1008 } 1009 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 1010 1011 if (IS_SCSI(isp)) { 1012 return (0); 1013 } 1014 1015 fcp = isp->isp_param; 1016 len = ISP2100_SCRLEN; 1017 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1018 BUS_DMA_NOWAIT) || 1019 bus_dmamem_map(dmat, &sg, rs, len, (caddr_t *)&fcp->isp_scratch, 1020 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1021 goto dmafail; 1022 } 1023 if (bus_dmamap_create(dmat, len, 1, len, 0, BUS_DMA_NOWAIT, 1024 &isp->isp_scdmap) || bus_dmamap_load(dmat, 1025 isp->isp_scdmap, (caddr_t)fcp->isp_scratch, len, NULL, 1026 BUS_DMA_NOWAIT)) { 1027 goto dmafail; 1028 } 1029 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1030 return (0); 1031 dmafail: 1032 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure"); 1033 for (i = 0; i < isp->isp_maxcmds; i++) { 1034 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1035 } 1036 free(isp->isp_xflist, M_DEVBUF); 1037 free(pcs->pci_xfer_dmap, M_DEVBUF); 1038 isp->isp_xflist = NULL; 1039 pcs->pci_xfer_dmap = NULL; 1040 return (1); 1041 } 1042 1043 static int 1044 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, ispreq_t *rq, 1045 u_int16_t *nxtip, u_int16_t optr) 1046 { 1047 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1048 bus_dmamap_t dmap; 1049 u_int16_t starti = isp->isp_reqidx, nxti = *nxtip; 1050 ispreq_t *qep; 1051 int segcnt, seg, error, ovseg, seglim, drq; 1052 1053 qep = (ispreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, starti); 1054 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)]; 1055 if (xs->datalen == 0) { 1056 rq->req_seg_count = 1; 1057 goto mbxsync; 1058 } 1059 if (xs->xs_control & XS_CTL_DATA_IN) { 1060 drq = REQFLAG_DATA_IN; 1061 } else { 1062 drq = REQFLAG_DATA_OUT; 1063 } 1064 1065 if (IS_FC(isp)) { 1066 seglim = ISP_RQDSEG_T2; 1067 ((ispreqt2_t *)rq)->req_totalcnt = xs->datalen; 1068 ((ispreqt2_t *)rq)->req_flags |= drq; 1069 } else { 1070 rq->req_flags |= drq; 1071 if (XS_CDBLEN(xs) > 12) { 1072 seglim = 0; 1073 } else { 1074 seglim = ISP_RQDSEG; 1075 } 1076 } 1077 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1078 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? 1079 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 1080 ((xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1081 if (error) { 1082 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error); 1083 XS_SETERR(xs, HBA_BOTCH); 1084 if (error == EAGAIN || error == ENOMEM) 1085 return (CMD_EAGAIN); 1086 else 1087 return (CMD_COMPLETE); 1088 } 1089 1090 segcnt = dmap->dm_nsegs; 1091 1092 isp_prt(isp, ISP_LOGDEBUG2, "%d byte %s %p in %d segs", 1093 xs->datalen, (xs->xs_control & XS_CTL_DATA_IN)? "read to" : 1094 "write from", xs->data, segcnt); 1095 1096 for (seg = 0, rq->req_seg_count = 0; 1097 seglim && seg < segcnt && rq->req_seg_count < seglim; 1098 seg++, rq->req_seg_count++) { 1099 if (IS_FC(isp)) { 1100 ispreqt2_t *rq2 = (ispreqt2_t *)rq; 1101 rq2->req_dataseg[rq2->req_seg_count].ds_count = 1102 dmap->dm_segs[seg].ds_len; 1103 rq2->req_dataseg[rq2->req_seg_count].ds_base = 1104 dmap->dm_segs[seg].ds_addr; 1105 } else { 1106 rq->req_dataseg[rq->req_seg_count].ds_count = 1107 dmap->dm_segs[seg].ds_len; 1108 rq->req_dataseg[rq->req_seg_count].ds_base = 1109 dmap->dm_segs[seg].ds_addr; 1110 } 1111 isp_prt(isp, ISP_LOGDEBUG2, "seg0.[%d]={0x%lx,%lu}", 1112 rq->req_seg_count, (long) dmap->dm_segs[seg].ds_addr, 1113 (unsigned long) dmap->dm_segs[seg].ds_len); 1114 } 1115 1116 if (seg == segcnt) { 1117 goto dmasync; 1118 } 1119 1120 do { 1121 u_int16_t onxti; 1122 ispcontreq_t *crq, *cqe, local; 1123 1124 crq = &local; 1125 1126 cqe = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); 1127 onxti = nxti; 1128 nxti = ISP_NXT_QENTRY(onxti, RQUEST_QUEUE_LEN(isp)); 1129 if (nxti == optr) { 1130 isp_prt(isp, /* ISP_LOGDEBUG0 */ ISP_LOGERR, "Request Queue Overflow++"); 1131 bus_dmamap_unload(isp->isp_dmatag, dmap); 1132 XS_SETERR(xs, HBA_BOTCH); 1133 return (CMD_EAGAIN); 1134 } 1135 rq->req_header.rqs_entry_count++; 1136 memset((void *)crq, 0, sizeof (*crq)); 1137 crq->req_header.rqs_entry_count = 1; 1138 crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; 1139 1140 for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG; 1141 rq->req_seg_count++, seg++, ovseg++) { 1142 crq->req_dataseg[ovseg].ds_count = 1143 dmap->dm_segs[seg].ds_len; 1144 crq->req_dataseg[ovseg].ds_base = 1145 dmap->dm_segs[seg].ds_addr; 1146 isp_prt(isp, ISP_LOGDEBUG2, "seg%d.[%d]={0x%lx,%lu}", 1147 rq->req_header.rqs_entry_count - 1, 1148 rq->req_seg_count, (long)dmap->dm_segs[seg].ds_addr, 1149 (unsigned long) dmap->dm_segs[seg].ds_len); 1150 } 1151 isp_put_cont_req(isp, crq, cqe); 1152 MEMORYBARRIER(isp, SYNC_REQUEST, onxti, QENTRY_LEN); 1153 } while (seg < segcnt); 1154 1155 1156 dmasync: 1157 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1158 (xs->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_PREREAD : 1159 BUS_DMASYNC_PREWRITE); 1160 1161 mbxsync: 1162 switch (rq->req_header.rqs_entry_type) { 1163 case RQSTYPE_REQUEST: 1164 isp_put_request(isp, rq, qep); 1165 break; 1166 case RQSTYPE_CMDONLY: 1167 isp_put_extended_request(isp, (ispextreq_t *)rq, 1168 (ispextreq_t *)qep); 1169 break; 1170 case RQSTYPE_T2RQS: 1171 isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) qep); 1172 break; 1173 } 1174 *nxtip = nxti; 1175 return (CMD_QUEUED); 1176 } 1177 1178 static int 1179 isp_pci_intr(void *arg) 1180 { 1181 u_int16_t isr, sema, mbox; 1182 struct ispsoftc *isp = arg; 1183 1184 isp->isp_intcnt++; 1185 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1186 isp->isp_intbogus++; 1187 return (0); 1188 } else { 1189 isp->isp_osinfo.onintstack = 1; 1190 isp_intr(isp, isr, sema, mbox); 1191 isp->isp_osinfo.onintstack = 0; 1192 return (1); 1193 } 1194 } 1195 1196 static void 1197 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, u_int16_t handle) 1198 { 1199 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1200 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)]; 1201 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1202 xs->xs_control & XS_CTL_DATA_IN ? 1203 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1204 bus_dmamap_unload(isp->isp_dmatag, dmap); 1205 } 1206 1207 static void 1208 isp_pci_reset1(struct ispsoftc *isp) 1209 { 1210 /* Make sure the BIOS is disabled */ 1211 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1212 if (isp->isp_osinfo.no_mbox_ints == 0) { 1213 ENABLE_INTS(isp); 1214 } 1215 1216 } 1217 1218 static void 1219 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1220 { 1221 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1222 if (msg) 1223 printf("%s: %s\n", isp->isp_name, msg); 1224 if (IS_SCSI(isp)) 1225 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1226 else 1227 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1228 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1229 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1230 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1231 1232 1233 if (IS_SCSI(isp)) { 1234 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1235 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1236 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1237 ISP_READ(isp, CDMA_FIFO_STS)); 1238 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1239 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1240 ISP_READ(isp, DDMA_FIFO_STS)); 1241 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1242 ISP_READ(isp, SXP_INTERRUPT), 1243 ISP_READ(isp, SXP_GROSS_ERR), 1244 ISP_READ(isp, SXP_PINS_CTRL)); 1245 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1246 } 1247 printf(" mbox regs: %x %x %x %x %x\n", 1248 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1249 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1250 ISP_READ(isp, OUTMAILBOX4)); 1251 printf(" PCI Status Command/Status=%x\n", 1252 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1253 }
Cache object: 87005f9535d8bb5544b38def060783a8
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