FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/mlyreg.h
1 /* $NetBSD: mlyreg.h,v 1.1 2001/07/30 19:59:07 ad Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran, Thor Lancelot Simon, and Eric Haszlakiewicz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*-
40 * Copyright (c) 2000 Michael Smith
41 * Copyright (c) 2000 BSDi
42 * All rights reserved.
43 *
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
46 * are met:
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63 * SUCH DAMAGE.
64 *
65 * from FreeBSD: mlyreg.h,v 1.1 2000/08/23 03:22:39 msmith Exp
66 */
67
68 /*
69 * Section numbers in this document refer to the Mylex "Firmware Software Interface"
70 * document ('FSI'), revision 0.11 04/11/00 unless otherwise qualified.
71 *
72 * Reference is made to the Mylex "Programming Guide for 6.x Controllers" document
73 * ('PG6'), document #771242 revision 0.02, 04/11/00
74 *
75 * Note that fields marked N/A are not supported by the PCI controllers, but are
76 * defined here to hold place in datastructures that are shared with the SCSI
77 * controllers. Items not relevant to PCI controllers are not described here.
78 *
79 * Ordering of items in this file is a little odd due to the constraints of
80 * nested declarations.
81 */
82
83 #ifndef _PCI_MLYREG_H_
84 #define _PCI_MLYREG_H_
85
86 /*
87 * 2.1 (Scatter Gather List Format)
88 */
89 struct mly_sg_entry {
90 u_int64_t physaddr;
91 u_int64_t length;
92 } __attribute__ ((__packed__));
93
94 /*
95 * 5.2 System Device Access
96 *
97 * This is corroborated by the layout of the MDACIOCTL_GETCONTROLLERINFO data
98 * in 21.8
99 */
100 #define MLY_MAX_CHANNELS 6
101 #define MLY_MAX_TARGETS 16
102 #define MLY_MAX_LUNS 1
103
104 /*
105 * 8.1 Different Device States
106 */
107 #define MLY_DEVICE_STATE_OFFLINE 0x08 /* DEAD/OFFLINE */
108 #define MLY_DEVICE_STATE_UNCONFIGURED 0x00
109 #define MLY_DEVICE_STATE_ONLINE 0x01
110 #define MLY_DEVICE_STATE_CRITICAL 0x09
111 #define MLY_DEVICE_STATE_WRITEONLY 0x03
112 #define MLY_DEVICE_STATE_STANDBY 0x21
113 #define MLY_DEVICE_STATE_MISSING 0x04 /* or-ed with (ONLINE or WRITEONLY or STANDBY) */
114
115 /*
116 * 8.2 Device Type Field definitions
117 */
118 #define MLY_DEVICE_TYPE_RAID0 0x0 /* RAID 0 */
119 #define MLY_DEVICE_TYPE_RAID1 0x1 /* RAID 1 */
120 #define MLY_DEVICE_TYPE_RAID3 0x3 /* RAID 3 right asymmetric parity */
121 #define MLY_DEVICE_TYPE_RAID5 0x5 /* RAID 5 right asymmetric parity */
122 #define MLY_DEVICE_TYPE_RAID6 0x6 /* RAID 6 (Mylex RAID 6) */
123 #define MLY_DEVICE_TYPE_RAID7 0x7 /* RAID 7 (JBOD) */
124 #define MLY_DEVICE_TYPE_NEWSPAN 0x8 /* New Mylex SPAN */
125 #define MLY_DEVICE_TYPE_RAID3F 0x9 /* RAID 3 fixed parity */
126 #define MLY_DEVICE_TYPE_RAID3L 0xb /* RAID 3 left symmetric parity */
127 #define MLY_DEVICE_TYPE_SPAN 0xc /* current spanning implementation */
128 #define MLY_DEVICE_TYPE_RAID5L 0xd /* RAID 5 left symmetric parity */
129 #define MLY_DEVICE_TYPE_RAIDE 0xe /* RAID E (concatenation) */
130 #define MLY_DEVICE_TYPE_PHYSICAL 0xf /* physical device */
131
132 /*
133 * 8.3 Stripe Size
134 */
135 #define MLY_STRIPE_ZERO 0x0 /* no stripe (RAID 1, RAID 7, etc) */
136 #define MLY_STRIPE_512b 0x1
137 #define MLY_STRIPE_1k 0x2
138 #define MLY_STRIPE_2k 0x3
139 #define MLY_STRIPE_4k 0x4
140 #define MLY_STRIPE_8k 0x5
141 #define MLY_STRIPE_16k 0x6
142 #define MLY_STRIPE_32k 0x7
143 #define MLY_STRIPE_64k 0x8
144 #define MLY_STRIPE_128k 0x9
145 #define MLY_STRIPE_256k 0xa
146 #define MLY_STRIPE_512k 0xb
147 #define MLY_STRIPE_1m 0xc
148
149 /*
150 * 8.4 Cacheline Size
151 */
152 #define MLY_CACHELINE_ZERO 0x0 /* caching cannot be enabled */
153 #define MLY_CACHELINE_512b 0x1
154 #define MLY_CACHELINE_1k 0x2
155 #define MLY_CACHELINE_2k 0x3
156 #define MLY_CACHELINE_4k 0x4
157 #define MLY_CACHELINE_8k 0x5
158 #define MLY_CACHELINE_16k 0x6
159 #define MLY_CACHELINE_32k 0x7
160 #define MLY_CACHELINE_64k 0x8
161
162 /*
163 * 8.5 Read/Write control
164 */
165 #define MLY_RWCtl_INITTED (1<<7) /* if set, the logical device is initialised */
166 /* write control */
167 #define MLY_RWCtl_WCD (0) /* write cache disabled */
168 #define MLY_RWCtl_WDISABLE (1<<3) /* writing disabled */
169 #define MLY_RWCtl_WCE (2<<3) /* write cache enabled */
170 #define MLY_RWCtl_IWCE (3<<3) /* intelligent write cache enabled */
171 /* read control */
172 #define MLY_RWCtl_RCD (0) /* read cache is disabled */
173 #define MLY_RWCtl_RCE (1) /* read cache enabled */
174 #define MLY_RWCtl_RAHEAD (2) /* readahead enabled */
175 #define MLY_RWCtl_IRAHEAD (3) /* intelligent readahead enabled */
176
177 /*
178 * 9.0 LUN Map Format
179 */
180 struct mly_lun_map {
181 u_int8_t res1:4;
182 u_int8_t host_port_mapped:1; /* this system drive visibile to host on this controller/port combination */
183 u_int8_t tid_valid:1; /* target ID valid */
184 u_int8_t hid_valid:1; /* host ID valid */
185 u_int8_t lun_valid:1; /* LUN valid */
186 u_int8_t res2;
187 u_int8_t lun; /* LUN */
188 u_int8_t tid; /* TID */
189 u_int8_t hid[32]; /* HID (one bit for each host) */
190 } __attribute__ ((__packed__));
191
192 /*
193 * 10.1 Controller Parameters
194 */
195 struct mly_param_controller {
196 u_int8_t rdahen:1; /* N/A */
197 u_int8_t bilodly:1; /* N/A */
198 u_int8_t fua_disable:1;
199 u_int8_t reass1s:1; /* N/A */
200 u_int8_t truvrfy:1; /* N/A */
201 u_int8_t dwtvrfy:1; /* N/A */
202 u_int8_t background_initialisation:1;
203 u_int8_t clustering:1; /* N/A */
204
205 u_int8_t bios_disable:1;
206 u_int8_t boot_from_cdrom:1;
207 u_int8_t drive_coercion:1;
208 u_int8_t write_same_disable:1;
209 u_int8_t hba_mode:1; /* N/A */
210 u_int8_t bios_geometry:2;
211 #define MLY_BIOSGEOM_2G 0x0
212 #define MLY_BIOSGEOM_8G 0x1
213 u_int8_t res1:1; /* N/A */
214
215 u_int8_t res2[2]; /* N/A */
216
217 u_int8_t v_dec:1;
218 u_int8_t safte:1; /* N/A */
219 u_int8_t ses:1; /* N/A */
220 u_int8_t res3:2; /* N/A */
221 u_int8_t v_arm:1;
222 u_int8_t v_ofm:1;
223 u_int8_t res4:1; /* N/A */
224
225 u_int8_t rebuild_check_rate;
226 u_int8_t cache_line_size; /* see 8.4 */
227 u_int8_t oem_code;
228 #define MLY_OEM_MYLEX 0x00
229 #define MLY_OEM_IBM 0x08
230 #define MLY_OEM_HP 0x0a
231 #define MLY_OEM_DEC 0x0c
232 #define MLY_OEM_SIEMENS 0x10
233 #define MLY_OEM_INTEL 0x12
234 u_int8_t spinup_mode;
235 #define MLY_SPIN_AUTO 0
236 #define MLY_SPIN_PWRSPIN 1
237 #define MLY_SPIN_WSSUSPIN 2
238 u_int8_t spinup_devices;
239 u_int8_t spinup_interval;
240 u_int8_t spinup_wait_time;
241
242 u_int8_t res5:3; /* N/A */
243 u_int8_t vutursns:1; /* N/A */
244 u_int8_t dccfil:1; /* N/A */
245 u_int8_t nopause:1; /* N/A */
246 u_int8_t disqfull:1; /* N/A */
247 u_int8_t disbusy:1; /* N/A */
248
249 u_int8_t res6:2; /* N/A */
250 u_int8_t failover_node_name; /* N/A */
251 u_int8_t res7:1; /* N/A */
252 u_int8_t ftopo:3; /* N/A */
253 u_int8_t disable_ups:1; /* N/A */
254
255 u_int8_t res8:1; /* N/A */
256 u_int8_t propagate_reset:1; /* N/A */
257 u_int8_t nonstd_mp_reset:1; /* N/A */
258 u_int8_t res9:5; /* N/A */
259
260 u_int8_t res10; /* N/A */
261 u_int8_t serial_port_baud_rate; /* N/A */
262 u_int8_t serial_port_control; /* N/A */
263 u_int8_t change_stripe_ok_developer_flag_only; /* N/A */
264
265 u_int8_t small_large_host_transfers:2; /* N/A */
266 u_int8_t frame_control:2; /* N/A */
267 u_int8_t pci_latency_control:2; /* N/A */
268 u_int8_t treat_lip_as_reset:1; /* N/A */
269 u_int8_t res11:1; /* N/A */
270
271 u_int8_t ms_autorest:1; /* N/A */
272 u_int8_t res12:7; /* N/A */
273
274 u_int8_t ms_aa_fsim:1; /* N/A */
275 u_int8_t ms_aa_ccach:1; /* N/A */
276 u_int8_t ms_aa_fault_signals:1; /* N/A */
277 u_int8_t ms_aa_c4_faults:1; /* N/A */
278 u_int8_t ms_aa_host_reset_delay_mask:4; /* N/A */
279
280 u_int8_t ms_flg_simplex_no_rstcom:1; /* N/A */
281 u_int8_t res13:7; /* N/A */
282
283 u_int8_t res14; /* N/A */
284 u_int8_t hardloopid[2][2]; /* N/A */
285 u_int8_t ctrlname[2][16+1]; /* N/A */
286 u_int8_t initiator_id;
287 u_int8_t startup_option;
288 #define MLY_STARTUP_IF_NO_CHANGE 0x0
289 #define MLY_STARTUP_IF_NO_LUN_CHANGE 0x1
290 #define MLY_STARTUP_IF_NO_LUN_OFFLINE 0x2
291 #define MLY_STARTUP_IF_LUN0_NO_CHANGE 0x3
292 #define MLY_STARTUP_IF_LUN0_NOT_OFFLINE 0x4
293 #define MLY_STARTUP_ALWAYS 0x5
294
295 u_int8_t res15[62];
296 } __attribute__ ((__packed__));
297
298 /*
299 * 10.2 Physical Device Parameters
300 */
301 struct mly_param_physical_device {
302 u_int16_t tags;
303 u_int16_t speed;
304 u_int8_t width;
305 u_int8_t combing:1;
306 u_int8_t res1:7;
307 u_int8_t res2[3];
308 } __attribute__ ((__packed__));
309
310 /*
311 * 10.3 Logical Device Parameters
312 */
313 struct mly_param_logical_device {
314 u_int8_t type; /* see 8.2 */
315 u_int8_t state; /* see 8.1 */
316 u_int16_t raid_device;
317 u_int8_t res1;
318 u_int8_t bios_geometry; /* BIOS control word? */
319 u_int8_t stripe_size; /* see 8.3 */
320 u_int8_t read_write_control; /* see 8.5 */
321 u_int8_t res2[8];
322 } __attribute__ ((__packed__));
323
324 /*
325 * 12.3 Health Status Buffer
326 *
327 * Pad to 128 bytes.
328 */
329 struct mly_health_status {
330 u_int32_t uptime_us; /* N/A */
331 u_int32_t uptime_ms; /* N/A */
332 u_int32_t realtime; /* N/A */
333 u_int32_t res1; /* N/A */
334 u_int32_t change_counter;
335 u_int32_t res2; /* N/A */
336 u_int32_t debug_message_index; /* N/A */
337 u_int32_t bios_message_index; /* N/A */
338 u_int32_t trace_page; /* N/A */
339 u_int32_t profiler_page; /* N/A */
340 u_int32_t next_event;
341 u_int8_t res3[4 + 16 + 64]; /* N/A */
342 } __attribute__ ((__packed__));
343
344 /*
345 * 14.2 Timeout Bit Format
346 */
347 #define MLY_TIMEOUT_SECONDS 0x00
348 #define MLY_TIMEOUT_MINUTES 0x40
349 #define MLY_TIMEOUT_HOURS 0x80
350
351 /*
352 * 14.3 Operation Device
353 */
354 #define MLY_OPDEVICE_PHYSICAL_DEVICE 0x0
355 #define MLY_OPDEVICE_RAID_DEVICE 0x1
356 #define MLY_OPDEVICE_PHYSICAL_CHANNEL 0x2
357 #define MLY_OPDEVICE_RAID_CHANNEL 0x3
358 #define MLY_OPDEVICE_PHYSICAL_CONTROLLER 0x4
359 #define MLY_OPDEVICE_RAID_CONTROLLER 0x5
360 #define MLY_OPDEVICE_CONFIGURATION_GROUP 0x10
361
362 /*
363 * 14.4 Status Bit Format
364 *
365 * AKA Status Mailbox Format
366 *
367 * XXX format conflict between FSI and PG6 over the ordering of the
368 * status and sense length fields.
369 */
370 struct mly_status {
371 u_int16_t command_id;
372 u_int8_t status;
373 u_int8_t sense_length;
374 int32_t residue;
375 } __attribute__ ((__packed__));
376
377 /*
378 * 14.5 Command Control Bit (CCB) format
379 *
380 * This byte is unfortunately named.
381 */
382 #define MLY_CMDCTL_FORCE_UNIT_ACCESS 0x01
383 #define MLY_CMDCTL_DISABLE_PAGE_OUT 0x02
384 #define MLY_CMDCTL_EXTENDED_SG_TABLE 0x08
385 #define MLY_CMDCTL_DATA_DIRECTION 0x10
386 #define MLY_CMDCTL_NO_AUTO_SENSE 0x40
387 #define MLY_CMDCTL_DISABLE_DISCONNECT 0x80
388
389 /*
390 * 15.0 Commands
391 *
392 * We use the command names as given by Mylex
393 */
394 #define MDACMD_MEMCOPY 0x1 /* memory to memory copy */
395 #define MDACMD_SCSIPT 0x2 /* SCSI passthrough (small command) */
396 #define MDACMD_SCSILCPT 0x3 /* SCSI passthrough (large command) */
397 #define MDACMD_SCSI 0x4 /* SCSI command for logical/phyiscal device (small command) */
398 #define MDACMD_SCSILC 0x5 /* SCSI command for logical/phyiscal device (large command) */
399 #define MDACMD_IOCTL 0x20 /* Management command */
400 #define MDACMD_IOCTLCHECK 0x23 /* Validate management command (not implemented) */
401
402 /*
403 * 16.0 IOCTL command
404 *
405 * We use the IOCTL names as given by Mylex
406 * Note that only ioctls supported by the PCI controller family are listed
407 */
408 #define MDACIOCTL_GETCONTROLLERINFO 0x1
409 #define MDACIOCTL_GETLOGDEVINFOVALID 0x3
410 #define MDACIOCTL_GETPHYSDEVINFOVALID 0x5
411 #define MDACIOCTL_GETCONTROLLERSTATISTICS 0xb
412 #define MDACIOCTL_GETLOGDEVSTATISTICS 0xd
413 #define MDACIOCTL_GETPHYSDEVSTATISTICS 0xf
414 #define MDACIOCTL_GETHEALTHSTATUS 0x11
415 #define MDACIOCTL_GETEVENT 0x15
416 /* flash update */
417 #define MDACIOCTL_STOREIMAGE 0x2c
418 #define MDACIOCTL_READIMAGE 0x2d
419 #define MDACIOCTL_FLASHIMAGES 0x2e
420 /* battery backup unit */
421 #define MDACIOCTL_GET_SUBSYSTEM_DATA 0x70
422 #define MDACIOCTL_SET_SUBSYSTEM_DATA 0x71
423 /* non-data commands */
424 #define MDACIOCTL_STARTDISOCVERY 0x81
425 #define MDACIOCTL_SETRAIDDEVSTATE 0x82
426 #define MDACIOCTL_INITPHYSDEVSTART 0x84
427 #define MDACIOCTL_INITPHYSDEVSTOP 0x85
428 #define MDACIOCTL_INITRAIDDEVSTART 0x86
429 #define MDACIOCTL_INITRAIDDEVSTOP 0x87
430 #define MDACIOCTL_REBUILDRAIDDEVSTART 0x88
431 #define MDACIOCTL_REBUILDRAIDDEVSTOP 0x89
432 #define MDACIOCTL_MAKECONSISTENTDATASTART 0x8a
433 #define MDACIOCTL_MAKECONSISTENTDATASTOP 0x8b
434 #define MDACIOCTL_CONSISTENCYCHECKSTART 0x8c
435 #define MDACIOCTL_CONSISTENCYCHECKSTOP 0x8d
436 #define MDACIOCTL_SETMEMORYMAILBOX 0x8e
437 #define MDACIOCTL_RESETDEVICE 0x90
438 #define MDACIOCTL_FLUSHDEVICEDATA 0x91
439 #define MDACIOCTL_PAUSEDEVICE 0x92
440 #define MDACIOCTL_UNPAUSEDEVICE 0x93
441 #define MDACIOCTL_LOCATEDEVICE 0x94
442 #define MDACIOCTL_SETMASTERSLAVEMODE 0x95
443 #define MDACIOCTL_SETREALTIMECLOCK 0xac
444 /* RAID configuration */
445 #define MDACIOCTL_CREATENEWCONF 0xc0
446 #define MDACIOCTL_DELETERAIDDEV 0xc1
447 #define MDACIOCTL_REPLACEINTERNALDEV 0xc2
448 #define MDACIOCTL_RENAMERAIDDEV 0xc3
449 #define MDACIOCTL_ADDNEWCONF 0xc4
450 #define MDACIOCTL_XLATEPHYSDEVTORAIDDEV 0xc5
451 #define MDACIOCTL_MORE 0xc6
452 #define MDACIOCTL_SETPHYSDEVPARAMETER 0xc8
453 #define MDACIOCTL_GETPHYSDEVPARAMETER 0xc9
454 #define MDACIOCTL_CLEARCONF 0xca
455 #define MDACIOCTL_GETDEVCONFINFO 0xcb
456 #define MDACIOCTL_GETGROUPCONFINFO 0xcc
457 #define MDACIOCTL_GETFREESPACELIST 0xcd
458 #define MDACIOCTL_GETLOGDEVPARAMETER 0xce
459 #define MDACIOCTL_SETLOGDEVPARAMETER 0xcf
460 #define MDACIOCTL_GETCONTROLLERPARAMETER 0xd0
461 #define MDACIOCTL_SETCONTRLLERPARAMETER 0xd1
462 #define MDACIOCTL_CLEARCONFSUSPMODE 0xd2
463 #define MDACIOCTL_GETBDT_FOR_SYSDRIVE 0xe0
464
465 /*
466 * 17.1.4 Data Transfer Memory Address Without SG List
467 */
468 struct mly_short_transfer {
469 struct mly_sg_entry sg[2];
470 } __attribute__ ((__packed__));
471
472 /*
473 * 17.1.5 Data Transfer Memory Address With SG List
474 *
475 * Note that only the first s/g table is currently used.
476 */
477 struct mly_sg_transfer {
478 u_int16_t entries[3];
479 u_int16_t res1;
480 u_int64_t table_physaddr[3];
481 } __attribute__ ((__packed__));
482
483 /*
484 * 17.1.3 Data Transfer Memory Address Format
485 */
486 union mly_cmd_transfer {
487 struct mly_short_transfer direct;
488 struct mly_sg_transfer indirect;
489 };
490
491 /*
492 * 21.1 MDACIOCTL_SETREALTIMECLOCK
493 * 21.7 MDACIOCTL_GETHEALTHSTATUS
494 * 21.8 MDACIOCTL_GETCONTROLLERINFO
495 * 21.9 MDACIOCTL_GETLOGDEVINFOVALID
496 * 21.10 MDACIOCTL_GETPHYSDEVINFOVALID
497 * 21.11 MDACIOCTL_GETPHYSDEVSTATISTICS
498 * 21.12 MDACIOCTL_GETLOGDEVSTATISTICS
499 * 21.13 MDACIOCTL_GETCONTROLLERSTATISTICS
500 * 21.27 MDACIOCTL_GETBDT_FOR_SYSDRIVE
501 * 23.4 MDACIOCTL_CREATENEWCONF
502 * 23.5 MDACIOCTL_ADDNEWCONF
503 * 23.8 MDACIOCTL_GETDEVCONFINFO
504 * 23.9 MDACIOCTL_GETFREESPACELIST
505 * 24.1 MDACIOCTL_MORE
506 * 25.1 MDACIOCTL_GETPHYSDEVPARAMETER
507 * 25.2 MDACIOCTL_SETPHYSDEVPARAMETER
508 * 25.3 MDACIOCTL_GETLOGDEVPARAMETER
509 * 25.4 MDACIOCTL_SETLOGDEVPARAMETER
510 * 25.5 MDACIOCTL_GETCONTROLLERPARAMETER
511 * 25.6 MDACIOCTL_SETCONTROLLERPARAMETER
512 *
513 * These commands just transfer data
514 */
515 struct mly_ioctl_param_data {
516 u_int8_t param[10];
517 union mly_cmd_transfer transfer;
518 } __attribute__ ((__packed__));
519
520 /*
521 * 21.2 MDACIOCTL_SETMEMORYMAILBOX
522 */
523 struct mly_ioctl_param_setmemorymailbox {
524 u_int8_t health_buffer_size;
525 u_int8_t res1;
526 u_int64_t health_buffer_physaddr;
527 u_int64_t command_mailbox_physaddr;
528 u_int64_t status_mailbox_physaddr;
529 u_int64_t res2[2];
530 } __attribute__ ((__packed__));
531
532 /*
533 * 21.8.2 MDACIOCTL_GETCONTROLLERINFO: Data Format
534 */
535 struct mly_ioctl_getcontrollerinfo {
536 u_int8_t res1; /* N/A */
537 u_int8_t interface_type;
538 u_int8_t controller_type;
539 u_int8_t res2; /* N/A */
540 u_int16_t interface_speed;
541 u_int8_t interface_width;
542 u_int8_t res3[9]; /* N/A */
543 char interface_name[16];
544 char controller_name[16];
545 u_int8_t res4[16]; /* N/A */
546 /* firmware release information */
547 u_int8_t fw_major;
548 u_int8_t fw_minor;
549 u_int8_t fw_turn;
550 u_int8_t fw_build;
551 u_int8_t fw_day;
552 u_int8_t fw_month;
553 u_int8_t fw_century;
554 u_int8_t fw_year;
555 /* hardware release information */
556 u_int8_t hw_revision; /* N/A */
557 u_int8_t res5[3]; /* N/A */
558 u_int8_t hw_release_day; /* N/A */
559 u_int8_t hw_release_month; /* N/A */
560 u_int8_t hw_release_century; /* N/A */
561 u_int8_t hw_release_year; /* N/A */
562 /* hardware manufacturing information */
563 u_int8_t batch_number; /* N/A */
564 u_int8_t res6; /* N/A */
565 u_int8_t plant_number;
566 u_int8_t res7;
567 u_int8_t hw_manuf_day;
568 u_int8_t hw_manuf_month;
569 u_int8_t hw_manuf_century;
570 u_int8_t hw_manuf_year;
571 u_int8_t max_pdd_per_xldd;
572 u_int8_t max_ildd_per_xldd;
573 u_int16_t nvram_size;
574 u_int8_t max_number_of_xld; /* N/A */
575 u_int8_t res8[3]; /* N/A */
576 /* unique information per controller */
577 char serial_number[16];
578 u_int8_t res9[16]; /* N/A */
579 /* vendor information */
580 u_int8_t res10[3]; /* N/A */
581 u_int8_t oem_information;
582 char vendor_name[16]; /* N/A */
583 /* other physical/controller/operation information */
584 u_int8_t bbu_present:1;
585 u_int8_t active_clustering:1;
586 u_int8_t res11:6; /* N/A */
587 u_int8_t res12[3]; /* N/A */
588 /* physical device scan information */
589 u_int8_t physical_scan_active:1;
590 u_int8_t res13:7; /* N/A */
591 u_int8_t physical_scan_channel;
592 u_int8_t physical_scan_target;
593 u_int8_t physical_scan_lun;
594 /* maximum command data transfer size */
595 u_int16_t maximum_block_count;
596 u_int16_t maximum_sg_entries;
597 /* logical/physical device counts */
598 u_int16_t logical_devices_present;
599 u_int16_t logical_devices_critical;
600 u_int16_t logical_devices_offline;
601 u_int16_t physical_devices_present;
602 u_int16_t physical_disks_present;
603 u_int16_t physical_disks_critical; /* N/A */
604 u_int16_t physical_disks_offline;
605 u_int16_t maximum_parallel_commands;
606 /* channel and target ID information */
607 u_int8_t physical_channels_present;
608 u_int8_t virtual_channels_present;
609 u_int8_t physical_channels_possible;
610 u_int8_t virtual_channels_possible;
611 u_int8_t maximum_targets_possible[16]; /* N/A (6 and up) */
612 u_int8_t res14[12]; /* N/A */
613 /* memory/cache information */
614 u_int16_t memory_size;
615 u_int16_t cache_size;
616 u_int32_t valid_cache_size; /* N/A */
617 u_int32_t dirty_cache_size; /* N/A */
618 u_int16_t memory_speed;
619 u_int8_t memory_width;
620 u_int8_t memory_type:5;
621 u_int8_t res15:1; /* N/A */
622 u_int8_t memory_parity:1;
623 u_int8_t memory_ecc:1;
624 char memory_information[16]; /* N/A */
625 /* execution memory information */
626 u_int16_t exmemory_size;
627 u_int16_t l2cache_size; /* N/A */
628 u_int8_t res16[8]; /* N/A */
629 u_int16_t exmemory_speed;
630 u_int8_t exmemory_width;
631 u_int8_t exmemory_type:5;
632 u_int8_t res17:1; /* N/A */
633 u_int8_t exmemory_parity:1;
634 u_int8_t exmemory_ecc:1;
635 char exmemory_name[16]; /* N/A */
636 /* CPU information */
637 struct {
638 u_int16_t speed;
639 u_int8_t type;
640 u_int8_t number;
641 u_int8_t res1[12]; /* N/A */
642 char name[16]; /* N/A */
643 } cpu[2] __attribute__ ((__packed__));
644 /* debugging/profiling/command time tracing information */
645 u_int16_t profiling_page; /* N/A */
646 u_int16_t profiling_programs; /* N/A */
647 u_int16_t time_trace_page; /* N/A */
648 u_int16_t time_trace_programs; /* N/A */
649 u_int8_t res18[8]; /* N/A */
650 /* error counters on physical devices */
651 u_int16_t physical_device_bus_resets; /* N/A */
652 u_int16_t physical_device_parity_errors; /* N/A */
653 u_int16_t physical_device_soft_errors; /* N/A */
654 u_int16_t physical_device_commands_failed; /* N/A */
655 u_int16_t physical_device_miscellaneous_errors; /* N/A */
656 u_int16_t physical_device_command_timeouts; /* N/A */
657 u_int16_t physical_device_selection_timeouts; /* N/A */
658 u_int16_t physical_device_retries; /* N/A */
659 u_int16_t physical_device_aborts; /* N/A */
660 u_int16_t physical_device_host_command_aborts; /* N/A */
661 u_int16_t physical_device_PFAs_detected; /* N/A */
662 u_int16_t physical_device_host_commands_failed; /* N/A */
663 u_int8_t res19[8]; /* N/A */
664 /* error counters on logical devices */
665 u_int16_t logical_device_soft_errors; /* N/A */
666 u_int16_t logical_device_commands_failed; /* N/A */
667 u_int16_t logical_device_host_command_aborts; /* N/A */
668 u_int16_t res20; /* N/A */
669 /* error counters on controller */
670 u_int16_t controller_parity_ecc_errors;
671 u_int16_t controller_host_command_aborts; /* N/A */
672 u_int8_t res21[4]; /* N/A */
673 /* long duration activity information */
674 u_int16_t background_inits_active;
675 u_int16_t logical_inits_active;
676 u_int16_t physical_inits_active;
677 u_int16_t consistency_checks_active;
678 u_int16_t rebuilds_active;
679 u_int16_t MORE_active;
680 u_int16_t patrol_active; /* N/A */
681 u_int8_t long_operation_status; /* N/A */
682 u_int8_t res22; /* N/A */
683 /* flash ROM information */
684 u_int8_t flash_type; /* N/A */
685 u_int8_t res23; /* N/A */
686 u_int16_t flash_size;
687 u_int32_t flash_maximum_age;
688 u_int32_t flash_age;
689 u_int8_t res24[4]; /* N/A */
690 char flash_name[16]; /* N/A */
691 /* firmware runtime information */
692 u_int8_t rebuild_rate;
693 u_int8_t background_init_rate;
694 u_int8_t init_rate;
695 u_int8_t consistency_check_rate;
696 u_int8_t res25[4]; /* N/A */
697 u_int32_t maximum_dp;
698 u_int32_t free_dp;
699 u_int32_t maximum_iop;
700 u_int32_t free_iop;
701 u_int16_t maximum_comb_length;
702 u_int16_t maximum_configuration_groups;
703 u_int8_t installation_abort:1;
704 u_int8_t maintenance:1;
705 u_int8_t res26:6; /* N/A */
706 u_int8_t res27[3]; /* N/A */
707 u_int8_t res28[32 + 512]; /* N/A */
708 } __attribute__ ((__packed__));
709
710 /*
711 * 21.9.2 MDACIOCTL_GETLOGDEVINFOVALID
712 */
713 struct mly_ioctl_getlogdevinfovalid {
714 u_int8_t res1; /* N/A */
715 u_int8_t channel;
716 u_int8_t target;
717 u_int8_t lun;
718 u_int8_t state; /* see 8.1 */
719 u_int8_t raid_level; /* see 8.2 */
720 u_int8_t stripe_size; /* see 8.3 */
721 u_int8_t cache_line_size; /* see 8.4 */
722 u_int8_t read_write_control; /* see 8.5 */
723 u_int8_t consistency_check:1;
724 u_int8_t rebuild:1;
725 u_int8_t make_consistent:1;
726 u_int8_t initialisation:1;
727 u_int8_t migration:1;
728 u_int8_t patrol:1;
729 u_int8_t res2:2; /* N/A */
730 u_int8_t ar5_limit;
731 u_int8_t ar5_algo;
732 u_int16_t logical_device_number;
733 u_int16_t bios_control;
734 /* erorr counters */
735 u_int16_t soft_errors; /* N/A */
736 u_int16_t commands_failed; /* N/A */
737 u_int16_t host_command_aborts; /* N/A */
738 u_int16_t deferred_write_errors; /* N/A */
739 u_int8_t res3[8]; /* N/A */
740 /* device size information */
741 u_int8_t res4[2]; /* N/A */
742 u_int16_t device_block_size;
743 u_int32_t original_device_size; /* N/A */
744 u_int32_t device_size; /* XXX "blocks or MB" Huh? */
745 u_int8_t res5[4]; /* N/A */
746 char device_name[32]; /* N/A */
747 u_int8_t inquiry[36];
748 u_int8_t res6[12]; /* N/A */
749 u_int64_t last_read_block; /* N/A */
750 u_int64_t last_written_block; /* N/A */
751 u_int64_t consistency_check_block;
752 u_int64_t rebuild_block;
753 u_int64_t make_consistent_block;
754 u_int64_t initialisation_block;
755 u_int64_t migration_block;
756 u_int64_t patrol_block; /* N/A */
757 u_int8_t res7[64]; /* N/A */
758 } __attribute__ ((__packed__));
759
760 /*
761 * 21.10.2 MDACIOCTL_GETPHYSDEVINFOVALID: Data Format
762 */
763 struct mly_ioctl_getphysdevinfovalid {
764 u_int8_t res1;
765 u_int8_t channel;
766 u_int8_t target;
767 u_int8_t lun;
768 u_int8_t raid_ft:1; /* configuration status */
769 u_int8_t res2:1; /* N/A */
770 u_int8_t local:1;
771 u_int8_t res3:5;
772 u_int8_t host_dead:1; /* multiple host/controller status *//* N/A */
773 u_int8_t host_connection_dead:1; /* N/A */
774 u_int8_t res4:6; /* N/A */
775 u_int8_t state; /* see 8.1 */
776 u_int8_t width;
777 u_int16_t speed;
778 /* multiported physical device information */
779 u_int8_t ports_available; /* N/A */
780 u_int8_t ports_inuse; /* N/A */
781 u_int8_t res5[4];
782 u_int8_t ether_address[16]; /* N/A */
783 u_int16_t command_tags;
784 u_int8_t consistency_check:1; /* N/A */
785 u_int8_t rebuild:1; /* N/A */
786 u_int8_t make_consistent:1; /* N/A */
787 u_int8_t initialisation:1;
788 u_int8_t migration:1; /* N/A */
789 u_int8_t patrol:1; /* N/A */
790 u_int8_t res6:2;
791 u_int8_t long_operation_status; /* N/A */
792 u_int8_t parity_errors;
793 u_int8_t soft_errors;
794 u_int8_t hard_errors;
795 u_int8_t miscellaneous_errors;
796 u_int8_t command_timeouts; /* N/A */
797 u_int8_t retries; /* N/A */
798 u_int8_t aborts; /* N/A */
799 u_int8_t PFAs_detected; /* N/A */
800 u_int8_t res7[6];
801 u_int16_t block_size;
802 u_int32_t original_device_size; /* XXX "blocks or MB" Huh? */
803 u_int32_t device_size; /* XXX "blocks or MB" Huh? */
804 u_int8_t res8[4];
805 char name[16]; /* N/A */
806 u_int8_t res9[16 + 32];
807 u_int8_t inquiry[36];
808 u_int8_t res10[12 + 16];
809 u_int64_t last_read_block; /* N/A */
810 u_int64_t last_written_block; /* N/A */
811 u_int64_t consistency_check_block; /* N/A */
812 u_int64_t rebuild_block; /* N/A */
813 u_int64_t make_consistent_block; /* N/A */
814 u_int64_t initialisation_block; /* N/A */
815 u_int64_t migration_block; /* N/A */
816 u_int64_t patrol_block; /* N/A */
817 u_int8_t res11[256];
818 } __attribute__ ((__packed__));
819
820 union mly_devinfo {
821 struct mly_ioctl_getlogdevinfovalid logdev;
822 struct mly_ioctl_getphysdevinfovalid physdev;
823 };
824
825 /*
826 * 21.11.2 MDACIOCTL_GETPHYSDEVSTATISTICS: Data Format
827 * 21.12.2 MDACIOCTL_GETLOGDEVSTATISTICS: Data Format
828 */
829 struct mly_ioctl_getdevstatistics {
830 u_int32_t uptime_ms; /* getphysedevstatistics only */
831 u_int8_t res1[5]; /* N/A */
832 u_int8_t channel;
833 u_int8_t target;
834 u_int8_t lun;
835 u_int16_t raid_device; /* getlogdevstatistics only */
836 u_int8_t res2[2]; /* N/A */
837 /* total read/write performance including cache data */
838 u_int32_t total_reads;
839 u_int32_t total_writes;
840 u_int32_t total_read_size;
841 u_int32_t total_write_size;
842 /* cache read/write performance */
843 u_int32_t cache_reads; /* N/A */
844 u_int32_t cache_writes; /* N/A */
845 u_int32_t cache_read_size; /* N/A */
846 u_int32_t cache_write_size; /* N/A */
847 /* commands active/wait information */
848 u_int32_t command_waits_done; /* N/A */
849 u_int16_t active_commands; /* N/A */
850 u_int16_t waiting_commands; /* N/A */
851 u_int8_t res3[8]; /* N/A */
852 } __attribute__ ((__packed__));
853
854 /*
855 * 21.13.2 MDACIOCTL_GETCONTROLLERSTATISTICS: Data Format
856 */
857 struct mly_ioctl_getcontrollerstatistics {
858 u_int32_t uptime_ms; /* N/A */
859 u_int8_t res1[12]; /* N/A */
860 /* target physical device performance data information */
861 u_int32_t target_physical_device_interrupts; /* N/A */
862 u_int32_t target_physical_device_stray_interrupts;/* N/A */
863 u_int8_t res2[8]; /* N/A */
864 u_int32_t target_physical_device_reads; /* N/A */
865 u_int32_t target_physical_device_writes; /* N/A */
866 u_int32_t target_physical_device_read_size; /* N/A */
867 u_int32_t target_physical_device_write_size; /* N/A */
868 /* host system performance data information */
869 u_int32_t host_system_interrupts; /* N/A */
870 u_int32_t host_system_stray_interrupts; /* N/A */
871 u_int32_t host_system_sent_interrupts; /* N/A */
872 u_int8_t res3[4]; /* N/A */
873 u_int32_t physical_device_reads; /* N/A */
874 u_int32_t physical_device_writes; /* N/A */
875 u_int32_t physical_device_read_size; /* N/A */
876 u_int32_t physical_device_write_size; /* N/A */
877 u_int32_t physical_device_cache_reads; /* N/A */
878 u_int32_t physical_device_cache_writes; /* N/A */
879 u_int32_t physical_device_cache_read_size; /* N/A */
880 u_int32_t physical_device_cache_write_size; /* N/A */
881 u_int32_t logical_device_reads; /* N/A */
882 u_int32_t logical_device_writes; /* N/A */
883 u_int32_t logical_device_read_size; /* N/A */
884 u_int32_t logical_device_write_size; /* N/A */
885 u_int32_t logical_device_cache_reads; /* N/A */
886 u_int32_t logical_device_cache_writes; /* N/A */
887 u_int32_t logical_device_cache_read_size; /* N/A */
888 u_int32_t logical_device_cache_write_size; /* N/A */
889 u_int16_t target_physical_device_commands_active; /* N/A */
890 u_int16_t target_physical_device_commands_waiting;/* N/A */
891 u_int16_t host_system_commands_active; /* N/A */
892 u_int16_t host_system_commands_waiting; /* N/A */
893 u_int8_t res4[48 + 64]; /* N/A */
894 } __attribute__ ((__packed__));
895
896 /*
897 * 21.2 MDACIOCTL_SETRAIDDEVSTATE
898 */
899 struct mly_ioctl_param_setraiddevstate {
900 u_int8_t state;
901 } __attribute__ ((__packed__));
902
903 /*
904 * 21.27.2 MDACIOCTL_GETBDT_FOR_SYSDRIVE: Data Format
905 */
906 #define MLY_MAX_BDT_ENTRIES 1022
907 struct mly_ioctl_getbdt_for_sysdrive {
908 u_int32_t num_of_bdt_entries;
909 u_int32_t bad_data_block_address[MLY_MAX_BDT_ENTRIES];
910 } __attribute__ ((__packed__));
911
912 /*
913 * 22.1 Physical Device Definition (PDD)
914 */
915 struct mly_pdd {
916 u_int8_t type; /* see 8.2 */
917 u_int8_t state; /* see 8.1 */
918 u_int16_t raid_device;
919 u_int32_t device_size; /* XXX "block or MB" Huh? */
920 u_int8_t controller;
921 u_int8_t channel;
922 u_int8_t target;
923 u_int8_t lun;
924 u_int32_t start_address;
925 } __attribute__ ((__packed__));
926
927 /*
928 * 22.2 RAID Device Use Definition (UDD)
929 */
930 struct mly_udd {
931 u_int8_t res1;
932 u_int8_t state; /* see 8.1 */
933 u_int16_t raid_device;
934 u_int32_t start_address;
935 } __attribute__ ((__packed__));
936
937 /*
938 * RAID Device Definition (LDD)
939 */
940 struct mly_ldd {
941 u_int8_t type; /* see 8.2 */
942 u_int8_t state; /* see 8.1 */
943 u_int16_t raid_device;
944 u_int32_t device_size; /* XXX "block or MB" Huh? */
945 u_int8_t devices_used_count;
946 u_int8_t stripe_size; /* see 8.3 */
947 u_int8_t cache_line_size; /* see 8.4 */
948 u_int8_t read_write_control; /* see 8.5 */
949 u_int32_t devices_used_size; /* XXX "block or MB" Huh? */
950 u_int16_t devices_used[32]; /* XXX actual size of this field unknown! */
951 } __attribute__ ((__packed__));
952
953 /*
954 * Define a datastructure giving the smallest allocation that will hold
955 * a PDD, UDD or LDD for MDACIOCTL_GETDEVCONFINFO.
956 */
957 struct mly_devconf_hdr {
958 u_int8_t type; /* see 8.2 */
959 u_int8_t state; /* see 8.1 */
960 u_int16_t raid_device;
961 };
962
963 union mly_ioctl_devconfinfo {
964 struct mly_pdd pdd;
965 struct mly_udd udd;
966 struct mly_ldd ldd;
967 struct mly_devconf_hdr hdr;
968 };
969
970 /*
971 * 22.3 MDACIOCTL_RENAMERAIDDEV
972 *
973 * XXX this command is listed as transferring data, but does not define the data.
974 */
975 struct mly_ioctl_param_renameraiddev {
976 u_int8_t new_raid_device;
977 } __attribute__ ((__packed__));
978
979 /*
980 * 23.6.2 MDACIOCTL_XLATEPHYSDEVTORAIDDEV
981 *
982 * XXX documentation suggests this format will change
983 */
984 struct mly_ioctl_param_xlatephysdevtoraiddev {
985 u_int16_t raid_device;
986 u_int8_t res1[2];
987 u_int8_t controller;
988 u_int8_t channel;
989 u_int8_t target;
990 u_int8_t lun;
991 } __attribute__ ((__packed__));
992
993 /*
994 * 23.7 MDACIOCTL_GETGROUPCONFINFO
995 */
996 struct mly_ioctl_param_getgroupconfinfo {
997 u_int16_t group;
998 u_int8_t res1[8];
999 union mly_cmd_transfer transfer;
1000 } __attribute__ ((__packed__));
1001
1002 /*
1003 * 23.9.2 MDACIOCTL_GETFREESPACELIST: Data Format
1004 *
1005 * The controller will populate as much of this structure as is provided,
1006 * or as is required to fully list the free space available.
1007 */
1008 struct mly_ioctl_getfreespacelist_entry {
1009 u_int16_t raid_device;
1010 u_int8_t res1[6];
1011 u_int32_t address; /* XXX "blocks or MB" Huh? */
1012 u_int32_t size; /* XXX "blocks or MB" Huh? */
1013 } __attribute__ ((__packed__));
1014
1015 struct mly_ioctl_getfrespacelist {
1016 u_int16_t returned_entries;
1017 u_int16_t total_entries;
1018 u_int8_t res1[12];
1019 struct mly_ioctl_getfreespacelist_entry space[0]; /* expand to suit */
1020 } __attribute__ ((__packed__));
1021
1022 /*
1023 * 27.1 MDACIOCTL_GETSUBSYSTEMDATA
1024 * 27.2 MDACIOCTL_SETSUBSYSTEMDATA
1025 *
1026 * PCI controller only supports a limited subset of the possible operations.
1027 *
1028 * XXX where does the status end up? (the command transfers no data)
1029 */
1030 struct mly_ioctl_param_subsystemdata {
1031 u_int8_t operation:4;
1032 #define MLY_BBU_GETSTATUS 0x00
1033 #define MLY_BBU_SET_THRESHOLD 0x00 /* minutes in param[0,1] */
1034 u_int8_t subsystem:4;
1035 #define MLY_SUBSYSTEM_BBU 0x01
1036 u_int parameter[3]; /* only for SETSUBSYSTEMDATA */
1037 } __attribute__ ((__packed__));
1038
1039 struct mly_ioctl_getsubsystemdata_bbustatus {
1040 u_int16_t current_power;
1041 u_int16_t maximum_power;
1042 u_int16_t power_threshold;
1043 u_int8_t charge_level;
1044 u_int8_t hardware_version;
1045 u_int8_t battery_type;
1046 #define MLY_BBU_TYPE_UNKNOWN 0x00
1047 #define MLY_BBU_TYPE_NICAD 0x01
1048 #define MLY_BBU_TYPE_MISSING 0xfe
1049 u_int8_t res1;
1050 u_int8_t operation_status;
1051 #define MLY_BBU_STATUS_NO_SYNC 0x01
1052 #define MLY_BBU_STATUS_OUT_OF_SYNC 0x02
1053 #define MLY_BBU_STATUS_FIRST_WARNING 0x04
1054 #define MLY_BBU_STATUS_SECOND_WARNING 0x08
1055 #define MLY_BBU_STATUS_RECONDITIONING 0x10
1056 #define MLY_BBU_STATUS_DISCHARGING 0x20
1057 #define MLY_BBU_STATUS_FASTCHARGING 0x40
1058 u_int8_t res2;
1059 } __attribute__ ((__packed__));
1060
1061 /*
1062 * 28.9 MDACIOCTL_RESETDEVICE
1063 * 28.10 MDACIOCTL_FLUSHDEVICEDATA
1064 * 28.11 MDACIOCTL_PAUSEDEVICE
1065 * 28.12 MDACIOCTL_UNPAUSEDEVICE
1066 */
1067 struct mly_ioctl_param_deviceoperation {
1068 u_int8_t operation_device; /* see 14.3 */
1069 } __attribute__ ((__packed__));
1070
1071 /*
1072 * 31.1 Event Data Format
1073 */
1074 struct mly_event {
1075 u_int32_t sequence_number;
1076 u_int32_t timestamp;
1077 u_int32_t code;
1078 u_int8_t controller;
1079 u_int8_t channel;
1080 u_int8_t target; /* also enclosure */
1081 u_int8_t lun; /* also enclosure unit */
1082 u_int8_t res1[4];
1083 u_int32_t param;
1084 u_int8_t sense[40];
1085 } __attribute__ ((__packed__));
1086
1087 /*
1088 * 31.2 MDACIOCTL_GETEVENT
1089 */
1090 struct mly_ioctl_param_getevent {
1091 u_int16_t sequence_number_low;
1092 u_int8_t res1[8];
1093 union mly_cmd_transfer transfer;
1094 } __attribute__ ((__packed__));
1095
1096 union mly_ioctl_param {
1097 struct mly_ioctl_param_data data;
1098 struct mly_ioctl_param_setmemorymailbox setmemorymailbox;
1099 struct mly_ioctl_param_setraiddevstate setraiddevstate;
1100 struct mly_ioctl_param_renameraiddev renameraiddev;
1101 struct mly_ioctl_param_xlatephysdevtoraiddev xlatephysdevtoraiddev;
1102 struct mly_ioctl_param_getgroupconfinfo getgroupconfinfo;
1103 struct mly_ioctl_param_subsystemdata subsystemdata;
1104 struct mly_ioctl_param_deviceoperation deviceoperation;
1105 struct mly_ioctl_param_getevent getevent;
1106 };
1107
1108 /*
1109 * 19 SCSI Command Format
1110 */
1111 #define MLY_PHYADDR(c, b, t, l) \
1112 ((l) | ((t) << 8) | ((b) << 16) | ((c) << 19))
1113 #define MLY_LOGADDR(c, u) \
1114 ((u) | ((c) << 19))
1115
1116 #define MLY_LOGADDR_DEV(a) (a & 0xffff)
1117 #define MLY_LOGADDR_CTLR(a) (a >> 19)
1118
1119 #define MLY_PHYADDR_LUN(a) (a & 0xff)
1120 #define MLY_PHYADDR_TARGET(a) ((a >> 8) & 0xff)
1121 #define MLY_PHYADDR_CHANNEL(a) ((a >> 16) & 0x07)
1122 #define MLY_PHYADDR_CTLR(a) ((a >> 19) & 0x1f)
1123
1124 /*
1125 * struct mly_cmd_address_physical {
1126 * u_int8_t lun;
1127 * u_int8_t target;
1128 * u_int8_t channel:3;
1129 * u_int8_t controller:5;
1130 * } __attribute__ ((__packed__));
1131 *
1132 * struct mly_cmd_address_logical {
1133 * u_int16_t logdev;
1134 * u_int8_t res1:3;
1135 * u_int8_t controller:5;
1136 * } __attribute__ ((__packed__));
1137 */
1138
1139 struct mly_cmd_generic {
1140 u_int16_t command_id;
1141 u_int8_t opcode;
1142 u_int8_t command_control;
1143 u_int32_t data_size;
1144 u_int64_t sense_buffer_address;
1145 u_int8_t addr[3];
1146 u_int8_t timeout;
1147 u_int8_t maximum_sense_size;
1148 u_int8_t res1[11];
1149 union mly_cmd_transfer transfer;
1150 } __attribute__ ((__packed__));
1151
1152
1153 /*
1154 * 19.1 MDACMD_SCSI & MDACMD_SCSIPT
1155 */
1156 #define MLY_CMD_SCSI_SMALL_CDB 10
1157 struct mly_cmd_scsi_small {
1158 u_int16_t command_id;
1159 u_int8_t opcode;
1160 u_int8_t command_control;
1161 u_int32_t data_size;
1162 u_int64_t sense_buffer_address;
1163 u_int8_t addr[3];
1164 u_int8_t timeout;
1165 u_int8_t maximum_sense_size;
1166 u_int8_t cdb_length;
1167 u_int8_t cdb[MLY_CMD_SCSI_SMALL_CDB];
1168 union mly_cmd_transfer transfer;
1169 } __attribute__ ((__packed__));
1170
1171 /*
1172 * 19.2 MDACMD_SCSILC & MDACMD_SCSILCPT
1173 */
1174 struct mly_cmd_scsi_large {
1175 u_int16_t command_id;
1176 u_int8_t opcode;
1177 u_int8_t command_control;
1178 u_int32_t data_size;
1179 u_int64_t sense_buffer_address;
1180 u_int8_t addr[3];
1181 u_int8_t timeout;
1182 u_int8_t maximum_sense_size;
1183 u_int8_t cdb_length;
1184 u_int16_t res1;
1185 u_int64_t cdb_physaddr;
1186 union mly_cmd_transfer transfer;
1187 } __attribute__ ((__packed__));
1188
1189 /*
1190 * 20.1 IOCTL Command Format: Internal Bus
1191 */
1192 struct mly_cmd_ioctl {
1193 u_int16_t command_id;
1194 u_int8_t opcode;
1195 u_int8_t command_control;
1196 u_int32_t data_size;
1197 u_int64_t sense_buffer_address;
1198 u_int8_t addr[3];
1199 u_int8_t timeout;
1200 u_int8_t maximum_sense_size;
1201 u_int8_t sub_ioctl;
1202 union mly_ioctl_param param;
1203 } __attribute__ ((__packed__));
1204
1205 /*
1206 * PG6: 8.2.2
1207 */
1208 struct mly_cmd_mmbox {
1209 u_int32_t flag;
1210 u_int8_t data[60];
1211 } __attribute__ ((__packed__));
1212
1213 union mly_cmd_packet {
1214 struct mly_cmd_generic generic;
1215 struct mly_cmd_scsi_small scsi_small;
1216 struct mly_cmd_scsi_large scsi_large;
1217 struct mly_cmd_ioctl ioctl;
1218 struct mly_cmd_mmbox mmbox;
1219 };
1220
1221 /*
1222 * PG6: 5.3
1223 */
1224 #define MLY_I960RX_COMMAND_MAILBOX 0x10
1225 #define MLY_I960RX_STATUS_MAILBOX 0x18
1226 #define MLY_I960RX_IDBR 0x20
1227 #define MLY_I960RX_ODBR 0x2c
1228 #define MLY_I960RX_ERROR_STATUS 0x2e
1229 #define MLY_I960RX_INTERRUPT_STATUS 0x30
1230 #define MLY_I960RX_INTERRUPT_MASK 0x34
1231
1232 #define MLY_STRONGARM_COMMAND_MAILBOX 0x50
1233 #define MLY_STRONGARM_STATUS_MAILBOX 0x58
1234 #define MLY_STRONGARM_IDBR 0x60
1235 #define MLY_STRONGARM_ODBR 0x61
1236 #define MLY_STRONGARM_ERROR_STATUS 0x63
1237 #define MLY_STRONGARM_INTERRUPT_STATUS 0x30
1238 #define MLY_STRONGARM_INTERRUPT_MASK 0x34
1239
1240 /*
1241 * PG6: 5.4.3 Doorbell 0
1242 */
1243 #define MLY_HM_CMDSENT (1<<0)
1244 #define MLY_HM_STSACK (1<<1)
1245 #define MLY_SOFT_RST (1<<3)
1246 #define MLY_AM_CMDSENT (1<<4)
1247
1248 /*
1249 * PG6: 5.4.4 Doorbell 1
1250 *
1251 * Note that the documentation claims that these bits are set when the
1252 * status queue(s) are empty, wheras the Linux driver and experience
1253 * suggest they are set when there is status available.
1254 */
1255 #define MLY_HM_STSREADY (1<<0)
1256 #define MLY_AM_STSREADY (1<<1)
1257
1258 /*
1259 * PG6: 5.4.6 Doorbell 3
1260 */
1261 #define MLY_MSG_EMPTY (1<<3)
1262 #define MLY_MSG_SPINUP 0x08
1263 #define MLY_MSG_RACE_RECOVERY_FAIL 0x60
1264 #define MLY_MSG_RACE_IN_PROGRESS 0x70
1265 #define MLY_MSG_RACE_ON_CRITICAL 0xb0
1266 #define MLY_MSG_PARITY_ERROR 0xf0
1267
1268 /*
1269 * PG6: 5.4.8 Outbound Interrupt Mask
1270 */
1271 #define MLY_INTERRUPT_MASK_DISABLE 0xff
1272 #define MLY_INTERRUPT_MASK_ENABLE (0xff & ~(1<<2))
1273
1274 /*
1275 * PG6: 8.2 Advanced Mailbox Scheme
1276 *
1277 * Note that this must be allocated on a 4k boundary, and all internal
1278 * fields must also reside on a 4k boundary.
1279 * We could dynamically size this structure, but the extra effort
1280 * is probably unjustified. Note that these buffers do not need to be
1281 * adjacent - we just group them to simplify allocation of the bus-visible
1282 * buffer.
1283 *
1284 * XXX Note that for some reason, if MLY_MMBOX_COMMANDS is > 64, the controller
1285 * fails to respond to the command at (MLY_MMBOX_COMMANDS - 64). It's not
1286 * wrapping to 0 at this point (determined by experimentation). This is not
1287 * consistent with the Linux driver's implementation.
1288 * Whilst it's handy to have lots of room for status returns in case we end up
1289 * being slow getting back to completed commands, it seems unlikely that we
1290 * would get 64 commands ahead of the controller on the submissions side, so
1291 * the current workaround is to simply limit the command ring to 64 entries.
1292 */
1293 union mly_status_packet {
1294 struct mly_status status;
1295 struct {
1296 u_int32_t flag;
1297 u_int8_t data[4];
1298 } __attribute__ ((__packed__)) mmbox;
1299 };
1300 union mly_health_region {
1301 struct mly_health_status status;
1302 u_int8_t pad[1024];
1303 };
1304
1305 #define MLY_MMBOX_COMMANDS 64
1306 #define MLY_MMBOX_STATUS 512
1307 struct mly_mmbox {
1308 union mly_cmd_packet mmm_command[MLY_MMBOX_COMMANDS];
1309 union mly_status_packet mmm_status[MLY_MMBOX_STATUS];
1310 union mly_health_region mmm_health;
1311 } __attribute__ ((__packed__));
1312
1313 #endif /* !defined _PCI_MLYREG_H_ */
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