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sys/dev/pci/pci.c
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1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD: releng/10.2/sys/dev/pci/pci.c 285991 2015-07-29 00:57:54Z gjb $"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 #include <machine/stdarg.h> 55 56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 57 #include <machine/intr_machdep.h> 58 #endif 59 60 #include <sys/pciio.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pci_private.h> 64 65 #include <dev/usb/controller/xhcireg.h> 66 #include <dev/usb/controller/ehcireg.h> 67 #include <dev/usb/controller/ohcireg.h> 68 #include <dev/usb/controller/uhcireg.h> 69 70 #include "pcib_if.h" 71 #include "pci_if.h" 72 73 #define PCIR_IS_BIOS(cfg, reg) \ 74 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 75 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 76 77 static int pci_has_quirk(uint32_t devid, int quirk); 78 static pci_addr_t pci_mapbase(uint64_t mapreg); 79 static const char *pci_maptype(uint64_t mapreg); 80 static int pci_mapsize(uint64_t testval); 81 static int pci_maprange(uint64_t mapreg); 82 static pci_addr_t pci_rombase(uint64_t mapreg); 83 static int pci_romsize(uint64_t testval); 84 static void pci_fixancient(pcicfgregs *cfg); 85 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 86 87 static int pci_porten(device_t dev); 88 static int pci_memen(device_t dev); 89 static void pci_assign_interrupt(device_t bus, device_t dev, 90 int force_route); 91 static int pci_add_map(device_t bus, device_t dev, int reg, 92 struct resource_list *rl, int force, int prefetch); 93 static int pci_probe(device_t dev); 94 static int pci_attach(device_t dev); 95 #ifdef PCI_RES_BUS 96 static int pci_detach(device_t dev); 97 #endif 98 static void pci_load_vendor_data(void); 99 static int pci_describe_parse_line(char **ptr, int *vendor, 100 int *device, char **desc); 101 static char *pci_describe_device(device_t dev); 102 static int pci_modevent(module_t mod, int what, void *arg); 103 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 104 pcicfgregs *cfg); 105 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 106 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 107 int reg, uint32_t *data); 108 #if 0 109 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 110 int reg, uint32_t data); 111 #endif 112 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 113 static void pci_disable_msi(device_t dev); 114 static void pci_enable_msi(device_t dev, uint64_t address, 115 uint16_t data); 116 static void pci_enable_msix(device_t dev, u_int index, 117 uint64_t address, uint32_t data); 118 static void pci_mask_msix(device_t dev, u_int index); 119 static void pci_unmask_msix(device_t dev, u_int index); 120 static int pci_msi_blacklisted(void); 121 static int pci_msix_blacklisted(void); 122 static void pci_resume_msi(device_t dev); 123 static void pci_resume_msix(device_t dev); 124 static int pci_remap_intr_method(device_t bus, device_t dev, 125 u_int irq); 126 127 static uint16_t pci_get_rid_method(device_t dev, device_t child); 128 129 static device_method_t pci_methods[] = { 130 /* Device interface */ 131 DEVMETHOD(device_probe, pci_probe), 132 DEVMETHOD(device_attach, pci_attach), 133 #ifdef PCI_RES_BUS 134 DEVMETHOD(device_detach, pci_detach), 135 #else 136 DEVMETHOD(device_detach, bus_generic_detach), 137 #endif 138 DEVMETHOD(device_shutdown, bus_generic_shutdown), 139 DEVMETHOD(device_suspend, pci_suspend), 140 DEVMETHOD(device_resume, pci_resume), 141 142 /* Bus interface */ 143 DEVMETHOD(bus_print_child, pci_print_child), 144 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 145 DEVMETHOD(bus_read_ivar, pci_read_ivar), 146 DEVMETHOD(bus_write_ivar, pci_write_ivar), 147 DEVMETHOD(bus_driver_added, pci_driver_added), 148 DEVMETHOD(bus_setup_intr, pci_setup_intr), 149 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 150 151 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 152 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 153 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 154 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 155 DEVMETHOD(bus_delete_resource, pci_delete_resource), 156 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 157 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 158 DEVMETHOD(bus_release_resource, pci_release_resource), 159 DEVMETHOD(bus_activate_resource, pci_activate_resource), 160 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 161 DEVMETHOD(bus_child_detached, pci_child_detached), 162 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 163 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 164 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 165 166 /* PCI interface */ 167 DEVMETHOD(pci_read_config, pci_read_config_method), 168 DEVMETHOD(pci_write_config, pci_write_config_method), 169 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 170 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 171 DEVMETHOD(pci_enable_io, pci_enable_io_method), 172 DEVMETHOD(pci_disable_io, pci_disable_io_method), 173 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 174 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 175 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 176 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 177 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 178 DEVMETHOD(pci_find_cap, pci_find_cap_method), 179 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 180 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 181 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 182 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 183 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 184 DEVMETHOD(pci_release_msi, pci_release_msi_method), 185 DEVMETHOD(pci_msi_count, pci_msi_count_method), 186 DEVMETHOD(pci_msix_count, pci_msix_count_method), 187 DEVMETHOD(pci_get_rid, pci_get_rid_method), 188 189 DEVMETHOD_END 190 }; 191 192 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 193 194 static devclass_t pci_devclass; 195 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL); 196 MODULE_VERSION(pci, 1); 197 198 static char *pci_vendordata; 199 static size_t pci_vendordata_size; 200 201 struct pci_quirk { 202 uint32_t devid; /* Vendor/device of the card */ 203 int type; 204 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 205 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 206 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 207 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 208 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 209 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 210 int arg1; 211 int arg2; 212 }; 213 214 static const struct pci_quirk pci_quirks[] = { 215 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 216 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 217 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 218 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 219 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 220 221 /* 222 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 223 * or the CMIC-SL (AKA ServerWorks GC_LE). 224 */ 225 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 226 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 227 228 /* 229 * MSI doesn't work on earlier Intel chipsets including 230 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 231 */ 232 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 233 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 234 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 235 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 236 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 237 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 238 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 239 240 /* 241 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 242 * bridge. 243 */ 244 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 245 246 /* 247 * MSI-X allocation doesn't work properly for devices passed through 248 * by VMware up to at least ESXi 5.1. 249 */ 250 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */ 251 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */ 252 253 /* 254 * Some virtualization environments emulate an older chipset 255 * but support MSI just fine. QEMU uses the Intel 82440. 256 */ 257 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 258 259 /* 260 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 261 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 262 * It prevents us from attaching hpet(4) when the bit is unset. 263 * Note this quirk only affects SB600 revision A13 and earlier. 264 * For SB600 A21 and later, firmware must set the bit to hide it. 265 * For SB700 and later, it is unused and hardcoded to zero. 266 */ 267 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 268 269 /* 270 * Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that 271 * MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the 272 * command register is set. 273 */ 274 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 275 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 276 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 277 278 /* 279 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 280 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 281 */ 282 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 283 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 284 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 285 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 286 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 287 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 288 289 { 0 } 290 }; 291 292 /* map register information */ 293 #define PCI_MAPMEM 0x01 /* memory map */ 294 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 295 #define PCI_MAPPORT 0x04 /* port map */ 296 297 struct devlist pci_devq; 298 uint32_t pci_generation; 299 uint32_t pci_numdevs = 0; 300 static int pcie_chipset, pcix_chipset; 301 302 /* sysctl vars */ 303 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 304 305 static int pci_enable_io_modes = 1; 306 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 307 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 308 &pci_enable_io_modes, 1, 309 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 310 enable these bits correctly. We'd like to do this all the time, but there\n\ 311 are some peripherals that this causes problems with."); 312 313 static int pci_do_realloc_bars = 0; 314 TUNABLE_INT("hw.pci.realloc_bars", &pci_do_realloc_bars); 315 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RW, 316 &pci_do_realloc_bars, 0, 317 "Attempt to allocate a new range for any BARs whose original firmware-assigned ranges fail to allocate during the initial device scan."); 318 319 static int pci_do_power_nodriver = 0; 320 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 321 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 322 &pci_do_power_nodriver, 0, 323 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 324 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 325 agressively place devices into D3 state. 3 means put absolutely everything\n\ 326 in D3 state."); 327 328 int pci_do_power_resume = 1; 329 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 330 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 331 &pci_do_power_resume, 1, 332 "Transition from D3 -> D0 on resume."); 333 334 int pci_do_power_suspend = 1; 335 TUNABLE_INT("hw.pci.do_power_suspend", &pci_do_power_suspend); 336 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RW, 337 &pci_do_power_suspend, 1, 338 "Transition from D0 -> D3 on suspend."); 339 340 static int pci_do_msi = 1; 341 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 342 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 343 "Enable support for MSI interrupts"); 344 345 static int pci_do_msix = 1; 346 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 347 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 348 "Enable support for MSI-X interrupts"); 349 350 static int pci_honor_msi_blacklist = 1; 351 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist); 352 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD, 353 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 354 355 #if defined(__i386__) || defined(__amd64__) 356 static int pci_usb_takeover = 1; 357 #else 358 static int pci_usb_takeover = 0; 359 #endif 360 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover); 361 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 362 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\ 363 Disable this if you depend on BIOS emulation of USB devices, that is\n\ 364 you use USB devices (like keyboard or mouse) but do not load USB drivers"); 365 366 static int pci_clear_bars; 367 TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars); 368 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 369 "Ignore firmware-assigned resources for BARs."); 370 371 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 372 static int pci_clear_buses; 373 TUNABLE_INT("hw.pci.clear_buses", &pci_clear_buses); 374 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 375 "Ignore firmware-assigned bus numbers."); 376 #endif 377 378 static int pci_enable_ari = 1; 379 TUNABLE_INT("hw.pci.enable_ari", &pci_enable_ari); 380 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 381 0, "Enable support for PCIe Alternative RID Interpretation"); 382 383 static int 384 pci_has_quirk(uint32_t devid, int quirk) 385 { 386 const struct pci_quirk *q; 387 388 for (q = &pci_quirks[0]; q->devid; q++) { 389 if (q->devid == devid && q->type == quirk) 390 return (1); 391 } 392 return (0); 393 } 394 395 /* Find a device_t by bus/slot/function in domain 0 */ 396 397 device_t 398 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 399 { 400 401 return (pci_find_dbsf(0, bus, slot, func)); 402 } 403 404 /* Find a device_t by domain/bus/slot/function */ 405 406 device_t 407 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 408 { 409 struct pci_devinfo *dinfo; 410 411 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 412 if ((dinfo->cfg.domain == domain) && 413 (dinfo->cfg.bus == bus) && 414 (dinfo->cfg.slot == slot) && 415 (dinfo->cfg.func == func)) { 416 return (dinfo->cfg.dev); 417 } 418 } 419 420 return (NULL); 421 } 422 423 /* Find a device_t by vendor/device ID */ 424 425 device_t 426 pci_find_device(uint16_t vendor, uint16_t device) 427 { 428 struct pci_devinfo *dinfo; 429 430 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 431 if ((dinfo->cfg.vendor == vendor) && 432 (dinfo->cfg.device == device)) { 433 return (dinfo->cfg.dev); 434 } 435 } 436 437 return (NULL); 438 } 439 440 device_t 441 pci_find_class(uint8_t class, uint8_t subclass) 442 { 443 struct pci_devinfo *dinfo; 444 445 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 446 if (dinfo->cfg.baseclass == class && 447 dinfo->cfg.subclass == subclass) { 448 return (dinfo->cfg.dev); 449 } 450 } 451 452 return (NULL); 453 } 454 455 static int 456 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 457 { 458 va_list ap; 459 int retval; 460 461 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 462 cfg->func); 463 va_start(ap, fmt); 464 retval += vprintf(fmt, ap); 465 va_end(ap); 466 return (retval); 467 } 468 469 /* return base address of memory or port map */ 470 471 static pci_addr_t 472 pci_mapbase(uint64_t mapreg) 473 { 474 475 if (PCI_BAR_MEM(mapreg)) 476 return (mapreg & PCIM_BAR_MEM_BASE); 477 else 478 return (mapreg & PCIM_BAR_IO_BASE); 479 } 480 481 /* return map type of memory or port map */ 482 483 static const char * 484 pci_maptype(uint64_t mapreg) 485 { 486 487 if (PCI_BAR_IO(mapreg)) 488 return ("I/O Port"); 489 if (mapreg & PCIM_BAR_MEM_PREFETCH) 490 return ("Prefetchable Memory"); 491 return ("Memory"); 492 } 493 494 /* return log2 of map size decoded for memory or port map */ 495 496 static int 497 pci_mapsize(uint64_t testval) 498 { 499 int ln2size; 500 501 testval = pci_mapbase(testval); 502 ln2size = 0; 503 if (testval != 0) { 504 while ((testval & 1) == 0) 505 { 506 ln2size++; 507 testval >>= 1; 508 } 509 } 510 return (ln2size); 511 } 512 513 /* return base address of device ROM */ 514 515 static pci_addr_t 516 pci_rombase(uint64_t mapreg) 517 { 518 519 return (mapreg & PCIM_BIOS_ADDR_MASK); 520 } 521 522 /* return log2 of map size decided for device ROM */ 523 524 static int 525 pci_romsize(uint64_t testval) 526 { 527 int ln2size; 528 529 testval = pci_rombase(testval); 530 ln2size = 0; 531 if (testval != 0) { 532 while ((testval & 1) == 0) 533 { 534 ln2size++; 535 testval >>= 1; 536 } 537 } 538 return (ln2size); 539 } 540 541 /* return log2 of address range supported by map register */ 542 543 static int 544 pci_maprange(uint64_t mapreg) 545 { 546 int ln2range = 0; 547 548 if (PCI_BAR_IO(mapreg)) 549 ln2range = 32; 550 else 551 switch (mapreg & PCIM_BAR_MEM_TYPE) { 552 case PCIM_BAR_MEM_32: 553 ln2range = 32; 554 break; 555 case PCIM_BAR_MEM_1MB: 556 ln2range = 20; 557 break; 558 case PCIM_BAR_MEM_64: 559 ln2range = 64; 560 break; 561 } 562 return (ln2range); 563 } 564 565 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 566 567 static void 568 pci_fixancient(pcicfgregs *cfg) 569 { 570 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 571 return; 572 573 /* PCI to PCI bridges use header type 1 */ 574 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 575 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 576 } 577 578 /* extract header type specific config data */ 579 580 static void 581 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 582 { 583 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 584 switch (cfg->hdrtype & PCIM_HDRTYPE) { 585 case PCIM_HDRTYPE_NORMAL: 586 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 587 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 588 cfg->mingnt = REG(PCIR_MINGNT, 1); 589 cfg->maxlat = REG(PCIR_MAXLAT, 1); 590 cfg->nummaps = PCI_MAXMAPS_0; 591 break; 592 case PCIM_HDRTYPE_BRIDGE: 593 cfg->nummaps = PCI_MAXMAPS_1; 594 break; 595 case PCIM_HDRTYPE_CARDBUS: 596 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 597 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 598 cfg->nummaps = PCI_MAXMAPS_2; 599 break; 600 } 601 #undef REG 602 } 603 604 /* read configuration header into pcicfgregs structure */ 605 struct pci_devinfo * 606 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size) 607 { 608 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 609 pcicfgregs *cfg = NULL; 610 struct pci_devinfo *devlist_entry; 611 struct devlist *devlist_head; 612 613 devlist_head = &pci_devq; 614 615 devlist_entry = NULL; 616 617 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) { 618 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 619 if (devlist_entry == NULL) 620 return (NULL); 621 622 cfg = &devlist_entry->cfg; 623 624 cfg->domain = d; 625 cfg->bus = b; 626 cfg->slot = s; 627 cfg->func = f; 628 cfg->vendor = REG(PCIR_VENDOR, 2); 629 cfg->device = REG(PCIR_DEVICE, 2); 630 cfg->cmdreg = REG(PCIR_COMMAND, 2); 631 cfg->statreg = REG(PCIR_STATUS, 2); 632 cfg->baseclass = REG(PCIR_CLASS, 1); 633 cfg->subclass = REG(PCIR_SUBCLASS, 1); 634 cfg->progif = REG(PCIR_PROGIF, 1); 635 cfg->revid = REG(PCIR_REVID, 1); 636 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 637 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 638 cfg->lattimer = REG(PCIR_LATTIMER, 1); 639 cfg->intpin = REG(PCIR_INTPIN, 1); 640 cfg->intline = REG(PCIR_INTLINE, 1); 641 642 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 643 cfg->hdrtype &= ~PCIM_MFDEV; 644 STAILQ_INIT(&cfg->maps); 645 646 pci_fixancient(cfg); 647 pci_hdrtypedata(pcib, b, s, f, cfg); 648 649 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 650 pci_read_cap(pcib, cfg); 651 652 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 653 654 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 655 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 656 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 657 devlist_entry->conf.pc_sel.pc_func = cfg->func; 658 devlist_entry->conf.pc_hdr = cfg->hdrtype; 659 660 devlist_entry->conf.pc_subvendor = cfg->subvendor; 661 devlist_entry->conf.pc_subdevice = cfg->subdevice; 662 devlist_entry->conf.pc_vendor = cfg->vendor; 663 devlist_entry->conf.pc_device = cfg->device; 664 665 devlist_entry->conf.pc_class = cfg->baseclass; 666 devlist_entry->conf.pc_subclass = cfg->subclass; 667 devlist_entry->conf.pc_progif = cfg->progif; 668 devlist_entry->conf.pc_revid = cfg->revid; 669 670 pci_numdevs++; 671 pci_generation++; 672 } 673 return (devlist_entry); 674 #undef REG 675 } 676 677 static void 678 pci_read_cap(device_t pcib, pcicfgregs *cfg) 679 { 680 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 681 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 682 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 683 uint64_t addr; 684 #endif 685 uint32_t val; 686 int ptr, nextptr, ptrptr; 687 688 switch (cfg->hdrtype & PCIM_HDRTYPE) { 689 case PCIM_HDRTYPE_NORMAL: 690 case PCIM_HDRTYPE_BRIDGE: 691 ptrptr = PCIR_CAP_PTR; 692 break; 693 case PCIM_HDRTYPE_CARDBUS: 694 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 695 break; 696 default: 697 return; /* no extended capabilities support */ 698 } 699 nextptr = REG(ptrptr, 1); /* sanity check? */ 700 701 /* 702 * Read capability entries. 703 */ 704 while (nextptr != 0) { 705 /* Sanity check */ 706 if (nextptr > 255) { 707 printf("illegal PCI extended capability offset %d\n", 708 nextptr); 709 return; 710 } 711 /* Find the next entry */ 712 ptr = nextptr; 713 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 714 715 /* Process this entry */ 716 switch (REG(ptr + PCICAP_ID, 1)) { 717 case PCIY_PMG: /* PCI power management */ 718 if (cfg->pp.pp_cap == 0) { 719 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 720 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 721 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 722 if ((nextptr - ptr) > PCIR_POWER_DATA) 723 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 724 } 725 break; 726 case PCIY_HT: /* HyperTransport */ 727 /* Determine HT-specific capability type. */ 728 val = REG(ptr + PCIR_HT_COMMAND, 2); 729 730 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 731 cfg->ht.ht_slave = ptr; 732 733 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 734 switch (val & PCIM_HTCMD_CAP_MASK) { 735 case PCIM_HTCAP_MSI_MAPPING: 736 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 737 /* Sanity check the mapping window. */ 738 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 739 4); 740 addr <<= 32; 741 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 742 4); 743 if (addr != MSI_INTEL_ADDR_BASE) 744 device_printf(pcib, 745 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 746 cfg->domain, cfg->bus, 747 cfg->slot, cfg->func, 748 (long long)addr); 749 } else 750 addr = MSI_INTEL_ADDR_BASE; 751 752 cfg->ht.ht_msimap = ptr; 753 cfg->ht.ht_msictrl = val; 754 cfg->ht.ht_msiaddr = addr; 755 break; 756 } 757 #endif 758 break; 759 case PCIY_MSI: /* PCI MSI */ 760 cfg->msi.msi_location = ptr; 761 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 762 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 763 PCIM_MSICTRL_MMC_MASK)>>1); 764 break; 765 case PCIY_MSIX: /* PCI MSI-X */ 766 cfg->msix.msix_location = ptr; 767 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 768 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 769 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 770 val = REG(ptr + PCIR_MSIX_TABLE, 4); 771 cfg->msix.msix_table_bar = PCIR_BAR(val & 772 PCIM_MSIX_BIR_MASK); 773 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 774 val = REG(ptr + PCIR_MSIX_PBA, 4); 775 cfg->msix.msix_pba_bar = PCIR_BAR(val & 776 PCIM_MSIX_BIR_MASK); 777 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 778 break; 779 case PCIY_VPD: /* PCI Vital Product Data */ 780 cfg->vpd.vpd_reg = ptr; 781 break; 782 case PCIY_SUBVENDOR: 783 /* Should always be true. */ 784 if ((cfg->hdrtype & PCIM_HDRTYPE) == 785 PCIM_HDRTYPE_BRIDGE) { 786 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 787 cfg->subvendor = val & 0xffff; 788 cfg->subdevice = val >> 16; 789 } 790 break; 791 case PCIY_PCIX: /* PCI-X */ 792 /* 793 * Assume we have a PCI-X chipset if we have 794 * at least one PCI-PCI bridge with a PCI-X 795 * capability. Note that some systems with 796 * PCI-express or HT chipsets might match on 797 * this check as well. 798 */ 799 if ((cfg->hdrtype & PCIM_HDRTYPE) == 800 PCIM_HDRTYPE_BRIDGE) 801 pcix_chipset = 1; 802 cfg->pcix.pcix_location = ptr; 803 break; 804 case PCIY_EXPRESS: /* PCI-express */ 805 /* 806 * Assume we have a PCI-express chipset if we have 807 * at least one PCI-express device. 808 */ 809 pcie_chipset = 1; 810 cfg->pcie.pcie_location = ptr; 811 val = REG(ptr + PCIER_FLAGS, 2); 812 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 813 break; 814 default: 815 break; 816 } 817 } 818 819 #if defined(__powerpc__) 820 /* 821 * Enable the MSI mapping window for all HyperTransport 822 * slaves. PCI-PCI bridges have their windows enabled via 823 * PCIB_MAP_MSI(). 824 */ 825 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 826 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 827 device_printf(pcib, 828 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 829 cfg->domain, cfg->bus, cfg->slot, cfg->func); 830 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 831 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 832 2); 833 } 834 #endif 835 /* REG and WREG use carry through to next functions */ 836 } 837 838 /* 839 * PCI Vital Product Data 840 */ 841 842 #define PCI_VPD_TIMEOUT 1000000 843 844 static int 845 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 846 { 847 int count = PCI_VPD_TIMEOUT; 848 849 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 850 851 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 852 853 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 854 if (--count < 0) 855 return (ENXIO); 856 DELAY(1); /* limit looping */ 857 } 858 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 859 860 return (0); 861 } 862 863 #if 0 864 static int 865 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 866 { 867 int count = PCI_VPD_TIMEOUT; 868 869 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 870 871 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 872 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 873 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 874 if (--count < 0) 875 return (ENXIO); 876 DELAY(1); /* limit looping */ 877 } 878 879 return (0); 880 } 881 #endif 882 883 #undef PCI_VPD_TIMEOUT 884 885 struct vpd_readstate { 886 device_t pcib; 887 pcicfgregs *cfg; 888 uint32_t val; 889 int bytesinval; 890 int off; 891 uint8_t cksum; 892 }; 893 894 static int 895 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 896 { 897 uint32_t reg; 898 uint8_t byte; 899 900 if (vrs->bytesinval == 0) { 901 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 902 return (ENXIO); 903 vrs->val = le32toh(reg); 904 vrs->off += 4; 905 byte = vrs->val & 0xff; 906 vrs->bytesinval = 3; 907 } else { 908 vrs->val = vrs->val >> 8; 909 byte = vrs->val & 0xff; 910 vrs->bytesinval--; 911 } 912 913 vrs->cksum += byte; 914 *data = byte; 915 return (0); 916 } 917 918 static void 919 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 920 { 921 struct vpd_readstate vrs; 922 int state; 923 int name; 924 int remain; 925 int i; 926 int alloc, off; /* alloc/off for RO/W arrays */ 927 int cksumvalid; 928 int dflen; 929 uint8_t byte; 930 uint8_t byte2; 931 932 /* init vpd reader */ 933 vrs.bytesinval = 0; 934 vrs.off = 0; 935 vrs.pcib = pcib; 936 vrs.cfg = cfg; 937 vrs.cksum = 0; 938 939 state = 0; 940 name = remain = i = 0; /* shut up stupid gcc */ 941 alloc = off = 0; /* shut up stupid gcc */ 942 dflen = 0; /* shut up stupid gcc */ 943 cksumvalid = -1; 944 while (state >= 0) { 945 if (vpd_nextbyte(&vrs, &byte)) { 946 state = -2; 947 break; 948 } 949 #if 0 950 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 951 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 952 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 953 #endif 954 switch (state) { 955 case 0: /* item name */ 956 if (byte & 0x80) { 957 if (vpd_nextbyte(&vrs, &byte2)) { 958 state = -2; 959 break; 960 } 961 remain = byte2; 962 if (vpd_nextbyte(&vrs, &byte2)) { 963 state = -2; 964 break; 965 } 966 remain |= byte2 << 8; 967 if (remain > (0x7f*4 - vrs.off)) { 968 state = -1; 969 pci_printf(cfg, 970 "invalid VPD data, remain %#x\n", 971 remain); 972 } 973 name = byte & 0x7f; 974 } else { 975 remain = byte & 0x7; 976 name = (byte >> 3) & 0xf; 977 } 978 switch (name) { 979 case 0x2: /* String */ 980 cfg->vpd.vpd_ident = malloc(remain + 1, 981 M_DEVBUF, M_WAITOK); 982 i = 0; 983 state = 1; 984 break; 985 case 0xf: /* End */ 986 state = -1; 987 break; 988 case 0x10: /* VPD-R */ 989 alloc = 8; 990 off = 0; 991 cfg->vpd.vpd_ros = malloc(alloc * 992 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 993 M_WAITOK | M_ZERO); 994 state = 2; 995 break; 996 case 0x11: /* VPD-W */ 997 alloc = 8; 998 off = 0; 999 cfg->vpd.vpd_w = malloc(alloc * 1000 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1001 M_WAITOK | M_ZERO); 1002 state = 5; 1003 break; 1004 default: /* Invalid data, abort */ 1005 state = -1; 1006 break; 1007 } 1008 break; 1009 1010 case 1: /* Identifier String */ 1011 cfg->vpd.vpd_ident[i++] = byte; 1012 remain--; 1013 if (remain == 0) { 1014 cfg->vpd.vpd_ident[i] = '\0'; 1015 state = 0; 1016 } 1017 break; 1018 1019 case 2: /* VPD-R Keyword Header */ 1020 if (off == alloc) { 1021 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1022 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1023 M_DEVBUF, M_WAITOK | M_ZERO); 1024 } 1025 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1026 if (vpd_nextbyte(&vrs, &byte2)) { 1027 state = -2; 1028 break; 1029 } 1030 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1031 if (vpd_nextbyte(&vrs, &byte2)) { 1032 state = -2; 1033 break; 1034 } 1035 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1036 if (dflen == 0 && 1037 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1038 2) == 0) { 1039 /* 1040 * if this happens, we can't trust the rest 1041 * of the VPD. 1042 */ 1043 pci_printf(cfg, "bad keyword length: %d\n", 1044 dflen); 1045 cksumvalid = 0; 1046 state = -1; 1047 break; 1048 } else if (dflen == 0) { 1049 cfg->vpd.vpd_ros[off].value = malloc(1 * 1050 sizeof(*cfg->vpd.vpd_ros[off].value), 1051 M_DEVBUF, M_WAITOK); 1052 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1053 } else 1054 cfg->vpd.vpd_ros[off].value = malloc( 1055 (dflen + 1) * 1056 sizeof(*cfg->vpd.vpd_ros[off].value), 1057 M_DEVBUF, M_WAITOK); 1058 remain -= 3; 1059 i = 0; 1060 /* keep in sync w/ state 3's transistions */ 1061 if (dflen == 0 && remain == 0) 1062 state = 0; 1063 else if (dflen == 0) 1064 state = 2; 1065 else 1066 state = 3; 1067 break; 1068 1069 case 3: /* VPD-R Keyword Value */ 1070 cfg->vpd.vpd_ros[off].value[i++] = byte; 1071 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1072 "RV", 2) == 0 && cksumvalid == -1) { 1073 if (vrs.cksum == 0) 1074 cksumvalid = 1; 1075 else { 1076 if (bootverbose) 1077 pci_printf(cfg, 1078 "bad VPD cksum, remain %hhu\n", 1079 vrs.cksum); 1080 cksumvalid = 0; 1081 state = -1; 1082 break; 1083 } 1084 } 1085 dflen--; 1086 remain--; 1087 /* keep in sync w/ state 2's transistions */ 1088 if (dflen == 0) 1089 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1090 if (dflen == 0 && remain == 0) { 1091 cfg->vpd.vpd_rocnt = off; 1092 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1093 off * sizeof(*cfg->vpd.vpd_ros), 1094 M_DEVBUF, M_WAITOK | M_ZERO); 1095 state = 0; 1096 } else if (dflen == 0) 1097 state = 2; 1098 break; 1099 1100 case 4: 1101 remain--; 1102 if (remain == 0) 1103 state = 0; 1104 break; 1105 1106 case 5: /* VPD-W Keyword Header */ 1107 if (off == alloc) { 1108 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1109 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1110 M_DEVBUF, M_WAITOK | M_ZERO); 1111 } 1112 cfg->vpd.vpd_w[off].keyword[0] = byte; 1113 if (vpd_nextbyte(&vrs, &byte2)) { 1114 state = -2; 1115 break; 1116 } 1117 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1118 if (vpd_nextbyte(&vrs, &byte2)) { 1119 state = -2; 1120 break; 1121 } 1122 cfg->vpd.vpd_w[off].len = dflen = byte2; 1123 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1124 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1125 sizeof(*cfg->vpd.vpd_w[off].value), 1126 M_DEVBUF, M_WAITOK); 1127 remain -= 3; 1128 i = 0; 1129 /* keep in sync w/ state 6's transistions */ 1130 if (dflen == 0 && remain == 0) 1131 state = 0; 1132 else if (dflen == 0) 1133 state = 5; 1134 else 1135 state = 6; 1136 break; 1137 1138 case 6: /* VPD-W Keyword Value */ 1139 cfg->vpd.vpd_w[off].value[i++] = byte; 1140 dflen--; 1141 remain--; 1142 /* keep in sync w/ state 5's transistions */ 1143 if (dflen == 0) 1144 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1145 if (dflen == 0 && remain == 0) { 1146 cfg->vpd.vpd_wcnt = off; 1147 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1148 off * sizeof(*cfg->vpd.vpd_w), 1149 M_DEVBUF, M_WAITOK | M_ZERO); 1150 state = 0; 1151 } else if (dflen == 0) 1152 state = 5; 1153 break; 1154 1155 default: 1156 pci_printf(cfg, "invalid state: %d\n", state); 1157 state = -1; 1158 break; 1159 } 1160 } 1161 1162 if (cksumvalid == 0 || state < -1) { 1163 /* read-only data bad, clean up */ 1164 if (cfg->vpd.vpd_ros != NULL) { 1165 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1166 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1167 free(cfg->vpd.vpd_ros, M_DEVBUF); 1168 cfg->vpd.vpd_ros = NULL; 1169 } 1170 } 1171 if (state < -1) { 1172 /* I/O error, clean up */ 1173 pci_printf(cfg, "failed to read VPD data.\n"); 1174 if (cfg->vpd.vpd_ident != NULL) { 1175 free(cfg->vpd.vpd_ident, M_DEVBUF); 1176 cfg->vpd.vpd_ident = NULL; 1177 } 1178 if (cfg->vpd.vpd_w != NULL) { 1179 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1180 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1181 free(cfg->vpd.vpd_w, M_DEVBUF); 1182 cfg->vpd.vpd_w = NULL; 1183 } 1184 } 1185 cfg->vpd.vpd_cached = 1; 1186 #undef REG 1187 #undef WREG 1188 } 1189 1190 int 1191 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1192 { 1193 struct pci_devinfo *dinfo = device_get_ivars(child); 1194 pcicfgregs *cfg = &dinfo->cfg; 1195 1196 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1197 pci_read_vpd(device_get_parent(dev), cfg); 1198 1199 *identptr = cfg->vpd.vpd_ident; 1200 1201 if (*identptr == NULL) 1202 return (ENXIO); 1203 1204 return (0); 1205 } 1206 1207 int 1208 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1209 const char **vptr) 1210 { 1211 struct pci_devinfo *dinfo = device_get_ivars(child); 1212 pcicfgregs *cfg = &dinfo->cfg; 1213 int i; 1214 1215 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1216 pci_read_vpd(device_get_parent(dev), cfg); 1217 1218 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1219 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1220 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1221 *vptr = cfg->vpd.vpd_ros[i].value; 1222 return (0); 1223 } 1224 1225 *vptr = NULL; 1226 return (ENXIO); 1227 } 1228 1229 struct pcicfg_vpd * 1230 pci_fetch_vpd_list(device_t dev) 1231 { 1232 struct pci_devinfo *dinfo = device_get_ivars(dev); 1233 pcicfgregs *cfg = &dinfo->cfg; 1234 1235 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1236 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1237 return (&cfg->vpd); 1238 } 1239 1240 /* 1241 * Find the requested HyperTransport capability and return the offset 1242 * in configuration space via the pointer provided. The function 1243 * returns 0 on success and an error code otherwise. 1244 */ 1245 int 1246 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1247 { 1248 int ptr, error; 1249 uint16_t val; 1250 1251 error = pci_find_cap(child, PCIY_HT, &ptr); 1252 if (error) 1253 return (error); 1254 1255 /* 1256 * Traverse the capabilities list checking each HT capability 1257 * to see if it matches the requested HT capability. 1258 */ 1259 while (ptr != 0) { 1260 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1261 if (capability == PCIM_HTCAP_SLAVE || 1262 capability == PCIM_HTCAP_HOST) 1263 val &= 0xe000; 1264 else 1265 val &= PCIM_HTCMD_CAP_MASK; 1266 if (val == capability) { 1267 if (capreg != NULL) 1268 *capreg = ptr; 1269 return (0); 1270 } 1271 1272 /* Skip to the next HT capability. */ 1273 while (ptr != 0) { 1274 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1275 if (pci_read_config(child, ptr + PCICAP_ID, 1) == 1276 PCIY_HT) 1277 break; 1278 } 1279 } 1280 return (ENOENT); 1281 } 1282 1283 /* 1284 * Find the requested capability and return the offset in 1285 * configuration space via the pointer provided. The function returns 1286 * 0 on success and an error code otherwise. 1287 */ 1288 int 1289 pci_find_cap_method(device_t dev, device_t child, int capability, 1290 int *capreg) 1291 { 1292 struct pci_devinfo *dinfo = device_get_ivars(child); 1293 pcicfgregs *cfg = &dinfo->cfg; 1294 u_int32_t status; 1295 u_int8_t ptr; 1296 1297 /* 1298 * Check the CAP_LIST bit of the PCI status register first. 1299 */ 1300 status = pci_read_config(child, PCIR_STATUS, 2); 1301 if (!(status & PCIM_STATUS_CAPPRESENT)) 1302 return (ENXIO); 1303 1304 /* 1305 * Determine the start pointer of the capabilities list. 1306 */ 1307 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1308 case PCIM_HDRTYPE_NORMAL: 1309 case PCIM_HDRTYPE_BRIDGE: 1310 ptr = PCIR_CAP_PTR; 1311 break; 1312 case PCIM_HDRTYPE_CARDBUS: 1313 ptr = PCIR_CAP_PTR_2; 1314 break; 1315 default: 1316 /* XXX: panic? */ 1317 return (ENXIO); /* no extended capabilities support */ 1318 } 1319 ptr = pci_read_config(child, ptr, 1); 1320 1321 /* 1322 * Traverse the capabilities list. 1323 */ 1324 while (ptr != 0) { 1325 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1326 if (capreg != NULL) 1327 *capreg = ptr; 1328 return (0); 1329 } 1330 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1331 } 1332 1333 return (ENOENT); 1334 } 1335 1336 /* 1337 * Find the requested extended capability and return the offset in 1338 * configuration space via the pointer provided. The function returns 1339 * 0 on success and an error code otherwise. 1340 */ 1341 int 1342 pci_find_extcap_method(device_t dev, device_t child, int capability, 1343 int *capreg) 1344 { 1345 struct pci_devinfo *dinfo = device_get_ivars(child); 1346 pcicfgregs *cfg = &dinfo->cfg; 1347 uint32_t ecap; 1348 uint16_t ptr; 1349 1350 /* Only supported for PCI-express devices. */ 1351 if (cfg->pcie.pcie_location == 0) 1352 return (ENXIO); 1353 1354 ptr = PCIR_EXTCAP; 1355 ecap = pci_read_config(child, ptr, 4); 1356 if (ecap == 0xffffffff || ecap == 0) 1357 return (ENOENT); 1358 for (;;) { 1359 if (PCI_EXTCAP_ID(ecap) == capability) { 1360 if (capreg != NULL) 1361 *capreg = ptr; 1362 return (0); 1363 } 1364 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1365 if (ptr == 0) 1366 break; 1367 ecap = pci_read_config(child, ptr, 4); 1368 } 1369 1370 return (ENOENT); 1371 } 1372 1373 /* 1374 * Support for MSI-X message interrupts. 1375 */ 1376 void 1377 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 1378 { 1379 struct pci_devinfo *dinfo = device_get_ivars(dev); 1380 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1381 uint32_t offset; 1382 1383 KASSERT(msix->msix_table_len > index, ("bogus index")); 1384 offset = msix->msix_table_offset + index * 16; 1385 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1386 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1387 bus_write_4(msix->msix_table_res, offset + 8, data); 1388 1389 /* Enable MSI -> HT mapping. */ 1390 pci_ht_map_msi(dev, address); 1391 } 1392 1393 void 1394 pci_mask_msix(device_t dev, u_int index) 1395 { 1396 struct pci_devinfo *dinfo = device_get_ivars(dev); 1397 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1398 uint32_t offset, val; 1399 1400 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1401 offset = msix->msix_table_offset + index * 16 + 12; 1402 val = bus_read_4(msix->msix_table_res, offset); 1403 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 1404 val |= PCIM_MSIX_VCTRL_MASK; 1405 bus_write_4(msix->msix_table_res, offset, val); 1406 } 1407 } 1408 1409 void 1410 pci_unmask_msix(device_t dev, u_int index) 1411 { 1412 struct pci_devinfo *dinfo = device_get_ivars(dev); 1413 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1414 uint32_t offset, val; 1415 1416 KASSERT(msix->msix_table_len > index, ("bogus index")); 1417 offset = msix->msix_table_offset + index * 16 + 12; 1418 val = bus_read_4(msix->msix_table_res, offset); 1419 if (val & PCIM_MSIX_VCTRL_MASK) { 1420 val &= ~PCIM_MSIX_VCTRL_MASK; 1421 bus_write_4(msix->msix_table_res, offset, val); 1422 } 1423 } 1424 1425 int 1426 pci_pending_msix(device_t dev, u_int index) 1427 { 1428 struct pci_devinfo *dinfo = device_get_ivars(dev); 1429 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1430 uint32_t offset, bit; 1431 1432 KASSERT(msix->msix_table_len > index, ("bogus index")); 1433 offset = msix->msix_pba_offset + (index / 32) * 4; 1434 bit = 1 << index % 32; 1435 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1436 } 1437 1438 /* 1439 * Restore MSI-X registers and table during resume. If MSI-X is 1440 * enabled then walk the virtual table to restore the actual MSI-X 1441 * table. 1442 */ 1443 static void 1444 pci_resume_msix(device_t dev) 1445 { 1446 struct pci_devinfo *dinfo = device_get_ivars(dev); 1447 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1448 struct msix_table_entry *mte; 1449 struct msix_vector *mv; 1450 int i; 1451 1452 if (msix->msix_alloc > 0) { 1453 /* First, mask all vectors. */ 1454 for (i = 0; i < msix->msix_msgnum; i++) 1455 pci_mask_msix(dev, i); 1456 1457 /* Second, program any messages with at least one handler. */ 1458 for (i = 0; i < msix->msix_table_len; i++) { 1459 mte = &msix->msix_table[i]; 1460 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1461 continue; 1462 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1463 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data); 1464 pci_unmask_msix(dev, i); 1465 } 1466 } 1467 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1468 msix->msix_ctrl, 2); 1469 } 1470 1471 /* 1472 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1473 * returned in *count. After this function returns, each message will be 1474 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1475 */ 1476 int 1477 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1478 { 1479 struct pci_devinfo *dinfo = device_get_ivars(child); 1480 pcicfgregs *cfg = &dinfo->cfg; 1481 struct resource_list_entry *rle; 1482 int actual, error, i, irq, max; 1483 1484 /* Don't let count == 0 get us into trouble. */ 1485 if (*count == 0) 1486 return (EINVAL); 1487 1488 /* If rid 0 is allocated, then fail. */ 1489 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1490 if (rle != NULL && rle->res != NULL) 1491 return (ENXIO); 1492 1493 /* Already have allocated messages? */ 1494 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1495 return (ENXIO); 1496 1497 /* If MSI-X is blacklisted for this system, fail. */ 1498 if (pci_msix_blacklisted()) 1499 return (ENXIO); 1500 1501 /* MSI-X capability present? */ 1502 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1503 return (ENODEV); 1504 1505 /* Make sure the appropriate BARs are mapped. */ 1506 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1507 cfg->msix.msix_table_bar); 1508 if (rle == NULL || rle->res == NULL || 1509 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1510 return (ENXIO); 1511 cfg->msix.msix_table_res = rle->res; 1512 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1513 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1514 cfg->msix.msix_pba_bar); 1515 if (rle == NULL || rle->res == NULL || 1516 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1517 return (ENXIO); 1518 } 1519 cfg->msix.msix_pba_res = rle->res; 1520 1521 if (bootverbose) 1522 device_printf(child, 1523 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1524 *count, cfg->msix.msix_msgnum); 1525 max = min(*count, cfg->msix.msix_msgnum); 1526 for (i = 0; i < max; i++) { 1527 /* Allocate a message. */ 1528 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1529 if (error) { 1530 if (i == 0) 1531 return (error); 1532 break; 1533 } 1534 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1535 irq, 1); 1536 } 1537 actual = i; 1538 1539 if (bootverbose) { 1540 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1541 if (actual == 1) 1542 device_printf(child, "using IRQ %lu for MSI-X\n", 1543 rle->start); 1544 else { 1545 int run; 1546 1547 /* 1548 * Be fancy and try to print contiguous runs of 1549 * IRQ values as ranges. 'irq' is the previous IRQ. 1550 * 'run' is true if we are in a range. 1551 */ 1552 device_printf(child, "using IRQs %lu", rle->start); 1553 irq = rle->start; 1554 run = 0; 1555 for (i = 1; i < actual; i++) { 1556 rle = resource_list_find(&dinfo->resources, 1557 SYS_RES_IRQ, i + 1); 1558 1559 /* Still in a run? */ 1560 if (rle->start == irq + 1) { 1561 run = 1; 1562 irq++; 1563 continue; 1564 } 1565 1566 /* Finish previous range. */ 1567 if (run) { 1568 printf("-%d", irq); 1569 run = 0; 1570 } 1571 1572 /* Start new range. */ 1573 printf(",%lu", rle->start); 1574 irq = rle->start; 1575 } 1576 1577 /* Unfinished range? */ 1578 if (run) 1579 printf("-%d", irq); 1580 printf(" for MSI-X\n"); 1581 } 1582 } 1583 1584 /* Mask all vectors. */ 1585 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1586 pci_mask_msix(child, i); 1587 1588 /* Allocate and initialize vector data and virtual table. */ 1589 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1590 M_DEVBUF, M_WAITOK | M_ZERO); 1591 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1592 M_DEVBUF, M_WAITOK | M_ZERO); 1593 for (i = 0; i < actual; i++) { 1594 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1595 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1596 cfg->msix.msix_table[i].mte_vector = i + 1; 1597 } 1598 1599 /* Update control register to enable MSI-X. */ 1600 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1601 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1602 cfg->msix.msix_ctrl, 2); 1603 1604 /* Update counts of alloc'd messages. */ 1605 cfg->msix.msix_alloc = actual; 1606 cfg->msix.msix_table_len = actual; 1607 *count = actual; 1608 return (0); 1609 } 1610 1611 /* 1612 * By default, pci_alloc_msix() will assign the allocated IRQ 1613 * resources consecutively to the first N messages in the MSI-X table. 1614 * However, device drivers may want to use different layouts if they 1615 * either receive fewer messages than they asked for, or they wish to 1616 * populate the MSI-X table sparsely. This method allows the driver 1617 * to specify what layout it wants. It must be called after a 1618 * successful pci_alloc_msix() but before any of the associated 1619 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1620 * 1621 * The 'vectors' array contains 'count' message vectors. The array 1622 * maps directly to the MSI-X table in that index 0 in the array 1623 * specifies the vector for the first message in the MSI-X table, etc. 1624 * The vector value in each array index can either be 0 to indicate 1625 * that no vector should be assigned to a message slot, or it can be a 1626 * number from 1 to N (where N is the count returned from a 1627 * succcessful call to pci_alloc_msix()) to indicate which message 1628 * vector (IRQ) to be used for the corresponding message. 1629 * 1630 * On successful return, each message with a non-zero vector will have 1631 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1632 * 1. Additionally, if any of the IRQs allocated via the previous 1633 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1634 * will be freed back to the system automatically. 1635 * 1636 * For example, suppose a driver has a MSI-X table with 6 messages and 1637 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1638 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1639 * C. After the call to pci_alloc_msix(), the device will be setup to 1640 * have an MSI-X table of ABC--- (where - means no vector assigned). 1641 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1642 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1643 * be freed back to the system. This device will also have valid 1644 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1645 * 1646 * In any case, the SYS_RES_IRQ rid X will always map to the message 1647 * at MSI-X table index X - 1 and will only be valid if a vector is 1648 * assigned to that table entry. 1649 */ 1650 int 1651 pci_remap_msix_method(device_t dev, device_t child, int count, 1652 const u_int *vectors) 1653 { 1654 struct pci_devinfo *dinfo = device_get_ivars(child); 1655 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1656 struct resource_list_entry *rle; 1657 int i, irq, j, *used; 1658 1659 /* 1660 * Have to have at least one message in the table but the 1661 * table can't be bigger than the actual MSI-X table in the 1662 * device. 1663 */ 1664 if (count == 0 || count > msix->msix_msgnum) 1665 return (EINVAL); 1666 1667 /* Sanity check the vectors. */ 1668 for (i = 0; i < count; i++) 1669 if (vectors[i] > msix->msix_alloc) 1670 return (EINVAL); 1671 1672 /* 1673 * Make sure there aren't any holes in the vectors to be used. 1674 * It's a big pain to support it, and it doesn't really make 1675 * sense anyway. Also, at least one vector must be used. 1676 */ 1677 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1678 M_ZERO); 1679 for (i = 0; i < count; i++) 1680 if (vectors[i] != 0) 1681 used[vectors[i] - 1] = 1; 1682 for (i = 0; i < msix->msix_alloc - 1; i++) 1683 if (used[i] == 0 && used[i + 1] == 1) { 1684 free(used, M_DEVBUF); 1685 return (EINVAL); 1686 } 1687 if (used[0] != 1) { 1688 free(used, M_DEVBUF); 1689 return (EINVAL); 1690 } 1691 1692 /* Make sure none of the resources are allocated. */ 1693 for (i = 0; i < msix->msix_table_len; i++) { 1694 if (msix->msix_table[i].mte_vector == 0) 1695 continue; 1696 if (msix->msix_table[i].mte_handlers > 0) 1697 return (EBUSY); 1698 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1699 KASSERT(rle != NULL, ("missing resource")); 1700 if (rle->res != NULL) 1701 return (EBUSY); 1702 } 1703 1704 /* Free the existing resource list entries. */ 1705 for (i = 0; i < msix->msix_table_len; i++) { 1706 if (msix->msix_table[i].mte_vector == 0) 1707 continue; 1708 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1709 } 1710 1711 /* 1712 * Build the new virtual table keeping track of which vectors are 1713 * used. 1714 */ 1715 free(msix->msix_table, M_DEVBUF); 1716 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1717 M_DEVBUF, M_WAITOK | M_ZERO); 1718 for (i = 0; i < count; i++) 1719 msix->msix_table[i].mte_vector = vectors[i]; 1720 msix->msix_table_len = count; 1721 1722 /* Free any unused IRQs and resize the vectors array if necessary. */ 1723 j = msix->msix_alloc - 1; 1724 if (used[j] == 0) { 1725 struct msix_vector *vec; 1726 1727 while (used[j] == 0) { 1728 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1729 msix->msix_vectors[j].mv_irq); 1730 j--; 1731 } 1732 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 1733 M_WAITOK); 1734 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 1735 (j + 1)); 1736 free(msix->msix_vectors, M_DEVBUF); 1737 msix->msix_vectors = vec; 1738 msix->msix_alloc = j + 1; 1739 } 1740 free(used, M_DEVBUF); 1741 1742 /* Map the IRQs onto the rids. */ 1743 for (i = 0; i < count; i++) { 1744 if (vectors[i] == 0) 1745 continue; 1746 irq = msix->msix_vectors[vectors[i]].mv_irq; 1747 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1748 irq, 1); 1749 } 1750 1751 if (bootverbose) { 1752 device_printf(child, "Remapped MSI-X IRQs as: "); 1753 for (i = 0; i < count; i++) { 1754 if (i != 0) 1755 printf(", "); 1756 if (vectors[i] == 0) 1757 printf("---"); 1758 else 1759 printf("%d", 1760 msix->msix_vectors[vectors[i]].mv_irq); 1761 } 1762 printf("\n"); 1763 } 1764 1765 return (0); 1766 } 1767 1768 static int 1769 pci_release_msix(device_t dev, device_t child) 1770 { 1771 struct pci_devinfo *dinfo = device_get_ivars(child); 1772 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1773 struct resource_list_entry *rle; 1774 int i; 1775 1776 /* Do we have any messages to release? */ 1777 if (msix->msix_alloc == 0) 1778 return (ENODEV); 1779 1780 /* Make sure none of the resources are allocated. */ 1781 for (i = 0; i < msix->msix_table_len; i++) { 1782 if (msix->msix_table[i].mte_vector == 0) 1783 continue; 1784 if (msix->msix_table[i].mte_handlers > 0) 1785 return (EBUSY); 1786 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1787 KASSERT(rle != NULL, ("missing resource")); 1788 if (rle->res != NULL) 1789 return (EBUSY); 1790 } 1791 1792 /* Update control register to disable MSI-X. */ 1793 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1794 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 1795 msix->msix_ctrl, 2); 1796 1797 /* Free the resource list entries. */ 1798 for (i = 0; i < msix->msix_table_len; i++) { 1799 if (msix->msix_table[i].mte_vector == 0) 1800 continue; 1801 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1802 } 1803 free(msix->msix_table, M_DEVBUF); 1804 msix->msix_table_len = 0; 1805 1806 /* Release the IRQs. */ 1807 for (i = 0; i < msix->msix_alloc; i++) 1808 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1809 msix->msix_vectors[i].mv_irq); 1810 free(msix->msix_vectors, M_DEVBUF); 1811 msix->msix_alloc = 0; 1812 return (0); 1813 } 1814 1815 /* 1816 * Return the max supported MSI-X messages this device supports. 1817 * Basically, assuming the MD code can alloc messages, this function 1818 * should return the maximum value that pci_alloc_msix() can return. 1819 * Thus, it is subject to the tunables, etc. 1820 */ 1821 int 1822 pci_msix_count_method(device_t dev, device_t child) 1823 { 1824 struct pci_devinfo *dinfo = device_get_ivars(child); 1825 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1826 1827 if (pci_do_msix && msix->msix_location != 0) 1828 return (msix->msix_msgnum); 1829 return (0); 1830 } 1831 1832 /* 1833 * HyperTransport MSI mapping control 1834 */ 1835 void 1836 pci_ht_map_msi(device_t dev, uint64_t addr) 1837 { 1838 struct pci_devinfo *dinfo = device_get_ivars(dev); 1839 struct pcicfg_ht *ht = &dinfo->cfg.ht; 1840 1841 if (!ht->ht_msimap) 1842 return; 1843 1844 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 1845 ht->ht_msiaddr >> 20 == addr >> 20) { 1846 /* Enable MSI -> HT mapping. */ 1847 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1848 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1849 ht->ht_msictrl, 2); 1850 } 1851 1852 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 1853 /* Disable MSI -> HT mapping. */ 1854 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 1855 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1856 ht->ht_msictrl, 2); 1857 } 1858 } 1859 1860 int 1861 pci_get_max_read_req(device_t dev) 1862 { 1863 struct pci_devinfo *dinfo = device_get_ivars(dev); 1864 int cap; 1865 uint16_t val; 1866 1867 cap = dinfo->cfg.pcie.pcie_location; 1868 if (cap == 0) 1869 return (0); 1870 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 1871 val &= PCIEM_CTL_MAX_READ_REQUEST; 1872 val >>= 12; 1873 return (1 << (val + 7)); 1874 } 1875 1876 int 1877 pci_set_max_read_req(device_t dev, int size) 1878 { 1879 struct pci_devinfo *dinfo = device_get_ivars(dev); 1880 int cap; 1881 uint16_t val; 1882 1883 cap = dinfo->cfg.pcie.pcie_location; 1884 if (cap == 0) 1885 return (0); 1886 if (size < 128) 1887 size = 128; 1888 if (size > 4096) 1889 size = 4096; 1890 size = (1 << (fls(size) - 1)); 1891 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 1892 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 1893 val |= (fls(size) - 8) << 12; 1894 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 1895 return (size); 1896 } 1897 1898 /* 1899 * Support for MSI message signalled interrupts. 1900 */ 1901 void 1902 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1903 { 1904 struct pci_devinfo *dinfo = device_get_ivars(dev); 1905 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1906 1907 /* Write data and address values. */ 1908 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1909 address & 0xffffffff, 4); 1910 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1911 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH, 1912 address >> 32, 4); 1913 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT, 1914 data, 2); 1915 } else 1916 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data, 1917 2); 1918 1919 /* Enable MSI in the control register. */ 1920 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1921 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1922 2); 1923 1924 /* Enable MSI -> HT mapping. */ 1925 pci_ht_map_msi(dev, address); 1926 } 1927 1928 void 1929 pci_disable_msi(device_t dev) 1930 { 1931 struct pci_devinfo *dinfo = device_get_ivars(dev); 1932 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1933 1934 /* Disable MSI -> HT mapping. */ 1935 pci_ht_map_msi(dev, 0); 1936 1937 /* Disable MSI in the control register. */ 1938 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 1939 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1940 2); 1941 } 1942 1943 /* 1944 * Restore MSI registers during resume. If MSI is enabled then 1945 * restore the data and address registers in addition to the control 1946 * register. 1947 */ 1948 static void 1949 pci_resume_msi(device_t dev) 1950 { 1951 struct pci_devinfo *dinfo = device_get_ivars(dev); 1952 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1953 uint64_t address; 1954 uint16_t data; 1955 1956 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1957 address = msi->msi_addr; 1958 data = msi->msi_data; 1959 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1960 address & 0xffffffff, 4); 1961 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1962 pci_write_config(dev, msi->msi_location + 1963 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1964 pci_write_config(dev, msi->msi_location + 1965 PCIR_MSI_DATA_64BIT, data, 2); 1966 } else 1967 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 1968 data, 2); 1969 } 1970 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1971 2); 1972 } 1973 1974 static int 1975 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 1976 { 1977 struct pci_devinfo *dinfo = device_get_ivars(dev); 1978 pcicfgregs *cfg = &dinfo->cfg; 1979 struct resource_list_entry *rle; 1980 struct msix_table_entry *mte; 1981 struct msix_vector *mv; 1982 uint64_t addr; 1983 uint32_t data; 1984 int error, i, j; 1985 1986 /* 1987 * Handle MSI first. We try to find this IRQ among our list 1988 * of MSI IRQs. If we find it, we request updated address and 1989 * data registers and apply the results. 1990 */ 1991 if (cfg->msi.msi_alloc > 0) { 1992 1993 /* If we don't have any active handlers, nothing to do. */ 1994 if (cfg->msi.msi_handlers == 0) 1995 return (0); 1996 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1997 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1998 i + 1); 1999 if (rle->start == irq) { 2000 error = PCIB_MAP_MSI(device_get_parent(bus), 2001 dev, irq, &addr, &data); 2002 if (error) 2003 return (error); 2004 pci_disable_msi(dev); 2005 dinfo->cfg.msi.msi_addr = addr; 2006 dinfo->cfg.msi.msi_data = data; 2007 pci_enable_msi(dev, addr, data); 2008 return (0); 2009 } 2010 } 2011 return (ENOENT); 2012 } 2013 2014 /* 2015 * For MSI-X, we check to see if we have this IRQ. If we do, 2016 * we request the updated mapping info. If that works, we go 2017 * through all the slots that use this IRQ and update them. 2018 */ 2019 if (cfg->msix.msix_alloc > 0) { 2020 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2021 mv = &cfg->msix.msix_vectors[i]; 2022 if (mv->mv_irq == irq) { 2023 error = PCIB_MAP_MSI(device_get_parent(bus), 2024 dev, irq, &addr, &data); 2025 if (error) 2026 return (error); 2027 mv->mv_address = addr; 2028 mv->mv_data = data; 2029 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2030 mte = &cfg->msix.msix_table[j]; 2031 if (mte->mte_vector != i + 1) 2032 continue; 2033 if (mte->mte_handlers == 0) 2034 continue; 2035 pci_mask_msix(dev, j); 2036 pci_enable_msix(dev, j, addr, data); 2037 pci_unmask_msix(dev, j); 2038 } 2039 } 2040 } 2041 return (ENOENT); 2042 } 2043 2044 return (ENOENT); 2045 } 2046 2047 /* 2048 * Returns true if the specified device is blacklisted because MSI 2049 * doesn't work. 2050 */ 2051 int 2052 pci_msi_device_blacklisted(device_t dev) 2053 { 2054 2055 if (!pci_honor_msi_blacklist) 2056 return (0); 2057 2058 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2059 } 2060 2061 /* 2062 * Determine if MSI is blacklisted globally on this system. Currently, 2063 * we just check for blacklisted chipsets as represented by the 2064 * host-PCI bridge at device 0:0:0. In the future, it may become 2065 * necessary to check other system attributes, such as the kenv values 2066 * that give the motherboard manufacturer and model number. 2067 */ 2068 static int 2069 pci_msi_blacklisted(void) 2070 { 2071 device_t dev; 2072 2073 if (!pci_honor_msi_blacklist) 2074 return (0); 2075 2076 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2077 if (!(pcie_chipset || pcix_chipset)) { 2078 if (vm_guest != VM_GUEST_NO) { 2079 /* 2080 * Whitelist older chipsets in virtual 2081 * machines known to support MSI. 2082 */ 2083 dev = pci_find_bsf(0, 0, 0); 2084 if (dev != NULL) 2085 return (!pci_has_quirk(pci_get_devid(dev), 2086 PCI_QUIRK_ENABLE_MSI_VM)); 2087 } 2088 return (1); 2089 } 2090 2091 dev = pci_find_bsf(0, 0, 0); 2092 if (dev != NULL) 2093 return (pci_msi_device_blacklisted(dev)); 2094 return (0); 2095 } 2096 2097 /* 2098 * Returns true if the specified device is blacklisted because MSI-X 2099 * doesn't work. Note that this assumes that if MSI doesn't work, 2100 * MSI-X doesn't either. 2101 */ 2102 int 2103 pci_msix_device_blacklisted(device_t dev) 2104 { 2105 2106 if (!pci_honor_msi_blacklist) 2107 return (0); 2108 2109 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2110 return (1); 2111 2112 return (pci_msi_device_blacklisted(dev)); 2113 } 2114 2115 /* 2116 * Determine if MSI-X is blacklisted globally on this system. If MSI 2117 * is blacklisted, assume that MSI-X is as well. Check for additional 2118 * chipsets where MSI works but MSI-X does not. 2119 */ 2120 static int 2121 pci_msix_blacklisted(void) 2122 { 2123 device_t dev; 2124 2125 if (!pci_honor_msi_blacklist) 2126 return (0); 2127 2128 dev = pci_find_bsf(0, 0, 0); 2129 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2130 PCI_QUIRK_DISABLE_MSIX)) 2131 return (1); 2132 2133 return (pci_msi_blacklisted()); 2134 } 2135 2136 /* 2137 * Attempt to allocate *count MSI messages. The actual number allocated is 2138 * returned in *count. After this function returns, each message will be 2139 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2140 */ 2141 int 2142 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2143 { 2144 struct pci_devinfo *dinfo = device_get_ivars(child); 2145 pcicfgregs *cfg = &dinfo->cfg; 2146 struct resource_list_entry *rle; 2147 int actual, error, i, irqs[32]; 2148 uint16_t ctrl; 2149 2150 /* Don't let count == 0 get us into trouble. */ 2151 if (*count == 0) 2152 return (EINVAL); 2153 2154 /* If rid 0 is allocated, then fail. */ 2155 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2156 if (rle != NULL && rle->res != NULL) 2157 return (ENXIO); 2158 2159 /* Already have allocated messages? */ 2160 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2161 return (ENXIO); 2162 2163 /* If MSI is blacklisted for this system, fail. */ 2164 if (pci_msi_blacklisted()) 2165 return (ENXIO); 2166 2167 /* MSI capability present? */ 2168 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2169 return (ENODEV); 2170 2171 if (bootverbose) 2172 device_printf(child, 2173 "attempting to allocate %d MSI vectors (%d supported)\n", 2174 *count, cfg->msi.msi_msgnum); 2175 2176 /* Don't ask for more than the device supports. */ 2177 actual = min(*count, cfg->msi.msi_msgnum); 2178 2179 /* Don't ask for more than 32 messages. */ 2180 actual = min(actual, 32); 2181 2182 /* MSI requires power of 2 number of messages. */ 2183 if (!powerof2(actual)) 2184 return (EINVAL); 2185 2186 for (;;) { 2187 /* Try to allocate N messages. */ 2188 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2189 actual, irqs); 2190 if (error == 0) 2191 break; 2192 if (actual == 1) 2193 return (error); 2194 2195 /* Try N / 2. */ 2196 actual >>= 1; 2197 } 2198 2199 /* 2200 * We now have N actual messages mapped onto SYS_RES_IRQ 2201 * resources in the irqs[] array, so add new resources 2202 * starting at rid 1. 2203 */ 2204 for (i = 0; i < actual; i++) 2205 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2206 irqs[i], irqs[i], 1); 2207 2208 if (bootverbose) { 2209 if (actual == 1) 2210 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2211 else { 2212 int run; 2213 2214 /* 2215 * Be fancy and try to print contiguous runs 2216 * of IRQ values as ranges. 'run' is true if 2217 * we are in a range. 2218 */ 2219 device_printf(child, "using IRQs %d", irqs[0]); 2220 run = 0; 2221 for (i = 1; i < actual; i++) { 2222 2223 /* Still in a run? */ 2224 if (irqs[i] == irqs[i - 1] + 1) { 2225 run = 1; 2226 continue; 2227 } 2228 2229 /* Finish previous range. */ 2230 if (run) { 2231 printf("-%d", irqs[i - 1]); 2232 run = 0; 2233 } 2234 2235 /* Start new range. */ 2236 printf(",%d", irqs[i]); 2237 } 2238 2239 /* Unfinished range? */ 2240 if (run) 2241 printf("-%d", irqs[actual - 1]); 2242 printf(" for MSI\n"); 2243 } 2244 } 2245 2246 /* Update control register with actual count. */ 2247 ctrl = cfg->msi.msi_ctrl; 2248 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2249 ctrl |= (ffs(actual) - 1) << 4; 2250 cfg->msi.msi_ctrl = ctrl; 2251 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2252 2253 /* Update counts of alloc'd messages. */ 2254 cfg->msi.msi_alloc = actual; 2255 cfg->msi.msi_handlers = 0; 2256 *count = actual; 2257 return (0); 2258 } 2259 2260 /* Release the MSI messages associated with this device. */ 2261 int 2262 pci_release_msi_method(device_t dev, device_t child) 2263 { 2264 struct pci_devinfo *dinfo = device_get_ivars(child); 2265 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2266 struct resource_list_entry *rle; 2267 int error, i, irqs[32]; 2268 2269 /* Try MSI-X first. */ 2270 error = pci_release_msix(dev, child); 2271 if (error != ENODEV) 2272 return (error); 2273 2274 /* Do we have any messages to release? */ 2275 if (msi->msi_alloc == 0) 2276 return (ENODEV); 2277 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2278 2279 /* Make sure none of the resources are allocated. */ 2280 if (msi->msi_handlers > 0) 2281 return (EBUSY); 2282 for (i = 0; i < msi->msi_alloc; i++) { 2283 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2284 KASSERT(rle != NULL, ("missing MSI resource")); 2285 if (rle->res != NULL) 2286 return (EBUSY); 2287 irqs[i] = rle->start; 2288 } 2289 2290 /* Update control register with 0 count. */ 2291 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2292 ("%s: MSI still enabled", __func__)); 2293 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2294 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2295 msi->msi_ctrl, 2); 2296 2297 /* Release the messages. */ 2298 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2299 for (i = 0; i < msi->msi_alloc; i++) 2300 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2301 2302 /* Update alloc count. */ 2303 msi->msi_alloc = 0; 2304 msi->msi_addr = 0; 2305 msi->msi_data = 0; 2306 return (0); 2307 } 2308 2309 /* 2310 * Return the max supported MSI messages this device supports. 2311 * Basically, assuming the MD code can alloc messages, this function 2312 * should return the maximum value that pci_alloc_msi() can return. 2313 * Thus, it is subject to the tunables, etc. 2314 */ 2315 int 2316 pci_msi_count_method(device_t dev, device_t child) 2317 { 2318 struct pci_devinfo *dinfo = device_get_ivars(child); 2319 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2320 2321 if (pci_do_msi && msi->msi_location != 0) 2322 return (msi->msi_msgnum); 2323 return (0); 2324 } 2325 2326 /* free pcicfgregs structure and all depending data structures */ 2327 2328 int 2329 pci_freecfg(struct pci_devinfo *dinfo) 2330 { 2331 struct devlist *devlist_head; 2332 struct pci_map *pm, *next; 2333 int i; 2334 2335 devlist_head = &pci_devq; 2336 2337 if (dinfo->cfg.vpd.vpd_reg) { 2338 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2339 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2340 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2341 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2342 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2343 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2344 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2345 } 2346 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2347 free(pm, M_DEVBUF); 2348 } 2349 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2350 free(dinfo, M_DEVBUF); 2351 2352 /* increment the generation count */ 2353 pci_generation++; 2354 2355 /* we're losing one device */ 2356 pci_numdevs--; 2357 return (0); 2358 } 2359 2360 /* 2361 * PCI power manangement 2362 */ 2363 int 2364 pci_set_powerstate_method(device_t dev, device_t child, int state) 2365 { 2366 struct pci_devinfo *dinfo = device_get_ivars(child); 2367 pcicfgregs *cfg = &dinfo->cfg; 2368 uint16_t status; 2369 int oldstate, highest, delay; 2370 2371 if (cfg->pp.pp_cap == 0) 2372 return (EOPNOTSUPP); 2373 2374 /* 2375 * Optimize a no state change request away. While it would be OK to 2376 * write to the hardware in theory, some devices have shown odd 2377 * behavior when going from D3 -> D3. 2378 */ 2379 oldstate = pci_get_powerstate(child); 2380 if (oldstate == state) 2381 return (0); 2382 2383 /* 2384 * The PCI power management specification states that after a state 2385 * transition between PCI power states, system software must 2386 * guarantee a minimal delay before the function accesses the device. 2387 * Compute the worst case delay that we need to guarantee before we 2388 * access the device. Many devices will be responsive much more 2389 * quickly than this delay, but there are some that don't respond 2390 * instantly to state changes. Transitions to/from D3 state require 2391 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2392 * is done below with DELAY rather than a sleeper function because 2393 * this function can be called from contexts where we cannot sleep. 2394 */ 2395 highest = (oldstate > state) ? oldstate : state; 2396 if (highest == PCI_POWERSTATE_D3) 2397 delay = 10000; 2398 else if (highest == PCI_POWERSTATE_D2) 2399 delay = 200; 2400 else 2401 delay = 0; 2402 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2403 & ~PCIM_PSTAT_DMASK; 2404 switch (state) { 2405 case PCI_POWERSTATE_D0: 2406 status |= PCIM_PSTAT_D0; 2407 break; 2408 case PCI_POWERSTATE_D1: 2409 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2410 return (EOPNOTSUPP); 2411 status |= PCIM_PSTAT_D1; 2412 break; 2413 case PCI_POWERSTATE_D2: 2414 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2415 return (EOPNOTSUPP); 2416 status |= PCIM_PSTAT_D2; 2417 break; 2418 case PCI_POWERSTATE_D3: 2419 status |= PCIM_PSTAT_D3; 2420 break; 2421 default: 2422 return (EINVAL); 2423 } 2424 2425 if (bootverbose) 2426 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2427 state); 2428 2429 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2430 if (delay) 2431 DELAY(delay); 2432 return (0); 2433 } 2434 2435 int 2436 pci_get_powerstate_method(device_t dev, device_t child) 2437 { 2438 struct pci_devinfo *dinfo = device_get_ivars(child); 2439 pcicfgregs *cfg = &dinfo->cfg; 2440 uint16_t status; 2441 int result; 2442 2443 if (cfg->pp.pp_cap != 0) { 2444 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2445 switch (status & PCIM_PSTAT_DMASK) { 2446 case PCIM_PSTAT_D0: 2447 result = PCI_POWERSTATE_D0; 2448 break; 2449 case PCIM_PSTAT_D1: 2450 result = PCI_POWERSTATE_D1; 2451 break; 2452 case PCIM_PSTAT_D2: 2453 result = PCI_POWERSTATE_D2; 2454 break; 2455 case PCIM_PSTAT_D3: 2456 result = PCI_POWERSTATE_D3; 2457 break; 2458 default: 2459 result = PCI_POWERSTATE_UNKNOWN; 2460 break; 2461 } 2462 } else { 2463 /* No support, device is always at D0 */ 2464 result = PCI_POWERSTATE_D0; 2465 } 2466 return (result); 2467 } 2468 2469 /* 2470 * Some convenience functions for PCI device drivers. 2471 */ 2472 2473 static __inline void 2474 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2475 { 2476 uint16_t command; 2477 2478 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2479 command |= bit; 2480 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2481 } 2482 2483 static __inline void 2484 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2485 { 2486 uint16_t command; 2487 2488 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2489 command &= ~bit; 2490 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2491 } 2492 2493 int 2494 pci_enable_busmaster_method(device_t dev, device_t child) 2495 { 2496 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2497 return (0); 2498 } 2499 2500 int 2501 pci_disable_busmaster_method(device_t dev, device_t child) 2502 { 2503 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2504 return (0); 2505 } 2506 2507 int 2508 pci_enable_io_method(device_t dev, device_t child, int space) 2509 { 2510 uint16_t bit; 2511 2512 switch(space) { 2513 case SYS_RES_IOPORT: 2514 bit = PCIM_CMD_PORTEN; 2515 break; 2516 case SYS_RES_MEMORY: 2517 bit = PCIM_CMD_MEMEN; 2518 break; 2519 default: 2520 return (EINVAL); 2521 } 2522 pci_set_command_bit(dev, child, bit); 2523 return (0); 2524 } 2525 2526 int 2527 pci_disable_io_method(device_t dev, device_t child, int space) 2528 { 2529 uint16_t bit; 2530 2531 switch(space) { 2532 case SYS_RES_IOPORT: 2533 bit = PCIM_CMD_PORTEN; 2534 break; 2535 case SYS_RES_MEMORY: 2536 bit = PCIM_CMD_MEMEN; 2537 break; 2538 default: 2539 return (EINVAL); 2540 } 2541 pci_clear_command_bit(dev, child, bit); 2542 return (0); 2543 } 2544 2545 /* 2546 * New style pci driver. Parent device is either a pci-host-bridge or a 2547 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2548 */ 2549 2550 void 2551 pci_print_verbose(struct pci_devinfo *dinfo) 2552 { 2553 2554 if (bootverbose) { 2555 pcicfgregs *cfg = &dinfo->cfg; 2556 2557 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2558 cfg->vendor, cfg->device, cfg->revid); 2559 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2560 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2561 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2562 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2563 cfg->mfdev); 2564 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2565 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2566 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2567 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2568 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2569 if (cfg->intpin > 0) 2570 printf("\tintpin=%c, irq=%d\n", 2571 cfg->intpin +'a' -1, cfg->intline); 2572 if (cfg->pp.pp_cap) { 2573 uint16_t status; 2574 2575 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2576 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2577 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2578 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2579 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2580 status & PCIM_PSTAT_DMASK); 2581 } 2582 if (cfg->msi.msi_location) { 2583 int ctrl; 2584 2585 ctrl = cfg->msi.msi_ctrl; 2586 printf("\tMSI supports %d message%s%s%s\n", 2587 cfg->msi.msi_msgnum, 2588 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2589 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2590 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2591 } 2592 if (cfg->msix.msix_location) { 2593 printf("\tMSI-X supports %d message%s ", 2594 cfg->msix.msix_msgnum, 2595 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2596 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2597 printf("in map 0x%x\n", 2598 cfg->msix.msix_table_bar); 2599 else 2600 printf("in maps 0x%x and 0x%x\n", 2601 cfg->msix.msix_table_bar, 2602 cfg->msix.msix_pba_bar); 2603 } 2604 } 2605 } 2606 2607 static int 2608 pci_porten(device_t dev) 2609 { 2610 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2611 } 2612 2613 static int 2614 pci_memen(device_t dev) 2615 { 2616 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2617 } 2618 2619 static void 2620 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp) 2621 { 2622 struct pci_devinfo *dinfo; 2623 pci_addr_t map, testval; 2624 int ln2range; 2625 uint16_t cmd; 2626 2627 /* 2628 * The device ROM BAR is special. It is always a 32-bit 2629 * memory BAR. Bit 0 is special and should not be set when 2630 * sizing the BAR. 2631 */ 2632 dinfo = device_get_ivars(dev); 2633 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 2634 map = pci_read_config(dev, reg, 4); 2635 pci_write_config(dev, reg, 0xfffffffe, 4); 2636 testval = pci_read_config(dev, reg, 4); 2637 pci_write_config(dev, reg, map, 4); 2638 *mapp = map; 2639 *testvalp = testval; 2640 return; 2641 } 2642 2643 map = pci_read_config(dev, reg, 4); 2644 ln2range = pci_maprange(map); 2645 if (ln2range == 64) 2646 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2647 2648 /* 2649 * Disable decoding via the command register before 2650 * determining the BAR's length since we will be placing it in 2651 * a weird state. 2652 */ 2653 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2654 pci_write_config(dev, PCIR_COMMAND, 2655 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 2656 2657 /* 2658 * Determine the BAR's length by writing all 1's. The bottom 2659 * log_2(size) bits of the BAR will stick as 0 when we read 2660 * the value back. 2661 */ 2662 pci_write_config(dev, reg, 0xffffffff, 4); 2663 testval = pci_read_config(dev, reg, 4); 2664 if (ln2range == 64) { 2665 pci_write_config(dev, reg + 4, 0xffffffff, 4); 2666 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2667 } 2668 2669 /* 2670 * Restore the original value of the BAR. We may have reprogrammed 2671 * the BAR of the low-level console device and when booting verbose, 2672 * we need the console device addressable. 2673 */ 2674 pci_write_config(dev, reg, map, 4); 2675 if (ln2range == 64) 2676 pci_write_config(dev, reg + 4, map >> 32, 4); 2677 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2678 2679 *mapp = map; 2680 *testvalp = testval; 2681 } 2682 2683 static void 2684 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 2685 { 2686 struct pci_devinfo *dinfo; 2687 int ln2range; 2688 2689 /* The device ROM BAR is always a 32-bit memory BAR. */ 2690 dinfo = device_get_ivars(dev); 2691 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 2692 ln2range = 32; 2693 else 2694 ln2range = pci_maprange(pm->pm_value); 2695 pci_write_config(dev, pm->pm_reg, base, 4); 2696 if (ln2range == 64) 2697 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 2698 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 2699 if (ln2range == 64) 2700 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 2701 pm->pm_reg + 4, 4) << 32; 2702 } 2703 2704 struct pci_map * 2705 pci_find_bar(device_t dev, int reg) 2706 { 2707 struct pci_devinfo *dinfo; 2708 struct pci_map *pm; 2709 2710 dinfo = device_get_ivars(dev); 2711 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 2712 if (pm->pm_reg == reg) 2713 return (pm); 2714 } 2715 return (NULL); 2716 } 2717 2718 int 2719 pci_bar_enabled(device_t dev, struct pci_map *pm) 2720 { 2721 struct pci_devinfo *dinfo; 2722 uint16_t cmd; 2723 2724 dinfo = device_get_ivars(dev); 2725 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 2726 !(pm->pm_value & PCIM_BIOS_ENABLE)) 2727 return (0); 2728 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2729 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 2730 return ((cmd & PCIM_CMD_MEMEN) != 0); 2731 else 2732 return ((cmd & PCIM_CMD_PORTEN) != 0); 2733 } 2734 2735 static struct pci_map * 2736 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 2737 { 2738 struct pci_devinfo *dinfo; 2739 struct pci_map *pm, *prev; 2740 2741 dinfo = device_get_ivars(dev); 2742 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 2743 pm->pm_reg = reg; 2744 pm->pm_value = value; 2745 pm->pm_size = size; 2746 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 2747 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 2748 reg)); 2749 if (STAILQ_NEXT(prev, pm_link) == NULL || 2750 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 2751 break; 2752 } 2753 if (prev != NULL) 2754 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 2755 else 2756 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 2757 return (pm); 2758 } 2759 2760 static void 2761 pci_restore_bars(device_t dev) 2762 { 2763 struct pci_devinfo *dinfo; 2764 struct pci_map *pm; 2765 int ln2range; 2766 2767 dinfo = device_get_ivars(dev); 2768 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 2769 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 2770 ln2range = 32; 2771 else 2772 ln2range = pci_maprange(pm->pm_value); 2773 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 2774 if (ln2range == 64) 2775 pci_write_config(dev, pm->pm_reg + 4, 2776 pm->pm_value >> 32, 4); 2777 } 2778 } 2779 2780 /* 2781 * Add a resource based on a pci map register. Return 1 if the map 2782 * register is a 32bit map register or 2 if it is a 64bit register. 2783 */ 2784 static int 2785 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 2786 int force, int prefetch) 2787 { 2788 struct pci_map *pm; 2789 pci_addr_t base, map, testval; 2790 pci_addr_t start, end, count; 2791 int barlen, basezero, flags, maprange, mapsize, type; 2792 uint16_t cmd; 2793 struct resource *res; 2794 2795 /* 2796 * The BAR may already exist if the device is a CardBus card 2797 * whose CIS is stored in this BAR. 2798 */ 2799 pm = pci_find_bar(dev, reg); 2800 if (pm != NULL) { 2801 maprange = pci_maprange(pm->pm_value); 2802 barlen = maprange == 64 ? 2 : 1; 2803 return (barlen); 2804 } 2805 2806 pci_read_bar(dev, reg, &map, &testval); 2807 if (PCI_BAR_MEM(map)) { 2808 type = SYS_RES_MEMORY; 2809 if (map & PCIM_BAR_MEM_PREFETCH) 2810 prefetch = 1; 2811 } else 2812 type = SYS_RES_IOPORT; 2813 mapsize = pci_mapsize(testval); 2814 base = pci_mapbase(map); 2815 #ifdef __PCI_BAR_ZERO_VALID 2816 basezero = 0; 2817 #else 2818 basezero = base == 0; 2819 #endif 2820 maprange = pci_maprange(map); 2821 barlen = maprange == 64 ? 2 : 1; 2822 2823 /* 2824 * For I/O registers, if bottom bit is set, and the next bit up 2825 * isn't clear, we know we have a BAR that doesn't conform to the 2826 * spec, so ignore it. Also, sanity check the size of the data 2827 * areas to the type of memory involved. Memory must be at least 2828 * 16 bytes in size, while I/O ranges must be at least 4. 2829 */ 2830 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 2831 return (barlen); 2832 if ((type == SYS_RES_MEMORY && mapsize < 4) || 2833 (type == SYS_RES_IOPORT && mapsize < 2)) 2834 return (barlen); 2835 2836 /* Save a record of this BAR. */ 2837 pm = pci_add_bar(dev, reg, map, mapsize); 2838 if (bootverbose) { 2839 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 2840 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 2841 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2842 printf(", port disabled\n"); 2843 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2844 printf(", memory disabled\n"); 2845 else 2846 printf(", enabled\n"); 2847 } 2848 2849 /* 2850 * If base is 0, then we have problems if this architecture does 2851 * not allow that. It is best to ignore such entries for the 2852 * moment. These will be allocated later if the driver specifically 2853 * requests them. However, some removable busses look better when 2854 * all resources are allocated, so allow '' to be overriden. 2855 * 2856 * Similarly treat maps whose values is the same as the test value 2857 * read back. These maps have had all f's written to them by the 2858 * BIOS in an attempt to disable the resources. 2859 */ 2860 if (!force && (basezero || map == testval)) 2861 return (barlen); 2862 if ((u_long)base != base) { 2863 device_printf(bus, 2864 "pci%d:%d:%d:%d bar %#x too many address bits", 2865 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 2866 pci_get_function(dev), reg); 2867 return (barlen); 2868 } 2869 2870 /* 2871 * This code theoretically does the right thing, but has 2872 * undesirable side effects in some cases where peripherals 2873 * respond oddly to having these bits enabled. Let the user 2874 * be able to turn them off (since pci_enable_io_modes is 1 by 2875 * default). 2876 */ 2877 if (pci_enable_io_modes) { 2878 /* Turn on resources that have been left off by a lazy BIOS */ 2879 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 2880 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2881 cmd |= PCIM_CMD_PORTEN; 2882 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2883 } 2884 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 2885 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2886 cmd |= PCIM_CMD_MEMEN; 2887 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2888 } 2889 } else { 2890 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2891 return (barlen); 2892 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2893 return (barlen); 2894 } 2895 2896 count = (pci_addr_t)1 << mapsize; 2897 flags = RF_ALIGNMENT_LOG2(mapsize); 2898 if (prefetch) 2899 flags |= RF_PREFETCHABLE; 2900 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 2901 start = 0; /* Let the parent decide. */ 2902 end = ~0ul; 2903 } else { 2904 start = base; 2905 end = base + count - 1; 2906 } 2907 resource_list_add(rl, type, reg, start, end, count); 2908 2909 /* 2910 * Try to allocate the resource for this BAR from our parent 2911 * so that this resource range is already reserved. The 2912 * driver for this device will later inherit this resource in 2913 * pci_alloc_resource(). 2914 */ 2915 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 2916 flags); 2917 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) { 2918 /* 2919 * If the allocation fails, try to allocate a resource for 2920 * this BAR using any available range. The firmware felt 2921 * it was important enough to assign a resource, so don't 2922 * disable decoding if we can help it. 2923 */ 2924 resource_list_delete(rl, type, reg); 2925 resource_list_add(rl, type, reg, 0, ~0ul, count); 2926 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul, 2927 count, flags); 2928 } 2929 if (res == NULL) { 2930 /* 2931 * If the allocation fails, delete the resource list entry 2932 * and disable decoding for this device. 2933 * 2934 * If the driver requests this resource in the future, 2935 * pci_reserve_map() will try to allocate a fresh 2936 * resource range. 2937 */ 2938 resource_list_delete(rl, type, reg); 2939 pci_disable_io(dev, type); 2940 if (bootverbose) 2941 device_printf(bus, 2942 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 2943 pci_get_domain(dev), pci_get_bus(dev), 2944 pci_get_slot(dev), pci_get_function(dev), reg); 2945 } else { 2946 start = rman_get_start(res); 2947 pci_write_bar(dev, pm, start); 2948 } 2949 return (barlen); 2950 } 2951 2952 /* 2953 * For ATA devices we need to decide early what addressing mode to use. 2954 * Legacy demands that the primary and secondary ATA ports sits on the 2955 * same addresses that old ISA hardware did. This dictates that we use 2956 * those addresses and ignore the BAR's if we cannot set PCI native 2957 * addressing mode. 2958 */ 2959 static void 2960 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 2961 uint32_t prefetchmask) 2962 { 2963 int rid, type, progif; 2964 #if 0 2965 /* if this device supports PCI native addressing use it */ 2966 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2967 if ((progif & 0x8a) == 0x8a) { 2968 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 2969 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 2970 printf("Trying ATA native PCI addressing mode\n"); 2971 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 2972 } 2973 } 2974 #endif 2975 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2976 type = SYS_RES_IOPORT; 2977 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 2978 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 2979 prefetchmask & (1 << 0)); 2980 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 2981 prefetchmask & (1 << 1)); 2982 } else { 2983 rid = PCIR_BAR(0); 2984 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 2985 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 2986 0x1f7, 8, 0); 2987 rid = PCIR_BAR(1); 2988 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 2989 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 2990 0x3f6, 1, 0); 2991 } 2992 if (progif & PCIP_STORAGE_IDE_MODESEC) { 2993 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 2994 prefetchmask & (1 << 2)); 2995 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 2996 prefetchmask & (1 << 3)); 2997 } else { 2998 rid = PCIR_BAR(2); 2999 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3000 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3001 0x177, 8, 0); 3002 rid = PCIR_BAR(3); 3003 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3004 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3005 0x376, 1, 0); 3006 } 3007 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3008 prefetchmask & (1 << 4)); 3009 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3010 prefetchmask & (1 << 5)); 3011 } 3012 3013 static void 3014 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3015 { 3016 struct pci_devinfo *dinfo = device_get_ivars(dev); 3017 pcicfgregs *cfg = &dinfo->cfg; 3018 char tunable_name[64]; 3019 int irq; 3020 3021 /* Has to have an intpin to have an interrupt. */ 3022 if (cfg->intpin == 0) 3023 return; 3024 3025 /* Let the user override the IRQ with a tunable. */ 3026 irq = PCI_INVALID_IRQ; 3027 snprintf(tunable_name, sizeof(tunable_name), 3028 "hw.pci%d.%d.%d.INT%c.irq", 3029 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3030 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3031 irq = PCI_INVALID_IRQ; 3032 3033 /* 3034 * If we didn't get an IRQ via the tunable, then we either use the 3035 * IRQ value in the intline register or we ask the bus to route an 3036 * interrupt for us. If force_route is true, then we only use the 3037 * value in the intline register if the bus was unable to assign an 3038 * IRQ. 3039 */ 3040 if (!PCI_INTERRUPT_VALID(irq)) { 3041 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3042 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3043 if (!PCI_INTERRUPT_VALID(irq)) 3044 irq = cfg->intline; 3045 } 3046 3047 /* If after all that we don't have an IRQ, just bail. */ 3048 if (!PCI_INTERRUPT_VALID(irq)) 3049 return; 3050 3051 /* Update the config register if it changed. */ 3052 if (irq != cfg->intline) { 3053 cfg->intline = irq; 3054 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3055 } 3056 3057 /* Add this IRQ as rid 0 interrupt resource. */ 3058 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3059 } 3060 3061 /* Perform early OHCI takeover from SMM. */ 3062 static void 3063 ohci_early_takeover(device_t self) 3064 { 3065 struct resource *res; 3066 uint32_t ctl; 3067 int rid; 3068 int i; 3069 3070 rid = PCIR_BAR(0); 3071 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3072 if (res == NULL) 3073 return; 3074 3075 ctl = bus_read_4(res, OHCI_CONTROL); 3076 if (ctl & OHCI_IR) { 3077 if (bootverbose) 3078 printf("ohci early: " 3079 "SMM active, request owner change\n"); 3080 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3081 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3082 DELAY(1000); 3083 ctl = bus_read_4(res, OHCI_CONTROL); 3084 } 3085 if (ctl & OHCI_IR) { 3086 if (bootverbose) 3087 printf("ohci early: " 3088 "SMM does not respond, resetting\n"); 3089 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3090 } 3091 /* Disable interrupts */ 3092 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3093 } 3094 3095 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3096 } 3097 3098 /* Perform early UHCI takeover from SMM. */ 3099 static void 3100 uhci_early_takeover(device_t self) 3101 { 3102 struct resource *res; 3103 int rid; 3104 3105 /* 3106 * Set the PIRQD enable bit and switch off all the others. We don't 3107 * want legacy support to interfere with us XXX Does this also mean 3108 * that the BIOS won't touch the keyboard anymore if it is connected 3109 * to the ports of the root hub? 3110 */ 3111 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3112 3113 /* Disable interrupts */ 3114 rid = PCI_UHCI_BASE_REG; 3115 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3116 if (res != NULL) { 3117 bus_write_2(res, UHCI_INTR, 0); 3118 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3119 } 3120 } 3121 3122 /* Perform early EHCI takeover from SMM. */ 3123 static void 3124 ehci_early_takeover(device_t self) 3125 { 3126 struct resource *res; 3127 uint32_t cparams; 3128 uint32_t eec; 3129 uint8_t eecp; 3130 uint8_t bios_sem; 3131 uint8_t offs; 3132 int rid; 3133 int i; 3134 3135 rid = PCIR_BAR(0); 3136 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3137 if (res == NULL) 3138 return; 3139 3140 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3141 3142 /* Synchronise with the BIOS if it owns the controller. */ 3143 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3144 eecp = EHCI_EECP_NEXT(eec)) { 3145 eec = pci_read_config(self, eecp, 4); 3146 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3147 continue; 3148 } 3149 bios_sem = pci_read_config(self, eecp + 3150 EHCI_LEGSUP_BIOS_SEM, 1); 3151 if (bios_sem == 0) { 3152 continue; 3153 } 3154 if (bootverbose) 3155 printf("ehci early: " 3156 "SMM active, request owner change\n"); 3157 3158 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3159 3160 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3161 DELAY(1000); 3162 bios_sem = pci_read_config(self, eecp + 3163 EHCI_LEGSUP_BIOS_SEM, 1); 3164 } 3165 3166 if (bios_sem != 0) { 3167 if (bootverbose) 3168 printf("ehci early: " 3169 "SMM does not respond\n"); 3170 } 3171 /* Disable interrupts */ 3172 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3173 bus_write_4(res, offs + EHCI_USBINTR, 0); 3174 } 3175 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3176 } 3177 3178 /* Perform early XHCI takeover from SMM. */ 3179 static void 3180 xhci_early_takeover(device_t self) 3181 { 3182 struct resource *res; 3183 uint32_t cparams; 3184 uint32_t eec; 3185 uint8_t eecp; 3186 uint8_t bios_sem; 3187 uint8_t offs; 3188 int rid; 3189 int i; 3190 3191 rid = PCIR_BAR(0); 3192 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3193 if (res == NULL) 3194 return; 3195 3196 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3197 3198 eec = -1; 3199 3200 /* Synchronise with the BIOS if it owns the controller. */ 3201 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3202 eecp += XHCI_XECP_NEXT(eec) << 2) { 3203 eec = bus_read_4(res, eecp); 3204 3205 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3206 continue; 3207 3208 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3209 if (bios_sem == 0) 3210 continue; 3211 3212 if (bootverbose) 3213 printf("xhci early: " 3214 "SMM active, request owner change\n"); 3215 3216 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3217 3218 /* wait a maximum of 5 second */ 3219 3220 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3221 DELAY(1000); 3222 bios_sem = bus_read_1(res, eecp + 3223 XHCI_XECP_BIOS_SEM); 3224 } 3225 3226 if (bios_sem != 0) { 3227 if (bootverbose) 3228 printf("xhci early: " 3229 "SMM does not respond\n"); 3230 } 3231 3232 /* Disable interrupts */ 3233 offs = bus_read_1(res, XHCI_CAPLENGTH); 3234 bus_write_4(res, offs + XHCI_USBCMD, 0); 3235 bus_read_4(res, offs + XHCI_USBSTS); 3236 } 3237 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3238 } 3239 3240 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3241 static void 3242 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3243 struct resource_list *rl) 3244 { 3245 struct resource *res; 3246 char *cp; 3247 u_long start, end, count; 3248 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3249 3250 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3251 case PCIM_HDRTYPE_BRIDGE: 3252 sec_reg = PCIR_SECBUS_1; 3253 sub_reg = PCIR_SUBBUS_1; 3254 break; 3255 case PCIM_HDRTYPE_CARDBUS: 3256 sec_reg = PCIR_SECBUS_2; 3257 sub_reg = PCIR_SUBBUS_2; 3258 break; 3259 default: 3260 return; 3261 } 3262 3263 /* 3264 * If the existing bus range is valid, attempt to reserve it 3265 * from our parent. If this fails for any reason, clear the 3266 * secbus and subbus registers. 3267 * 3268 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3269 * This would at least preserve the existing sec_bus if it is 3270 * valid. 3271 */ 3272 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3273 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3274 3275 /* Quirk handling. */ 3276 switch (pci_get_devid(dev)) { 3277 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3278 sup_bus = pci_read_config(dev, 0x41, 1); 3279 if (sup_bus != 0xff) { 3280 sec_bus = sup_bus + 1; 3281 sub_bus = sup_bus + 1; 3282 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3283 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3284 } 3285 break; 3286 3287 case 0x00dd10de: 3288 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3289 if ((cp = getenv("smbios.planar.maker")) == NULL) 3290 break; 3291 if (strncmp(cp, "Compal", 6) != 0) { 3292 freeenv(cp); 3293 break; 3294 } 3295 freeenv(cp); 3296 if ((cp = getenv("smbios.planar.product")) == NULL) 3297 break; 3298 if (strncmp(cp, "08A0", 4) != 0) { 3299 freeenv(cp); 3300 break; 3301 } 3302 freeenv(cp); 3303 if (sub_bus < 0xa) { 3304 sub_bus = 0xa; 3305 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3306 } 3307 break; 3308 } 3309 3310 if (bootverbose) 3311 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3312 if (sec_bus > 0 && sub_bus >= sec_bus) { 3313 start = sec_bus; 3314 end = sub_bus; 3315 count = end - start + 1; 3316 3317 resource_list_add(rl, PCI_RES_BUS, 0, 0ul, ~0ul, count); 3318 3319 /* 3320 * If requested, clear secondary bus registers in 3321 * bridge devices to force a complete renumbering 3322 * rather than reserving the existing range. However, 3323 * preserve the existing size. 3324 */ 3325 if (pci_clear_buses) 3326 goto clear; 3327 3328 rid = 0; 3329 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3330 start, end, count, 0); 3331 if (res != NULL) 3332 return; 3333 3334 if (bootverbose) 3335 device_printf(bus, 3336 "pci%d:%d:%d:%d secbus failed to allocate\n", 3337 pci_get_domain(dev), pci_get_bus(dev), 3338 pci_get_slot(dev), pci_get_function(dev)); 3339 } 3340 3341 clear: 3342 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3343 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3344 } 3345 3346 static struct resource * 3347 pci_alloc_secbus(device_t dev, device_t child, int *rid, u_long start, 3348 u_long end, u_long count, u_int flags) 3349 { 3350 struct pci_devinfo *dinfo; 3351 pcicfgregs *cfg; 3352 struct resource_list *rl; 3353 struct resource *res; 3354 int sec_reg, sub_reg; 3355 3356 dinfo = device_get_ivars(child); 3357 cfg = &dinfo->cfg; 3358 rl = &dinfo->resources; 3359 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3360 case PCIM_HDRTYPE_BRIDGE: 3361 sec_reg = PCIR_SECBUS_1; 3362 sub_reg = PCIR_SUBBUS_1; 3363 break; 3364 case PCIM_HDRTYPE_CARDBUS: 3365 sec_reg = PCIR_SECBUS_2; 3366 sub_reg = PCIR_SUBBUS_2; 3367 break; 3368 default: 3369 return (NULL); 3370 } 3371 3372 if (*rid != 0) 3373 return (NULL); 3374 3375 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3376 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3377 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3378 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3379 start, end, count, flags & ~RF_ACTIVE); 3380 if (res == NULL) { 3381 resource_list_delete(rl, PCI_RES_BUS, *rid); 3382 device_printf(child, "allocating %lu bus%s failed\n", 3383 count, count == 1 ? "" : "es"); 3384 return (NULL); 3385 } 3386 if (bootverbose) 3387 device_printf(child, 3388 "Lazy allocation of %lu bus%s at %lu\n", count, 3389 count == 1 ? "" : "es", rman_get_start(res)); 3390 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3391 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3392 } 3393 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3394 end, count, flags)); 3395 } 3396 #endif 3397 3398 void 3399 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3400 { 3401 struct pci_devinfo *dinfo; 3402 pcicfgregs *cfg; 3403 struct resource_list *rl; 3404 const struct pci_quirk *q; 3405 uint32_t devid; 3406 int i; 3407 3408 dinfo = device_get_ivars(dev); 3409 cfg = &dinfo->cfg; 3410 rl = &dinfo->resources; 3411 devid = (cfg->device << 16) | cfg->vendor; 3412 3413 /* ATA devices needs special map treatment */ 3414 if ((pci_get_class(dev) == PCIC_STORAGE) && 3415 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3416 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3417 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3418 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3419 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3420 else 3421 for (i = 0; i < cfg->nummaps;) { 3422 /* 3423 * Skip quirked resources. 3424 */ 3425 for (q = &pci_quirks[0]; q->devid != 0; q++) 3426 if (q->devid == devid && 3427 q->type == PCI_QUIRK_UNMAP_REG && 3428 q->arg1 == PCIR_BAR(i)) 3429 break; 3430 if (q->devid != 0) { 3431 i++; 3432 continue; 3433 } 3434 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 3435 prefetchmask & (1 << i)); 3436 } 3437 3438 /* 3439 * Add additional, quirked resources. 3440 */ 3441 for (q = &pci_quirks[0]; q->devid != 0; q++) 3442 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 3443 pci_add_map(bus, dev, q->arg1, rl, force, 0); 3444 3445 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 3446 #ifdef __PCI_REROUTE_INTERRUPT 3447 /* 3448 * Try to re-route interrupts. Sometimes the BIOS or 3449 * firmware may leave bogus values in these registers. 3450 * If the re-route fails, then just stick with what we 3451 * have. 3452 */ 3453 pci_assign_interrupt(bus, dev, 1); 3454 #else 3455 pci_assign_interrupt(bus, dev, 0); 3456 #endif 3457 } 3458 3459 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 3460 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 3461 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 3462 xhci_early_takeover(dev); 3463 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 3464 ehci_early_takeover(dev); 3465 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 3466 ohci_early_takeover(dev); 3467 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 3468 uhci_early_takeover(dev); 3469 } 3470 3471 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3472 /* 3473 * Reserve resources for secondary bus ranges behind bridge 3474 * devices. 3475 */ 3476 pci_reserve_secbus(bus, dev, cfg, rl); 3477 #endif 3478 } 3479 3480 static struct pci_devinfo * 3481 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 3482 int slot, int func, size_t dinfo_size) 3483 { 3484 struct pci_devinfo *dinfo; 3485 3486 dinfo = pci_read_device(pcib, domain, busno, slot, func, dinfo_size); 3487 if (dinfo != NULL) 3488 pci_add_child(dev, dinfo); 3489 3490 return (dinfo); 3491 } 3492 3493 void 3494 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size) 3495 { 3496 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 3497 device_t pcib = device_get_parent(dev); 3498 struct pci_devinfo *dinfo; 3499 int maxslots; 3500 int s, f, pcifunchigh; 3501 uint8_t hdrtype; 3502 int first_func; 3503 3504 /* 3505 * Try to detect a device at slot 0, function 0. If it exists, try to 3506 * enable ARI. We must enable ARI before detecting the rest of the 3507 * functions on this bus as ARI changes the set of slots and functions 3508 * that are legal on this bus. 3509 */ 3510 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0, 3511 dinfo_size); 3512 if (dinfo != NULL && pci_enable_ari) 3513 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 3514 3515 /* 3516 * Start looking for new devices on slot 0 at function 1 because we 3517 * just identified the device at slot 0, function 0. 3518 */ 3519 first_func = 1; 3520 3521 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 3522 ("dinfo_size too small")); 3523 maxslots = PCIB_MAXSLOTS(pcib); 3524 for (s = 0; s <= maxslots; s++, first_func = 0) { 3525 pcifunchigh = 0; 3526 f = 0; 3527 DELAY(1); 3528 hdrtype = REG(PCIR_HDRTYPE, 1); 3529 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 3530 continue; 3531 if (hdrtype & PCIM_MFDEV) 3532 pcifunchigh = PCIB_MAXFUNCS(pcib); 3533 for (f = first_func; f <= pcifunchigh; f++) 3534 pci_identify_function(pcib, dev, domain, busno, s, f, 3535 dinfo_size); 3536 } 3537 #undef REG 3538 } 3539 3540 void 3541 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 3542 { 3543 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 3544 device_set_ivars(dinfo->cfg.dev, dinfo); 3545 resource_list_init(&dinfo->resources); 3546 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 3547 pci_cfg_restore(dinfo->cfg.dev, dinfo); 3548 pci_print_verbose(dinfo); 3549 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 3550 } 3551 3552 static int 3553 pci_probe(device_t dev) 3554 { 3555 3556 device_set_desc(dev, "PCI bus"); 3557 3558 /* Allow other subclasses to override this driver. */ 3559 return (BUS_PROBE_GENERIC); 3560 } 3561 3562 int 3563 pci_attach_common(device_t dev) 3564 { 3565 struct pci_softc *sc; 3566 int busno, domain; 3567 #ifdef PCI_DMA_BOUNDARY 3568 int error, tag_valid; 3569 #endif 3570 #ifdef PCI_RES_BUS 3571 int rid; 3572 #endif 3573 3574 sc = device_get_softc(dev); 3575 domain = pcib_get_domain(dev); 3576 busno = pcib_get_bus(dev); 3577 #ifdef PCI_RES_BUS 3578 rid = 0; 3579 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 3580 1, 0); 3581 if (sc->sc_bus == NULL) { 3582 device_printf(dev, "failed to allocate bus number\n"); 3583 return (ENXIO); 3584 } 3585 #endif 3586 if (bootverbose) 3587 device_printf(dev, "domain=%d, physical bus=%d\n", 3588 domain, busno); 3589 #ifdef PCI_DMA_BOUNDARY 3590 tag_valid = 0; 3591 if (device_get_devclass(device_get_parent(device_get_parent(dev))) != 3592 devclass_find("pci")) { 3593 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 3594 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3595 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, 3596 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag); 3597 if (error) 3598 device_printf(dev, "Failed to create DMA tag: %d\n", 3599 error); 3600 else 3601 tag_valid = 1; 3602 } 3603 if (!tag_valid) 3604 #endif 3605 sc->sc_dma_tag = bus_get_dma_tag(dev); 3606 return (0); 3607 } 3608 3609 static int 3610 pci_attach(device_t dev) 3611 { 3612 int busno, domain, error; 3613 3614 error = pci_attach_common(dev); 3615 if (error) 3616 return (error); 3617 3618 /* 3619 * Since there can be multiple independantly numbered PCI 3620 * busses on systems with multiple PCI domains, we can't use 3621 * the unit number to decide which bus we are probing. We ask 3622 * the parent pcib what our domain and bus numbers are. 3623 */ 3624 domain = pcib_get_domain(dev); 3625 busno = pcib_get_bus(dev); 3626 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo)); 3627 return (bus_generic_attach(dev)); 3628 } 3629 3630 #ifdef PCI_RES_BUS 3631 static int 3632 pci_detach(device_t dev) 3633 { 3634 struct pci_softc *sc; 3635 int error; 3636 3637 error = bus_generic_detach(dev); 3638 if (error) 3639 return (error); 3640 sc = device_get_softc(dev); 3641 return (bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus)); 3642 } 3643 #endif 3644 3645 static void 3646 pci_set_power_children(device_t dev, device_t *devlist, int numdevs, 3647 int state) 3648 { 3649 device_t child, pcib; 3650 int dstate, i; 3651 3652 /* 3653 * Set the device to the given state. If the firmware suggests 3654 * a different power state, use it instead. If power management 3655 * is not present, the firmware is responsible for managing 3656 * device power. Skip children who aren't attached since they 3657 * are handled separately. 3658 */ 3659 pcib = device_get_parent(dev); 3660 for (i = 0; i < numdevs; i++) { 3661 child = devlist[i]; 3662 dstate = state; 3663 if (device_is_attached(child) && 3664 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 3665 pci_set_powerstate(child, dstate); 3666 } 3667 } 3668 3669 int 3670 pci_suspend(device_t dev) 3671 { 3672 device_t child, *devlist; 3673 struct pci_devinfo *dinfo; 3674 int error, i, numdevs; 3675 3676 /* 3677 * Save the PCI configuration space for each child and set the 3678 * device in the appropriate power state for this sleep state. 3679 */ 3680 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 3681 return (error); 3682 for (i = 0; i < numdevs; i++) { 3683 child = devlist[i]; 3684 dinfo = device_get_ivars(child); 3685 pci_cfg_save(child, dinfo, 0); 3686 } 3687 3688 /* Suspend devices before potentially powering them down. */ 3689 error = bus_generic_suspend(dev); 3690 if (error) { 3691 free(devlist, M_TEMP); 3692 return (error); 3693 } 3694 if (pci_do_power_suspend) 3695 pci_set_power_children(dev, devlist, numdevs, 3696 PCI_POWERSTATE_D3); 3697 free(devlist, M_TEMP); 3698 return (0); 3699 } 3700 3701 int 3702 pci_resume(device_t dev) 3703 { 3704 device_t child, *devlist; 3705 struct pci_devinfo *dinfo; 3706 int error, i, numdevs; 3707 3708 /* 3709 * Set each child to D0 and restore its PCI configuration space. 3710 */ 3711 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 3712 return (error); 3713 if (pci_do_power_resume) 3714 pci_set_power_children(dev, devlist, numdevs, 3715 PCI_POWERSTATE_D0); 3716 3717 /* Now the device is powered up, restore its config space. */ 3718 for (i = 0; i < numdevs; i++) { 3719 child = devlist[i]; 3720 dinfo = device_get_ivars(child); 3721 3722 pci_cfg_restore(child, dinfo); 3723 if (!device_is_attached(child)) 3724 pci_cfg_save(child, dinfo, 1); 3725 } 3726 3727 /* 3728 * Resume critical devices first, then everything else later. 3729 */ 3730 for (i = 0; i < numdevs; i++) { 3731 child = devlist[i]; 3732 switch (pci_get_class(child)) { 3733 case PCIC_DISPLAY: 3734 case PCIC_MEMORY: 3735 case PCIC_BRIDGE: 3736 case PCIC_BASEPERIPH: 3737 DEVICE_RESUME(child); 3738 break; 3739 } 3740 } 3741 for (i = 0; i < numdevs; i++) { 3742 child = devlist[i]; 3743 switch (pci_get_class(child)) { 3744 case PCIC_DISPLAY: 3745 case PCIC_MEMORY: 3746 case PCIC_BRIDGE: 3747 case PCIC_BASEPERIPH: 3748 break; 3749 default: 3750 DEVICE_RESUME(child); 3751 } 3752 } 3753 free(devlist, M_TEMP); 3754 return (0); 3755 } 3756 3757 static void 3758 pci_load_vendor_data(void) 3759 { 3760 caddr_t data; 3761 void *ptr; 3762 size_t sz; 3763 3764 data = preload_search_by_type("pci_vendor_data"); 3765 if (data != NULL) { 3766 ptr = preload_fetch_addr(data); 3767 sz = preload_fetch_size(data); 3768 if (ptr != NULL && sz != 0) { 3769 pci_vendordata = ptr; 3770 pci_vendordata_size = sz; 3771 /* terminate the database */ 3772 pci_vendordata[pci_vendordata_size] = '\n'; 3773 } 3774 } 3775 } 3776 3777 void 3778 pci_driver_added(device_t dev, driver_t *driver) 3779 { 3780 int numdevs; 3781 device_t *devlist; 3782 device_t child; 3783 struct pci_devinfo *dinfo; 3784 int i; 3785 3786 if (bootverbose) 3787 device_printf(dev, "driver added\n"); 3788 DEVICE_IDENTIFY(driver, dev); 3789 if (device_get_children(dev, &devlist, &numdevs) != 0) 3790 return; 3791 for (i = 0; i < numdevs; i++) { 3792 child = devlist[i]; 3793 if (device_get_state(child) != DS_NOTPRESENT) 3794 continue; 3795 dinfo = device_get_ivars(child); 3796 pci_print_verbose(dinfo); 3797 if (bootverbose) 3798 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 3799 pci_cfg_restore(child, dinfo); 3800 if (device_probe_and_attach(child) != 0) 3801 pci_child_detached(dev, child); 3802 } 3803 free(devlist, M_TEMP); 3804 } 3805 3806 int 3807 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 3808 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 3809 { 3810 struct pci_devinfo *dinfo; 3811 struct msix_table_entry *mte; 3812 struct msix_vector *mv; 3813 uint64_t addr; 3814 uint32_t data; 3815 void *cookie; 3816 int error, rid; 3817 3818 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 3819 arg, &cookie); 3820 if (error) 3821 return (error); 3822 3823 /* If this is not a direct child, just bail out. */ 3824 if (device_get_parent(child) != dev) { 3825 *cookiep = cookie; 3826 return(0); 3827 } 3828 3829 rid = rman_get_rid(irq); 3830 if (rid == 0) { 3831 /* Make sure that INTx is enabled */ 3832 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 3833 } else { 3834 /* 3835 * Check to see if the interrupt is MSI or MSI-X. 3836 * Ask our parent to map the MSI and give 3837 * us the address and data register values. 3838 * If we fail for some reason, teardown the 3839 * interrupt handler. 3840 */ 3841 dinfo = device_get_ivars(child); 3842 if (dinfo->cfg.msi.msi_alloc > 0) { 3843 if (dinfo->cfg.msi.msi_addr == 0) { 3844 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 3845 ("MSI has handlers, but vectors not mapped")); 3846 error = PCIB_MAP_MSI(device_get_parent(dev), 3847 child, rman_get_start(irq), &addr, &data); 3848 if (error) 3849 goto bad; 3850 dinfo->cfg.msi.msi_addr = addr; 3851 dinfo->cfg.msi.msi_data = data; 3852 } 3853 if (dinfo->cfg.msi.msi_handlers == 0) 3854 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 3855 dinfo->cfg.msi.msi_data); 3856 dinfo->cfg.msi.msi_handlers++; 3857 } else { 3858 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3859 ("No MSI or MSI-X interrupts allocated")); 3860 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3861 ("MSI-X index too high")); 3862 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3863 KASSERT(mte->mte_vector != 0, ("no message vector")); 3864 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 3865 KASSERT(mv->mv_irq == rman_get_start(irq), 3866 ("IRQ mismatch")); 3867 if (mv->mv_address == 0) { 3868 KASSERT(mte->mte_handlers == 0, 3869 ("MSI-X table entry has handlers, but vector not mapped")); 3870 error = PCIB_MAP_MSI(device_get_parent(dev), 3871 child, rman_get_start(irq), &addr, &data); 3872 if (error) 3873 goto bad; 3874 mv->mv_address = addr; 3875 mv->mv_data = data; 3876 } 3877 if (mte->mte_handlers == 0) { 3878 pci_enable_msix(child, rid - 1, mv->mv_address, 3879 mv->mv_data); 3880 pci_unmask_msix(child, rid - 1); 3881 } 3882 mte->mte_handlers++; 3883 } 3884 3885 /* 3886 * Make sure that INTx is disabled if we are using MSI/MSI-X, 3887 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 3888 * in which case we "enable" INTx so MSI/MSI-X actually works. 3889 */ 3890 if (!pci_has_quirk(pci_get_devid(child), 3891 PCI_QUIRK_MSI_INTX_BUG)) 3892 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3893 else 3894 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 3895 bad: 3896 if (error) { 3897 (void)bus_generic_teardown_intr(dev, child, irq, 3898 cookie); 3899 return (error); 3900 } 3901 } 3902 *cookiep = cookie; 3903 return (0); 3904 } 3905 3906 int 3907 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 3908 void *cookie) 3909 { 3910 struct msix_table_entry *mte; 3911 struct resource_list_entry *rle; 3912 struct pci_devinfo *dinfo; 3913 int error, rid; 3914 3915 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 3916 return (EINVAL); 3917 3918 /* If this isn't a direct child, just bail out */ 3919 if (device_get_parent(child) != dev) 3920 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 3921 3922 rid = rman_get_rid(irq); 3923 if (rid == 0) { 3924 /* Mask INTx */ 3925 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3926 } else { 3927 /* 3928 * Check to see if the interrupt is MSI or MSI-X. If so, 3929 * decrement the appropriate handlers count and mask the 3930 * MSI-X message, or disable MSI messages if the count 3931 * drops to 0. 3932 */ 3933 dinfo = device_get_ivars(child); 3934 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 3935 if (rle->res != irq) 3936 return (EINVAL); 3937 if (dinfo->cfg.msi.msi_alloc > 0) { 3938 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 3939 ("MSI-X index too high")); 3940 if (dinfo->cfg.msi.msi_handlers == 0) 3941 return (EINVAL); 3942 dinfo->cfg.msi.msi_handlers--; 3943 if (dinfo->cfg.msi.msi_handlers == 0) 3944 pci_disable_msi(child); 3945 } else { 3946 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3947 ("No MSI or MSI-X interrupts allocated")); 3948 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3949 ("MSI-X index too high")); 3950 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3951 if (mte->mte_handlers == 0) 3952 return (EINVAL); 3953 mte->mte_handlers--; 3954 if (mte->mte_handlers == 0) 3955 pci_mask_msix(child, rid - 1); 3956 } 3957 } 3958 error = bus_generic_teardown_intr(dev, child, irq, cookie); 3959 if (rid > 0) 3960 KASSERT(error == 0, 3961 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 3962 return (error); 3963 } 3964 3965 int 3966 pci_print_child(device_t dev, device_t child) 3967 { 3968 struct pci_devinfo *dinfo; 3969 struct resource_list *rl; 3970 int retval = 0; 3971 3972 dinfo = device_get_ivars(child); 3973 rl = &dinfo->resources; 3974 3975 retval += bus_print_child_header(dev, child); 3976 3977 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 3978 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 3979 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 3980 if (device_get_flags(dev)) 3981 retval += printf(" flags %#x", device_get_flags(dev)); 3982 3983 retval += printf(" at device %d.%d", pci_get_slot(child), 3984 pci_get_function(child)); 3985 3986 retval += bus_print_child_domain(dev, child); 3987 retval += bus_print_child_footer(dev, child); 3988 3989 return (retval); 3990 } 3991 3992 static const struct 3993 { 3994 int class; 3995 int subclass; 3996 int report; /* 0 = bootverbose, 1 = always */ 3997 const char *desc; 3998 } pci_nomatch_tab[] = { 3999 {PCIC_OLD, -1, 1, "old"}, 4000 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4001 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4002 {PCIC_STORAGE, -1, 1, "mass storage"}, 4003 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4004 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4005 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4006 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4007 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4008 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4009 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4010 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4011 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4012 {PCIC_NETWORK, -1, 1, "network"}, 4013 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4014 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4015 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4016 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4017 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4018 {PCIC_DISPLAY, -1, 1, "display"}, 4019 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4020 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4021 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4022 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4023 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4024 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4025 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4026 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4027 {PCIC_MEMORY, -1, 1, "memory"}, 4028 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4029 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4030 {PCIC_BRIDGE, -1, 1, "bridge"}, 4031 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4032 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4033 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4034 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4035 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4036 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4037 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4038 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4039 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4040 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4041 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4042 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4043 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4044 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4045 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4046 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4047 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4048 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4049 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4050 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4051 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4052 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4053 {PCIC_INPUTDEV, -1, 1, "input device"}, 4054 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4055 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4056 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4057 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4058 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4059 {PCIC_DOCKING, -1, 1, "docking station"}, 4060 {PCIC_PROCESSOR, -1, 1, "processor"}, 4061 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4062 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4063 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4064 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4065 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4066 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4067 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4068 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4069 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4070 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4071 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4072 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4073 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4074 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4075 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4076 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4077 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4078 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4079 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4080 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4081 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4082 {PCIC_DASP, -1, 0, "dasp"}, 4083 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4084 {0, 0, 0, NULL} 4085 }; 4086 4087 void 4088 pci_probe_nomatch(device_t dev, device_t child) 4089 { 4090 int i, report; 4091 const char *cp, *scp; 4092 char *device; 4093 4094 /* 4095 * Look for a listing for this device in a loaded device database. 4096 */ 4097 report = 1; 4098 if ((device = pci_describe_device(child)) != NULL) { 4099 device_printf(dev, "<%s>", device); 4100 free(device, M_DEVBUF); 4101 } else { 4102 /* 4103 * Scan the class/subclass descriptions for a general 4104 * description. 4105 */ 4106 cp = "unknown"; 4107 scp = NULL; 4108 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4109 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4110 if (pci_nomatch_tab[i].subclass == -1) { 4111 cp = pci_nomatch_tab[i].desc; 4112 report = pci_nomatch_tab[i].report; 4113 } else if (pci_nomatch_tab[i].subclass == 4114 pci_get_subclass(child)) { 4115 scp = pci_nomatch_tab[i].desc; 4116 report = pci_nomatch_tab[i].report; 4117 } 4118 } 4119 } 4120 if (report || bootverbose) { 4121 device_printf(dev, "<%s%s%s>", 4122 cp ? cp : "", 4123 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4124 scp ? scp : ""); 4125 } 4126 } 4127 if (report || bootverbose) { 4128 printf(" at device %d.%d (no driver attached)\n", 4129 pci_get_slot(child), pci_get_function(child)); 4130 } 4131 pci_cfg_save(child, device_get_ivars(child), 1); 4132 } 4133 4134 void 4135 pci_child_detached(device_t dev, device_t child) 4136 { 4137 struct pci_devinfo *dinfo; 4138 struct resource_list *rl; 4139 4140 dinfo = device_get_ivars(child); 4141 rl = &dinfo->resources; 4142 4143 /* 4144 * Have to deallocate IRQs before releasing any MSI messages and 4145 * have to release MSI messages before deallocating any memory 4146 * BARs. 4147 */ 4148 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4149 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4150 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4151 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4152 (void)pci_release_msi(child); 4153 } 4154 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4155 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4156 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4157 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4158 #ifdef PCI_RES_BUS 4159 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4160 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4161 #endif 4162 4163 pci_cfg_save(child, dinfo, 1); 4164 } 4165 4166 /* 4167 * Parse the PCI device database, if loaded, and return a pointer to a 4168 * description of the device. 4169 * 4170 * The database is flat text formatted as follows: 4171 * 4172 * Any line not in a valid format is ignored. 4173 * Lines are terminated with newline '\n' characters. 4174 * 4175 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4176 * the vendor name. 4177 * 4178 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 4179 * - devices cannot be listed without a corresponding VENDOR line. 4180 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 4181 * another TAB, then the device name. 4182 */ 4183 4184 /* 4185 * Assuming (ptr) points to the beginning of a line in the database, 4186 * return the vendor or device and description of the next entry. 4187 * The value of (vendor) or (device) inappropriate for the entry type 4188 * is set to -1. Returns nonzero at the end of the database. 4189 * 4190 * Note that this is slightly unrobust in the face of corrupt data; 4191 * we attempt to safeguard against this by spamming the end of the 4192 * database with a newline when we initialise. 4193 */ 4194 static int 4195 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 4196 { 4197 char *cp = *ptr; 4198 int left; 4199 4200 *device = -1; 4201 *vendor = -1; 4202 **desc = '\0'; 4203 for (;;) { 4204 left = pci_vendordata_size - (cp - pci_vendordata); 4205 if (left <= 0) { 4206 *ptr = cp; 4207 return(1); 4208 } 4209 4210 /* vendor entry? */ 4211 if (*cp != '\t' && 4212 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 4213 break; 4214 /* device entry? */ 4215 if (*cp == '\t' && 4216 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 4217 break; 4218 4219 /* skip to next line */ 4220 while (*cp != '\n' && left > 0) { 4221 cp++; 4222 left--; 4223 } 4224 if (*cp == '\n') { 4225 cp++; 4226 left--; 4227 } 4228 } 4229 /* skip to next line */ 4230 while (*cp != '\n' && left > 0) { 4231 cp++; 4232 left--; 4233 } 4234 if (*cp == '\n' && left > 0) 4235 cp++; 4236 *ptr = cp; 4237 return(0); 4238 } 4239 4240 static char * 4241 pci_describe_device(device_t dev) 4242 { 4243 int vendor, device; 4244 char *desc, *vp, *dp, *line; 4245 4246 desc = vp = dp = NULL; 4247 4248 /* 4249 * If we have no vendor data, we can't do anything. 4250 */ 4251 if (pci_vendordata == NULL) 4252 goto out; 4253 4254 /* 4255 * Scan the vendor data looking for this device 4256 */ 4257 line = pci_vendordata; 4258 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 4259 goto out; 4260 for (;;) { 4261 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 4262 goto out; 4263 if (vendor == pci_get_vendor(dev)) 4264 break; 4265 } 4266 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 4267 goto out; 4268 for (;;) { 4269 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 4270 *dp = 0; 4271 break; 4272 } 4273 if (vendor != -1) { 4274 *dp = 0; 4275 break; 4276 } 4277 if (device == pci_get_device(dev)) 4278 break; 4279 } 4280 if (dp[0] == '\0') 4281 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 4282 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 4283 NULL) 4284 sprintf(desc, "%s, %s", vp, dp); 4285 out: 4286 if (vp != NULL) 4287 free(vp, M_DEVBUF); 4288 if (dp != NULL) 4289 free(dp, M_DEVBUF); 4290 return(desc); 4291 } 4292 4293 int 4294 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 4295 { 4296 struct pci_devinfo *dinfo; 4297 pcicfgregs *cfg; 4298 4299 dinfo = device_get_ivars(child); 4300 cfg = &dinfo->cfg; 4301 4302 switch (which) { 4303 case PCI_IVAR_ETHADDR: 4304 /* 4305 * The generic accessor doesn't deal with failure, so 4306 * we set the return value, then return an error. 4307 */ 4308 *((uint8_t **) result) = NULL; 4309 return (EINVAL); 4310 case PCI_IVAR_SUBVENDOR: 4311 *result = cfg->subvendor; 4312 break; 4313 case PCI_IVAR_SUBDEVICE: 4314 *result = cfg->subdevice; 4315 break; 4316 case PCI_IVAR_VENDOR: 4317 *result = cfg->vendor; 4318 break; 4319 case PCI_IVAR_DEVICE: 4320 *result = cfg->device; 4321 break; 4322 case PCI_IVAR_DEVID: 4323 *result = (cfg->device << 16) | cfg->vendor; 4324 break; 4325 case PCI_IVAR_CLASS: 4326 *result = cfg->baseclass; 4327 break; 4328 case PCI_IVAR_SUBCLASS: 4329 *result = cfg->subclass; 4330 break; 4331 case PCI_IVAR_PROGIF: 4332 *result = cfg->progif; 4333 break; 4334 case PCI_IVAR_REVID: 4335 *result = cfg->revid; 4336 break; 4337 case PCI_IVAR_INTPIN: 4338 *result = cfg->intpin; 4339 break; 4340 case PCI_IVAR_IRQ: 4341 *result = cfg->intline; 4342 break; 4343 case PCI_IVAR_DOMAIN: 4344 *result = cfg->domain; 4345 break; 4346 case PCI_IVAR_BUS: 4347 *result = cfg->bus; 4348 break; 4349 case PCI_IVAR_SLOT: 4350 *result = cfg->slot; 4351 break; 4352 case PCI_IVAR_FUNCTION: 4353 *result = cfg->func; 4354 break; 4355 case PCI_IVAR_CMDREG: 4356 *result = cfg->cmdreg; 4357 break; 4358 case PCI_IVAR_CACHELNSZ: 4359 *result = cfg->cachelnsz; 4360 break; 4361 case PCI_IVAR_MINGNT: 4362 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 4363 *result = -1; 4364 return (EINVAL); 4365 } 4366 *result = cfg->mingnt; 4367 break; 4368 case PCI_IVAR_MAXLAT: 4369 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 4370 *result = -1; 4371 return (EINVAL); 4372 } 4373 *result = cfg->maxlat; 4374 break; 4375 case PCI_IVAR_LATTIMER: 4376 *result = cfg->lattimer; 4377 break; 4378 default: 4379 return (ENOENT); 4380 } 4381 return (0); 4382 } 4383 4384 int 4385 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 4386 { 4387 struct pci_devinfo *dinfo; 4388 4389 dinfo = device_get_ivars(child); 4390 4391 switch (which) { 4392 case PCI_IVAR_INTPIN: 4393 dinfo->cfg.intpin = value; 4394 return (0); 4395 case PCI_IVAR_ETHADDR: 4396 case PCI_IVAR_SUBVENDOR: 4397 case PCI_IVAR_SUBDEVICE: 4398 case PCI_IVAR_VENDOR: 4399 case PCI_IVAR_DEVICE: 4400 case PCI_IVAR_DEVID: 4401 case PCI_IVAR_CLASS: 4402 case PCI_IVAR_SUBCLASS: 4403 case PCI_IVAR_PROGIF: 4404 case PCI_IVAR_REVID: 4405 case PCI_IVAR_IRQ: 4406 case PCI_IVAR_DOMAIN: 4407 case PCI_IVAR_BUS: 4408 case PCI_IVAR_SLOT: 4409 case PCI_IVAR_FUNCTION: 4410 return (EINVAL); /* disallow for now */ 4411 4412 default: 4413 return (ENOENT); 4414 } 4415 } 4416 4417 #include "opt_ddb.h" 4418 #ifdef DDB 4419 #include <ddb/ddb.h> 4420 #include <sys/cons.h> 4421 4422 /* 4423 * List resources based on pci map registers, used for within ddb 4424 */ 4425 4426 DB_SHOW_COMMAND(pciregs, db_pci_dump) 4427 { 4428 struct pci_devinfo *dinfo; 4429 struct devlist *devlist_head; 4430 struct pci_conf *p; 4431 const char *name; 4432 int i, error, none_count; 4433 4434 none_count = 0; 4435 /* get the head of the device queue */ 4436 devlist_head = &pci_devq; 4437 4438 /* 4439 * Go through the list of devices and print out devices 4440 */ 4441 for (error = 0, i = 0, 4442 dinfo = STAILQ_FIRST(devlist_head); 4443 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 4444 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 4445 4446 /* Populate pd_name and pd_unit */ 4447 name = NULL; 4448 if (dinfo->cfg.dev) 4449 name = device_get_name(dinfo->cfg.dev); 4450 4451 p = &dinfo->conf; 4452 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 4453 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 4454 (name && *name) ? name : "none", 4455 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 4456 none_count++, 4457 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 4458 p->pc_sel.pc_func, (p->pc_class << 16) | 4459 (p->pc_subclass << 8) | p->pc_progif, 4460 (p->pc_subdevice << 16) | p->pc_subvendor, 4461 (p->pc_device << 16) | p->pc_vendor, 4462 p->pc_revid, p->pc_hdr); 4463 } 4464 } 4465 #endif /* DDB */ 4466 4467 static struct resource * 4468 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 4469 u_long start, u_long end, u_long count, u_int flags) 4470 { 4471 struct pci_devinfo *dinfo = device_get_ivars(child); 4472 struct resource_list *rl = &dinfo->resources; 4473 struct resource *res; 4474 struct pci_map *pm; 4475 pci_addr_t map, testval; 4476 int mapsize; 4477 4478 res = NULL; 4479 pm = pci_find_bar(child, *rid); 4480 if (pm != NULL) { 4481 /* This is a BAR that we failed to allocate earlier. */ 4482 mapsize = pm->pm_size; 4483 map = pm->pm_value; 4484 } else { 4485 /* 4486 * Weed out the bogons, and figure out how large the 4487 * BAR/map is. BARs that read back 0 here are bogus 4488 * and unimplemented. Note: atapci in legacy mode are 4489 * special and handled elsewhere in the code. If you 4490 * have a atapci device in legacy mode and it fails 4491 * here, that other code is broken. 4492 */ 4493 pci_read_bar(child, *rid, &map, &testval); 4494 4495 /* 4496 * Determine the size of the BAR and ignore BARs with a size 4497 * of 0. Device ROM BARs use a different mask value. 4498 */ 4499 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 4500 mapsize = pci_romsize(testval); 4501 else 4502 mapsize = pci_mapsize(testval); 4503 if (mapsize == 0) 4504 goto out; 4505 pm = pci_add_bar(child, *rid, map, mapsize); 4506 } 4507 4508 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 4509 if (type != SYS_RES_MEMORY) { 4510 if (bootverbose) 4511 device_printf(dev, 4512 "child %s requested type %d for rid %#x," 4513 " but the BAR says it is an memio\n", 4514 device_get_nameunit(child), type, *rid); 4515 goto out; 4516 } 4517 } else { 4518 if (type != SYS_RES_IOPORT) { 4519 if (bootverbose) 4520 device_printf(dev, 4521 "child %s requested type %d for rid %#x," 4522 " but the BAR says it is an ioport\n", 4523 device_get_nameunit(child), type, *rid); 4524 goto out; 4525 } 4526 } 4527 4528 /* 4529 * For real BARs, we need to override the size that 4530 * the driver requests, because that's what the BAR 4531 * actually uses and we would otherwise have a 4532 * situation where we might allocate the excess to 4533 * another driver, which won't work. 4534 */ 4535 count = (pci_addr_t)1 << mapsize; 4536 if (RF_ALIGNMENT(flags) < mapsize) 4537 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 4538 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 4539 flags |= RF_PREFETCHABLE; 4540 4541 /* 4542 * Allocate enough resource, and then write back the 4543 * appropriate BAR for that resource. 4544 */ 4545 resource_list_add(rl, type, *rid, start, end, count); 4546 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 4547 count, flags & ~RF_ACTIVE); 4548 if (res == NULL) { 4549 resource_list_delete(rl, type, *rid); 4550 device_printf(child, 4551 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 4552 count, *rid, type, start, end); 4553 goto out; 4554 } 4555 if (bootverbose) 4556 device_printf(child, 4557 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 4558 count, *rid, type, rman_get_start(res)); 4559 map = rman_get_start(res); 4560 pci_write_bar(child, pm, map); 4561 out: 4562 return (res); 4563 } 4564 4565 struct resource * 4566 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 4567 u_long start, u_long end, u_long count, u_int flags) 4568 { 4569 struct pci_devinfo *dinfo; 4570 struct resource_list *rl; 4571 struct resource_list_entry *rle; 4572 struct resource *res; 4573 pcicfgregs *cfg; 4574 4575 if (device_get_parent(child) != dev) 4576 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 4577 type, rid, start, end, count, flags)); 4578 4579 /* 4580 * Perform lazy resource allocation 4581 */ 4582 dinfo = device_get_ivars(child); 4583 rl = &dinfo->resources; 4584 cfg = &dinfo->cfg; 4585 switch (type) { 4586 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4587 case PCI_RES_BUS: 4588 return (pci_alloc_secbus(dev, child, rid, start, end, count, 4589 flags)); 4590 #endif 4591 case SYS_RES_IRQ: 4592 /* 4593 * Can't alloc legacy interrupt once MSI messages have 4594 * been allocated. 4595 */ 4596 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 4597 cfg->msix.msix_alloc > 0)) 4598 return (NULL); 4599 4600 /* 4601 * If the child device doesn't have an interrupt 4602 * routed and is deserving of an interrupt, try to 4603 * assign it one. 4604 */ 4605 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 4606 (cfg->intpin != 0)) 4607 pci_assign_interrupt(dev, child, 0); 4608 break; 4609 case SYS_RES_IOPORT: 4610 case SYS_RES_MEMORY: 4611 #ifdef NEW_PCIB 4612 /* 4613 * PCI-PCI bridge I/O window resources are not BARs. 4614 * For those allocations just pass the request up the 4615 * tree. 4616 */ 4617 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 4618 switch (*rid) { 4619 case PCIR_IOBASEL_1: 4620 case PCIR_MEMBASE_1: 4621 case PCIR_PMBASEL_1: 4622 /* 4623 * XXX: Should we bother creating a resource 4624 * list entry? 4625 */ 4626 return (bus_generic_alloc_resource(dev, child, 4627 type, rid, start, end, count, flags)); 4628 } 4629 } 4630 #endif 4631 /* Reserve resources for this BAR if needed. */ 4632 rle = resource_list_find(rl, type, *rid); 4633 if (rle == NULL) { 4634 res = pci_reserve_map(dev, child, type, rid, start, end, 4635 count, flags); 4636 if (res == NULL) 4637 return (NULL); 4638 } 4639 } 4640 return (resource_list_alloc(rl, dev, child, type, rid, 4641 start, end, count, flags)); 4642 } 4643 4644 int 4645 pci_release_resource(device_t dev, device_t child, int type, int rid, 4646 struct resource *r) 4647 { 4648 struct pci_devinfo *dinfo; 4649 struct resource_list *rl; 4650 pcicfgregs *cfg; 4651 4652 if (device_get_parent(child) != dev) 4653 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 4654 type, rid, r)); 4655 4656 dinfo = device_get_ivars(child); 4657 cfg = &dinfo->cfg; 4658 #ifdef NEW_PCIB 4659 /* 4660 * PCI-PCI bridge I/O window resources are not BARs. For 4661 * those allocations just pass the request up the tree. 4662 */ 4663 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 4664 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 4665 switch (rid) { 4666 case PCIR_IOBASEL_1: 4667 case PCIR_MEMBASE_1: 4668 case PCIR_PMBASEL_1: 4669 return (bus_generic_release_resource(dev, child, type, 4670 rid, r)); 4671 } 4672 } 4673 #endif 4674 4675 rl = &dinfo->resources; 4676 return (resource_list_release(rl, dev, child, type, rid, r)); 4677 } 4678 4679 int 4680 pci_activate_resource(device_t dev, device_t child, int type, int rid, 4681 struct resource *r) 4682 { 4683 struct pci_devinfo *dinfo; 4684 int error; 4685 4686 error = bus_generic_activate_resource(dev, child, type, rid, r); 4687 if (error) 4688 return (error); 4689 4690 /* Enable decoding in the command register when activating BARs. */ 4691 if (device_get_parent(child) == dev) { 4692 /* Device ROMs need their decoding explicitly enabled. */ 4693 dinfo = device_get_ivars(child); 4694 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 4695 pci_write_bar(child, pci_find_bar(child, rid), 4696 rman_get_start(r) | PCIM_BIOS_ENABLE); 4697 switch (type) { 4698 case SYS_RES_IOPORT: 4699 case SYS_RES_MEMORY: 4700 error = PCI_ENABLE_IO(dev, child, type); 4701 break; 4702 } 4703 } 4704 return (error); 4705 } 4706 4707 int 4708 pci_deactivate_resource(device_t dev, device_t child, int type, 4709 int rid, struct resource *r) 4710 { 4711 struct pci_devinfo *dinfo; 4712 int error; 4713 4714 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 4715 if (error) 4716 return (error); 4717 4718 /* Disable decoding for device ROMs. */ 4719 if (device_get_parent(child) == dev) { 4720 dinfo = device_get_ivars(child); 4721 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 4722 pci_write_bar(child, pci_find_bar(child, rid), 4723 rman_get_start(r)); 4724 } 4725 return (0); 4726 } 4727 4728 void 4729 pci_delete_child(device_t dev, device_t child) 4730 { 4731 struct resource_list_entry *rle; 4732 struct resource_list *rl; 4733 struct pci_devinfo *dinfo; 4734 4735 dinfo = device_get_ivars(child); 4736 rl = &dinfo->resources; 4737 4738 if (device_is_attached(child)) 4739 device_detach(child); 4740 4741 /* Turn off access to resources we're about to free */ 4742 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 4743 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 4744 4745 /* Free all allocated resources */ 4746 STAILQ_FOREACH(rle, rl, link) { 4747 if (rle->res) { 4748 if (rman_get_flags(rle->res) & RF_ACTIVE || 4749 resource_list_busy(rl, rle->type, rle->rid)) { 4750 pci_printf(&dinfo->cfg, 4751 "Resource still owned, oops. " 4752 "(type=%d, rid=%d, addr=%lx)\n", 4753 rle->type, rle->rid, 4754 rman_get_start(rle->res)); 4755 bus_release_resource(child, rle->type, rle->rid, 4756 rle->res); 4757 } 4758 resource_list_unreserve(rl, dev, child, rle->type, 4759 rle->rid); 4760 } 4761 } 4762 resource_list_free(rl); 4763 4764 device_delete_child(dev, child); 4765 pci_freecfg(dinfo); 4766 } 4767 4768 void 4769 pci_delete_resource(device_t dev, device_t child, int type, int rid) 4770 { 4771 struct pci_devinfo *dinfo; 4772 struct resource_list *rl; 4773 struct resource_list_entry *rle; 4774 4775 if (device_get_parent(child) != dev) 4776 return; 4777 4778 dinfo = device_get_ivars(child); 4779 rl = &dinfo->resources; 4780 rle = resource_list_find(rl, type, rid); 4781 if (rle == NULL) 4782 return; 4783 4784 if (rle->res) { 4785 if (rman_get_flags(rle->res) & RF_ACTIVE || 4786 resource_list_busy(rl, type, rid)) { 4787 device_printf(dev, "delete_resource: " 4788 "Resource still owned by child, oops. " 4789 "(type=%d, rid=%d, addr=%lx)\n", 4790 type, rid, rman_get_start(rle->res)); 4791 return; 4792 } 4793 resource_list_unreserve(rl, dev, child, type, rid); 4794 } 4795 resource_list_delete(rl, type, rid); 4796 } 4797 4798 struct resource_list * 4799 pci_get_resource_list (device_t dev, device_t child) 4800 { 4801 struct pci_devinfo *dinfo = device_get_ivars(child); 4802 4803 return (&dinfo->resources); 4804 } 4805 4806 bus_dma_tag_t 4807 pci_get_dma_tag(device_t bus, device_t dev) 4808 { 4809 struct pci_softc *sc = device_get_softc(bus); 4810 4811 return (sc->sc_dma_tag); 4812 } 4813 4814 uint32_t 4815 pci_read_config_method(device_t dev, device_t child, int reg, int width) 4816 { 4817 struct pci_devinfo *dinfo = device_get_ivars(child); 4818 pcicfgregs *cfg = &dinfo->cfg; 4819 4820 return (PCIB_READ_CONFIG(device_get_parent(dev), 4821 cfg->bus, cfg->slot, cfg->func, reg, width)); 4822 } 4823 4824 void 4825 pci_write_config_method(device_t dev, device_t child, int reg, 4826 uint32_t val, int width) 4827 { 4828 struct pci_devinfo *dinfo = device_get_ivars(child); 4829 pcicfgregs *cfg = &dinfo->cfg; 4830 4831 PCIB_WRITE_CONFIG(device_get_parent(dev), 4832 cfg->bus, cfg->slot, cfg->func, reg, val, width); 4833 } 4834 4835 int 4836 pci_child_location_str_method(device_t dev, device_t child, char *buf, 4837 size_t buflen) 4838 { 4839 4840 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 4841 pci_get_function(child)); 4842 return (0); 4843 } 4844 4845 int 4846 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 4847 size_t buflen) 4848 { 4849 struct pci_devinfo *dinfo; 4850 pcicfgregs *cfg; 4851 4852 dinfo = device_get_ivars(child); 4853 cfg = &dinfo->cfg; 4854 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 4855 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 4856 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 4857 cfg->progif); 4858 return (0); 4859 } 4860 4861 int 4862 pci_assign_interrupt_method(device_t dev, device_t child) 4863 { 4864 struct pci_devinfo *dinfo = device_get_ivars(child); 4865 pcicfgregs *cfg = &dinfo->cfg; 4866 4867 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 4868 cfg->intpin)); 4869 } 4870 4871 static int 4872 pci_modevent(module_t mod, int what, void *arg) 4873 { 4874 static struct cdev *pci_cdev; 4875 4876 switch (what) { 4877 case MOD_LOAD: 4878 STAILQ_INIT(&pci_devq); 4879 pci_generation = 0; 4880 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 4881 "pci"); 4882 pci_load_vendor_data(); 4883 break; 4884 4885 case MOD_UNLOAD: 4886 destroy_dev(pci_cdev); 4887 break; 4888 } 4889 4890 return (0); 4891 } 4892 4893 static void 4894 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 4895 { 4896 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 4897 struct pcicfg_pcie *cfg; 4898 int version, pos; 4899 4900 cfg = &dinfo->cfg.pcie; 4901 pos = cfg->pcie_location; 4902 4903 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 4904 4905 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 4906 4907 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4908 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 4909 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 4910 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 4911 4912 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4913 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 4914 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 4915 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 4916 4917 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4918 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 4919 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 4920 4921 if (version > 1) { 4922 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 4923 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 4924 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 4925 } 4926 #undef WREG 4927 } 4928 4929 static void 4930 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 4931 { 4932 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 4933 dinfo->cfg.pcix.pcix_command, 2); 4934 } 4935 4936 void 4937 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 4938 { 4939 4940 /* 4941 * Only do header type 0 devices. Type 1 devices are bridges, 4942 * which we know need special treatment. Type 2 devices are 4943 * cardbus bridges which also require special treatment. 4944 * Other types are unknown, and we err on the side of safety 4945 * by ignoring them. 4946 */ 4947 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 4948 return; 4949 4950 /* 4951 * Restore the device to full power mode. We must do this 4952 * before we restore the registers because moving from D3 to 4953 * D0 will cause the chip's BARs and some other registers to 4954 * be reset to some unknown power on reset values. Cut down 4955 * the noise on boot by doing nothing if we are already in 4956 * state D0. 4957 */ 4958 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 4959 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 4960 pci_restore_bars(dev); 4961 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 4962 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 4963 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 4964 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 4965 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 4966 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 4967 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 4968 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 4969 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 4970 4971 /* 4972 * Restore extended capabilities for PCI-Express and PCI-X 4973 */ 4974 if (dinfo->cfg.pcie.pcie_location != 0) 4975 pci_cfg_restore_pcie(dev, dinfo); 4976 if (dinfo->cfg.pcix.pcix_location != 0) 4977 pci_cfg_restore_pcix(dev, dinfo); 4978 4979 /* Restore MSI and MSI-X configurations if they are present. */ 4980 if (dinfo->cfg.msi.msi_location != 0) 4981 pci_resume_msi(dev); 4982 if (dinfo->cfg.msix.msix_location != 0) 4983 pci_resume_msix(dev); 4984 } 4985 4986 static void 4987 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 4988 { 4989 #define RREG(n) pci_read_config(dev, pos + (n), 2) 4990 struct pcicfg_pcie *cfg; 4991 int version, pos; 4992 4993 cfg = &dinfo->cfg.pcie; 4994 pos = cfg->pcie_location; 4995 4996 cfg->pcie_flags = RREG(PCIER_FLAGS); 4997 4998 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 4999 5000 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 5001 5002 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5003 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5004 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5005 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 5006 5007 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5008 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5009 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5010 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 5011 5012 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5013 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5014 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 5015 5016 if (version > 1) { 5017 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 5018 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 5019 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 5020 } 5021 #undef RREG 5022 } 5023 5024 static void 5025 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 5026 { 5027 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 5028 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 5029 } 5030 5031 void 5032 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 5033 { 5034 uint32_t cls; 5035 int ps; 5036 5037 /* 5038 * Only do header type 0 devices. Type 1 devices are bridges, which 5039 * we know need special treatment. Type 2 devices are cardbus bridges 5040 * which also require special treatment. Other types are unknown, and 5041 * we err on the side of safety by ignoring them. Powering down 5042 * bridges should not be undertaken lightly. 5043 */ 5044 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 5045 return; 5046 5047 /* 5048 * Some drivers apparently write to these registers w/o updating our 5049 * cached copy. No harm happens if we update the copy, so do so here 5050 * so we can restore them. The COMMAND register is modified by the 5051 * bus w/o updating the cache. This should represent the normally 5052 * writable portion of the 'defined' part of type 0 headers. In 5053 * theory we also need to save/restore the PCI capability structures 5054 * we know about, but apart from power we don't know any that are 5055 * writable. 5056 */ 5057 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 5058 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5059 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 5060 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 5061 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 5062 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 5063 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 5064 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 5065 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 5066 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 5067 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 5068 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 5069 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 5070 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 5071 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 5072 5073 if (dinfo->cfg.pcie.pcie_location != 0) 5074 pci_cfg_save_pcie(dev, dinfo); 5075 5076 if (dinfo->cfg.pcix.pcix_location != 0) 5077 pci_cfg_save_pcix(dev, dinfo); 5078 5079 /* 5080 * don't set the state for display devices, base peripherals and 5081 * memory devices since bad things happen when they are powered down. 5082 * We should (a) have drivers that can easily detach and (b) use 5083 * generic drivers for these devices so that some device actually 5084 * attaches. We need to make sure that when we implement (a) we don't 5085 * power the device down on a reattach. 5086 */ 5087 cls = pci_get_class(dev); 5088 if (!setstate) 5089 return; 5090 switch (pci_do_power_nodriver) 5091 { 5092 case 0: /* NO powerdown at all */ 5093 return; 5094 case 1: /* Conservative about what to power down */ 5095 if (cls == PCIC_STORAGE) 5096 return; 5097 /*FALLTHROUGH*/ 5098 case 2: /* Agressive about what to power down */ 5099 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 5100 cls == PCIC_BASEPERIPH) 5101 return; 5102 /*FALLTHROUGH*/ 5103 case 3: /* Power down everything */ 5104 break; 5105 } 5106 /* 5107 * PCI spec says we can only go into D3 state from D0 state. 5108 * Transition from D[12] into D0 before going to D3 state. 5109 */ 5110 ps = pci_get_powerstate(dev); 5111 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 5112 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5113 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 5114 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 5115 } 5116 5117 /* Wrapper APIs suitable for device driver use. */ 5118 void 5119 pci_save_state(device_t dev) 5120 { 5121 struct pci_devinfo *dinfo; 5122 5123 dinfo = device_get_ivars(dev); 5124 pci_cfg_save(dev, dinfo, 0); 5125 } 5126 5127 void 5128 pci_restore_state(device_t dev) 5129 { 5130 struct pci_devinfo *dinfo; 5131 5132 dinfo = device_get_ivars(dev); 5133 pci_cfg_restore(dev, dinfo); 5134 } 5135 5136 static uint16_t 5137 pci_get_rid_method(device_t dev, device_t child) 5138 { 5139 5140 return (PCIB_GET_RID(device_get_parent(dev), child)); 5141 }
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