Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pci.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD: releng/5.3/sys/dev/pci/pci.c 131459 2004-07-02 13:42:36Z imp $"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 static uint32_t pci_mapbase(unsigned mapreg); 64 static int pci_maptype(unsigned mapreg); 65 static int pci_mapsize(unsigned testval); 66 static int pci_maprange(unsigned mapreg); 67 static void pci_fixancient(pcicfgregs *cfg); 68 69 static int pci_porten(device_t pcib, int b, int s, int f); 70 static int pci_memen(device_t pcib, int b, int s, int f); 71 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 72 int b, int s, int f, int reg, 73 struct resource_list *rl); 74 static void pci_add_resources(device_t pcib, device_t bus, 75 device_t dev); 76 static int pci_probe(device_t dev); 77 static int pci_attach(device_t dev); 78 static void pci_load_vendor_data(void); 79 static int pci_describe_parse_line(char **ptr, int *vendor, 80 int *device, char **desc); 81 static char *pci_describe_device(device_t dev); 82 static int pci_modevent(module_t mod, int what, void *arg); 83 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 84 pcicfgregs *cfg); 85 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 86 static void pci_cfg_restore(device_t, struct pci_devinfo *); 87 static void pci_cfg_save(device_t, struct pci_devinfo *, int); 88 89 static device_method_t pci_methods[] = { 90 /* Device interface */ 91 DEVMETHOD(device_probe, pci_probe), 92 DEVMETHOD(device_attach, pci_attach), 93 DEVMETHOD(device_shutdown, bus_generic_shutdown), 94 DEVMETHOD(device_suspend, pci_suspend), 95 DEVMETHOD(device_resume, pci_resume), 96 97 /* Bus interface */ 98 DEVMETHOD(bus_print_child, pci_print_child), 99 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 100 DEVMETHOD(bus_read_ivar, pci_read_ivar), 101 DEVMETHOD(bus_write_ivar, pci_write_ivar), 102 DEVMETHOD(bus_driver_added, pci_driver_added), 103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 105 106 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 107 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 108 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 109 DEVMETHOD(bus_delete_resource, pci_delete_resource), 110 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 111 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 112 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 113 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 114 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 115 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 116 117 /* PCI interface */ 118 DEVMETHOD(pci_read_config, pci_read_config_method), 119 DEVMETHOD(pci_write_config, pci_write_config_method), 120 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 121 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 122 DEVMETHOD(pci_enable_io, pci_enable_io_method), 123 DEVMETHOD(pci_disable_io, pci_disable_io_method), 124 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 125 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 126 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 127 128 { 0, 0 } 129 }; 130 131 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 132 133 devclass_t pci_devclass; 134 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 135 MODULE_VERSION(pci, 1); 136 137 static char *pci_vendordata; 138 static size_t pci_vendordata_size; 139 140 141 struct pci_quirk { 142 uint32_t devid; /* Vendor/device of the card */ 143 int type; 144 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 145 int arg1; 146 int arg2; 147 }; 148 149 struct pci_quirk pci_quirks[] = { 150 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 151 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 154 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 155 156 { 0 } 157 }; 158 159 /* map register information */ 160 #define PCI_MAPMEM 0x01 /* memory map */ 161 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 162 #define PCI_MAPPORT 0x04 /* port map */ 163 164 struct devlist pci_devq; 165 uint32_t pci_generation; 166 uint32_t pci_numdevs = 0; 167 168 /* sysctl vars */ 169 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 170 171 static int pci_enable_io_modes = 1; 172 TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 173 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 174 &pci_enable_io_modes, 1, 175 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 176 enable these bits correctly. We'd like to do this all the time, but there\n\ 177 are some peripherals that this causes problems with."); 178 179 static int pci_do_powerstate = 0; 180 TUNABLE_INT("hw.pci.do_powerstate", (int *)&pci_do_powerstate); 181 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 182 &pci_do_powerstate, 0, 183 "Power down devices into D3 state when no driver attaches to them.\n\ 184 Otherwise, leave the device in D0 state when no driver attaches."); 185 186 /* Find a device_t by bus/slot/function */ 187 188 device_t 189 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 190 { 191 struct pci_devinfo *dinfo; 192 193 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 194 if ((dinfo->cfg.bus == bus) && 195 (dinfo->cfg.slot == slot) && 196 (dinfo->cfg.func == func)) { 197 return (dinfo->cfg.dev); 198 } 199 } 200 201 return (NULL); 202 } 203 204 /* Find a device_t by vendor/device ID */ 205 206 device_t 207 pci_find_device(uint16_t vendor, uint16_t device) 208 { 209 struct pci_devinfo *dinfo; 210 211 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 212 if ((dinfo->cfg.vendor == vendor) && 213 (dinfo->cfg.device == device)) { 214 return (dinfo->cfg.dev); 215 } 216 } 217 218 return (NULL); 219 } 220 221 /* return base address of memory or port map */ 222 223 static uint32_t 224 pci_mapbase(unsigned mapreg) 225 { 226 int mask = 0x03; 227 if ((mapreg & 0x01) == 0) 228 mask = 0x0f; 229 return (mapreg & ~mask); 230 } 231 232 /* return map type of memory or port map */ 233 234 static int 235 pci_maptype(unsigned mapreg) 236 { 237 static uint8_t maptype[0x10] = { 238 PCI_MAPMEM, PCI_MAPPORT, 239 PCI_MAPMEM, 0, 240 PCI_MAPMEM, PCI_MAPPORT, 241 0, 0, 242 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 243 PCI_MAPMEM|PCI_MAPMEMP, 0, 244 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 245 0, 0, 246 }; 247 248 return maptype[mapreg & 0x0f]; 249 } 250 251 /* return log2 of map size decoded for memory or port map */ 252 253 static int 254 pci_mapsize(unsigned testval) 255 { 256 int ln2size; 257 258 testval = pci_mapbase(testval); 259 ln2size = 0; 260 if (testval != 0) { 261 while ((testval & 1) == 0) 262 { 263 ln2size++; 264 testval >>= 1; 265 } 266 } 267 return (ln2size); 268 } 269 270 /* return log2 of address range supported by map register */ 271 272 static int 273 pci_maprange(unsigned mapreg) 274 { 275 int ln2range = 0; 276 switch (mapreg & 0x07) { 277 case 0x00: 278 case 0x01: 279 case 0x05: 280 ln2range = 32; 281 break; 282 case 0x02: 283 ln2range = 20; 284 break; 285 case 0x04: 286 ln2range = 64; 287 break; 288 } 289 return (ln2range); 290 } 291 292 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 293 294 static void 295 pci_fixancient(pcicfgregs *cfg) 296 { 297 if (cfg->hdrtype != 0) 298 return; 299 300 /* PCI to PCI bridges use header type 1 */ 301 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 302 cfg->hdrtype = 1; 303 } 304 305 /* extract header type specific config data */ 306 307 static void 308 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 309 { 310 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 311 switch (cfg->hdrtype) { 312 case 0: 313 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 314 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 315 cfg->nummaps = PCI_MAXMAPS_0; 316 break; 317 case 1: 318 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 319 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 320 cfg->nummaps = PCI_MAXMAPS_1; 321 break; 322 case 2: 323 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 324 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 325 cfg->nummaps = PCI_MAXMAPS_2; 326 break; 327 } 328 #undef REG 329 } 330 331 /* read configuration header into pcicfgregs structure */ 332 333 struct pci_devinfo * 334 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 335 { 336 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 337 pcicfgregs *cfg = NULL; 338 struct pci_devinfo *devlist_entry; 339 struct devlist *devlist_head; 340 341 devlist_head = &pci_devq; 342 343 devlist_entry = NULL; 344 345 if (REG(PCIR_DEVVENDOR, 4) != -1) { 346 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 347 if (devlist_entry == NULL) 348 return (NULL); 349 350 cfg = &devlist_entry->cfg; 351 352 cfg->bus = b; 353 cfg->slot = s; 354 cfg->func = f; 355 cfg->vendor = REG(PCIR_VENDOR, 2); 356 cfg->device = REG(PCIR_DEVICE, 2); 357 cfg->cmdreg = REG(PCIR_COMMAND, 2); 358 cfg->statreg = REG(PCIR_STATUS, 2); 359 cfg->baseclass = REG(PCIR_CLASS, 1); 360 cfg->subclass = REG(PCIR_SUBCLASS, 1); 361 cfg->progif = REG(PCIR_PROGIF, 1); 362 cfg->revid = REG(PCIR_REVID, 1); 363 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 364 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 365 cfg->lattimer = REG(PCIR_LATTIMER, 1); 366 cfg->intpin = REG(PCIR_INTPIN, 1); 367 cfg->intline = REG(PCIR_INTLINE, 1); 368 369 cfg->mingnt = REG(PCIR_MINGNT, 1); 370 cfg->maxlat = REG(PCIR_MAXLAT, 1); 371 372 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 373 cfg->hdrtype &= ~PCIM_MFDEV; 374 375 pci_fixancient(cfg); 376 pci_hdrtypedata(pcib, b, s, f, cfg); 377 378 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 379 pci_read_extcap(pcib, cfg); 380 381 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 382 383 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 384 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 385 devlist_entry->conf.pc_sel.pc_func = cfg->func; 386 devlist_entry->conf.pc_hdr = cfg->hdrtype; 387 388 devlist_entry->conf.pc_subvendor = cfg->subvendor; 389 devlist_entry->conf.pc_subdevice = cfg->subdevice; 390 devlist_entry->conf.pc_vendor = cfg->vendor; 391 devlist_entry->conf.pc_device = cfg->device; 392 393 devlist_entry->conf.pc_class = cfg->baseclass; 394 devlist_entry->conf.pc_subclass = cfg->subclass; 395 devlist_entry->conf.pc_progif = cfg->progif; 396 devlist_entry->conf.pc_revid = cfg->revid; 397 398 pci_numdevs++; 399 pci_generation++; 400 } 401 return (devlist_entry); 402 #undef REG 403 } 404 405 static void 406 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 407 { 408 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 409 int ptr, nextptr, ptrptr; 410 411 switch (cfg->hdrtype & PCIM_HDRTYPE) { 412 case 0: 413 ptrptr = PCIR_CAP_PTR; 414 break; 415 case 2: 416 ptrptr = 0x14; 417 break; 418 default: 419 return; /* no extended capabilities support */ 420 } 421 nextptr = REG(ptrptr, 1); /* sanity check? */ 422 423 /* 424 * Read capability entries. 425 */ 426 while (nextptr != 0) { 427 /* Sanity check */ 428 if (nextptr > 255) { 429 printf("illegal PCI extended capability offset %d\n", 430 nextptr); 431 return; 432 } 433 /* Find the next entry */ 434 ptr = nextptr; 435 nextptr = REG(ptr + 1, 1); 436 437 /* Process this entry */ 438 switch (REG(ptr, 1)) { 439 case PCIY_PMG: /* PCI power management */ 440 if (cfg->pp.pp_cap == 0) { 441 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 442 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 443 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 444 if ((nextptr - ptr) > PCIR_POWER_DATA) 445 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 446 } 447 break; 448 case PCIY_MSI: /* PCI MSI */ 449 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 450 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 451 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 452 else 453 cfg->msi.msi_data = PCIR_MSI_DATA; 454 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 455 PCIM_MSICTRL_MMC_MASK)>>1); 456 default: 457 break; 458 } 459 } 460 #undef REG 461 } 462 463 /* free pcicfgregs structure and all depending data structures */ 464 465 int 466 pci_freecfg(struct pci_devinfo *dinfo) 467 { 468 struct devlist *devlist_head; 469 470 devlist_head = &pci_devq; 471 472 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 473 free(dinfo, M_DEVBUF); 474 475 /* increment the generation count */ 476 pci_generation++; 477 478 /* we're losing one device */ 479 pci_numdevs--; 480 return (0); 481 } 482 483 /* 484 * PCI power manangement 485 */ 486 int 487 pci_set_powerstate_method(device_t dev, device_t child, int state) 488 { 489 struct pci_devinfo *dinfo = device_get_ivars(child); 490 pcicfgregs *cfg = &dinfo->cfg; 491 uint16_t status; 492 int result; 493 494 /* 495 * Dx -> Dx is a nop always. 496 */ 497 if (pci_get_powerstate(child) == state) 498 return (0); 499 500 if (cfg->pp.pp_cap != 0) { 501 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 502 & ~PCIM_PSTAT_DMASK; 503 result = 0; 504 switch (state) { 505 case PCI_POWERSTATE_D0: 506 status |= PCIM_PSTAT_D0; 507 break; 508 case PCI_POWERSTATE_D1: 509 if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) { 510 status |= PCIM_PSTAT_D1; 511 } else { 512 result = EOPNOTSUPP; 513 } 514 break; 515 case PCI_POWERSTATE_D2: 516 if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) { 517 status |= PCIM_PSTAT_D2; 518 } else { 519 result = EOPNOTSUPP; 520 } 521 break; 522 case PCI_POWERSTATE_D3: 523 status |= PCIM_PSTAT_D3; 524 break; 525 default: 526 result = EINVAL; 527 } 528 if (result == 0) 529 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 530 2); 531 } else { 532 result = ENXIO; 533 } 534 return(result); 535 } 536 537 int 538 pci_get_powerstate_method(device_t dev, device_t child) 539 { 540 struct pci_devinfo *dinfo = device_get_ivars(child); 541 pcicfgregs *cfg = &dinfo->cfg; 542 uint16_t status; 543 int result; 544 545 if (cfg->pp.pp_cap != 0) { 546 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 547 switch (status & PCIM_PSTAT_DMASK) { 548 case PCIM_PSTAT_D0: 549 result = PCI_POWERSTATE_D0; 550 break; 551 case PCIM_PSTAT_D1: 552 result = PCI_POWERSTATE_D1; 553 break; 554 case PCIM_PSTAT_D2: 555 result = PCI_POWERSTATE_D2; 556 break; 557 case PCIM_PSTAT_D3: 558 result = PCI_POWERSTATE_D3; 559 break; 560 default: 561 result = PCI_POWERSTATE_UNKNOWN; 562 break; 563 } 564 } else { 565 /* No support, device is always at D0 */ 566 result = PCI_POWERSTATE_D0; 567 } 568 return(result); 569 } 570 571 /* 572 * Some convenience functions for PCI device drivers. 573 */ 574 575 static __inline void 576 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 577 { 578 uint16_t command; 579 580 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 581 command |= bit; 582 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 583 } 584 585 static __inline void 586 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 587 { 588 uint16_t command; 589 590 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 591 command &= ~bit; 592 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 593 } 594 595 int 596 pci_enable_busmaster_method(device_t dev, device_t child) 597 { 598 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 599 return (0); 600 } 601 602 int 603 pci_disable_busmaster_method(device_t dev, device_t child) 604 { 605 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 606 return (0); 607 } 608 609 int 610 pci_enable_io_method(device_t dev, device_t child, int space) 611 { 612 uint16_t command; 613 uint16_t bit; 614 char *error; 615 616 bit = 0; 617 error = NULL; 618 619 switch(space) { 620 case SYS_RES_IOPORT: 621 bit = PCIM_CMD_PORTEN; 622 error = "port"; 623 break; 624 case SYS_RES_MEMORY: 625 bit = PCIM_CMD_MEMEN; 626 error = "memory"; 627 break; 628 default: 629 return (EINVAL); 630 } 631 pci_set_command_bit(dev, child, bit); 632 /* Some devices seem to need a brief stall here, what do to? */ 633 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 634 if (command & bit) 635 return (0); 636 device_printf(child, "failed to enable %s mapping!\n", error); 637 return (ENXIO); 638 } 639 640 int 641 pci_disable_io_method(device_t dev, device_t child, int space) 642 { 643 uint16_t command; 644 uint16_t bit; 645 char *error; 646 647 bit = 0; 648 error = NULL; 649 650 switch(space) { 651 case SYS_RES_IOPORT: 652 bit = PCIM_CMD_PORTEN; 653 error = "port"; 654 break; 655 case SYS_RES_MEMORY: 656 bit = PCIM_CMD_MEMEN; 657 error = "memory"; 658 break; 659 default: 660 return (EINVAL); 661 } 662 pci_clear_command_bit(dev, child, bit); 663 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 664 if (command & bit) { 665 device_printf(child, "failed to disable %s mapping!\n", error); 666 return (ENXIO); 667 } 668 return (0); 669 } 670 671 /* 672 * New style pci driver. Parent device is either a pci-host-bridge or a 673 * pci-pci-bridge. Both kinds are represented by instances of pcib. 674 */ 675 676 void 677 pci_print_verbose(struct pci_devinfo *dinfo) 678 { 679 if (bootverbose) { 680 pcicfgregs *cfg = &dinfo->cfg; 681 682 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 683 cfg->vendor, cfg->device, cfg->revid); 684 printf("\tbus=%d, slot=%d, func=%d\n", 685 cfg->bus, cfg->slot, cfg->func); 686 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 687 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 688 cfg->mfdev); 689 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 690 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 691 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 692 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 693 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 694 if (cfg->intpin > 0) 695 printf("\tintpin=%c, irq=%d\n", 696 cfg->intpin +'a' -1, cfg->intline); 697 if (cfg->pp.pp_cap) { 698 uint16_t status; 699 700 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 701 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 702 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 703 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 704 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 705 status & PCIM_PSTAT_DMASK); 706 } 707 if (cfg->msi.msi_data) { 708 int ctrl; 709 710 ctrl = cfg->msi.msi_ctrl; 711 printf("\tMSI supports %d message%s%s%s\n", 712 cfg->msi.msi_msgnum, 713 (cfg->msi.msi_msgnum == 1) ? "" : "s", 714 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 715 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 716 } 717 } 718 } 719 720 static int 721 pci_porten(device_t pcib, int b, int s, int f) 722 { 723 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 724 & PCIM_CMD_PORTEN) != 0; 725 } 726 727 static int 728 pci_memen(device_t pcib, int b, int s, int f) 729 { 730 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 731 & PCIM_CMD_MEMEN) != 0; 732 } 733 734 /* 735 * Add a resource based on a pci map register. Return 1 if the map 736 * register is a 32bit map register or 2 if it is a 64bit register. 737 */ 738 static int 739 pci_add_map(device_t pcib, device_t bus, device_t dev, 740 int b, int s, int f, int reg, struct resource_list *rl) 741 { 742 uint32_t map; 743 uint64_t base; 744 uint64_t start, end, count; 745 uint8_t ln2size; 746 uint8_t ln2range; 747 uint32_t testval; 748 uint16_t cmd; 749 int type; 750 751 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 752 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 753 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 754 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 755 756 if (pci_maptype(map) & PCI_MAPMEM) 757 type = SYS_RES_MEMORY; 758 else 759 type = SYS_RES_IOPORT; 760 ln2size = pci_mapsize(testval); 761 ln2range = pci_maprange(testval); 762 base = pci_mapbase(map); 763 764 /* 765 * For I/O registers, if bottom bit is set, and the next bit up 766 * isn't clear, we know we have a BAR that doesn't conform to the 767 * spec, so ignore it. Also, sanity check the size of the data 768 * areas to the type of memory involved. Memory must be at least 769 * 32 bytes in size, while I/O ranges must be at least 4. 770 */ 771 if ((testval & 0x1) == 0x1 && 772 (testval & 0x2) != 0) 773 return (1); 774 if ((type == SYS_RES_MEMORY && ln2size < 5) || 775 (type == SYS_RES_IOPORT && ln2size < 2)) 776 return (1); 777 778 if (ln2range == 64) 779 /* Read the other half of a 64bit map register */ 780 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 781 782 if (bootverbose) { 783 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 784 reg, pci_maptype(map), ln2range, 785 (unsigned int) base, ln2size); 786 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 787 printf(", port disabled\n"); 788 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 789 printf(", memory disabled\n"); 790 else 791 printf(", enabled\n"); 792 } 793 794 /* 795 * This code theoretically does the right thing, but has 796 * undesirable side effects in some cases where peripherals 797 * respond oddly to having these bits enabled. Let the user 798 * be able to turn them off (since pci_enable_io_modes is 1 by 799 * default). 800 */ 801 if (pci_enable_io_modes) { 802 /* Turn on resources that have been left off by a lazy BIOS */ 803 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 804 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 805 cmd |= PCIM_CMD_PORTEN; 806 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 807 } 808 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 809 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 810 cmd |= PCIM_CMD_MEMEN; 811 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 812 } 813 } else { 814 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 815 return (1); 816 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 817 return (1); 818 } 819 /* 820 * If base is 0, then we have problems. It is best to ignore 821 * such entires for the moment. These will be allocated later if 822 * the driver specifically requests them. 823 */ 824 if (base == 0) 825 return 1; 826 827 start = base; 828 end = base + (1 << ln2size) - 1; 829 count = 1 << ln2size; 830 resource_list_add(rl, type, reg, start, end, count); 831 832 /* 833 * Not quite sure what to do on failure of allocating the resource 834 * since I can postulate several right answers. 835 */ 836 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 837 return ((ln2range == 64) ? 2 : 1); 838 } 839 840 /* 841 * For ATA devices we need to decide early what addressing mode to use. 842 * Legacy demands that the primary and secondary ATA ports sits on the 843 * same addresses that old ISA hardware did. This dictates that we use 844 * those addresses and ignore the BAR's if we cannot set PCI native 845 * addressing mode. 846 */ 847 static void 848 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 849 int s, int f, struct resource_list *rl) 850 { 851 int rid, type, progif; 852 #if 0 853 /* if this device supports PCI native addressing use it */ 854 progif = pci_read_config(dev, PCIR_PROGIF, 1); 855 if ((progif & 0x8a) == 0x8a) { 856 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 857 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 858 printf("Trying ATA native PCI addressing mode\n"); 859 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 860 } 861 } 862 #endif 863 progif = pci_read_config(dev, PCIR_PROGIF, 1); 864 type = SYS_RES_IOPORT; 865 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 866 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 867 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 868 } 869 else { 870 rid = PCIR_BAR(0); 871 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 872 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 873 rid = PCIR_BAR(1); 874 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 875 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 876 } 877 if (progif & PCIP_STORAGE_IDE_MODESEC) { 878 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 879 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 880 } 881 else { 882 rid = PCIR_BAR(2); 883 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 884 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 885 rid = PCIR_BAR(3); 886 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 887 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 888 } 889 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 890 } 891 892 static void 893 pci_add_resources(device_t pcib, device_t bus, device_t dev) 894 { 895 struct pci_devinfo *dinfo = device_get_ivars(dev); 896 pcicfgregs *cfg = &dinfo->cfg; 897 struct resource_list *rl = &dinfo->resources; 898 struct pci_quirk *q; 899 int b, i, irq, f, s; 900 901 b = cfg->bus; 902 s = cfg->slot; 903 f = cfg->func; 904 905 /* ATA devices needs special map treatment */ 906 if ((pci_get_class(dev) == PCIC_STORAGE) && 907 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 908 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 909 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 910 else 911 for (i = 0; i < cfg->nummaps;) 912 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 913 rl); 914 915 for (q = &pci_quirks[0]; q->devid; q++) { 916 if (q->devid == ((cfg->device << 16) | cfg->vendor) 917 && q->type == PCI_QUIRK_MAP_REG) 918 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 919 } 920 921 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 922 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) 923 /* 924 * Try to re-route interrupts. Sometimes the BIOS or 925 * firmware may leave bogus values in these registers. 926 * If the re-route fails, then just stick with what we 927 * have. 928 */ 929 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 930 if (PCI_INTERRUPT_VALID(irq)) { 931 pci_write_config(dev, PCIR_INTLINE, irq, 1); 932 cfg->intline = irq; 933 } else 934 #endif 935 irq = cfg->intline; 936 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 937 } 938 } 939 940 void 941 pci_add_children(device_t dev, int busno, size_t dinfo_size) 942 { 943 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 944 device_t pcib = device_get_parent(dev); 945 struct pci_devinfo *dinfo; 946 int maxslots; 947 int s, f, pcifunchigh; 948 uint8_t hdrtype; 949 950 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 951 ("dinfo_size too small")); 952 maxslots = PCIB_MAXSLOTS(pcib); 953 for (s = 0; s <= maxslots; s++) { 954 pcifunchigh = 0; 955 f = 0; 956 hdrtype = REG(PCIR_HDRTYPE, 1); 957 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 958 continue; 959 if (hdrtype & PCIM_MFDEV) 960 pcifunchigh = PCI_FUNCMAX; 961 for (f = 0; f <= pcifunchigh; f++) { 962 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 963 if (dinfo != NULL) { 964 pci_add_child(dev, dinfo); 965 } 966 } 967 } 968 #undef REG 969 } 970 971 void 972 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 973 { 974 device_t pcib; 975 976 pcib = device_get_parent(bus); 977 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 978 device_set_ivars(dinfo->cfg.dev, dinfo); 979 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 980 pci_cfg_restore(dinfo->cfg.dev, dinfo); 981 pci_add_resources(pcib, bus, dinfo->cfg.dev); 982 pci_print_verbose(dinfo); 983 } 984 985 static int 986 pci_probe(device_t dev) 987 { 988 989 device_set_desc(dev, "PCI bus"); 990 991 /* Allow other subclasses to override this driver. */ 992 return (-1000); 993 } 994 995 static int 996 pci_attach(device_t dev) 997 { 998 int busno; 999 1000 /* 1001 * Since there can be multiple independantly numbered PCI 1002 * busses on some large alpha systems, we can't use the unit 1003 * number to decide what bus we are probing. We ask the parent 1004 * pcib what our bus number is. 1005 */ 1006 busno = pcib_get_bus(dev); 1007 if (bootverbose) 1008 device_printf(dev, "physical bus=%d\n", busno); 1009 1010 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1011 1012 return (bus_generic_attach(dev)); 1013 } 1014 1015 int 1016 pci_suspend(device_t dev) 1017 { 1018 int numdevs; 1019 device_t *devlist; 1020 device_t child; 1021 struct pci_devinfo *dinfo; 1022 int i; 1023 1024 /* 1025 * Save the pci configuration space for each child. We don't need 1026 * to do this, unless the BIOS suspend code powers down the bus and 1027 * the devices on the bus. 1028 */ 1029 device_get_children(dev, &devlist, &numdevs); 1030 for (i = 0; i < numdevs; i++) { 1031 child = devlist[i]; 1032 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1033 pci_cfg_save(child, dinfo, 0); 1034 } 1035 free(devlist, M_TEMP); 1036 return (bus_generic_suspend(dev)); 1037 } 1038 1039 int 1040 pci_resume(device_t dev) 1041 { 1042 int numdevs; 1043 device_t *devlist; 1044 device_t child; 1045 struct pci_devinfo *dinfo; 1046 int i; 1047 1048 /* 1049 * Restore the pci configuration space for each child. 1050 */ 1051 device_get_children(dev, &devlist, &numdevs); 1052 for (i = 0; i < numdevs; i++) { 1053 child = devlist[i]; 1054 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1055 pci_cfg_restore(child, dinfo); 1056 } 1057 free(devlist, M_TEMP); 1058 return (bus_generic_resume(dev)); 1059 } 1060 1061 static void 1062 pci_load_vendor_data(void) 1063 { 1064 caddr_t vendordata, info; 1065 1066 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1067 info = preload_search_info(vendordata, MODINFO_ADDR); 1068 pci_vendordata = *(char **)info; 1069 info = preload_search_info(vendordata, MODINFO_SIZE); 1070 pci_vendordata_size = *(size_t *)info; 1071 /* terminate the database */ 1072 pci_vendordata[pci_vendordata_size] = '\n'; 1073 } 1074 } 1075 1076 void 1077 pci_driver_added(device_t dev, driver_t *driver) 1078 { 1079 int numdevs; 1080 device_t *devlist; 1081 device_t child; 1082 struct pci_devinfo *dinfo; 1083 int i; 1084 1085 if (bootverbose) 1086 device_printf(dev, "driver added\n"); 1087 DEVICE_IDENTIFY(driver, dev); 1088 device_get_children(dev, &devlist, &numdevs); 1089 for (i = 0; i < numdevs; i++) { 1090 child = devlist[i]; 1091 if (device_get_state(child) != DS_NOTPRESENT) 1092 continue; 1093 dinfo = device_get_ivars(child); 1094 pci_print_verbose(dinfo); 1095 /*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1096 if (bootverbose) 1097 printf("pci%d:%d:%d: reprobing on driver added\n", 1098 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1099 pci_cfg_restore(child, dinfo); 1100 if (device_probe_and_attach(child) != 0) 1101 pci_cfg_save(child, dinfo, 1); 1102 } 1103 free(devlist, M_TEMP); 1104 } 1105 1106 int 1107 pci_print_child(device_t dev, device_t child) 1108 { 1109 struct pci_devinfo *dinfo; 1110 struct resource_list *rl; 1111 int retval = 0; 1112 1113 dinfo = device_get_ivars(child); 1114 rl = &dinfo->resources; 1115 1116 retval += bus_print_child_header(dev, child); 1117 1118 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1119 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1120 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1121 if (device_get_flags(dev)) 1122 retval += printf(" flags %#x", device_get_flags(dev)); 1123 1124 retval += printf(" at device %d.%d", pci_get_slot(child), 1125 pci_get_function(child)); 1126 1127 retval += bus_print_child_footer(dev, child); 1128 1129 return (retval); 1130 } 1131 1132 static struct 1133 { 1134 int class; 1135 int subclass; 1136 char *desc; 1137 } pci_nomatch_tab[] = { 1138 {PCIC_OLD, -1, "old"}, 1139 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1140 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1141 {PCIC_STORAGE, -1, "mass storage"}, 1142 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1143 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1144 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1145 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1146 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1147 {PCIC_NETWORK, -1, "network"}, 1148 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1149 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1150 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1151 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1152 {PCIC_DISPLAY, -1, "display"}, 1153 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1154 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1155 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1156 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1157 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1158 {PCIC_MEMORY, -1, "memory"}, 1159 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1160 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1161 {PCIC_BRIDGE, -1, "bridge"}, 1162 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1163 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1164 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1165 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1166 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1167 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1168 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1169 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1170 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1171 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1172 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1173 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1174 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1175 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1176 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1177 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1178 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1179 {PCIC_INPUTDEV, -1, "input device"}, 1180 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1181 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1182 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1183 {PCIC_DOCKING, -1, "docking station"}, 1184 {PCIC_PROCESSOR, -1, "processor"}, 1185 {PCIC_SERIALBUS, -1, "serial bus"}, 1186 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1187 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1188 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1189 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1190 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1191 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1192 {0, 0, NULL} 1193 }; 1194 1195 void 1196 pci_probe_nomatch(device_t dev, device_t child) 1197 { 1198 int i; 1199 char *cp, *scp, *device; 1200 1201 /* 1202 * Look for a listing for this device in a loaded device database. 1203 */ 1204 if ((device = pci_describe_device(child)) != NULL) { 1205 device_printf(dev, "<%s>", device); 1206 free(device, M_DEVBUF); 1207 } else { 1208 /* 1209 * Scan the class/subclass descriptions for a general 1210 * description. 1211 */ 1212 cp = "unknown"; 1213 scp = NULL; 1214 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1215 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1216 if (pci_nomatch_tab[i].subclass == -1) { 1217 cp = pci_nomatch_tab[i].desc; 1218 } else if (pci_nomatch_tab[i].subclass == 1219 pci_get_subclass(child)) { 1220 scp = pci_nomatch_tab[i].desc; 1221 } 1222 } 1223 } 1224 device_printf(dev, "<%s%s%s>", 1225 cp ? cp : "", 1226 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1227 scp ? scp : ""); 1228 } 1229 printf(" at device %d.%d (no driver attached)\n", 1230 pci_get_slot(child), pci_get_function(child)); 1231 if (pci_do_powerstate) 1232 pci_cfg_save(child, 1233 (struct pci_devinfo *) device_get_ivars(child), 1); 1234 return; 1235 } 1236 1237 /* 1238 * Parse the PCI device database, if loaded, and return a pointer to a 1239 * description of the device. 1240 * 1241 * The database is flat text formatted as follows: 1242 * 1243 * Any line not in a valid format is ignored. 1244 * Lines are terminated with newline '\n' characters. 1245 * 1246 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1247 * the vendor name. 1248 * 1249 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1250 * - devices cannot be listed without a corresponding VENDOR line. 1251 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1252 * another TAB, then the device name. 1253 */ 1254 1255 /* 1256 * Assuming (ptr) points to the beginning of a line in the database, 1257 * return the vendor or device and description of the next entry. 1258 * The value of (vendor) or (device) inappropriate for the entry type 1259 * is set to -1. Returns nonzero at the end of the database. 1260 * 1261 * Note that this is slightly unrobust in the face of corrupt data; 1262 * we attempt to safeguard against this by spamming the end of the 1263 * database with a newline when we initialise. 1264 */ 1265 static int 1266 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1267 { 1268 char *cp = *ptr; 1269 int left; 1270 1271 *device = -1; 1272 *vendor = -1; 1273 **desc = '\0'; 1274 for (;;) { 1275 left = pci_vendordata_size - (cp - pci_vendordata); 1276 if (left <= 0) { 1277 *ptr = cp; 1278 return(1); 1279 } 1280 1281 /* vendor entry? */ 1282 if (*cp != '\t' && 1283 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1284 break; 1285 /* device entry? */ 1286 if (*cp == '\t' && 1287 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1288 break; 1289 1290 /* skip to next line */ 1291 while (*cp != '\n' && left > 0) { 1292 cp++; 1293 left--; 1294 } 1295 if (*cp == '\n') { 1296 cp++; 1297 left--; 1298 } 1299 } 1300 /* skip to next line */ 1301 while (*cp != '\n' && left > 0) { 1302 cp++; 1303 left--; 1304 } 1305 if (*cp == '\n' && left > 0) 1306 cp++; 1307 *ptr = cp; 1308 return(0); 1309 } 1310 1311 static char * 1312 pci_describe_device(device_t dev) 1313 { 1314 int vendor, device; 1315 char *desc, *vp, *dp, *line; 1316 1317 desc = vp = dp = NULL; 1318 1319 /* 1320 * If we have no vendor data, we can't do anything. 1321 */ 1322 if (pci_vendordata == NULL) 1323 goto out; 1324 1325 /* 1326 * Scan the vendor data looking for this device 1327 */ 1328 line = pci_vendordata; 1329 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1330 goto out; 1331 for (;;) { 1332 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1333 goto out; 1334 if (vendor == pci_get_vendor(dev)) 1335 break; 1336 } 1337 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1338 goto out; 1339 for (;;) { 1340 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1341 *dp = 0; 1342 break; 1343 } 1344 if (vendor != -1) { 1345 *dp = 0; 1346 break; 1347 } 1348 if (device == pci_get_device(dev)) 1349 break; 1350 } 1351 if (dp[0] == '\0') 1352 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1353 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1354 NULL) 1355 sprintf(desc, "%s, %s", vp, dp); 1356 out: 1357 if (vp != NULL) 1358 free(vp, M_DEVBUF); 1359 if (dp != NULL) 1360 free(dp, M_DEVBUF); 1361 return(desc); 1362 } 1363 1364 int 1365 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1366 { 1367 struct pci_devinfo *dinfo; 1368 pcicfgregs *cfg; 1369 1370 dinfo = device_get_ivars(child); 1371 cfg = &dinfo->cfg; 1372 1373 switch (which) { 1374 case PCI_IVAR_ETHADDR: 1375 /* 1376 * The generic accessor doesn't deal with failure, so 1377 * we set the return value, then return an error. 1378 */ 1379 *((uint8_t **) result) = NULL; 1380 return (EINVAL); 1381 case PCI_IVAR_SUBVENDOR: 1382 *result = cfg->subvendor; 1383 break; 1384 case PCI_IVAR_SUBDEVICE: 1385 *result = cfg->subdevice; 1386 break; 1387 case PCI_IVAR_VENDOR: 1388 *result = cfg->vendor; 1389 break; 1390 case PCI_IVAR_DEVICE: 1391 *result = cfg->device; 1392 break; 1393 case PCI_IVAR_DEVID: 1394 *result = (cfg->device << 16) | cfg->vendor; 1395 break; 1396 case PCI_IVAR_CLASS: 1397 *result = cfg->baseclass; 1398 break; 1399 case PCI_IVAR_SUBCLASS: 1400 *result = cfg->subclass; 1401 break; 1402 case PCI_IVAR_PROGIF: 1403 *result = cfg->progif; 1404 break; 1405 case PCI_IVAR_REVID: 1406 *result = cfg->revid; 1407 break; 1408 case PCI_IVAR_INTPIN: 1409 *result = cfg->intpin; 1410 break; 1411 case PCI_IVAR_IRQ: 1412 *result = cfg->intline; 1413 break; 1414 case PCI_IVAR_BUS: 1415 *result = cfg->bus; 1416 break; 1417 case PCI_IVAR_SLOT: 1418 *result = cfg->slot; 1419 break; 1420 case PCI_IVAR_FUNCTION: 1421 *result = cfg->func; 1422 break; 1423 default: 1424 return (ENOENT); 1425 } 1426 return (0); 1427 } 1428 1429 int 1430 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1431 { 1432 struct pci_devinfo *dinfo; 1433 1434 dinfo = device_get_ivars(child); 1435 1436 switch (which) { 1437 case PCI_IVAR_INTPIN: 1438 dinfo->cfg.intpin = value; 1439 return (0); 1440 case PCI_IVAR_ETHADDR: 1441 case PCI_IVAR_SUBVENDOR: 1442 case PCI_IVAR_SUBDEVICE: 1443 case PCI_IVAR_VENDOR: 1444 case PCI_IVAR_DEVICE: 1445 case PCI_IVAR_DEVID: 1446 case PCI_IVAR_CLASS: 1447 case PCI_IVAR_SUBCLASS: 1448 case PCI_IVAR_PROGIF: 1449 case PCI_IVAR_REVID: 1450 case PCI_IVAR_IRQ: 1451 case PCI_IVAR_BUS: 1452 case PCI_IVAR_SLOT: 1453 case PCI_IVAR_FUNCTION: 1454 return (EINVAL); /* disallow for now */ 1455 1456 default: 1457 return (ENOENT); 1458 } 1459 } 1460 1461 1462 #include "opt_ddb.h" 1463 #ifdef DDB 1464 #include <ddb/ddb.h> 1465 #include <sys/cons.h> 1466 1467 /* 1468 * List resources based on pci map registers, used for within ddb 1469 */ 1470 1471 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1472 { 1473 struct pci_devinfo *dinfo; 1474 struct devlist *devlist_head; 1475 struct pci_conf *p; 1476 const char *name; 1477 int i, error, none_count, quit; 1478 1479 none_count = 0; 1480 /* get the head of the device queue */ 1481 devlist_head = &pci_devq; 1482 1483 /* 1484 * Go through the list of devices and print out devices 1485 */ 1486 db_setup_paging(db_simple_pager, &quit, DB_LINES_PER_PAGE); 1487 for (error = 0, i = 0, quit = 0, 1488 dinfo = STAILQ_FIRST(devlist_head); 1489 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1490 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1491 1492 /* Populate pd_name and pd_unit */ 1493 name = NULL; 1494 if (dinfo->cfg.dev) 1495 name = device_get_name(dinfo->cfg.dev); 1496 1497 p = &dinfo->conf; 1498 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1499 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1500 (name && *name) ? name : "none", 1501 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1502 none_count++, 1503 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1504 p->pc_sel.pc_func, (p->pc_class << 16) | 1505 (p->pc_subclass << 8) | p->pc_progif, 1506 (p->pc_subdevice << 16) | p->pc_subvendor, 1507 (p->pc_device << 16) | p->pc_vendor, 1508 p->pc_revid, p->pc_hdr); 1509 } 1510 } 1511 #endif /* DDB */ 1512 1513 static struct resource * 1514 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1515 u_long start, u_long end, u_long count, u_int flags) 1516 { 1517 struct pci_devinfo *dinfo = device_get_ivars(child); 1518 struct resource_list *rl = &dinfo->resources; 1519 struct resource_list_entry *rle; 1520 struct resource *res; 1521 uint32_t map, testval; 1522 int mapsize; 1523 1524 /* 1525 * Weed out the bogons, and figure out how large the BAR/map 1526 * is. Bars that read back 0 here are bogus and unimplemented. 1527 * Note: atapci in legacy mode are special and handled elsewhere 1528 * in the code. If you have a atapci device in legacy mode and 1529 * it fails here, that other code is broken. 1530 */ 1531 res = NULL; 1532 map = pci_read_config(child, *rid, 4); 1533 pci_write_config(child, *rid, 0xffffffff, 4); 1534 testval = pci_read_config(child, *rid, 4); 1535 if (testval == 0) 1536 return (NULL); 1537 if (pci_maptype(testval) & PCI_MAPMEM) { 1538 if (type != SYS_RES_MEMORY) { 1539 device_printf(child, 1540 "failed: rid %#x is memory, requested %d\n", 1541 *rid, type); 1542 goto out; 1543 } 1544 } else { 1545 if (type != SYS_RES_IOPORT) { 1546 device_printf(child, 1547 "failed: rid %#x is ioport, requested %d\n", 1548 *rid, type); 1549 goto out; 1550 } 1551 } 1552 /* 1553 * For real BARs, we need to override the size that 1554 * the driver requests, because that's what the BAR 1555 * actually uses and we would otherwise have a 1556 * situation where we might allocate the excess to 1557 * another driver, which won't work. 1558 */ 1559 mapsize = pci_mapsize(testval); 1560 count = 1 << mapsize; 1561 if (RF_ALIGNMENT(flags) < mapsize) 1562 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1563 1564 /* 1565 * Allocate enough resource, and then write back the 1566 * appropriate bar for that resource. 1567 */ 1568 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1569 start, end, count, flags); 1570 if (res == NULL) { 1571 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1572 count, *rid, type); 1573 goto out; 1574 } 1575 resource_list_add(rl, type, *rid, start, end, count); 1576 rle = resource_list_find(rl, type, *rid); 1577 if (rle == NULL) 1578 panic("pci_alloc_map: unexpedly can't find resource."); 1579 rle->res = res; 1580 if (bootverbose) 1581 device_printf(child, 1582 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1583 count, *rid, type, rman_get_start(res)); 1584 map = rman_get_start(res); 1585 out:; 1586 pci_write_config(child, *rid, map, 4); 1587 return (res); 1588 } 1589 1590 1591 struct resource * 1592 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1593 u_long start, u_long end, u_long count, u_int flags) 1594 { 1595 struct pci_devinfo *dinfo = device_get_ivars(child); 1596 struct resource_list *rl = &dinfo->resources; 1597 struct resource_list_entry *rle; 1598 pcicfgregs *cfg = &dinfo->cfg; 1599 1600 /* 1601 * Perform lazy resource allocation 1602 */ 1603 if (device_get_parent(child) == dev) { 1604 switch (type) { 1605 case SYS_RES_IRQ: 1606 /* 1607 * If the child device doesn't have an 1608 * interrupt routed and is deserving of an 1609 * interrupt, try to assign it one. 1610 */ 1611 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1612 (cfg->intpin != 0)) { 1613 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1614 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1615 pci_write_config(child, PCIR_INTLINE, 1616 cfg->intline, 1); 1617 resource_list_add(rl, SYS_RES_IRQ, 0, 1618 cfg->intline, cfg->intline, 1); 1619 } 1620 } 1621 break; 1622 case SYS_RES_IOPORT: 1623 case SYS_RES_MEMORY: 1624 if (*rid < PCIR_BAR(cfg->nummaps)) { 1625 /* 1626 * Enable the I/O mode. We should 1627 * also be assigning resources too 1628 * when none are present. The 1629 * resource_list_alloc kind of sorta does 1630 * this... 1631 */ 1632 if (PCI_ENABLE_IO(dev, child, type)) 1633 return (NULL); 1634 } 1635 rle = resource_list_find(rl, type, *rid); 1636 if (rle == NULL) 1637 return (pci_alloc_map(dev, child, type, rid, 1638 start, end, count, flags)); 1639 break; 1640 } 1641 /* 1642 * If we've already allocated the resource, then 1643 * return it now. But first we may need to activate 1644 * it, since we don't allocate the resource as active 1645 * above. Normally this would be done down in the 1646 * nexus, but since we short-circuit that path we have 1647 * to do its job here. Not sure if we should free the 1648 * resource if it fails to activate. 1649 */ 1650 rle = resource_list_find(rl, type, *rid); 1651 if (rle != NULL && rle->res != NULL) { 1652 if (bootverbose) 1653 device_printf(child, 1654 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1655 rman_get_size(rle->res), *rid, type, 1656 rman_get_start(rle->res)); 1657 if ((flags & RF_ACTIVE) && 1658 bus_generic_activate_resource(dev, child, type, 1659 *rid, rle->res) != 0) 1660 return NULL; 1661 return (rle->res); 1662 } 1663 } 1664 return (resource_list_alloc(rl, dev, child, type, rid, 1665 start, end, count, flags)); 1666 } 1667 1668 void 1669 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1670 { 1671 struct pci_devinfo *dinfo; 1672 struct resource_list *rl; 1673 struct resource_list_entry *rle; 1674 1675 if (device_get_parent(child) != dev) 1676 return; 1677 1678 dinfo = device_get_ivars(child); 1679 rl = &dinfo->resources; 1680 rle = resource_list_find(rl, type, rid); 1681 if (rle) { 1682 if (rle->res) { 1683 if (rman_get_device(rle->res) != dev || 1684 rman_get_flags(rle->res) & RF_ACTIVE) { 1685 device_printf(dev, "delete_resource: " 1686 "Resource still owned by child, oops. " 1687 "(type=%d, rid=%d, addr=%lx)\n", 1688 rle->type, rle->rid, 1689 rman_get_start(rle->res)); 1690 return; 1691 } 1692 bus_release_resource(dev, type, rid, rle->res); 1693 } 1694 resource_list_delete(rl, type, rid); 1695 } 1696 /* 1697 * Why do we turn off the PCI configuration BAR when we delete a 1698 * resource? -- imp 1699 */ 1700 pci_write_config(child, rid, 0, 4); 1701 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1702 } 1703 1704 struct resource_list * 1705 pci_get_resource_list (device_t dev, device_t child) 1706 { 1707 struct pci_devinfo *dinfo = device_get_ivars(child); 1708 1709 return (&dinfo->resources); 1710 } 1711 1712 uint32_t 1713 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1714 { 1715 struct pci_devinfo *dinfo = device_get_ivars(child); 1716 pcicfgregs *cfg = &dinfo->cfg; 1717 1718 return (PCIB_READ_CONFIG(device_get_parent(dev), 1719 cfg->bus, cfg->slot, cfg->func, reg, width)); 1720 } 1721 1722 void 1723 pci_write_config_method(device_t dev, device_t child, int reg, 1724 uint32_t val, int width) 1725 { 1726 struct pci_devinfo *dinfo = device_get_ivars(child); 1727 pcicfgregs *cfg = &dinfo->cfg; 1728 1729 PCIB_WRITE_CONFIG(device_get_parent(dev), 1730 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1731 } 1732 1733 int 1734 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1735 size_t buflen) 1736 { 1737 struct pci_devinfo *dinfo; 1738 1739 dinfo = device_get_ivars(child); 1740 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1741 pci_get_function(child)); 1742 return (0); 1743 } 1744 1745 int 1746 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1747 size_t buflen) 1748 { 1749 struct pci_devinfo *dinfo; 1750 pcicfgregs *cfg; 1751 1752 dinfo = device_get_ivars(child); 1753 cfg = &dinfo->cfg; 1754 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1755 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1756 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1757 cfg->progif); 1758 return (0); 1759 } 1760 1761 int 1762 pci_assign_interrupt_method(device_t dev, device_t child) 1763 { 1764 struct pci_devinfo *dinfo = device_get_ivars(child); 1765 pcicfgregs *cfg = &dinfo->cfg; 1766 1767 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1768 cfg->intpin)); 1769 } 1770 1771 static int 1772 pci_modevent(module_t mod, int what, void *arg) 1773 { 1774 static struct cdev *pci_cdev; 1775 1776 switch (what) { 1777 case MOD_LOAD: 1778 STAILQ_INIT(&pci_devq); 1779 pci_generation = 0; 1780 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1781 "pci"); 1782 pci_load_vendor_data(); 1783 break; 1784 1785 case MOD_UNLOAD: 1786 destroy_dev(pci_cdev); 1787 break; 1788 } 1789 1790 return (0); 1791 } 1792 1793 static void 1794 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1795 { 1796 int i; 1797 1798 /* 1799 * Only do header type 0 devices. Type 1 devices are bridges, 1800 * which we know need special treatment. Type 2 devices are 1801 * cardbus bridges which also require special treatment. 1802 * Other types are unknown, and we err on the side of safety 1803 * by ignoring them. 1804 */ 1805 if (dinfo->cfg.hdrtype != 0) 1806 return; 1807 1808 /* 1809 * Restore the device to full power mode. We must do this 1810 * before we restore the registers because moving from D3 to 1811 * D0 will cause the chip's BARs and some other registers to 1812 * be reset to some unknown power on reset values. Cut down 1813 * the noise on boot by doing nothing if we are already in 1814 * state D0. 1815 */ 1816 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1817 if (bootverbose) 1818 printf( 1819 "pci%d:%d:%d: Transition from D%d to D0\n", 1820 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1821 pci_get_powerstate(dev)); 1822 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1823 } 1824 for (i = 0; i < dinfo->cfg.nummaps; i++) 1825 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1826 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1827 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1828 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1829 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1830 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1831 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1832 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1833 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1834 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1835 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1836 } 1837 1838 static void 1839 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1840 { 1841 int i; 1842 uint32_t cls; 1843 int ps; 1844 1845 /* 1846 * Only do header type 0 devices. Type 1 devices are bridges, which 1847 * we know need special treatment. Type 2 devices are cardbus bridges 1848 * which also require special treatment. Other types are unknown, and 1849 * we err on the side of safety by ignoring them. Powering down 1850 * bridges should not be undertaken lightly. 1851 */ 1852 if (dinfo->cfg.hdrtype != 0) 1853 return; 1854 for (i = 0; i < dinfo->cfg.nummaps; i++) 1855 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1856 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1857 1858 /* 1859 * Some drivers apparently write to these registers w/o 1860 * updating our cahced copy. No harm happens if we update the 1861 * copy, so do so here so we can restore them. The COMMAND 1862 * register is modified by the bus w/o updating the cache. This 1863 * should represent the normally writable portion of the 'defined' 1864 * part of type 0 headers. In theory we also need to save/restore 1865 * the PCI capability structures we know about, but apart from power 1866 * we don't know any that are writable. 1867 */ 1868 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1869 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1870 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1871 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1872 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1873 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1874 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1875 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1876 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1877 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1878 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1879 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1880 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1881 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1882 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1883 1884 /* 1885 * don't set the state for display devices and for memory devices 1886 * since bad things happen. we should (a) have drivers that can easily 1887 * detach and (b) use generic drivers for these devices so that some 1888 * device actually attaches. We need to make sure that when we 1889 * implement (a) we don't power the device down on a reattach. 1890 */ 1891 cls = pci_get_class(dev); 1892 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY) { 1893 /* 1894 * PCI spec is clear that we can only go into D3 state from 1895 * D0 state. Transition from D[12] into D0 before going 1896 * to D3 state. 1897 */ 1898 ps = pci_get_powerstate(dev); 1899 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1900 if (bootverbose) 1901 printf( 1902 "pci%d:%d:%d: Transition from D%d to D0\n", 1903 dinfo->cfg.bus, dinfo->cfg.slot, 1904 dinfo->cfg.func, ps); 1905 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1906 } 1907 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1908 if (bootverbose) 1909 printf( 1910 "pci%d:%d:%d: Transition from D0 to D3\n", 1911 dinfo->cfg.bus, dinfo->cfg.slot, 1912 dinfo->cfg.func); 1913 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1914 } 1915 } 1916 }
Cache object: 03351ce8354edc0897327065a63b7363
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]