FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pci.c
1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: releng/6.0/sys/dev/pci/pci.c 151739 2005-10-27 16:44:06Z wpaul $");
31
32 #include "opt_bus.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
40 #include <sys/conf.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/types.h>
45
46 #include <vm/vm.h>
47 #include <vm/pmap.h>
48 #include <vm/vm_extern.h>
49
50 #include <sys/bus.h>
51 #include <machine/bus.h>
52 #include <sys/rman.h>
53 #include <machine/resource.h>
54
55 #include <sys/pciio.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pci_private.h>
59
60 #include "pcib_if.h"
61 #include "pci_if.h"
62
63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \
64 defined (__ia64__)
65 #include <contrib/dev/acpica/acpi.h>
66 #include "acpi_if.h"
67 #else
68 #define ACPI_PWR_FOR_SLEEP(x, y, z)
69 #endif
70
71 static uint32_t pci_mapbase(unsigned mapreg);
72 static int pci_maptype(unsigned mapreg);
73 static int pci_mapsize(unsigned testval);
74 static int pci_maprange(unsigned mapreg);
75 static void pci_fixancient(pcicfgregs *cfg);
76
77 static int pci_porten(device_t pcib, int b, int s, int f);
78 static int pci_memen(device_t pcib, int b, int s, int f);
79 static void pci_assign_interrupt(device_t bus, device_t dev,
80 int force_route);
81 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
82 int b, int s, int f, int reg,
83 struct resource_list *rl);
84 static void pci_add_resources(device_t pcib, device_t bus,
85 device_t dev);
86 static int pci_probe(device_t dev);
87 static int pci_attach(device_t dev);
88 static void pci_load_vendor_data(void);
89 static int pci_describe_parse_line(char **ptr, int *vendor,
90 int *device, char **desc);
91 static char *pci_describe_device(device_t dev);
92 static int pci_modevent(module_t mod, int what, void *arg);
93 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
94 pcicfgregs *cfg);
95 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
96
97 static device_method_t pci_methods[] = {
98 /* Device interface */
99 DEVMETHOD(device_probe, pci_probe),
100 DEVMETHOD(device_attach, pci_attach),
101 DEVMETHOD(device_detach, bus_generic_detach),
102 DEVMETHOD(device_shutdown, bus_generic_shutdown),
103 DEVMETHOD(device_suspend, pci_suspend),
104 DEVMETHOD(device_resume, pci_resume),
105
106 /* Bus interface */
107 DEVMETHOD(bus_print_child, pci_print_child),
108 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
109 DEVMETHOD(bus_read_ivar, pci_read_ivar),
110 DEVMETHOD(bus_write_ivar, pci_write_ivar),
111 DEVMETHOD(bus_driver_added, pci_driver_added),
112 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
113 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
114
115 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
116 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
117 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
118 DEVMETHOD(bus_delete_resource, pci_delete_resource),
119 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
120 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
121 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
122 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
123 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
124 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
125
126 /* PCI interface */
127 DEVMETHOD(pci_read_config, pci_read_config_method),
128 DEVMETHOD(pci_write_config, pci_write_config_method),
129 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
130 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
131 DEVMETHOD(pci_enable_io, pci_enable_io_method),
132 DEVMETHOD(pci_disable_io, pci_disable_io_method),
133 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
134 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
135 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
136
137 { 0, 0 }
138 };
139
140 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
141
142 devclass_t pci_devclass;
143 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
144 MODULE_VERSION(pci, 1);
145
146 static char *pci_vendordata;
147 static size_t pci_vendordata_size;
148
149
150 struct pci_quirk {
151 uint32_t devid; /* Vendor/device of the card */
152 int type;
153 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
154 int arg1;
155 int arg2;
156 };
157
158 struct pci_quirk pci_quirks[] = {
159 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
160 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
161 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
162 /* As does the Serverworks OSB4 (the SMBus mapping register) */
163 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
164
165 { 0 }
166 };
167
168 /* map register information */
169 #define PCI_MAPMEM 0x01 /* memory map */
170 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
171 #define PCI_MAPPORT 0x04 /* port map */
172
173 struct devlist pci_devq;
174 uint32_t pci_generation;
175 uint32_t pci_numdevs = 0;
176
177 /* sysctl vars */
178 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
179
180 static int pci_enable_io_modes = 1;
181 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
182 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
183 &pci_enable_io_modes, 1,
184 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
185 enable these bits correctly. We'd like to do this all the time, but there\n\
186 are some peripherals that this causes problems with.");
187
188 static int pci_do_power_nodriver = 0;
189 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
190 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
191 &pci_do_power_nodriver, 0,
192 "Place a function into D3 state when no driver attaches to it. 0 means\n\
193 disable. 1 means conservatively place devices into D3 state. 2 means\n\
194 agressively place devices into D3 state. 3 means put absolutely everything\n\
195 in D3 state.");
196
197 static int pci_do_power_resume = 1;
198 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
199 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
200 &pci_do_power_resume, 1,
201 "Transition from D3 -> D0 on resume.");
202
203 /* Find a device_t by bus/slot/function */
204
205 device_t
206 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
207 {
208 struct pci_devinfo *dinfo;
209
210 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
211 if ((dinfo->cfg.bus == bus) &&
212 (dinfo->cfg.slot == slot) &&
213 (dinfo->cfg.func == func)) {
214 return (dinfo->cfg.dev);
215 }
216 }
217
218 return (NULL);
219 }
220
221 /* Find a device_t by vendor/device ID */
222
223 device_t
224 pci_find_device(uint16_t vendor, uint16_t device)
225 {
226 struct pci_devinfo *dinfo;
227
228 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
229 if ((dinfo->cfg.vendor == vendor) &&
230 (dinfo->cfg.device == device)) {
231 return (dinfo->cfg.dev);
232 }
233 }
234
235 return (NULL);
236 }
237
238 /* return base address of memory or port map */
239
240 static uint32_t
241 pci_mapbase(unsigned mapreg)
242 {
243 int mask = 0x03;
244 if ((mapreg & 0x01) == 0)
245 mask = 0x0f;
246 return (mapreg & ~mask);
247 }
248
249 /* return map type of memory or port map */
250
251 static int
252 pci_maptype(unsigned mapreg)
253 {
254 static uint8_t maptype[0x10] = {
255 PCI_MAPMEM, PCI_MAPPORT,
256 PCI_MAPMEM, 0,
257 PCI_MAPMEM, PCI_MAPPORT,
258 0, 0,
259 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
260 PCI_MAPMEM|PCI_MAPMEMP, 0,
261 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
262 0, 0,
263 };
264
265 return maptype[mapreg & 0x0f];
266 }
267
268 /* return log2 of map size decoded for memory or port map */
269
270 static int
271 pci_mapsize(unsigned testval)
272 {
273 int ln2size;
274
275 testval = pci_mapbase(testval);
276 ln2size = 0;
277 if (testval != 0) {
278 while ((testval & 1) == 0)
279 {
280 ln2size++;
281 testval >>= 1;
282 }
283 }
284 return (ln2size);
285 }
286
287 /* return log2 of address range supported by map register */
288
289 static int
290 pci_maprange(unsigned mapreg)
291 {
292 int ln2range = 0;
293 switch (mapreg & 0x07) {
294 case 0x00:
295 case 0x01:
296 case 0x05:
297 ln2range = 32;
298 break;
299 case 0x02:
300 ln2range = 20;
301 break;
302 case 0x04:
303 ln2range = 64;
304 break;
305 }
306 return (ln2range);
307 }
308
309 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
310
311 static void
312 pci_fixancient(pcicfgregs *cfg)
313 {
314 if (cfg->hdrtype != 0)
315 return;
316
317 /* PCI to PCI bridges use header type 1 */
318 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
319 cfg->hdrtype = 1;
320 }
321
322 /* extract header type specific config data */
323
324 static void
325 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
326 {
327 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
328 switch (cfg->hdrtype) {
329 case 0:
330 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
331 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
332 cfg->nummaps = PCI_MAXMAPS_0;
333 break;
334 case 1:
335 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
336 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
337 cfg->nummaps = PCI_MAXMAPS_1;
338 break;
339 case 2:
340 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
341 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
342 cfg->nummaps = PCI_MAXMAPS_2;
343 break;
344 }
345 #undef REG
346 }
347
348 /* read configuration header into pcicfgregs structure */
349
350 struct pci_devinfo *
351 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
352 {
353 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
354 pcicfgregs *cfg = NULL;
355 struct pci_devinfo *devlist_entry;
356 struct devlist *devlist_head;
357
358 devlist_head = &pci_devq;
359
360 devlist_entry = NULL;
361
362 if (REG(PCIR_DEVVENDOR, 4) != -1) {
363 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
364 if (devlist_entry == NULL)
365 return (NULL);
366
367 cfg = &devlist_entry->cfg;
368
369 cfg->bus = b;
370 cfg->slot = s;
371 cfg->func = f;
372 cfg->vendor = REG(PCIR_VENDOR, 2);
373 cfg->device = REG(PCIR_DEVICE, 2);
374 cfg->cmdreg = REG(PCIR_COMMAND, 2);
375 cfg->statreg = REG(PCIR_STATUS, 2);
376 cfg->baseclass = REG(PCIR_CLASS, 1);
377 cfg->subclass = REG(PCIR_SUBCLASS, 1);
378 cfg->progif = REG(PCIR_PROGIF, 1);
379 cfg->revid = REG(PCIR_REVID, 1);
380 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
381 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
382 cfg->lattimer = REG(PCIR_LATTIMER, 1);
383 cfg->intpin = REG(PCIR_INTPIN, 1);
384 cfg->intline = REG(PCIR_INTLINE, 1);
385
386 cfg->mingnt = REG(PCIR_MINGNT, 1);
387 cfg->maxlat = REG(PCIR_MAXLAT, 1);
388
389 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
390 cfg->hdrtype &= ~PCIM_MFDEV;
391
392 pci_fixancient(cfg);
393 pci_hdrtypedata(pcib, b, s, f, cfg);
394
395 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
396 pci_read_extcap(pcib, cfg);
397
398 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
399
400 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
401 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
402 devlist_entry->conf.pc_sel.pc_func = cfg->func;
403 devlist_entry->conf.pc_hdr = cfg->hdrtype;
404
405 devlist_entry->conf.pc_subvendor = cfg->subvendor;
406 devlist_entry->conf.pc_subdevice = cfg->subdevice;
407 devlist_entry->conf.pc_vendor = cfg->vendor;
408 devlist_entry->conf.pc_device = cfg->device;
409
410 devlist_entry->conf.pc_class = cfg->baseclass;
411 devlist_entry->conf.pc_subclass = cfg->subclass;
412 devlist_entry->conf.pc_progif = cfg->progif;
413 devlist_entry->conf.pc_revid = cfg->revid;
414
415 pci_numdevs++;
416 pci_generation++;
417 }
418 return (devlist_entry);
419 #undef REG
420 }
421
422 static void
423 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
424 {
425 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
426 int ptr, nextptr, ptrptr;
427
428 switch (cfg->hdrtype & PCIM_HDRTYPE) {
429 case 0:
430 ptrptr = PCIR_CAP_PTR;
431 break;
432 case 2:
433 ptrptr = 0x14;
434 break;
435 default:
436 return; /* no extended capabilities support */
437 }
438 nextptr = REG(ptrptr, 1); /* sanity check? */
439
440 /*
441 * Read capability entries.
442 */
443 while (nextptr != 0) {
444 /* Sanity check */
445 if (nextptr > 255) {
446 printf("illegal PCI extended capability offset %d\n",
447 nextptr);
448 return;
449 }
450 /* Find the next entry */
451 ptr = nextptr;
452 nextptr = REG(ptr + 1, 1);
453
454 /* Process this entry */
455 switch (REG(ptr, 1)) {
456 case PCIY_PMG: /* PCI power management */
457 if (cfg->pp.pp_cap == 0) {
458 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
459 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
460 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
461 if ((nextptr - ptr) > PCIR_POWER_DATA)
462 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
463 }
464 break;
465 case PCIY_MSI: /* PCI MSI */
466 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
467 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT)
468 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT;
469 else
470 cfg->msi.msi_data = PCIR_MSI_DATA;
471 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
472 PCIM_MSICTRL_MMC_MASK)>>1);
473 default:
474 break;
475 }
476 }
477 #undef REG
478 }
479
480 /* free pcicfgregs structure and all depending data structures */
481
482 int
483 pci_freecfg(struct pci_devinfo *dinfo)
484 {
485 struct devlist *devlist_head;
486
487 devlist_head = &pci_devq;
488
489 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
490 free(dinfo, M_DEVBUF);
491
492 /* increment the generation count */
493 pci_generation++;
494
495 /* we're losing one device */
496 pci_numdevs--;
497 return (0);
498 }
499
500 /*
501 * PCI power manangement
502 */
503 int
504 pci_set_powerstate_method(device_t dev, device_t child, int state)
505 {
506 struct pci_devinfo *dinfo = device_get_ivars(child);
507 pcicfgregs *cfg = &dinfo->cfg;
508 uint16_t status;
509 int result, oldstate, highest, delay;
510
511 if (cfg->pp.pp_cap == 0)
512 return (EOPNOTSUPP);
513
514 /*
515 * Optimize a no state change request away. While it would be OK to
516 * write to the hardware in theory, some devices have shown odd
517 * behavior when going from D3 -> D3.
518 */
519 oldstate = pci_get_powerstate(child);
520 if (oldstate == state)
521 return (0);
522
523 /*
524 * The PCI power management specification states that after a state
525 * transition between PCI power states, system software must
526 * guarantee a minimal delay before the function accesses the device.
527 * Compute the worst case delay that we need to guarantee before we
528 * access the device. Many devices will be responsive much more
529 * quickly than this delay, but there are some that don't respond
530 * instantly to state changes. Transitions to/from D3 state require
531 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
532 * is done below with DELAY rather than a sleeper function because
533 * this function can be called from contexts where we cannot sleep.
534 */
535 highest = (oldstate > state) ? oldstate : state;
536 if (highest == PCI_POWERSTATE_D3)
537 delay = 10000;
538 else if (highest == PCI_POWERSTATE_D2)
539 delay = 200;
540 else
541 delay = 0;
542 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
543 & ~PCIM_PSTAT_DMASK;
544 result = 0;
545 switch (state) {
546 case PCI_POWERSTATE_D0:
547 status |= PCIM_PSTAT_D0;
548 break;
549 case PCI_POWERSTATE_D1:
550 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
551 return (EOPNOTSUPP);
552 status |= PCIM_PSTAT_D1;
553 break;
554 case PCI_POWERSTATE_D2:
555 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
556 return (EOPNOTSUPP);
557 status |= PCIM_PSTAT_D2;
558 break;
559 case PCI_POWERSTATE_D3:
560 status |= PCIM_PSTAT_D3;
561 break;
562 default:
563 return (EINVAL);
564 }
565
566 if (bootverbose)
567 printf(
568 "pci%d:%d:%d: Transition from D%d to D%d\n",
569 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func,
570 oldstate, state);
571
572 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
573 if (delay)
574 DELAY(delay);
575 return (0);
576 }
577
578 int
579 pci_get_powerstate_method(device_t dev, device_t child)
580 {
581 struct pci_devinfo *dinfo = device_get_ivars(child);
582 pcicfgregs *cfg = &dinfo->cfg;
583 uint16_t status;
584 int result;
585
586 if (cfg->pp.pp_cap != 0) {
587 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
588 switch (status & PCIM_PSTAT_DMASK) {
589 case PCIM_PSTAT_D0:
590 result = PCI_POWERSTATE_D0;
591 break;
592 case PCIM_PSTAT_D1:
593 result = PCI_POWERSTATE_D1;
594 break;
595 case PCIM_PSTAT_D2:
596 result = PCI_POWERSTATE_D2;
597 break;
598 case PCIM_PSTAT_D3:
599 result = PCI_POWERSTATE_D3;
600 break;
601 default:
602 result = PCI_POWERSTATE_UNKNOWN;
603 break;
604 }
605 } else {
606 /* No support, device is always at D0 */
607 result = PCI_POWERSTATE_D0;
608 }
609 return (result);
610 }
611
612 /*
613 * Some convenience functions for PCI device drivers.
614 */
615
616 static __inline void
617 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
618 {
619 uint16_t command;
620
621 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
622 command |= bit;
623 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
624 }
625
626 static __inline void
627 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
628 {
629 uint16_t command;
630
631 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
632 command &= ~bit;
633 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
634 }
635
636 int
637 pci_enable_busmaster_method(device_t dev, device_t child)
638 {
639 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
640 return (0);
641 }
642
643 int
644 pci_disable_busmaster_method(device_t dev, device_t child)
645 {
646 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
647 return (0);
648 }
649
650 int
651 pci_enable_io_method(device_t dev, device_t child, int space)
652 {
653 uint16_t command;
654 uint16_t bit;
655 char *error;
656
657 bit = 0;
658 error = NULL;
659
660 switch(space) {
661 case SYS_RES_IOPORT:
662 bit = PCIM_CMD_PORTEN;
663 error = "port";
664 break;
665 case SYS_RES_MEMORY:
666 bit = PCIM_CMD_MEMEN;
667 error = "memory";
668 break;
669 default:
670 return (EINVAL);
671 }
672 pci_set_command_bit(dev, child, bit);
673 /* Some devices seem to need a brief stall here, what do to? */
674 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
675 if (command & bit)
676 return (0);
677 device_printf(child, "failed to enable %s mapping!\n", error);
678 return (ENXIO);
679 }
680
681 int
682 pci_disable_io_method(device_t dev, device_t child, int space)
683 {
684 uint16_t command;
685 uint16_t bit;
686 char *error;
687
688 bit = 0;
689 error = NULL;
690
691 switch(space) {
692 case SYS_RES_IOPORT:
693 bit = PCIM_CMD_PORTEN;
694 error = "port";
695 break;
696 case SYS_RES_MEMORY:
697 bit = PCIM_CMD_MEMEN;
698 error = "memory";
699 break;
700 default:
701 return (EINVAL);
702 }
703 pci_clear_command_bit(dev, child, bit);
704 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
705 if (command & bit) {
706 device_printf(child, "failed to disable %s mapping!\n", error);
707 return (ENXIO);
708 }
709 return (0);
710 }
711
712 /*
713 * New style pci driver. Parent device is either a pci-host-bridge or a
714 * pci-pci-bridge. Both kinds are represented by instances of pcib.
715 */
716
717 void
718 pci_print_verbose(struct pci_devinfo *dinfo)
719 {
720 if (bootverbose) {
721 pcicfgregs *cfg = &dinfo->cfg;
722
723 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
724 cfg->vendor, cfg->device, cfg->revid);
725 printf("\tbus=%d, slot=%d, func=%d\n",
726 cfg->bus, cfg->slot, cfg->func);
727 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
728 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
729 cfg->mfdev);
730 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
731 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
732 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
733 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
734 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
735 if (cfg->intpin > 0)
736 printf("\tintpin=%c, irq=%d\n",
737 cfg->intpin +'a' -1, cfg->intline);
738 if (cfg->pp.pp_cap) {
739 uint16_t status;
740
741 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
742 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
743 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
744 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
745 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
746 status & PCIM_PSTAT_DMASK);
747 }
748 if (cfg->msi.msi_data) {
749 int ctrl;
750
751 ctrl = cfg->msi.msi_ctrl;
752 printf("\tMSI supports %d message%s%s%s\n",
753 cfg->msi.msi_msgnum,
754 (cfg->msi.msi_msgnum == 1) ? "" : "s",
755 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
756 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
757 }
758 }
759 }
760
761 static int
762 pci_porten(device_t pcib, int b, int s, int f)
763 {
764 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
765 & PCIM_CMD_PORTEN) != 0;
766 }
767
768 static int
769 pci_memen(device_t pcib, int b, int s, int f)
770 {
771 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
772 & PCIM_CMD_MEMEN) != 0;
773 }
774
775 /*
776 * Add a resource based on a pci map register. Return 1 if the map
777 * register is a 32bit map register or 2 if it is a 64bit register.
778 */
779 static int
780 pci_add_map(device_t pcib, device_t bus, device_t dev,
781 int b, int s, int f, int reg, struct resource_list *rl)
782 {
783 uint32_t map;
784 uint64_t base;
785 uint64_t start, end, count;
786 uint8_t ln2size;
787 uint8_t ln2range;
788 uint32_t testval;
789 uint16_t cmd;
790 int type;
791
792 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
793 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
794 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
795 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
796
797 if (pci_maptype(map) & PCI_MAPMEM)
798 type = SYS_RES_MEMORY;
799 else
800 type = SYS_RES_IOPORT;
801 ln2size = pci_mapsize(testval);
802 ln2range = pci_maprange(testval);
803 base = pci_mapbase(map);
804
805 /*
806 * For I/O registers, if bottom bit is set, and the next bit up
807 * isn't clear, we know we have a BAR that doesn't conform to the
808 * spec, so ignore it. Also, sanity check the size of the data
809 * areas to the type of memory involved. Memory must be at least
810 * 32 bytes in size, while I/O ranges must be at least 4.
811 */
812 if ((testval & 0x1) == 0x1 &&
813 (testval & 0x2) != 0)
814 return (1);
815 if ((type == SYS_RES_MEMORY && ln2size < 5) ||
816 (type == SYS_RES_IOPORT && ln2size < 2))
817 return (1);
818
819 if (ln2range == 64)
820 /* Read the other half of a 64bit map register */
821 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
822
823 if (bootverbose) {
824 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
825 reg, pci_maptype(map), ln2range,
826 (unsigned int) base, ln2size);
827 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
828 printf(", port disabled\n");
829 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
830 printf(", memory disabled\n");
831 else
832 printf(", enabled\n");
833 }
834
835 /*
836 * If base is 0, then we have problems. It is best to ignore
837 * such entries for the moment. These will be allocated later if
838 * the driver specifically requests them.
839 *
840 * Similarly treat maps whose values is the same as the test value
841 * read back. These maps have had all f's written to them by the
842 * BIOS in an attempt to disable the resources.
843 */
844 if (base == 0 || map == testval)
845 return 1;
846
847 /*
848 * This code theoretically does the right thing, but has
849 * undesirable side effects in some cases where peripherals
850 * respond oddly to having these bits enabled. Let the user
851 * be able to turn them off (since pci_enable_io_modes is 1 by
852 * default).
853 */
854 if (pci_enable_io_modes) {
855 /* Turn on resources that have been left off by a lazy BIOS */
856 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
857 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
858 cmd |= PCIM_CMD_PORTEN;
859 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
860 }
861 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
862 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
863 cmd |= PCIM_CMD_MEMEN;
864 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
865 }
866 } else {
867 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
868 return (1);
869 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
870 return (1);
871 }
872
873 start = base;
874 end = base + (1 << ln2size) - 1;
875 count = 1 << ln2size;
876 resource_list_add(rl, type, reg, start, end, count);
877
878 /*
879 * Not quite sure what to do on failure of allocating the resource
880 * since I can postulate several right answers.
881 */
882 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0);
883 return ((ln2range == 64) ? 2 : 1);
884 }
885
886 /*
887 * For ATA devices we need to decide early what addressing mode to use.
888 * Legacy demands that the primary and secondary ATA ports sits on the
889 * same addresses that old ISA hardware did. This dictates that we use
890 * those addresses and ignore the BAR's if we cannot set PCI native
891 * addressing mode.
892 */
893 static void
894 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
895 int s, int f, struct resource_list *rl)
896 {
897 int rid, type, progif;
898 #if 0
899 /* if this device supports PCI native addressing use it */
900 progif = pci_read_config(dev, PCIR_PROGIF, 1);
901 if ((progif & 0x8a) == 0x8a) {
902 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
903 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
904 printf("Trying ATA native PCI addressing mode\n");
905 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
906 }
907 }
908 #endif
909 progif = pci_read_config(dev, PCIR_PROGIF, 1);
910 type = SYS_RES_IOPORT;
911 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
912 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl);
913 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl);
914 }
915 else {
916 rid = PCIR_BAR(0);
917 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
918 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0);
919 rid = PCIR_BAR(1);
920 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
921 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0);
922 }
923 if (progif & PCIP_STORAGE_IDE_MODESEC) {
924 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl);
925 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl);
926 }
927 else {
928 rid = PCIR_BAR(2);
929 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
930 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0);
931 rid = PCIR_BAR(3);
932 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
933 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0);
934 }
935 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl);
936 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl);
937 }
938
939 static void
940 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
941 {
942 struct pci_devinfo *dinfo = device_get_ivars(dev);
943 pcicfgregs *cfg = &dinfo->cfg;
944 char tunable_name[64];
945 int irq;
946
947 /* Has to have an intpin to have an interrupt. */
948 if (cfg->intpin == 0)
949 return;
950
951 /* Let the user override the IRQ with a tunable. */
952 irq = PCI_INVALID_IRQ;
953 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq",
954 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
955 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
956 irq = PCI_INVALID_IRQ;
957
958 /*
959 * If we didn't get an IRQ via the tunable, then we either use the
960 * IRQ value in the intline register or we ask the bus to route an
961 * interrupt for us. If force_route is true, then we only use the
962 * value in the intline register if the bus was unable to assign an
963 * IRQ.
964 */
965 if (!PCI_INTERRUPT_VALID(irq)) {
966 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
967 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
968 if (!PCI_INTERRUPT_VALID(irq))
969 irq = cfg->intline;
970 }
971
972 /* If after all that we don't have an IRQ, just bail. */
973 if (!PCI_INTERRUPT_VALID(irq))
974 return;
975
976 /* Update the config register if it changed. */
977 if (irq != cfg->intline) {
978 cfg->intline = irq;
979 pci_write_config(dev, PCIR_INTLINE, irq, 1);
980 }
981
982 /* Add this IRQ as rid 0 interrupt resource. */
983 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
984 }
985
986 static void
987 pci_add_resources(device_t pcib, device_t bus, device_t dev)
988 {
989 struct pci_devinfo *dinfo = device_get_ivars(dev);
990 pcicfgregs *cfg = &dinfo->cfg;
991 struct resource_list *rl = &dinfo->resources;
992 struct pci_quirk *q;
993 int b, i, f, s;
994
995 b = cfg->bus;
996 s = cfg->slot;
997 f = cfg->func;
998
999 /* ATA devices needs special map treatment */
1000 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1001 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
1002 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV))
1003 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1004 else
1005 for (i = 0; i < cfg->nummaps;)
1006 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
1007 rl);
1008
1009 for (q = &pci_quirks[0]; q->devid; q++) {
1010 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1011 && q->type == PCI_QUIRK_MAP_REG)
1012 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl);
1013 }
1014
1015 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1016 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \
1017 defined(__arm__) || defined(__alpha__)
1018 /*
1019 * Try to re-route interrupts. Sometimes the BIOS or
1020 * firmware may leave bogus values in these registers.
1021 * If the re-route fails, then just stick with what we
1022 * have.
1023 */
1024 pci_assign_interrupt(bus, dev, 1);
1025 #else
1026 pci_assign_interrupt(bus, dev, 0);
1027 #endif
1028 }
1029 }
1030
1031 void
1032 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1033 {
1034 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1035 device_t pcib = device_get_parent(dev);
1036 struct pci_devinfo *dinfo;
1037 int maxslots;
1038 int s, f, pcifunchigh;
1039 uint8_t hdrtype;
1040
1041 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
1042 ("dinfo_size too small"));
1043 maxslots = PCIB_MAXSLOTS(pcib);
1044 for (s = 0; s <= maxslots; s++) {
1045 pcifunchigh = 0;
1046 f = 0;
1047 DELAY(1);
1048 hdrtype = REG(PCIR_HDRTYPE, 1);
1049 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1050 continue;
1051 if (hdrtype & PCIM_MFDEV)
1052 pcifunchigh = PCI_FUNCMAX;
1053 for (f = 0; f <= pcifunchigh; f++) {
1054 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1055 if (dinfo != NULL) {
1056 pci_add_child(dev, dinfo);
1057 }
1058 }
1059 }
1060 #undef REG
1061 }
1062
1063 void
1064 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1065 {
1066 device_t pcib;
1067
1068 pcib = device_get_parent(bus);
1069 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1070 device_set_ivars(dinfo->cfg.dev, dinfo);
1071 resource_list_init(&dinfo->resources);
1072 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
1073 pci_cfg_restore(dinfo->cfg.dev, dinfo);
1074 pci_print_verbose(dinfo);
1075 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1076 }
1077
1078 static int
1079 pci_probe(device_t dev)
1080 {
1081
1082 device_set_desc(dev, "PCI bus");
1083
1084 /* Allow other subclasses to override this driver. */
1085 return (-1000);
1086 }
1087
1088 static int
1089 pci_attach(device_t dev)
1090 {
1091 int busno;
1092
1093 /*
1094 * Since there can be multiple independantly numbered PCI
1095 * busses on some large alpha systems, we can't use the unit
1096 * number to decide what bus we are probing. We ask the parent
1097 * pcib what our bus number is.
1098 */
1099 busno = pcib_get_bus(dev);
1100 if (bootverbose)
1101 device_printf(dev, "physical bus=%d\n", busno);
1102
1103 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1104
1105 return (bus_generic_attach(dev));
1106 }
1107
1108 int
1109 pci_suspend(device_t dev)
1110 {
1111 int dstate, error, i, numdevs;
1112 device_t acpi_dev, child, *devlist;
1113 struct pci_devinfo *dinfo;
1114
1115 /*
1116 * Save the PCI configuration space for each child and set the
1117 * device in the appropriate power state for this sleep state.
1118 */
1119 acpi_dev = NULL;
1120 if (pci_do_power_resume)
1121 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
1122 device_get_children(dev, &devlist, &numdevs);
1123 for (i = 0; i < numdevs; i++) {
1124 child = devlist[i];
1125 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1126 pci_cfg_save(child, dinfo, 0);
1127 }
1128
1129 /* Suspend devices before potentially powering them down. */
1130 error = bus_generic_suspend(dev);
1131 if (error) {
1132 free(devlist, M_TEMP);
1133 return (error);
1134 }
1135
1136 /*
1137 * Always set the device to D3. If ACPI suggests a different
1138 * power state, use it instead. If ACPI is not present, the
1139 * firmware is responsible for managing device power. Skip
1140 * children who aren't attached since they are powered down
1141 * separately. Only manage type 0 devices for now.
1142 */
1143 for (i = 0; acpi_dev && i < numdevs; i++) {
1144 child = devlist[i];
1145 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1146 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
1147 dstate = PCI_POWERSTATE_D3;
1148 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
1149 pci_set_powerstate(child, dstate);
1150 }
1151 }
1152 free(devlist, M_TEMP);
1153 return (0);
1154 }
1155
1156 int
1157 pci_resume(device_t dev)
1158 {
1159 int i, numdevs;
1160 device_t acpi_dev, child, *devlist;
1161 struct pci_devinfo *dinfo;
1162
1163 /*
1164 * Set each child to D0 and restore its PCI configuration space.
1165 */
1166 acpi_dev = NULL;
1167 if (pci_do_power_resume)
1168 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
1169 device_get_children(dev, &devlist, &numdevs);
1170 for (i = 0; i < numdevs; i++) {
1171 /*
1172 * Notify ACPI we're going to D0 but ignore the result. If
1173 * ACPI is not present, the firmware is responsible for
1174 * managing device power. Only manage type 0 devices for now.
1175 */
1176 child = devlist[i];
1177 dinfo = (struct pci_devinfo *) device_get_ivars(child);
1178 if (acpi_dev && device_is_attached(child) &&
1179 dinfo->cfg.hdrtype == 0) {
1180 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
1181 pci_set_powerstate(child, PCI_POWERSTATE_D0);
1182 }
1183
1184 /* Now the device is powered up, restore its config space. */
1185 pci_cfg_restore(child, dinfo);
1186 }
1187 free(devlist, M_TEMP);
1188 return (bus_generic_resume(dev));
1189 }
1190
1191 static void
1192 pci_load_vendor_data(void)
1193 {
1194 caddr_t vendordata, info;
1195
1196 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
1197 info = preload_search_info(vendordata, MODINFO_ADDR);
1198 pci_vendordata = *(char **)info;
1199 info = preload_search_info(vendordata, MODINFO_SIZE);
1200 pci_vendordata_size = *(size_t *)info;
1201 /* terminate the database */
1202 pci_vendordata[pci_vendordata_size] = '\n';
1203 }
1204 }
1205
1206 void
1207 pci_driver_added(device_t dev, driver_t *driver)
1208 {
1209 int numdevs;
1210 device_t *devlist;
1211 device_t child;
1212 struct pci_devinfo *dinfo;
1213 int i;
1214
1215 if (bootverbose)
1216 device_printf(dev, "driver added\n");
1217 DEVICE_IDENTIFY(driver, dev);
1218 device_get_children(dev, &devlist, &numdevs);
1219 for (i = 0; i < numdevs; i++) {
1220 child = devlist[i];
1221 if (device_get_state(child) != DS_NOTPRESENT)
1222 continue;
1223 dinfo = device_get_ivars(child);
1224 pci_print_verbose(dinfo);
1225 if (bootverbose)
1226 printf("pci%d:%d:%d: reprobing on driver added\n",
1227 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
1228 pci_cfg_restore(child, dinfo);
1229 if (device_probe_and_attach(child) != 0)
1230 pci_cfg_save(child, dinfo, 1);
1231 }
1232 free(devlist, M_TEMP);
1233 }
1234
1235 int
1236 pci_print_child(device_t dev, device_t child)
1237 {
1238 struct pci_devinfo *dinfo;
1239 struct resource_list *rl;
1240 int retval = 0;
1241
1242 dinfo = device_get_ivars(child);
1243 rl = &dinfo->resources;
1244
1245 retval += bus_print_child_header(dev, child);
1246
1247 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
1248 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
1249 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
1250 if (device_get_flags(dev))
1251 retval += printf(" flags %#x", device_get_flags(dev));
1252
1253 retval += printf(" at device %d.%d", pci_get_slot(child),
1254 pci_get_function(child));
1255
1256 retval += bus_print_child_footer(dev, child);
1257
1258 return (retval);
1259 }
1260
1261 static struct
1262 {
1263 int class;
1264 int subclass;
1265 char *desc;
1266 } pci_nomatch_tab[] = {
1267 {PCIC_OLD, -1, "old"},
1268 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
1269 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
1270 {PCIC_STORAGE, -1, "mass storage"},
1271 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
1272 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
1273 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
1274 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
1275 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
1276 {PCIC_NETWORK, -1, "network"},
1277 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
1278 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
1279 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
1280 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
1281 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
1282 {PCIC_DISPLAY, -1, "display"},
1283 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
1284 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
1285 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
1286 {PCIC_MULTIMEDIA, -1, "multimedia"},
1287 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
1288 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
1289 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
1290 {PCIC_MEMORY, -1, "memory"},
1291 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
1292 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
1293 {PCIC_BRIDGE, -1, "bridge"},
1294 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
1295 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
1296 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
1297 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
1298 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
1299 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
1300 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
1301 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
1302 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
1303 {PCIC_SIMPLECOMM, -1, "simple comms"},
1304 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
1305 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
1306 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
1307 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
1308 {PCIC_BASEPERIPH, -1, "base peripheral"},
1309 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
1310 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
1311 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
1312 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
1313 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
1314 {PCIC_INPUTDEV, -1, "input device"},
1315 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
1316 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
1317 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
1318 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
1319 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
1320 {PCIC_DOCKING, -1, "docking station"},
1321 {PCIC_PROCESSOR, -1, "processor"},
1322 {PCIC_SERIALBUS, -1, "serial bus"},
1323 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
1324 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
1325 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
1326 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
1327 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
1328 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
1329 {PCIC_WIRELESS, -1, "wireless controller"},
1330 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
1331 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
1332 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
1333 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
1334 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
1335 {PCIC_SATCOM, -1, "satellite communication"},
1336 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
1337 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
1338 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
1339 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
1340 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
1341 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
1342 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"},
1343 {PCIC_DASP, -1, "dasp"},
1344 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
1345 {0, 0, NULL}
1346 };
1347
1348 void
1349 pci_probe_nomatch(device_t dev, device_t child)
1350 {
1351 int i;
1352 char *cp, *scp, *device;
1353
1354 /*
1355 * Look for a listing for this device in a loaded device database.
1356 */
1357 if ((device = pci_describe_device(child)) != NULL) {
1358 device_printf(dev, "<%s>", device);
1359 free(device, M_DEVBUF);
1360 } else {
1361 /*
1362 * Scan the class/subclass descriptions for a general
1363 * description.
1364 */
1365 cp = "unknown";
1366 scp = NULL;
1367 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
1368 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
1369 if (pci_nomatch_tab[i].subclass == -1) {
1370 cp = pci_nomatch_tab[i].desc;
1371 } else if (pci_nomatch_tab[i].subclass ==
1372 pci_get_subclass(child)) {
1373 scp = pci_nomatch_tab[i].desc;
1374 }
1375 }
1376 }
1377 device_printf(dev, "<%s%s%s>",
1378 cp ? cp : "",
1379 ((cp != NULL) && (scp != NULL)) ? ", " : "",
1380 scp ? scp : "");
1381 }
1382 printf(" at device %d.%d (no driver attached)\n",
1383 pci_get_slot(child), pci_get_function(child));
1384 if (pci_do_power_nodriver)
1385 pci_cfg_save(child,
1386 (struct pci_devinfo *) device_get_ivars(child), 1);
1387 return;
1388 }
1389
1390 /*
1391 * Parse the PCI device database, if loaded, and return a pointer to a
1392 * description of the device.
1393 *
1394 * The database is flat text formatted as follows:
1395 *
1396 * Any line not in a valid format is ignored.
1397 * Lines are terminated with newline '\n' characters.
1398 *
1399 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
1400 * the vendor name.
1401 *
1402 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
1403 * - devices cannot be listed without a corresponding VENDOR line.
1404 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
1405 * another TAB, then the device name.
1406 */
1407
1408 /*
1409 * Assuming (ptr) points to the beginning of a line in the database,
1410 * return the vendor or device and description of the next entry.
1411 * The value of (vendor) or (device) inappropriate for the entry type
1412 * is set to -1. Returns nonzero at the end of the database.
1413 *
1414 * Note that this is slightly unrobust in the face of corrupt data;
1415 * we attempt to safeguard against this by spamming the end of the
1416 * database with a newline when we initialise.
1417 */
1418 static int
1419 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
1420 {
1421 char *cp = *ptr;
1422 int left;
1423
1424 *device = -1;
1425 *vendor = -1;
1426 **desc = '\0';
1427 for (;;) {
1428 left = pci_vendordata_size - (cp - pci_vendordata);
1429 if (left <= 0) {
1430 *ptr = cp;
1431 return(1);
1432 }
1433
1434 /* vendor entry? */
1435 if (*cp != '\t' &&
1436 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
1437 break;
1438 /* device entry? */
1439 if (*cp == '\t' &&
1440 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
1441 break;
1442
1443 /* skip to next line */
1444 while (*cp != '\n' && left > 0) {
1445 cp++;
1446 left--;
1447 }
1448 if (*cp == '\n') {
1449 cp++;
1450 left--;
1451 }
1452 }
1453 /* skip to next line */
1454 while (*cp != '\n' && left > 0) {
1455 cp++;
1456 left--;
1457 }
1458 if (*cp == '\n' && left > 0)
1459 cp++;
1460 *ptr = cp;
1461 return(0);
1462 }
1463
1464 static char *
1465 pci_describe_device(device_t dev)
1466 {
1467 int vendor, device;
1468 char *desc, *vp, *dp, *line;
1469
1470 desc = vp = dp = NULL;
1471
1472 /*
1473 * If we have no vendor data, we can't do anything.
1474 */
1475 if (pci_vendordata == NULL)
1476 goto out;
1477
1478 /*
1479 * Scan the vendor data looking for this device
1480 */
1481 line = pci_vendordata;
1482 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
1483 goto out;
1484 for (;;) {
1485 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
1486 goto out;
1487 if (vendor == pci_get_vendor(dev))
1488 break;
1489 }
1490 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
1491 goto out;
1492 for (;;) {
1493 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
1494 *dp = 0;
1495 break;
1496 }
1497 if (vendor != -1) {
1498 *dp = 0;
1499 break;
1500 }
1501 if (device == pci_get_device(dev))
1502 break;
1503 }
1504 if (dp[0] == '\0')
1505 snprintf(dp, 80, "0x%x", pci_get_device(dev));
1506 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
1507 NULL)
1508 sprintf(desc, "%s, %s", vp, dp);
1509 out:
1510 if (vp != NULL)
1511 free(vp, M_DEVBUF);
1512 if (dp != NULL)
1513 free(dp, M_DEVBUF);
1514 return(desc);
1515 }
1516
1517 int
1518 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1519 {
1520 struct pci_devinfo *dinfo;
1521 pcicfgregs *cfg;
1522
1523 dinfo = device_get_ivars(child);
1524 cfg = &dinfo->cfg;
1525
1526 switch (which) {
1527 case PCI_IVAR_ETHADDR:
1528 /*
1529 * The generic accessor doesn't deal with failure, so
1530 * we set the return value, then return an error.
1531 */
1532 *((uint8_t **) result) = NULL;
1533 return (EINVAL);
1534 case PCI_IVAR_SUBVENDOR:
1535 *result = cfg->subvendor;
1536 break;
1537 case PCI_IVAR_SUBDEVICE:
1538 *result = cfg->subdevice;
1539 break;
1540 case PCI_IVAR_VENDOR:
1541 *result = cfg->vendor;
1542 break;
1543 case PCI_IVAR_DEVICE:
1544 *result = cfg->device;
1545 break;
1546 case PCI_IVAR_DEVID:
1547 *result = (cfg->device << 16) | cfg->vendor;
1548 break;
1549 case PCI_IVAR_CLASS:
1550 *result = cfg->baseclass;
1551 break;
1552 case PCI_IVAR_SUBCLASS:
1553 *result = cfg->subclass;
1554 break;
1555 case PCI_IVAR_PROGIF:
1556 *result = cfg->progif;
1557 break;
1558 case PCI_IVAR_REVID:
1559 *result = cfg->revid;
1560 break;
1561 case PCI_IVAR_INTPIN:
1562 *result = cfg->intpin;
1563 break;
1564 case PCI_IVAR_IRQ:
1565 *result = cfg->intline;
1566 break;
1567 case PCI_IVAR_BUS:
1568 *result = cfg->bus;
1569 break;
1570 case PCI_IVAR_SLOT:
1571 *result = cfg->slot;
1572 break;
1573 case PCI_IVAR_FUNCTION:
1574 *result = cfg->func;
1575 break;
1576 default:
1577 return (ENOENT);
1578 }
1579 return (0);
1580 }
1581
1582 int
1583 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1584 {
1585 struct pci_devinfo *dinfo;
1586
1587 dinfo = device_get_ivars(child);
1588
1589 switch (which) {
1590 case PCI_IVAR_INTPIN:
1591 dinfo->cfg.intpin = value;
1592 return (0);
1593 case PCI_IVAR_ETHADDR:
1594 case PCI_IVAR_SUBVENDOR:
1595 case PCI_IVAR_SUBDEVICE:
1596 case PCI_IVAR_VENDOR:
1597 case PCI_IVAR_DEVICE:
1598 case PCI_IVAR_DEVID:
1599 case PCI_IVAR_CLASS:
1600 case PCI_IVAR_SUBCLASS:
1601 case PCI_IVAR_PROGIF:
1602 case PCI_IVAR_REVID:
1603 case PCI_IVAR_IRQ:
1604 case PCI_IVAR_BUS:
1605 case PCI_IVAR_SLOT:
1606 case PCI_IVAR_FUNCTION:
1607 return (EINVAL); /* disallow for now */
1608
1609 default:
1610 return (ENOENT);
1611 }
1612 }
1613
1614
1615 #include "opt_ddb.h"
1616 #ifdef DDB
1617 #include <ddb/ddb.h>
1618 #include <sys/cons.h>
1619
1620 /*
1621 * List resources based on pci map registers, used for within ddb
1622 */
1623
1624 DB_SHOW_COMMAND(pciregs, db_pci_dump)
1625 {
1626 struct pci_devinfo *dinfo;
1627 struct devlist *devlist_head;
1628 struct pci_conf *p;
1629 const char *name;
1630 int i, error, none_count, quit;
1631
1632 none_count = 0;
1633 /* get the head of the device queue */
1634 devlist_head = &pci_devq;
1635
1636 /*
1637 * Go through the list of devices and print out devices
1638 */
1639 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
1640 for (error = 0, i = 0, quit = 0,
1641 dinfo = STAILQ_FIRST(devlist_head);
1642 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit;
1643 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1644
1645 /* Populate pd_name and pd_unit */
1646 name = NULL;
1647 if (dinfo->cfg.dev)
1648 name = device_get_name(dinfo->cfg.dev);
1649
1650 p = &dinfo->conf;
1651 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x "
1652 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
1653 (name && *name) ? name : "none",
1654 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
1655 none_count++,
1656 p->pc_sel.pc_bus, p->pc_sel.pc_dev,
1657 p->pc_sel.pc_func, (p->pc_class << 16) |
1658 (p->pc_subclass << 8) | p->pc_progif,
1659 (p->pc_subdevice << 16) | p->pc_subvendor,
1660 (p->pc_device << 16) | p->pc_vendor,
1661 p->pc_revid, p->pc_hdr);
1662 }
1663 }
1664 #endif /* DDB */
1665
1666 static struct resource *
1667 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
1668 u_long start, u_long end, u_long count, u_int flags)
1669 {
1670 struct pci_devinfo *dinfo = device_get_ivars(child);
1671 struct resource_list *rl = &dinfo->resources;
1672 struct resource_list_entry *rle;
1673 struct resource *res;
1674 uint32_t map, testval;
1675 int mapsize;
1676
1677 /*
1678 * Weed out the bogons, and figure out how large the BAR/map
1679 * is. Bars that read back 0 here are bogus and unimplemented.
1680 * Note: atapci in legacy mode are special and handled elsewhere
1681 * in the code. If you have a atapci device in legacy mode and
1682 * it fails here, that other code is broken.
1683 */
1684 res = NULL;
1685 map = pci_read_config(child, *rid, 4);
1686 pci_write_config(child, *rid, 0xffffffff, 4);
1687 testval = pci_read_config(child, *rid, 4);
1688 if (pci_mapbase(testval) == 0)
1689 goto out;
1690 if (pci_maptype(testval) & PCI_MAPMEM) {
1691 if (type != SYS_RES_MEMORY) {
1692 if (bootverbose)
1693 device_printf(child,
1694 "rid %#x is memory, requested %d\n",
1695 *rid, type);
1696 goto out;
1697 }
1698 } else {
1699 if (type != SYS_RES_IOPORT) {
1700 if (bootverbose)
1701 device_printf(child,
1702 "rid %#x is ioport, requested %d\n",
1703 *rid, type);
1704 goto out;
1705 }
1706 }
1707 /*
1708 * For real BARs, we need to override the size that
1709 * the driver requests, because that's what the BAR
1710 * actually uses and we would otherwise have a
1711 * situation where we might allocate the excess to
1712 * another driver, which won't work.
1713 */
1714 mapsize = pci_mapsize(testval);
1715 count = 1 << mapsize;
1716 if (RF_ALIGNMENT(flags) < mapsize)
1717 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
1718
1719 /*
1720 * Allocate enough resource, and then write back the
1721 * appropriate bar for that resource.
1722 */
1723 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1724 start, end, count, flags);
1725 if (res == NULL) {
1726 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n",
1727 count, *rid, type);
1728 goto out;
1729 }
1730 resource_list_add(rl, type, *rid, start, end, count);
1731 rle = resource_list_find(rl, type, *rid);
1732 if (rle == NULL)
1733 panic("pci_alloc_map: unexpectedly can't find resource.");
1734 rle->res = res;
1735 if (bootverbose)
1736 device_printf(child,
1737 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
1738 count, *rid, type, rman_get_start(res));
1739 map = rman_get_start(res);
1740 out:;
1741 pci_write_config(child, *rid, map, 4);
1742 return (res);
1743 }
1744
1745
1746 struct resource *
1747 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1748 u_long start, u_long end, u_long count, u_int flags)
1749 {
1750 struct pci_devinfo *dinfo = device_get_ivars(child);
1751 struct resource_list *rl = &dinfo->resources;
1752 struct resource_list_entry *rle;
1753 pcicfgregs *cfg = &dinfo->cfg;
1754
1755 /*
1756 * Perform lazy resource allocation
1757 */
1758 if (device_get_parent(child) == dev) {
1759 switch (type) {
1760 case SYS_RES_IRQ:
1761 /*
1762 * If the child device doesn't have an
1763 * interrupt routed and is deserving of an
1764 * interrupt, try to assign it one.
1765 */
1766 if (!PCI_INTERRUPT_VALID(cfg->intline) &&
1767 (cfg->intpin != 0))
1768 pci_assign_interrupt(dev, child, 0);
1769 break;
1770 case SYS_RES_IOPORT:
1771 case SYS_RES_MEMORY:
1772 if (*rid < PCIR_BAR(cfg->nummaps)) {
1773 /*
1774 * Enable the I/O mode. We should
1775 * also be assigning resources too
1776 * when none are present. The
1777 * resource_list_alloc kind of sorta does
1778 * this...
1779 */
1780 if (PCI_ENABLE_IO(dev, child, type))
1781 return (NULL);
1782 }
1783 rle = resource_list_find(rl, type, *rid);
1784 if (rle == NULL)
1785 return (pci_alloc_map(dev, child, type, rid,
1786 start, end, count, flags));
1787 break;
1788 }
1789 /*
1790 * If we've already allocated the resource, then
1791 * return it now. But first we may need to activate
1792 * it, since we don't allocate the resource as active
1793 * above. Normally this would be done down in the
1794 * nexus, but since we short-circuit that path we have
1795 * to do its job here. Not sure if we should free the
1796 * resource if it fails to activate.
1797 */
1798 rle = resource_list_find(rl, type, *rid);
1799 if (rle != NULL && rle->res != NULL) {
1800 if (bootverbose)
1801 device_printf(child,
1802 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
1803 rman_get_size(rle->res), *rid, type,
1804 rman_get_start(rle->res));
1805 if ((flags & RF_ACTIVE) &&
1806 bus_generic_activate_resource(dev, child, type,
1807 *rid, rle->res) != 0)
1808 return NULL;
1809 return (rle->res);
1810 }
1811 }
1812 return (resource_list_alloc(rl, dev, child, type, rid,
1813 start, end, count, flags));
1814 }
1815
1816 void
1817 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1818 {
1819 struct pci_devinfo *dinfo;
1820 struct resource_list *rl;
1821 struct resource_list_entry *rle;
1822
1823 if (device_get_parent(child) != dev)
1824 return;
1825
1826 dinfo = device_get_ivars(child);
1827 rl = &dinfo->resources;
1828 rle = resource_list_find(rl, type, rid);
1829 if (rle) {
1830 if (rle->res) {
1831 if (rman_get_device(rle->res) != dev ||
1832 rman_get_flags(rle->res) & RF_ACTIVE) {
1833 device_printf(dev, "delete_resource: "
1834 "Resource still owned by child, oops. "
1835 "(type=%d, rid=%d, addr=%lx)\n",
1836 rle->type, rle->rid,
1837 rman_get_start(rle->res));
1838 return;
1839 }
1840 bus_release_resource(dev, type, rid, rle->res);
1841 }
1842 resource_list_delete(rl, type, rid);
1843 }
1844 /*
1845 * Why do we turn off the PCI configuration BAR when we delete a
1846 * resource? -- imp
1847 */
1848 pci_write_config(child, rid, 0, 4);
1849 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
1850 }
1851
1852 struct resource_list *
1853 pci_get_resource_list (device_t dev, device_t child)
1854 {
1855 struct pci_devinfo *dinfo = device_get_ivars(child);
1856
1857 return (&dinfo->resources);
1858 }
1859
1860 uint32_t
1861 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1862 {
1863 struct pci_devinfo *dinfo = device_get_ivars(child);
1864 pcicfgregs *cfg = &dinfo->cfg;
1865
1866 return (PCIB_READ_CONFIG(device_get_parent(dev),
1867 cfg->bus, cfg->slot, cfg->func, reg, width));
1868 }
1869
1870 void
1871 pci_write_config_method(device_t dev, device_t child, int reg,
1872 uint32_t val, int width)
1873 {
1874 struct pci_devinfo *dinfo = device_get_ivars(child);
1875 pcicfgregs *cfg = &dinfo->cfg;
1876
1877 PCIB_WRITE_CONFIG(device_get_parent(dev),
1878 cfg->bus, cfg->slot, cfg->func, reg, val, width);
1879 }
1880
1881 int
1882 pci_child_location_str_method(device_t dev, device_t child, char *buf,
1883 size_t buflen)
1884 {
1885
1886 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1887 pci_get_function(child));
1888 return (0);
1889 }
1890
1891 int
1892 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1893 size_t buflen)
1894 {
1895 struct pci_devinfo *dinfo;
1896 pcicfgregs *cfg;
1897
1898 dinfo = device_get_ivars(child);
1899 cfg = &dinfo->cfg;
1900 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
1901 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
1902 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
1903 cfg->progif);
1904 return (0);
1905 }
1906
1907 int
1908 pci_assign_interrupt_method(device_t dev, device_t child)
1909 {
1910 struct pci_devinfo *dinfo = device_get_ivars(child);
1911 pcicfgregs *cfg = &dinfo->cfg;
1912
1913 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
1914 cfg->intpin));
1915 }
1916
1917 static int
1918 pci_modevent(module_t mod, int what, void *arg)
1919 {
1920 static struct cdev *pci_cdev;
1921
1922 switch (what) {
1923 case MOD_LOAD:
1924 STAILQ_INIT(&pci_devq);
1925 pci_generation = 0;
1926 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
1927 "pci");
1928 pci_load_vendor_data();
1929 break;
1930
1931 case MOD_UNLOAD:
1932 destroy_dev(pci_cdev);
1933 break;
1934 }
1935
1936 return (0);
1937 }
1938
1939 void
1940 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
1941 {
1942 int i;
1943
1944 /*
1945 * Only do header type 0 devices. Type 1 devices are bridges,
1946 * which we know need special treatment. Type 2 devices are
1947 * cardbus bridges which also require special treatment.
1948 * Other types are unknown, and we err on the side of safety
1949 * by ignoring them.
1950 */
1951 if (dinfo->cfg.hdrtype != 0)
1952 return;
1953
1954 /*
1955 * Restore the device to full power mode. We must do this
1956 * before we restore the registers because moving from D3 to
1957 * D0 will cause the chip's BARs and some other registers to
1958 * be reset to some unknown power on reset values. Cut down
1959 * the noise on boot by doing nothing if we are already in
1960 * state D0.
1961 */
1962 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1963 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1964 }
1965 for (i = 0; i < dinfo->cfg.nummaps; i++)
1966 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
1967 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
1968 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
1969 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
1970 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
1971 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
1972 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
1973 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
1974 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
1975 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
1976 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
1977 }
1978
1979 void
1980 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
1981 {
1982 int i;
1983 uint32_t cls;
1984 int ps;
1985
1986 /*
1987 * Only do header type 0 devices. Type 1 devices are bridges, which
1988 * we know need special treatment. Type 2 devices are cardbus bridges
1989 * which also require special treatment. Other types are unknown, and
1990 * we err on the side of safety by ignoring them. Powering down
1991 * bridges should not be undertaken lightly.
1992 */
1993 if (dinfo->cfg.hdrtype != 0)
1994 return;
1995 for (i = 0; i < dinfo->cfg.nummaps; i++)
1996 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
1997 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
1998
1999 /*
2000 * Some drivers apparently write to these registers w/o updating our
2001 * cached copy. No harm happens if we update the copy, so do so here
2002 * so we can restore them. The COMMAND register is modified by the
2003 * bus w/o updating the cache. This should represent the normally
2004 * writable portion of the 'defined' part of type 0 headers. In
2005 * theory we also need to save/restore the PCI capability structures
2006 * we know about, but apart from power we don't know any that are
2007 * writable.
2008 */
2009 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2010 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2011 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
2012 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
2013 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
2014 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
2015 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
2016 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
2017 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
2018 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2019 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2020 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
2021 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
2022 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
2023 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
2024
2025 /*
2026 * don't set the state for display devices, base peripherals and
2027 * memory devices since bad things happen when they are powered down.
2028 * We should (a) have drivers that can easily detach and (b) use
2029 * generic drivers for these devices so that some device actually
2030 * attaches. We need to make sure that when we implement (a) we don't
2031 * power the device down on a reattach.
2032 */
2033 cls = pci_get_class(dev);
2034 if (!setstate)
2035 return;
2036 switch (pci_do_power_nodriver)
2037 {
2038 case 0: /* NO powerdown at all */
2039 return;
2040 case 1: /* Conservative about what to power down */
2041 if (cls == PCIC_STORAGE)
2042 return;
2043 /*FALLTHROUGH*/
2044 case 2: /* Agressive about what to power down */
2045 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
2046 cls == PCIC_BASEPERIPH)
2047 return;
2048 /*FALLTHROUGH*/
2049 case 3: /* Power down everything */
2050 break;
2051 }
2052 /*
2053 * PCI spec says we can only go into D3 state from D0 state.
2054 * Transition from D[12] into D0 before going to D3 state.
2055 */
2056 ps = pci_get_powerstate(dev);
2057 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
2058 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2059 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
2060 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
2061 }
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