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sys/dev/pci/pci.c
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1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD: releng/6.2/sys/dev/pci/pci.c 162634 2006-09-25 15:49:51Z marcel $"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include "acpi_if.h" 67 #else 68 #define ACPI_PWR_FOR_SLEEP(x, y, z) 69 #endif 70 71 static uint32_t pci_mapbase(unsigned mapreg); 72 static int pci_maptype(unsigned mapreg); 73 static int pci_mapsize(unsigned testval); 74 static int pci_maprange(unsigned mapreg); 75 static void pci_fixancient(pcicfgregs *cfg); 76 77 static int pci_porten(device_t pcib, int b, int s, int f); 78 static int pci_memen(device_t pcib, int b, int s, int f); 79 static void pci_assign_interrupt(device_t bus, device_t dev, 80 int force_route); 81 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 82 int b, int s, int f, int reg, 83 struct resource_list *rl, int force, int prefetch); 84 static int pci_probe(device_t dev); 85 static int pci_attach(device_t dev); 86 static void pci_load_vendor_data(void); 87 static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89 static char *pci_describe_device(device_t dev); 90 static int pci_modevent(module_t mod, int what, void *arg); 91 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95 static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_detach, bus_generic_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, pci_suspend), 102 DEVMETHOD(device_resume, pci_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_print_child, pci_print_child), 106 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 107 DEVMETHOD(bus_read_ivar, pci_read_ivar), 108 DEVMETHOD(bus_write_ivar, pci_write_ivar), 109 DEVMETHOD(bus_driver_added, pci_driver_added), 110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 112 113 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 114 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 115 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 116 DEVMETHOD(bus_delete_resource, pci_delete_resource), 117 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 118 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 119 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 120 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 121 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 122 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 123 124 /* PCI interface */ 125 DEVMETHOD(pci_read_config, pci_read_config_method), 126 DEVMETHOD(pci_write_config, pci_write_config_method), 127 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 128 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 129 DEVMETHOD(pci_enable_io, pci_enable_io_method), 130 DEVMETHOD(pci_disable_io, pci_disable_io_method), 131 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 132 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 133 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 134 135 { 0, 0 } 136 }; 137 138 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 139 140 devclass_t pci_devclass; 141 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 142 MODULE_VERSION(pci, 1); 143 144 static char *pci_vendordata; 145 static size_t pci_vendordata_size; 146 147 148 struct pci_quirk { 149 uint32_t devid; /* Vendor/device of the card */ 150 int type; 151 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 152 int arg1; 153 int arg2; 154 }; 155 156 struct pci_quirk pci_quirks[] = { 157 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 158 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 161 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 163 { 0 } 164 }; 165 166 /* map register information */ 167 #define PCI_MAPMEM 0x01 /* memory map */ 168 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 169 #define PCI_MAPPORT 0x04 /* port map */ 170 171 struct devlist pci_devq; 172 uint32_t pci_generation; 173 uint32_t pci_numdevs = 0; 174 175 /* sysctl vars */ 176 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 177 178 static int pci_enable_io_modes = 1; 179 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 180 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 181 &pci_enable_io_modes, 1, 182 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 183 enable these bits correctly. We'd like to do this all the time, but there\n\ 184 are some peripherals that this causes problems with."); 185 186 static int pci_do_power_nodriver = 0; 187 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 188 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 189 &pci_do_power_nodriver, 0, 190 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 191 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 192 agressively place devices into D3 state. 3 means put absolutely everything\n\ 193 in D3 state."); 194 195 static int pci_do_power_resume = 1; 196 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 197 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 198 &pci_do_power_resume, 1, 199 "Transition from D3 -> D0 on resume."); 200 201 /* Find a device_t by bus/slot/function */ 202 203 device_t 204 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 205 { 206 struct pci_devinfo *dinfo; 207 208 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 209 if ((dinfo->cfg.bus == bus) && 210 (dinfo->cfg.slot == slot) && 211 (dinfo->cfg.func == func)) { 212 return (dinfo->cfg.dev); 213 } 214 } 215 216 return (NULL); 217 } 218 219 /* Find a device_t by vendor/device ID */ 220 221 device_t 222 pci_find_device(uint16_t vendor, uint16_t device) 223 { 224 struct pci_devinfo *dinfo; 225 226 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 227 if ((dinfo->cfg.vendor == vendor) && 228 (dinfo->cfg.device == device)) { 229 return (dinfo->cfg.dev); 230 } 231 } 232 233 return (NULL); 234 } 235 236 /* return base address of memory or port map */ 237 238 static uint32_t 239 pci_mapbase(unsigned mapreg) 240 { 241 int mask = 0x03; 242 if ((mapreg & 0x01) == 0) 243 mask = 0x0f; 244 return (mapreg & ~mask); 245 } 246 247 /* return map type of memory or port map */ 248 249 static int 250 pci_maptype(unsigned mapreg) 251 { 252 static uint8_t maptype[0x10] = { 253 PCI_MAPMEM, PCI_MAPPORT, 254 PCI_MAPMEM, 0, 255 PCI_MAPMEM, PCI_MAPPORT, 256 0, 0, 257 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 258 PCI_MAPMEM|PCI_MAPMEMP, 0, 259 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 260 0, 0, 261 }; 262 263 return maptype[mapreg & 0x0f]; 264 } 265 266 /* return log2 of map size decoded for memory or port map */ 267 268 static int 269 pci_mapsize(unsigned testval) 270 { 271 int ln2size; 272 273 testval = pci_mapbase(testval); 274 ln2size = 0; 275 if (testval != 0) { 276 while ((testval & 1) == 0) 277 { 278 ln2size++; 279 testval >>= 1; 280 } 281 } 282 return (ln2size); 283 } 284 285 /* return log2 of address range supported by map register */ 286 287 static int 288 pci_maprange(unsigned mapreg) 289 { 290 int ln2range = 0; 291 switch (mapreg & 0x07) { 292 case 0x00: 293 case 0x01: 294 case 0x05: 295 ln2range = 32; 296 break; 297 case 0x02: 298 ln2range = 20; 299 break; 300 case 0x04: 301 ln2range = 64; 302 break; 303 } 304 return (ln2range); 305 } 306 307 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 308 309 static void 310 pci_fixancient(pcicfgregs *cfg) 311 { 312 if (cfg->hdrtype != 0) 313 return; 314 315 /* PCI to PCI bridges use header type 1 */ 316 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 317 cfg->hdrtype = 1; 318 } 319 320 /* extract header type specific config data */ 321 322 static void 323 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 324 { 325 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 326 switch (cfg->hdrtype) { 327 case 0: 328 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 329 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 330 cfg->nummaps = PCI_MAXMAPS_0; 331 break; 332 case 1: 333 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 334 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 335 cfg->nummaps = PCI_MAXMAPS_1; 336 break; 337 case 2: 338 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 339 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 340 cfg->nummaps = PCI_MAXMAPS_2; 341 break; 342 } 343 #undef REG 344 } 345 346 /* read configuration header into pcicfgregs structure */ 347 348 struct pci_devinfo * 349 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 350 { 351 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 352 pcicfgregs *cfg = NULL; 353 struct pci_devinfo *devlist_entry; 354 struct devlist *devlist_head; 355 356 devlist_head = &pci_devq; 357 358 devlist_entry = NULL; 359 360 if (REG(PCIR_DEVVENDOR, 4) != -1) { 361 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 362 if (devlist_entry == NULL) 363 return (NULL); 364 365 cfg = &devlist_entry->cfg; 366 367 cfg->bus = b; 368 cfg->slot = s; 369 cfg->func = f; 370 cfg->vendor = REG(PCIR_VENDOR, 2); 371 cfg->device = REG(PCIR_DEVICE, 2); 372 cfg->cmdreg = REG(PCIR_COMMAND, 2); 373 cfg->statreg = REG(PCIR_STATUS, 2); 374 cfg->baseclass = REG(PCIR_CLASS, 1); 375 cfg->subclass = REG(PCIR_SUBCLASS, 1); 376 cfg->progif = REG(PCIR_PROGIF, 1); 377 cfg->revid = REG(PCIR_REVID, 1); 378 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 379 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 380 cfg->lattimer = REG(PCIR_LATTIMER, 1); 381 cfg->intpin = REG(PCIR_INTPIN, 1); 382 cfg->intline = REG(PCIR_INTLINE, 1); 383 384 cfg->mingnt = REG(PCIR_MINGNT, 1); 385 cfg->maxlat = REG(PCIR_MAXLAT, 1); 386 387 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 388 cfg->hdrtype &= ~PCIM_MFDEV; 389 390 pci_fixancient(cfg); 391 pci_hdrtypedata(pcib, b, s, f, cfg); 392 393 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 394 pci_read_extcap(pcib, cfg); 395 396 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 397 398 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 399 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 400 devlist_entry->conf.pc_sel.pc_func = cfg->func; 401 devlist_entry->conf.pc_hdr = cfg->hdrtype; 402 403 devlist_entry->conf.pc_subvendor = cfg->subvendor; 404 devlist_entry->conf.pc_subdevice = cfg->subdevice; 405 devlist_entry->conf.pc_vendor = cfg->vendor; 406 devlist_entry->conf.pc_device = cfg->device; 407 408 devlist_entry->conf.pc_class = cfg->baseclass; 409 devlist_entry->conf.pc_subclass = cfg->subclass; 410 devlist_entry->conf.pc_progif = cfg->progif; 411 devlist_entry->conf.pc_revid = cfg->revid; 412 413 pci_numdevs++; 414 pci_generation++; 415 } 416 return (devlist_entry); 417 #undef REG 418 } 419 420 static void 421 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 422 { 423 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 424 int ptr, nextptr, ptrptr; 425 426 switch (cfg->hdrtype & PCIM_HDRTYPE) { 427 case 0: 428 ptrptr = PCIR_CAP_PTR; 429 break; 430 case 2: 431 ptrptr = 0x14; 432 break; 433 default: 434 return; /* no extended capabilities support */ 435 } 436 nextptr = REG(ptrptr, 1); /* sanity check? */ 437 438 /* 439 * Read capability entries. 440 */ 441 while (nextptr != 0) { 442 /* Sanity check */ 443 if (nextptr > 255) { 444 printf("illegal PCI extended capability offset %d\n", 445 nextptr); 446 return; 447 } 448 /* Find the next entry */ 449 ptr = nextptr; 450 nextptr = REG(ptr + 1, 1); 451 452 /* Process this entry */ 453 switch (REG(ptr, 1)) { 454 case PCIY_PMG: /* PCI power management */ 455 if (cfg->pp.pp_cap == 0) { 456 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 457 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 458 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 459 if ((nextptr - ptr) > PCIR_POWER_DATA) 460 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 461 } 462 break; 463 case PCIY_MSI: /* PCI MSI */ 464 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 465 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 466 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 467 else 468 cfg->msi.msi_data = PCIR_MSI_DATA; 469 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 470 PCIM_MSICTRL_MMC_MASK)>>1); 471 default: 472 break; 473 } 474 } 475 #undef REG 476 } 477 478 /* free pcicfgregs structure and all depending data structures */ 479 480 int 481 pci_freecfg(struct pci_devinfo *dinfo) 482 { 483 struct devlist *devlist_head; 484 485 devlist_head = &pci_devq; 486 487 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 488 free(dinfo, M_DEVBUF); 489 490 /* increment the generation count */ 491 pci_generation++; 492 493 /* we're losing one device */ 494 pci_numdevs--; 495 return (0); 496 } 497 498 /* 499 * PCI power manangement 500 */ 501 int 502 pci_set_powerstate_method(device_t dev, device_t child, int state) 503 { 504 struct pci_devinfo *dinfo = device_get_ivars(child); 505 pcicfgregs *cfg = &dinfo->cfg; 506 uint16_t status; 507 int result, oldstate, highest, delay; 508 509 if (cfg->pp.pp_cap == 0) 510 return (EOPNOTSUPP); 511 512 /* 513 * Optimize a no state change request away. While it would be OK to 514 * write to the hardware in theory, some devices have shown odd 515 * behavior when going from D3 -> D3. 516 */ 517 oldstate = pci_get_powerstate(child); 518 if (oldstate == state) 519 return (0); 520 521 /* 522 * The PCI power management specification states that after a state 523 * transition between PCI power states, system software must 524 * guarantee a minimal delay before the function accesses the device. 525 * Compute the worst case delay that we need to guarantee before we 526 * access the device. Many devices will be responsive much more 527 * quickly than this delay, but there are some that don't respond 528 * instantly to state changes. Transitions to/from D3 state require 529 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 530 * is done below with DELAY rather than a sleeper function because 531 * this function can be called from contexts where we cannot sleep. 532 */ 533 highest = (oldstate > state) ? oldstate : state; 534 if (highest == PCI_POWERSTATE_D3) 535 delay = 10000; 536 else if (highest == PCI_POWERSTATE_D2) 537 delay = 200; 538 else 539 delay = 0; 540 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 541 & ~PCIM_PSTAT_DMASK; 542 result = 0; 543 switch (state) { 544 case PCI_POWERSTATE_D0: 545 status |= PCIM_PSTAT_D0; 546 break; 547 case PCI_POWERSTATE_D1: 548 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 549 return (EOPNOTSUPP); 550 status |= PCIM_PSTAT_D1; 551 break; 552 case PCI_POWERSTATE_D2: 553 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 554 return (EOPNOTSUPP); 555 status |= PCIM_PSTAT_D2; 556 break; 557 case PCI_POWERSTATE_D3: 558 status |= PCIM_PSTAT_D3; 559 break; 560 default: 561 return (EINVAL); 562 } 563 564 if (bootverbose) 565 printf( 566 "pci%d:%d:%d: Transition from D%d to D%d\n", 567 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 568 oldstate, state); 569 570 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 571 if (delay) 572 DELAY(delay); 573 return (0); 574 } 575 576 int 577 pci_get_powerstate_method(device_t dev, device_t child) 578 { 579 struct pci_devinfo *dinfo = device_get_ivars(child); 580 pcicfgregs *cfg = &dinfo->cfg; 581 uint16_t status; 582 int result; 583 584 if (cfg->pp.pp_cap != 0) { 585 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 586 switch (status & PCIM_PSTAT_DMASK) { 587 case PCIM_PSTAT_D0: 588 result = PCI_POWERSTATE_D0; 589 break; 590 case PCIM_PSTAT_D1: 591 result = PCI_POWERSTATE_D1; 592 break; 593 case PCIM_PSTAT_D2: 594 result = PCI_POWERSTATE_D2; 595 break; 596 case PCIM_PSTAT_D3: 597 result = PCI_POWERSTATE_D3; 598 break; 599 default: 600 result = PCI_POWERSTATE_UNKNOWN; 601 break; 602 } 603 } else { 604 /* No support, device is always at D0 */ 605 result = PCI_POWERSTATE_D0; 606 } 607 return (result); 608 } 609 610 /* 611 * Some convenience functions for PCI device drivers. 612 */ 613 614 static __inline void 615 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 616 { 617 uint16_t command; 618 619 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 620 command |= bit; 621 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 622 } 623 624 static __inline void 625 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 626 { 627 uint16_t command; 628 629 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 630 command &= ~bit; 631 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 632 } 633 634 int 635 pci_enable_busmaster_method(device_t dev, device_t child) 636 { 637 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 638 return (0); 639 } 640 641 int 642 pci_disable_busmaster_method(device_t dev, device_t child) 643 { 644 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 645 return (0); 646 } 647 648 int 649 pci_enable_io_method(device_t dev, device_t child, int space) 650 { 651 uint16_t command; 652 uint16_t bit; 653 char *error; 654 655 bit = 0; 656 error = NULL; 657 658 switch(space) { 659 case SYS_RES_IOPORT: 660 bit = PCIM_CMD_PORTEN; 661 error = "port"; 662 break; 663 case SYS_RES_MEMORY: 664 bit = PCIM_CMD_MEMEN; 665 error = "memory"; 666 break; 667 default: 668 return (EINVAL); 669 } 670 pci_set_command_bit(dev, child, bit); 671 /* Some devices seem to need a brief stall here, what do to? */ 672 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 673 if (command & bit) 674 return (0); 675 device_printf(child, "failed to enable %s mapping!\n", error); 676 return (ENXIO); 677 } 678 679 int 680 pci_disable_io_method(device_t dev, device_t child, int space) 681 { 682 uint16_t command; 683 uint16_t bit; 684 char *error; 685 686 bit = 0; 687 error = NULL; 688 689 switch(space) { 690 case SYS_RES_IOPORT: 691 bit = PCIM_CMD_PORTEN; 692 error = "port"; 693 break; 694 case SYS_RES_MEMORY: 695 bit = PCIM_CMD_MEMEN; 696 error = "memory"; 697 break; 698 default: 699 return (EINVAL); 700 } 701 pci_clear_command_bit(dev, child, bit); 702 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 703 if (command & bit) { 704 device_printf(child, "failed to disable %s mapping!\n", error); 705 return (ENXIO); 706 } 707 return (0); 708 } 709 710 /* 711 * New style pci driver. Parent device is either a pci-host-bridge or a 712 * pci-pci-bridge. Both kinds are represented by instances of pcib. 713 */ 714 715 void 716 pci_print_verbose(struct pci_devinfo *dinfo) 717 { 718 if (bootverbose) { 719 pcicfgregs *cfg = &dinfo->cfg; 720 721 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 722 cfg->vendor, cfg->device, cfg->revid); 723 printf("\tbus=%d, slot=%d, func=%d\n", 724 cfg->bus, cfg->slot, cfg->func); 725 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 726 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 727 cfg->mfdev); 728 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 729 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 730 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 731 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 732 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 733 if (cfg->intpin > 0) 734 printf("\tintpin=%c, irq=%d\n", 735 cfg->intpin +'a' -1, cfg->intline); 736 if (cfg->pp.pp_cap) { 737 uint16_t status; 738 739 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 740 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 741 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 742 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 743 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 744 status & PCIM_PSTAT_DMASK); 745 } 746 if (cfg->msi.msi_data) { 747 int ctrl; 748 749 ctrl = cfg->msi.msi_ctrl; 750 printf("\tMSI supports %d message%s%s%s\n", 751 cfg->msi.msi_msgnum, 752 (cfg->msi.msi_msgnum == 1) ? "" : "s", 753 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 754 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 755 } 756 } 757 } 758 759 static int 760 pci_porten(device_t pcib, int b, int s, int f) 761 { 762 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 763 & PCIM_CMD_PORTEN) != 0; 764 } 765 766 static int 767 pci_memen(device_t pcib, int b, int s, int f) 768 { 769 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 770 & PCIM_CMD_MEMEN) != 0; 771 } 772 773 /* 774 * Add a resource based on a pci map register. Return 1 if the map 775 * register is a 32bit map register or 2 if it is a 64bit register. 776 */ 777 static int 778 pci_add_map(device_t pcib, device_t bus, device_t dev, 779 int b, int s, int f, int reg, struct resource_list *rl, int force, 780 int prefetch) 781 { 782 uint32_t map; 783 uint64_t base; 784 uint64_t start, end, count; 785 uint8_t ln2size; 786 uint8_t ln2range; 787 uint32_t testval; 788 uint16_t cmd; 789 int type; 790 int barlen; 791 struct resource *res; 792 793 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 794 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 795 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 796 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 797 798 if (pci_maptype(map) & PCI_MAPMEM) 799 type = SYS_RES_MEMORY; 800 else 801 type = SYS_RES_IOPORT; 802 ln2size = pci_mapsize(testval); 803 ln2range = pci_maprange(testval); 804 base = pci_mapbase(map); 805 barlen = ln2range == 64 ? 2 : 1; 806 807 /* 808 * For I/O registers, if bottom bit is set, and the next bit up 809 * isn't clear, we know we have a BAR that doesn't conform to the 810 * spec, so ignore it. Also, sanity check the size of the data 811 * areas to the type of memory involved. Memory must be at least 812 * 16 bytes in size, while I/O ranges must be at least 4. 813 */ 814 if ((testval & 0x1) == 0x1 && 815 (testval & 0x2) != 0) 816 return (barlen); 817 if ((type == SYS_RES_MEMORY && ln2size < 4) || 818 (type == SYS_RES_IOPORT && ln2size < 2)) 819 return (barlen); 820 821 if (ln2range == 64) 822 /* Read the other half of a 64bit map register */ 823 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 824 825 if (bootverbose) { 826 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 827 reg, pci_maptype(map), ln2range, 828 (unsigned int) base, ln2size); 829 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 830 printf(", port disabled\n"); 831 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 832 printf(", memory disabled\n"); 833 else 834 printf(", enabled\n"); 835 } 836 837 /* 838 * If base is 0, then we have problems. It is best to ignore 839 * such entries for the moment. These will be allocated later if 840 * the driver specifically requests them. However, some 841 * removable busses look better when all resources are allocated, 842 * so allow '' to be overriden. 843 * 844 * Similarly treat maps whose values is the same as the test value 845 * read back. These maps have had all f's written to them by the 846 * BIOS in an attempt to disable the resources. 847 */ 848 if (!force && (base == 0 || map == testval)) 849 return (barlen); 850 851 /* 852 * This code theoretically does the right thing, but has 853 * undesirable side effects in some cases where peripherals 854 * respond oddly to having these bits enabled. Let the user 855 * be able to turn them off (since pci_enable_io_modes is 1 by 856 * default). 857 */ 858 if (pci_enable_io_modes) { 859 /* Turn on resources that have been left off by a lazy BIOS */ 860 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 861 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 862 cmd |= PCIM_CMD_PORTEN; 863 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 864 } 865 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 866 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 867 cmd |= PCIM_CMD_MEMEN; 868 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 869 } 870 } else { 871 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 872 return (barlen); 873 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 874 return (barlen); 875 } 876 877 count = 1 << ln2size; 878 if (base == 0 || base == pci_mapbase(testval)) { 879 start = 0; /* Let the parent deside */ 880 end = ~0ULL; 881 } else { 882 start = base; 883 end = base + (1 << ln2size) - 1; 884 } 885 resource_list_add(rl, type, reg, start, end, count); 886 887 /* 888 * Not quite sure what to do on failure of allocating the resource 889 * since I can postulate several right answers. 890 */ 891 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 892 prefetch ? RF_PREFETCHABLE : 0); 893 if (res != NULL) 894 pci_write_config(dev, reg, rman_get_start(res), 4); 895 return (barlen); 896 } 897 898 /* 899 * For ATA devices we need to decide early what addressing mode to use. 900 * Legacy demands that the primary and secondary ATA ports sits on the 901 * same addresses that old ISA hardware did. This dictates that we use 902 * those addresses and ignore the BAR's if we cannot set PCI native 903 * addressing mode. 904 */ 905 static void 906 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 907 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 908 { 909 int rid, type, progif; 910 #if 0 911 /* if this device supports PCI native addressing use it */ 912 progif = pci_read_config(dev, PCIR_PROGIF, 1); 913 if ((progif & 0x8a) == 0x8a) { 914 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 915 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 916 printf("Trying ATA native PCI addressing mode\n"); 917 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 918 } 919 } 920 #endif 921 progif = pci_read_config(dev, PCIR_PROGIF, 1); 922 type = SYS_RES_IOPORT; 923 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 924 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 925 prefetchmask & (1 << 0)); 926 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 927 prefetchmask & (1 << 1)); 928 } else { 929 rid = PCIR_BAR(0); 930 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 931 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 932 0); 933 rid = PCIR_BAR(1); 934 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 935 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 936 0); 937 } 938 if (progif & PCIP_STORAGE_IDE_MODESEC) { 939 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 940 prefetchmask & (1 << 2)); 941 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 942 prefetchmask & (1 << 3)); 943 } else { 944 rid = PCIR_BAR(2); 945 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 946 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 947 0); 948 rid = PCIR_BAR(3); 949 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 950 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 951 0); 952 } 953 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 954 prefetchmask & (1 << 4)); 955 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 956 prefetchmask & (1 << 5)); 957 } 958 959 static void 960 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 961 { 962 struct pci_devinfo *dinfo = device_get_ivars(dev); 963 pcicfgregs *cfg = &dinfo->cfg; 964 char tunable_name[64]; 965 int irq; 966 967 /* Has to have an intpin to have an interrupt. */ 968 if (cfg->intpin == 0) 969 return; 970 971 /* Let the user override the IRQ with a tunable. */ 972 irq = PCI_INVALID_IRQ; 973 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 974 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 975 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 976 irq = PCI_INVALID_IRQ; 977 978 /* 979 * If we didn't get an IRQ via the tunable, then we either use the 980 * IRQ value in the intline register or we ask the bus to route an 981 * interrupt for us. If force_route is true, then we only use the 982 * value in the intline register if the bus was unable to assign an 983 * IRQ. 984 */ 985 if (!PCI_INTERRUPT_VALID(irq)) { 986 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 987 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 988 if (!PCI_INTERRUPT_VALID(irq)) 989 irq = cfg->intline; 990 } 991 992 /* If after all that we don't have an IRQ, just bail. */ 993 if (!PCI_INTERRUPT_VALID(irq)) 994 return; 995 996 /* Update the config register if it changed. */ 997 if (irq != cfg->intline) { 998 cfg->intline = irq; 999 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1000 } 1001 1002 /* Add this IRQ as rid 0 interrupt resource. */ 1003 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1004 } 1005 1006 void 1007 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1008 { 1009 device_t pcib; 1010 struct pci_devinfo *dinfo = device_get_ivars(dev); 1011 pcicfgregs *cfg = &dinfo->cfg; 1012 struct resource_list *rl = &dinfo->resources; 1013 struct pci_quirk *q; 1014 int b, i, f, s; 1015 1016 pcib = device_get_parent(bus); 1017 1018 b = cfg->bus; 1019 s = cfg->slot; 1020 f = cfg->func; 1021 1022 /* ATA devices needs special map treatment */ 1023 if ((pci_get_class(dev) == PCIC_STORAGE) && 1024 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1025 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1026 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1027 else 1028 for (i = 0; i < cfg->nummaps;) 1029 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1030 rl, force, prefetchmask & (1 << i)); 1031 1032 /* 1033 * Add additional, quirked resources. 1034 */ 1035 for (q = &pci_quirks[0]; q->devid; q++) { 1036 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1037 && q->type == PCI_QUIRK_MAP_REG) 1038 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1039 force, 0); 1040 } 1041 1042 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1043 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 1044 defined(__arm__) || defined(__alpha__) 1045 /* 1046 * Try to re-route interrupts. Sometimes the BIOS or 1047 * firmware may leave bogus values in these registers. 1048 * If the re-route fails, then just stick with what we 1049 * have. 1050 */ 1051 pci_assign_interrupt(bus, dev, 1); 1052 #else 1053 pci_assign_interrupt(bus, dev, 0); 1054 #endif 1055 } 1056 } 1057 1058 void 1059 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1060 { 1061 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1062 device_t pcib = device_get_parent(dev); 1063 struct pci_devinfo *dinfo; 1064 int maxslots; 1065 int s, f, pcifunchigh; 1066 uint8_t hdrtype; 1067 1068 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1069 ("dinfo_size too small")); 1070 maxslots = PCIB_MAXSLOTS(pcib); 1071 for (s = 0; s <= maxslots; s++) { 1072 pcifunchigh = 0; 1073 f = 0; 1074 DELAY(1); 1075 hdrtype = REG(PCIR_HDRTYPE, 1); 1076 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1077 continue; 1078 if (hdrtype & PCIM_MFDEV) 1079 pcifunchigh = PCI_FUNCMAX; 1080 for (f = 0; f <= pcifunchigh; f++) { 1081 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1082 if (dinfo != NULL) { 1083 pci_add_child(dev, dinfo); 1084 } 1085 } 1086 } 1087 #undef REG 1088 } 1089 1090 void 1091 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1092 { 1093 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1094 device_set_ivars(dinfo->cfg.dev, dinfo); 1095 resource_list_init(&dinfo->resources); 1096 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1097 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1098 pci_print_verbose(dinfo); 1099 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 1100 } 1101 1102 static int 1103 pci_probe(device_t dev) 1104 { 1105 1106 device_set_desc(dev, "PCI bus"); 1107 1108 /* Allow other subclasses to override this driver. */ 1109 return (-1000); 1110 } 1111 1112 static int 1113 pci_attach(device_t dev) 1114 { 1115 int busno; 1116 1117 /* 1118 * Since there can be multiple independantly numbered PCI 1119 * busses on some large alpha systems, we can't use the unit 1120 * number to decide what bus we are probing. We ask the parent 1121 * pcib what our bus number is. 1122 */ 1123 busno = pcib_get_bus(dev); 1124 if (bootverbose) 1125 device_printf(dev, "physical bus=%d\n", busno); 1126 1127 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1128 1129 return (bus_generic_attach(dev)); 1130 } 1131 1132 int 1133 pci_suspend(device_t dev) 1134 { 1135 int dstate, error, i, numdevs; 1136 device_t acpi_dev, child, *devlist; 1137 struct pci_devinfo *dinfo; 1138 1139 /* 1140 * Save the PCI configuration space for each child and set the 1141 * device in the appropriate power state for this sleep state. 1142 */ 1143 acpi_dev = NULL; 1144 if (pci_do_power_resume) 1145 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1146 device_get_children(dev, &devlist, &numdevs); 1147 for (i = 0; i < numdevs; i++) { 1148 child = devlist[i]; 1149 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1150 pci_cfg_save(child, dinfo, 0); 1151 } 1152 1153 /* Suspend devices before potentially powering them down. */ 1154 error = bus_generic_suspend(dev); 1155 if (error) { 1156 free(devlist, M_TEMP); 1157 return (error); 1158 } 1159 1160 /* 1161 * Always set the device to D3. If ACPI suggests a different 1162 * power state, use it instead. If ACPI is not present, the 1163 * firmware is responsible for managing device power. Skip 1164 * children who aren't attached since they are powered down 1165 * separately. Only manage type 0 devices for now. 1166 */ 1167 for (i = 0; acpi_dev && i < numdevs; i++) { 1168 child = devlist[i]; 1169 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1170 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1171 dstate = PCI_POWERSTATE_D3; 1172 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1173 pci_set_powerstate(child, dstate); 1174 } 1175 } 1176 free(devlist, M_TEMP); 1177 return (0); 1178 } 1179 1180 int 1181 pci_resume(device_t dev) 1182 { 1183 int i, numdevs; 1184 device_t acpi_dev, child, *devlist; 1185 struct pci_devinfo *dinfo; 1186 1187 /* 1188 * Set each child to D0 and restore its PCI configuration space. 1189 */ 1190 acpi_dev = NULL; 1191 if (pci_do_power_resume) 1192 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1193 device_get_children(dev, &devlist, &numdevs); 1194 for (i = 0; i < numdevs; i++) { 1195 /* 1196 * Notify ACPI we're going to D0 but ignore the result. If 1197 * ACPI is not present, the firmware is responsible for 1198 * managing device power. Only manage type 0 devices for now. 1199 */ 1200 child = devlist[i]; 1201 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1202 if (acpi_dev && device_is_attached(child) && 1203 dinfo->cfg.hdrtype == 0) { 1204 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1205 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1206 } 1207 1208 /* Now the device is powered up, restore its config space. */ 1209 pci_cfg_restore(child, dinfo); 1210 } 1211 free(devlist, M_TEMP); 1212 return (bus_generic_resume(dev)); 1213 } 1214 1215 static void 1216 pci_load_vendor_data(void) 1217 { 1218 caddr_t vendordata, info; 1219 1220 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1221 info = preload_search_info(vendordata, MODINFO_ADDR); 1222 pci_vendordata = *(char **)info; 1223 info = preload_search_info(vendordata, MODINFO_SIZE); 1224 pci_vendordata_size = *(size_t *)info; 1225 /* terminate the database */ 1226 pci_vendordata[pci_vendordata_size] = '\n'; 1227 } 1228 } 1229 1230 void 1231 pci_driver_added(device_t dev, driver_t *driver) 1232 { 1233 int numdevs; 1234 device_t *devlist; 1235 device_t child; 1236 struct pci_devinfo *dinfo; 1237 int i; 1238 1239 if (bootverbose) 1240 device_printf(dev, "driver added\n"); 1241 DEVICE_IDENTIFY(driver, dev); 1242 device_get_children(dev, &devlist, &numdevs); 1243 for (i = 0; i < numdevs; i++) { 1244 child = devlist[i]; 1245 if (device_get_state(child) != DS_NOTPRESENT) 1246 continue; 1247 dinfo = device_get_ivars(child); 1248 pci_print_verbose(dinfo); 1249 if (bootverbose) 1250 printf("pci%d:%d:%d: reprobing on driver added\n", 1251 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1252 pci_cfg_restore(child, dinfo); 1253 if (device_probe_and_attach(child) != 0) 1254 pci_cfg_save(child, dinfo, 1); 1255 } 1256 free(devlist, M_TEMP); 1257 } 1258 1259 int 1260 pci_print_child(device_t dev, device_t child) 1261 { 1262 struct pci_devinfo *dinfo; 1263 struct resource_list *rl; 1264 int retval = 0; 1265 1266 dinfo = device_get_ivars(child); 1267 rl = &dinfo->resources; 1268 1269 retval += bus_print_child_header(dev, child); 1270 1271 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1272 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1273 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1274 if (device_get_flags(dev)) 1275 retval += printf(" flags %#x", device_get_flags(dev)); 1276 1277 retval += printf(" at device %d.%d", pci_get_slot(child), 1278 pci_get_function(child)); 1279 1280 retval += bus_print_child_footer(dev, child); 1281 1282 return (retval); 1283 } 1284 1285 static struct 1286 { 1287 int class; 1288 int subclass; 1289 char *desc; 1290 } pci_nomatch_tab[] = { 1291 {PCIC_OLD, -1, "old"}, 1292 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1293 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1294 {PCIC_STORAGE, -1, "mass storage"}, 1295 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1296 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1297 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1298 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1299 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1300 {PCIC_NETWORK, -1, "network"}, 1301 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1302 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1303 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1304 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1305 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1306 {PCIC_DISPLAY, -1, "display"}, 1307 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1308 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1309 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1310 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1311 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1312 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1313 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1314 {PCIC_MEMORY, -1, "memory"}, 1315 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1316 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1317 {PCIC_BRIDGE, -1, "bridge"}, 1318 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1319 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1320 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1321 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1322 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1323 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1324 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1325 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1326 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1327 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1328 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1329 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1330 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1331 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1332 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1333 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1334 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1335 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1336 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1337 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1338 {PCIC_INPUTDEV, -1, "input device"}, 1339 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1340 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1341 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1342 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1343 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1344 {PCIC_DOCKING, -1, "docking station"}, 1345 {PCIC_PROCESSOR, -1, "processor"}, 1346 {PCIC_SERIALBUS, -1, "serial bus"}, 1347 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1348 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1349 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1350 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1351 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1352 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1353 {PCIC_WIRELESS, -1, "wireless controller"}, 1354 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1355 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1356 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1357 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1358 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1359 {PCIC_SATCOM, -1, "satellite communication"}, 1360 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1361 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1362 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1363 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1364 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1365 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1366 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 1367 {PCIC_DASP, -1, "dasp"}, 1368 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1369 {0, 0, NULL} 1370 }; 1371 1372 void 1373 pci_probe_nomatch(device_t dev, device_t child) 1374 { 1375 int i; 1376 char *cp, *scp, *device; 1377 1378 /* 1379 * Look for a listing for this device in a loaded device database. 1380 */ 1381 if ((device = pci_describe_device(child)) != NULL) { 1382 device_printf(dev, "<%s>", device); 1383 free(device, M_DEVBUF); 1384 } else { 1385 /* 1386 * Scan the class/subclass descriptions for a general 1387 * description. 1388 */ 1389 cp = "unknown"; 1390 scp = NULL; 1391 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1392 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1393 if (pci_nomatch_tab[i].subclass == -1) { 1394 cp = pci_nomatch_tab[i].desc; 1395 } else if (pci_nomatch_tab[i].subclass == 1396 pci_get_subclass(child)) { 1397 scp = pci_nomatch_tab[i].desc; 1398 } 1399 } 1400 } 1401 device_printf(dev, "<%s%s%s>", 1402 cp ? cp : "", 1403 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1404 scp ? scp : ""); 1405 } 1406 printf(" at device %d.%d (no driver attached)\n", 1407 pci_get_slot(child), pci_get_function(child)); 1408 if (pci_do_power_nodriver) 1409 pci_cfg_save(child, 1410 (struct pci_devinfo *) device_get_ivars(child), 1); 1411 return; 1412 } 1413 1414 /* 1415 * Parse the PCI device database, if loaded, and return a pointer to a 1416 * description of the device. 1417 * 1418 * The database is flat text formatted as follows: 1419 * 1420 * Any line not in a valid format is ignored. 1421 * Lines are terminated with newline '\n' characters. 1422 * 1423 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1424 * the vendor name. 1425 * 1426 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1427 * - devices cannot be listed without a corresponding VENDOR line. 1428 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1429 * another TAB, then the device name. 1430 */ 1431 1432 /* 1433 * Assuming (ptr) points to the beginning of a line in the database, 1434 * return the vendor or device and description of the next entry. 1435 * The value of (vendor) or (device) inappropriate for the entry type 1436 * is set to -1. Returns nonzero at the end of the database. 1437 * 1438 * Note that this is slightly unrobust in the face of corrupt data; 1439 * we attempt to safeguard against this by spamming the end of the 1440 * database with a newline when we initialise. 1441 */ 1442 static int 1443 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1444 { 1445 char *cp = *ptr; 1446 int left; 1447 1448 *device = -1; 1449 *vendor = -1; 1450 **desc = '\0'; 1451 for (;;) { 1452 left = pci_vendordata_size - (cp - pci_vendordata); 1453 if (left <= 0) { 1454 *ptr = cp; 1455 return(1); 1456 } 1457 1458 /* vendor entry? */ 1459 if (*cp != '\t' && 1460 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1461 break; 1462 /* device entry? */ 1463 if (*cp == '\t' && 1464 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1465 break; 1466 1467 /* skip to next line */ 1468 while (*cp != '\n' && left > 0) { 1469 cp++; 1470 left--; 1471 } 1472 if (*cp == '\n') { 1473 cp++; 1474 left--; 1475 } 1476 } 1477 /* skip to next line */ 1478 while (*cp != '\n' && left > 0) { 1479 cp++; 1480 left--; 1481 } 1482 if (*cp == '\n' && left > 0) 1483 cp++; 1484 *ptr = cp; 1485 return(0); 1486 } 1487 1488 static char * 1489 pci_describe_device(device_t dev) 1490 { 1491 int vendor, device; 1492 char *desc, *vp, *dp, *line; 1493 1494 desc = vp = dp = NULL; 1495 1496 /* 1497 * If we have no vendor data, we can't do anything. 1498 */ 1499 if (pci_vendordata == NULL) 1500 goto out; 1501 1502 /* 1503 * Scan the vendor data looking for this device 1504 */ 1505 line = pci_vendordata; 1506 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1507 goto out; 1508 for (;;) { 1509 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1510 goto out; 1511 if (vendor == pci_get_vendor(dev)) 1512 break; 1513 } 1514 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1515 goto out; 1516 for (;;) { 1517 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1518 *dp = 0; 1519 break; 1520 } 1521 if (vendor != -1) { 1522 *dp = 0; 1523 break; 1524 } 1525 if (device == pci_get_device(dev)) 1526 break; 1527 } 1528 if (dp[0] == '\0') 1529 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1530 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1531 NULL) 1532 sprintf(desc, "%s, %s", vp, dp); 1533 out: 1534 if (vp != NULL) 1535 free(vp, M_DEVBUF); 1536 if (dp != NULL) 1537 free(dp, M_DEVBUF); 1538 return(desc); 1539 } 1540 1541 int 1542 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1543 { 1544 struct pci_devinfo *dinfo; 1545 pcicfgregs *cfg; 1546 1547 dinfo = device_get_ivars(child); 1548 cfg = &dinfo->cfg; 1549 1550 switch (which) { 1551 case PCI_IVAR_ETHADDR: 1552 /* 1553 * The generic accessor doesn't deal with failure, so 1554 * we set the return value, then return an error. 1555 */ 1556 *((uint8_t **) result) = NULL; 1557 return (EINVAL); 1558 case PCI_IVAR_SUBVENDOR: 1559 *result = cfg->subvendor; 1560 break; 1561 case PCI_IVAR_SUBDEVICE: 1562 *result = cfg->subdevice; 1563 break; 1564 case PCI_IVAR_VENDOR: 1565 *result = cfg->vendor; 1566 break; 1567 case PCI_IVAR_DEVICE: 1568 *result = cfg->device; 1569 break; 1570 case PCI_IVAR_DEVID: 1571 *result = (cfg->device << 16) | cfg->vendor; 1572 break; 1573 case PCI_IVAR_CLASS: 1574 *result = cfg->baseclass; 1575 break; 1576 case PCI_IVAR_SUBCLASS: 1577 *result = cfg->subclass; 1578 break; 1579 case PCI_IVAR_PROGIF: 1580 *result = cfg->progif; 1581 break; 1582 case PCI_IVAR_REVID: 1583 *result = cfg->revid; 1584 break; 1585 case PCI_IVAR_INTPIN: 1586 *result = cfg->intpin; 1587 break; 1588 case PCI_IVAR_IRQ: 1589 *result = cfg->intline; 1590 break; 1591 case PCI_IVAR_BUS: 1592 *result = cfg->bus; 1593 break; 1594 case PCI_IVAR_SLOT: 1595 *result = cfg->slot; 1596 break; 1597 case PCI_IVAR_FUNCTION: 1598 *result = cfg->func; 1599 break; 1600 case PCI_IVAR_CMDREG: 1601 *result = cfg->cmdreg; 1602 break; 1603 case PCI_IVAR_CACHELNSZ: 1604 *result = cfg->cachelnsz; 1605 break; 1606 case PCI_IVAR_MINGNT: 1607 *result = cfg->mingnt; 1608 break; 1609 case PCI_IVAR_MAXLAT: 1610 *result = cfg->maxlat; 1611 break; 1612 case PCI_IVAR_LATTIMER: 1613 *result = cfg->lattimer; 1614 break; 1615 default: 1616 return (ENOENT); 1617 } 1618 return (0); 1619 } 1620 1621 int 1622 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1623 { 1624 struct pci_devinfo *dinfo; 1625 1626 dinfo = device_get_ivars(child); 1627 1628 switch (which) { 1629 case PCI_IVAR_INTPIN: 1630 dinfo->cfg.intpin = value; 1631 return (0); 1632 case PCI_IVAR_ETHADDR: 1633 case PCI_IVAR_SUBVENDOR: 1634 case PCI_IVAR_SUBDEVICE: 1635 case PCI_IVAR_VENDOR: 1636 case PCI_IVAR_DEVICE: 1637 case PCI_IVAR_DEVID: 1638 case PCI_IVAR_CLASS: 1639 case PCI_IVAR_SUBCLASS: 1640 case PCI_IVAR_PROGIF: 1641 case PCI_IVAR_REVID: 1642 case PCI_IVAR_IRQ: 1643 case PCI_IVAR_BUS: 1644 case PCI_IVAR_SLOT: 1645 case PCI_IVAR_FUNCTION: 1646 return (EINVAL); /* disallow for now */ 1647 1648 default: 1649 return (ENOENT); 1650 } 1651 } 1652 1653 1654 #include "opt_ddb.h" 1655 #ifdef DDB 1656 #include <ddb/ddb.h> 1657 #include <sys/cons.h> 1658 1659 /* 1660 * List resources based on pci map registers, used for within ddb 1661 */ 1662 1663 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1664 { 1665 struct pci_devinfo *dinfo; 1666 struct devlist *devlist_head; 1667 struct pci_conf *p; 1668 const char *name; 1669 int i, error, none_count, quit; 1670 1671 none_count = 0; 1672 /* get the head of the device queue */ 1673 devlist_head = &pci_devq; 1674 1675 /* 1676 * Go through the list of devices and print out devices 1677 */ 1678 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1679 for (error = 0, i = 0, quit = 0, 1680 dinfo = STAILQ_FIRST(devlist_head); 1681 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1682 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1683 1684 /* Populate pd_name and pd_unit */ 1685 name = NULL; 1686 if (dinfo->cfg.dev) 1687 name = device_get_name(dinfo->cfg.dev); 1688 1689 p = &dinfo->conf; 1690 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1691 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1692 (name && *name) ? name : "none", 1693 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1694 none_count++, 1695 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1696 p->pc_sel.pc_func, (p->pc_class << 16) | 1697 (p->pc_subclass << 8) | p->pc_progif, 1698 (p->pc_subdevice << 16) | p->pc_subvendor, 1699 (p->pc_device << 16) | p->pc_vendor, 1700 p->pc_revid, p->pc_hdr); 1701 } 1702 } 1703 #endif /* DDB */ 1704 1705 static struct resource * 1706 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1707 u_long start, u_long end, u_long count, u_int flags) 1708 { 1709 struct pci_devinfo *dinfo = device_get_ivars(child); 1710 struct resource_list *rl = &dinfo->resources; 1711 struct resource_list_entry *rle; 1712 struct resource *res; 1713 uint32_t map, testval; 1714 int mapsize; 1715 1716 /* 1717 * Weed out the bogons, and figure out how large the BAR/map 1718 * is. Bars that read back 0 here are bogus and unimplemented. 1719 * Note: atapci in legacy mode are special and handled elsewhere 1720 * in the code. If you have a atapci device in legacy mode and 1721 * it fails here, that other code is broken. 1722 */ 1723 res = NULL; 1724 map = pci_read_config(child, *rid, 4); 1725 pci_write_config(child, *rid, 0xffffffff, 4); 1726 testval = pci_read_config(child, *rid, 4); 1727 if (pci_mapbase(testval) == 0) 1728 goto out; 1729 if (pci_maptype(testval) & PCI_MAPMEM) { 1730 if (type != SYS_RES_MEMORY) { 1731 if (bootverbose) 1732 device_printf(dev, 1733 "child %s requested type %d for rid %#x," 1734 " but the BAR says it is an memio\n", 1735 device_get_nameunit(child), type, *rid); 1736 goto out; 1737 } 1738 } else { 1739 if (type != SYS_RES_IOPORT) { 1740 if (bootverbose) 1741 device_printf(dev, 1742 "child %s requested type %d for rid %#x," 1743 " but the BAR says it is an ioport\n", 1744 device_get_nameunit(child), type, *rid); 1745 goto out; 1746 } 1747 } 1748 /* 1749 * For real BARs, we need to override the size that 1750 * the driver requests, because that's what the BAR 1751 * actually uses and we would otherwise have a 1752 * situation where we might allocate the excess to 1753 * another driver, which won't work. 1754 */ 1755 mapsize = pci_mapsize(testval); 1756 count = 1 << mapsize; 1757 if (RF_ALIGNMENT(flags) < mapsize) 1758 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1759 1760 /* 1761 * Allocate enough resource, and then write back the 1762 * appropriate bar for that resource. 1763 */ 1764 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1765 start, end, count, flags); 1766 if (res == NULL) { 1767 device_printf(child, 1768 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 1769 count, *rid, type, start, end); 1770 goto out; 1771 } 1772 resource_list_add(rl, type, *rid, start, end, count); 1773 rle = resource_list_find(rl, type, *rid); 1774 if (rle == NULL) 1775 panic("pci_alloc_map: unexpectedly can't find resource."); 1776 rle->res = res; 1777 rle->start = rman_get_start(res); 1778 rle->end = rman_get_end(res); 1779 rle->count = count; 1780 if (bootverbose) 1781 device_printf(child, 1782 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1783 count, *rid, type, rman_get_start(res)); 1784 map = rman_get_start(res); 1785 out:; 1786 pci_write_config(child, *rid, map, 4); 1787 return (res); 1788 } 1789 1790 1791 struct resource * 1792 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1793 u_long start, u_long end, u_long count, u_int flags) 1794 { 1795 struct pci_devinfo *dinfo = device_get_ivars(child); 1796 struct resource_list *rl = &dinfo->resources; 1797 struct resource_list_entry *rle; 1798 pcicfgregs *cfg = &dinfo->cfg; 1799 1800 /* 1801 * Perform lazy resource allocation 1802 */ 1803 if (device_get_parent(child) == dev) { 1804 switch (type) { 1805 case SYS_RES_IRQ: 1806 /* 1807 * If the child device doesn't have an 1808 * interrupt routed and is deserving of an 1809 * interrupt, try to assign it one. 1810 */ 1811 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1812 (cfg->intpin != 0)) 1813 pci_assign_interrupt(dev, child, 0); 1814 break; 1815 case SYS_RES_IOPORT: 1816 case SYS_RES_MEMORY: 1817 if (*rid < PCIR_BAR(cfg->nummaps)) { 1818 /* 1819 * Enable the I/O mode. We should 1820 * also be assigning resources too 1821 * when none are present. The 1822 * resource_list_alloc kind of sorta does 1823 * this... 1824 */ 1825 if (PCI_ENABLE_IO(dev, child, type)) 1826 return (NULL); 1827 } 1828 rle = resource_list_find(rl, type, *rid); 1829 if (rle == NULL) 1830 return (pci_alloc_map(dev, child, type, rid, 1831 start, end, count, flags)); 1832 break; 1833 } 1834 /* 1835 * If we've already allocated the resource, then 1836 * return it now. But first we may need to activate 1837 * it, since we don't allocate the resource as active 1838 * above. Normally this would be done down in the 1839 * nexus, but since we short-circuit that path we have 1840 * to do its job here. Not sure if we should free the 1841 * resource if it fails to activate. 1842 */ 1843 rle = resource_list_find(rl, type, *rid); 1844 if (rle != NULL && rle->res != NULL) { 1845 if (bootverbose) 1846 device_printf(child, 1847 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1848 rman_get_size(rle->res), *rid, type, 1849 rman_get_start(rle->res)); 1850 if ((flags & RF_ACTIVE) && 1851 bus_generic_activate_resource(dev, child, type, 1852 *rid, rle->res) != 0) 1853 return NULL; 1854 return (rle->res); 1855 } 1856 } 1857 return (resource_list_alloc(rl, dev, child, type, rid, 1858 start, end, count, flags)); 1859 } 1860 1861 void 1862 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1863 { 1864 struct pci_devinfo *dinfo; 1865 struct resource_list *rl; 1866 struct resource_list_entry *rle; 1867 1868 if (device_get_parent(child) != dev) 1869 return; 1870 1871 dinfo = device_get_ivars(child); 1872 rl = &dinfo->resources; 1873 rle = resource_list_find(rl, type, rid); 1874 if (rle) { 1875 if (rle->res) { 1876 if (rman_get_device(rle->res) != dev || 1877 rman_get_flags(rle->res) & RF_ACTIVE) { 1878 device_printf(dev, "delete_resource: " 1879 "Resource still owned by child, oops. " 1880 "(type=%d, rid=%d, addr=%lx)\n", 1881 rle->type, rle->rid, 1882 rman_get_start(rle->res)); 1883 return; 1884 } 1885 bus_release_resource(dev, type, rid, rle->res); 1886 } 1887 resource_list_delete(rl, type, rid); 1888 } 1889 /* 1890 * Why do we turn off the PCI configuration BAR when we delete a 1891 * resource? -- imp 1892 */ 1893 pci_write_config(child, rid, 0, 4); 1894 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1895 } 1896 1897 struct resource_list * 1898 pci_get_resource_list (device_t dev, device_t child) 1899 { 1900 struct pci_devinfo *dinfo = device_get_ivars(child); 1901 1902 return (&dinfo->resources); 1903 } 1904 1905 uint32_t 1906 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1907 { 1908 struct pci_devinfo *dinfo = device_get_ivars(child); 1909 pcicfgregs *cfg = &dinfo->cfg; 1910 1911 return (PCIB_READ_CONFIG(device_get_parent(dev), 1912 cfg->bus, cfg->slot, cfg->func, reg, width)); 1913 } 1914 1915 void 1916 pci_write_config_method(device_t dev, device_t child, int reg, 1917 uint32_t val, int width) 1918 { 1919 struct pci_devinfo *dinfo = device_get_ivars(child); 1920 pcicfgregs *cfg = &dinfo->cfg; 1921 1922 PCIB_WRITE_CONFIG(device_get_parent(dev), 1923 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1924 } 1925 1926 int 1927 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1928 size_t buflen) 1929 { 1930 1931 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1932 pci_get_function(child)); 1933 return (0); 1934 } 1935 1936 int 1937 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1938 size_t buflen) 1939 { 1940 struct pci_devinfo *dinfo; 1941 pcicfgregs *cfg; 1942 1943 dinfo = device_get_ivars(child); 1944 cfg = &dinfo->cfg; 1945 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1946 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1947 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1948 cfg->progif); 1949 return (0); 1950 } 1951 1952 int 1953 pci_assign_interrupt_method(device_t dev, device_t child) 1954 { 1955 struct pci_devinfo *dinfo = device_get_ivars(child); 1956 pcicfgregs *cfg = &dinfo->cfg; 1957 1958 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1959 cfg->intpin)); 1960 } 1961 1962 static int 1963 pci_modevent(module_t mod, int what, void *arg) 1964 { 1965 static struct cdev *pci_cdev; 1966 1967 switch (what) { 1968 case MOD_LOAD: 1969 STAILQ_INIT(&pci_devq); 1970 pci_generation = 0; 1971 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1972 "pci"); 1973 pci_load_vendor_data(); 1974 break; 1975 1976 case MOD_UNLOAD: 1977 destroy_dev(pci_cdev); 1978 break; 1979 } 1980 1981 return (0); 1982 } 1983 1984 void 1985 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1986 { 1987 int i; 1988 1989 /* 1990 * Only do header type 0 devices. Type 1 devices are bridges, 1991 * which we know need special treatment. Type 2 devices are 1992 * cardbus bridges which also require special treatment. 1993 * Other types are unknown, and we err on the side of safety 1994 * by ignoring them. 1995 */ 1996 if (dinfo->cfg.hdrtype != 0) 1997 return; 1998 1999 /* 2000 * Restore the device to full power mode. We must do this 2001 * before we restore the registers because moving from D3 to 2002 * D0 will cause the chip's BARs and some other registers to 2003 * be reset to some unknown power on reset values. Cut down 2004 * the noise on boot by doing nothing if we are already in 2005 * state D0. 2006 */ 2007 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2008 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2009 } 2010 for (i = 0; i < dinfo->cfg.nummaps; i++) 2011 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2012 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2013 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2014 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2015 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2016 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2017 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2018 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2019 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2020 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2021 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2022 } 2023 2024 void 2025 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2026 { 2027 int i; 2028 uint32_t cls; 2029 int ps; 2030 2031 /* 2032 * Only do header type 0 devices. Type 1 devices are bridges, which 2033 * we know need special treatment. Type 2 devices are cardbus bridges 2034 * which also require special treatment. Other types are unknown, and 2035 * we err on the side of safety by ignoring them. Powering down 2036 * bridges should not be undertaken lightly. 2037 */ 2038 if (dinfo->cfg.hdrtype != 0) 2039 return; 2040 for (i = 0; i < dinfo->cfg.nummaps; i++) 2041 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2042 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2043 2044 /* 2045 * Some drivers apparently write to these registers w/o updating our 2046 * cached copy. No harm happens if we update the copy, so do so here 2047 * so we can restore them. The COMMAND register is modified by the 2048 * bus w/o updating the cache. This should represent the normally 2049 * writable portion of the 'defined' part of type 0 headers. In 2050 * theory we also need to save/restore the PCI capability structures 2051 * we know about, but apart from power we don't know any that are 2052 * writable. 2053 */ 2054 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2055 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2056 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2057 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2058 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2059 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2060 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2061 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2062 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2063 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2064 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2065 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2066 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2067 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2068 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2069 2070 /* 2071 * don't set the state for display devices, base peripherals and 2072 * memory devices since bad things happen when they are powered down. 2073 * We should (a) have drivers that can easily detach and (b) use 2074 * generic drivers for these devices so that some device actually 2075 * attaches. We need to make sure that when we implement (a) we don't 2076 * power the device down on a reattach. 2077 */ 2078 cls = pci_get_class(dev); 2079 if (!setstate) 2080 return; 2081 switch (pci_do_power_nodriver) 2082 { 2083 case 0: /* NO powerdown at all */ 2084 return; 2085 case 1: /* Conservative about what to power down */ 2086 if (cls == PCIC_STORAGE) 2087 return; 2088 /*FALLTHROUGH*/ 2089 case 2: /* Agressive about what to power down */ 2090 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2091 cls == PCIC_BASEPERIPH) 2092 return; 2093 /*FALLTHROUGH*/ 2094 case 3: /* Power down everything */ 2095 break; 2096 } 2097 /* 2098 * PCI spec says we can only go into D3 state from D0 state. 2099 * Transition from D[12] into D0 before going to D3 state. 2100 */ 2101 ps = pci_get_powerstate(dev); 2102 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2103 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2104 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2105 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2106 }
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