FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pci.c
1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include "opt_bus.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
40 #include <sys/conf.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/types.h>
45
46 #include <vm/vm.h>
47 #include <vm/pmap.h>
48 #include <vm/vm_extern.h>
49
50 #include <sys/bus.h>
51 #include <machine/bus.h>
52 #include <sys/rman.h>
53 #include <machine/resource.h>
54
55 #if defined(__i386__) || defined(__amd64__)
56 #include <machine/intr_machdep.h>
57 #endif
58
59 #include <sys/pciio.h>
60 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pci_private.h>
63
64 #include "pcib_if.h"
65 #include "pci_if.h"
66
67 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \
68 defined (__ia64__)
69 #include <contrib/dev/acpica/acpi.h>
70 #include "acpi_if.h"
71 #else
72 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 #endif
74
75 static uint32_t pci_mapbase(unsigned mapreg);
76 static int pci_maptype(unsigned mapreg);
77 static int pci_mapsize(unsigned testval);
78 static int pci_maprange(unsigned mapreg);
79 static void pci_fixancient(pcicfgregs *cfg);
80
81 static int pci_porten(device_t pcib, int b, int s, int f);
82 static int pci_memen(device_t pcib, int b, int s, int f);
83 static void pci_assign_interrupt(device_t bus, device_t dev,
84 int force_route);
85 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
86 int b, int s, int f, int reg,
87 struct resource_list *rl, int force, int prefetch);
88 static int pci_probe(device_t dev);
89 static int pci_attach(device_t dev);
90 static void pci_load_vendor_data(void);
91 static int pci_describe_parse_line(char **ptr, int *vendor,
92 int *device, char **desc);
93 static char *pci_describe_device(device_t dev);
94 static int pci_modevent(module_t mod, int what, void *arg);
95 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
96 pcicfgregs *cfg);
97 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
98 static void pci_disable_msi(device_t dev);
99 static void pci_enable_msi(device_t dev, uint64_t address,
100 uint16_t data);
101 static void pci_enable_msix(device_t dev, u_int index,
102 uint64_t address, uint32_t data);
103 static void pci_mask_msix(device_t dev, u_int index);
104 static void pci_unmask_msix(device_t dev, u_int index);
105 static int pci_msi_blacklisted(void);
106 static void pci_resume_msi(device_t dev);
107 static void pci_resume_msix(device_t dev);
108
109 static device_method_t pci_methods[] = {
110 /* Device interface */
111 DEVMETHOD(device_probe, pci_probe),
112 DEVMETHOD(device_attach, pci_attach),
113 DEVMETHOD(device_detach, bus_generic_detach),
114 DEVMETHOD(device_shutdown, bus_generic_shutdown),
115 DEVMETHOD(device_suspend, pci_suspend),
116 DEVMETHOD(device_resume, pci_resume),
117
118 /* Bus interface */
119 DEVMETHOD(bus_print_child, pci_print_child),
120 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
121 DEVMETHOD(bus_read_ivar, pci_read_ivar),
122 DEVMETHOD(bus_write_ivar, pci_write_ivar),
123 DEVMETHOD(bus_driver_added, pci_driver_added),
124 DEVMETHOD(bus_setup_intr, pci_setup_intr),
125 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
126
127 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
128 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
129 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
130 DEVMETHOD(bus_delete_resource, pci_delete_resource),
131 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
132 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
133 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
134 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
135 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
136 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
137
138 /* PCI interface */
139 DEVMETHOD(pci_read_config, pci_read_config_method),
140 DEVMETHOD(pci_write_config, pci_write_config_method),
141 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
142 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
143 DEVMETHOD(pci_enable_io, pci_enable_io_method),
144 DEVMETHOD(pci_disable_io, pci_disable_io_method),
145 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
146 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
147 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
148 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
149 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
150 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
151 DEVMETHOD(pci_release_msi, pci_release_msi_method),
152 DEVMETHOD(pci_msi_count, pci_msi_count_method),
153 DEVMETHOD(pci_msix_count, pci_msix_count_method),
154
155 { 0, 0 }
156 };
157
158 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
159
160 static devclass_t pci_devclass;
161 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
162 MODULE_VERSION(pci, 1);
163
164 static char *pci_vendordata;
165 static size_t pci_vendordata_size;
166
167
168 struct pci_quirk {
169 uint32_t devid; /* Vendor/device of the card */
170 int type;
171 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
172 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
173 int arg1;
174 int arg2;
175 };
176
177 struct pci_quirk pci_quirks[] = {
178 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
179 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
180 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
181 /* As does the Serverworks OSB4 (the SMBus mapping register) */
182 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
183
184 /*
185 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
186 * or the CMIC-SL (AKA ServerWorks GC_LE).
187 */
188 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
189 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
190
191 /*
192 * MSI doesn't work on earlier Intel chipsets including
193 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
194 */
195 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
196 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
197 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
198 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
199 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
200 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
201 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
202
203 /*
204 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
205 * bridge.
206 */
207 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208
209 { 0 }
210 };
211
212 /* map register information */
213 #define PCI_MAPMEM 0x01 /* memory map */
214 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
215 #define PCI_MAPPORT 0x04 /* port map */
216
217 struct devlist pci_devq;
218 uint32_t pci_generation;
219 uint32_t pci_numdevs = 0;
220 static int pcie_chipset, pcix_chipset;
221
222 /* sysctl vars */
223 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
224
225 static int pci_enable_io_modes = 1;
226 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
227 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
228 &pci_enable_io_modes, 1,
229 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
230 enable these bits correctly. We'd like to do this all the time, but there\n\
231 are some peripherals that this causes problems with.");
232
233 static int pci_do_power_nodriver = 0;
234 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
235 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
236 &pci_do_power_nodriver, 0,
237 "Place a function into D3 state when no driver attaches to it. 0 means\n\
238 disable. 1 means conservatively place devices into D3 state. 2 means\n\
239 agressively place devices into D3 state. 3 means put absolutely everything\n\
240 in D3 state.");
241
242 static int pci_do_power_resume = 1;
243 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
244 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
245 &pci_do_power_resume, 1,
246 "Transition from D3 -> D0 on resume.");
247
248 static int pci_do_msi = 1;
249 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
250 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
251 "Enable support for MSI interrupts");
252
253 static int pci_do_msix = 1;
254 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
255 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
256 "Enable support for MSI-X interrupts");
257
258 static int pci_honor_msi_blacklist = 1;
259 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
260 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
261 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
262
263 /* Find a device_t by bus/slot/function */
264
265 device_t
266 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
267 {
268 struct pci_devinfo *dinfo;
269
270 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
271 if ((dinfo->cfg.bus == bus) &&
272 (dinfo->cfg.slot == slot) &&
273 (dinfo->cfg.func == func)) {
274 return (dinfo->cfg.dev);
275 }
276 }
277
278 return (NULL);
279 }
280
281 /* Find a device_t by vendor/device ID */
282
283 device_t
284 pci_find_device(uint16_t vendor, uint16_t device)
285 {
286 struct pci_devinfo *dinfo;
287
288 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
289 if ((dinfo->cfg.vendor == vendor) &&
290 (dinfo->cfg.device == device)) {
291 return (dinfo->cfg.dev);
292 }
293 }
294
295 return (NULL);
296 }
297
298 /* return base address of memory or port map */
299
300 static uint32_t
301 pci_mapbase(unsigned mapreg)
302 {
303 int mask = 0x03;
304 if ((mapreg & 0x01) == 0)
305 mask = 0x0f;
306 return (mapreg & ~mask);
307 }
308
309 /* return map type of memory or port map */
310
311 static int
312 pci_maptype(unsigned mapreg)
313 {
314 static uint8_t maptype[0x10] = {
315 PCI_MAPMEM, PCI_MAPPORT,
316 PCI_MAPMEM, 0,
317 PCI_MAPMEM, PCI_MAPPORT,
318 0, 0,
319 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
320 PCI_MAPMEM|PCI_MAPMEMP, 0,
321 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
322 0, 0,
323 };
324
325 return maptype[mapreg & 0x0f];
326 }
327
328 /* return log2 of map size decoded for memory or port map */
329
330 static int
331 pci_mapsize(unsigned testval)
332 {
333 int ln2size;
334
335 testval = pci_mapbase(testval);
336 ln2size = 0;
337 if (testval != 0) {
338 while ((testval & 1) == 0)
339 {
340 ln2size++;
341 testval >>= 1;
342 }
343 }
344 return (ln2size);
345 }
346
347 /* return log2 of address range supported by map register */
348
349 static int
350 pci_maprange(unsigned mapreg)
351 {
352 int ln2range = 0;
353 switch (mapreg & 0x07) {
354 case 0x00:
355 case 0x01:
356 case 0x05:
357 ln2range = 32;
358 break;
359 case 0x02:
360 ln2range = 20;
361 break;
362 case 0x04:
363 ln2range = 64;
364 break;
365 }
366 return (ln2range);
367 }
368
369 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
370
371 static void
372 pci_fixancient(pcicfgregs *cfg)
373 {
374 if (cfg->hdrtype != 0)
375 return;
376
377 /* PCI to PCI bridges use header type 1 */
378 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
379 cfg->hdrtype = 1;
380 }
381
382 /* extract header type specific config data */
383
384 static void
385 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
386 {
387 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
388 switch (cfg->hdrtype) {
389 case 0:
390 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
391 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
392 cfg->nummaps = PCI_MAXMAPS_0;
393 break;
394 case 1:
395 cfg->nummaps = PCI_MAXMAPS_1;
396 break;
397 case 2:
398 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
399 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
400 cfg->nummaps = PCI_MAXMAPS_2;
401 break;
402 }
403 #undef REG
404 }
405
406 /* read configuration header into pcicfgregs structure */
407
408 struct pci_devinfo *
409 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
410 {
411 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
412 pcicfgregs *cfg = NULL;
413 struct pci_devinfo *devlist_entry;
414 struct devlist *devlist_head;
415
416 devlist_head = &pci_devq;
417
418 devlist_entry = NULL;
419
420 if (REG(PCIR_DEVVENDOR, 4) != -1) {
421 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
422 if (devlist_entry == NULL)
423 return (NULL);
424
425 cfg = &devlist_entry->cfg;
426
427 cfg->bus = b;
428 cfg->slot = s;
429 cfg->func = f;
430 cfg->vendor = REG(PCIR_VENDOR, 2);
431 cfg->device = REG(PCIR_DEVICE, 2);
432 cfg->cmdreg = REG(PCIR_COMMAND, 2);
433 cfg->statreg = REG(PCIR_STATUS, 2);
434 cfg->baseclass = REG(PCIR_CLASS, 1);
435 cfg->subclass = REG(PCIR_SUBCLASS, 1);
436 cfg->progif = REG(PCIR_PROGIF, 1);
437 cfg->revid = REG(PCIR_REVID, 1);
438 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
439 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
440 cfg->lattimer = REG(PCIR_LATTIMER, 1);
441 cfg->intpin = REG(PCIR_INTPIN, 1);
442 cfg->intline = REG(PCIR_INTLINE, 1);
443
444 cfg->mingnt = REG(PCIR_MINGNT, 1);
445 cfg->maxlat = REG(PCIR_MAXLAT, 1);
446
447 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
448 cfg->hdrtype &= ~PCIM_MFDEV;
449
450 pci_fixancient(cfg);
451 pci_hdrtypedata(pcib, b, s, f, cfg);
452
453 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
454 pci_read_extcap(pcib, cfg);
455
456 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
457
458 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
459 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
460 devlist_entry->conf.pc_sel.pc_func = cfg->func;
461 devlist_entry->conf.pc_hdr = cfg->hdrtype;
462
463 devlist_entry->conf.pc_subvendor = cfg->subvendor;
464 devlist_entry->conf.pc_subdevice = cfg->subdevice;
465 devlist_entry->conf.pc_vendor = cfg->vendor;
466 devlist_entry->conf.pc_device = cfg->device;
467
468 devlist_entry->conf.pc_class = cfg->baseclass;
469 devlist_entry->conf.pc_subclass = cfg->subclass;
470 devlist_entry->conf.pc_progif = cfg->progif;
471 devlist_entry->conf.pc_revid = cfg->revid;
472
473 pci_numdevs++;
474 pci_generation++;
475 }
476 return (devlist_entry);
477 #undef REG
478 }
479
480 static void
481 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
482 {
483 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
484 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
485 #if defined(__i386__) || defined(__amd64__)
486 uint64_t addr;
487 #endif
488 uint32_t val;
489 int ptr, nextptr, ptrptr;
490
491 switch (cfg->hdrtype & PCIM_HDRTYPE) {
492 case 0:
493 case 1:
494 ptrptr = PCIR_CAP_PTR;
495 break;
496 case 2:
497 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
498 break;
499 default:
500 return; /* no extended capabilities support */
501 }
502 nextptr = REG(ptrptr, 1); /* sanity check? */
503
504 /*
505 * Read capability entries.
506 */
507 while (nextptr != 0) {
508 /* Sanity check */
509 if (nextptr > 255) {
510 printf("illegal PCI extended capability offset %d\n",
511 nextptr);
512 return;
513 }
514 /* Find the next entry */
515 ptr = nextptr;
516 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
517
518 /* Process this entry */
519 switch (REG(ptr + PCICAP_ID, 1)) {
520 case PCIY_PMG: /* PCI power management */
521 if (cfg->pp.pp_cap == 0) {
522 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
523 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
524 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
525 if ((nextptr - ptr) > PCIR_POWER_DATA)
526 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
527 }
528 break;
529 #if defined(__i386__) || defined(__amd64__)
530 case PCIY_HT: /* HyperTransport */
531 /* Determine HT-specific capability type. */
532 val = REG(ptr + PCIR_HT_COMMAND, 2);
533 switch (val & PCIM_HTCMD_CAP_MASK) {
534 case PCIM_HTCAP_MSI_MAPPING:
535 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
536 /* Sanity check the mapping window. */
537 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
538 4);
539 addr <<= 32;
540 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
541 4);
542 if (addr != MSI_INTEL_ADDR_BASE)
543 device_printf(pcib,
544 "HT Bridge at %d:%d:%d has non-default MSI window 0x%llx\n",
545 cfg->bus, cfg->slot,
546 cfg->func, (long long)addr);
547 } else
548 addr = MSI_INTEL_ADDR_BASE;
549
550 cfg->ht.ht_msimap = ptr;
551 cfg->ht.ht_msictrl = val;
552 cfg->ht.ht_msiaddr = addr;
553 break;
554 }
555 break;
556 #endif
557 case PCIY_MSI: /* PCI MSI */
558 cfg->msi.msi_location = ptr;
559 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
560 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
561 PCIM_MSICTRL_MMC_MASK)>>1);
562 break;
563 case PCIY_MSIX: /* PCI MSI-X */
564 cfg->msix.msix_location = ptr;
565 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
566 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
567 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
568 val = REG(ptr + PCIR_MSIX_TABLE, 4);
569 cfg->msix.msix_table_bar = PCIR_BAR(val &
570 PCIM_MSIX_BIR_MASK);
571 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
572 val = REG(ptr + PCIR_MSIX_PBA, 4);
573 cfg->msix.msix_pba_bar = PCIR_BAR(val &
574 PCIM_MSIX_BIR_MASK);
575 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
576 break;
577 case PCIY_SUBVENDOR:
578 /* Should always be true. */
579 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
580 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
581 cfg->subvendor = val & 0xffff;
582 cfg->subdevice = val >> 16;
583 }
584 break;
585 case PCIY_PCIX: /* PCI-X */
586 /*
587 * Assume we have a PCI-X chipset if we have
588 * at least one PCI-PCI bridge with a PCI-X
589 * capability. Note that some systems with
590 * PCI-express or HT chipsets might match on
591 * this check as well.
592 */
593 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
594 pcix_chipset = 1;
595 break;
596 case PCIY_EXPRESS: /* PCI-express */
597 /*
598 * Assume we have a PCI-express chipset if we have
599 * at least one PCI-express device.
600 */
601 pcie_chipset = 1;
602 break;
603 default:
604 break;
605 }
606 }
607 #undef REG
608 #undef WREG
609 }
610
611 /*
612 * Return the offset in configuration space of the requested extended
613 * capability entry or 0 if the specified capability was not found.
614 */
615 int
616 pci_find_extcap_method(device_t dev, device_t child, int capability,
617 int *capreg)
618 {
619 struct pci_devinfo *dinfo = device_get_ivars(child);
620 pcicfgregs *cfg = &dinfo->cfg;
621 u_int32_t status;
622 u_int8_t ptr;
623
624 /*
625 * Check the CAP_LIST bit of the PCI status register first.
626 */
627 status = pci_read_config(child, PCIR_STATUS, 2);
628 if (!(status & PCIM_STATUS_CAPPRESENT))
629 return (ENXIO);
630
631 /*
632 * Determine the start pointer of the capabilities list.
633 */
634 switch (cfg->hdrtype & PCIM_HDRTYPE) {
635 case 0:
636 case 1:
637 ptr = PCIR_CAP_PTR;
638 break;
639 case 2:
640 ptr = PCIR_CAP_PTR_2;
641 break;
642 default:
643 /* XXX: panic? */
644 return (ENXIO); /* no extended capabilities support */
645 }
646 ptr = pci_read_config(child, ptr, 1);
647
648 /*
649 * Traverse the capabilities list.
650 */
651 while (ptr != 0) {
652 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
653 if (capreg != NULL)
654 *capreg = ptr;
655 return (0);
656 }
657 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
658 }
659
660 return (ENOENT);
661 }
662
663 /*
664 * Support for MSI-X message interrupts.
665 */
666 void
667 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
668 {
669 struct pci_devinfo *dinfo = device_get_ivars(dev);
670 struct pcicfg_msix *msix = &dinfo->cfg.msix;
671 uint32_t offset;
672
673 KASSERT(msix->msix_table_len > index, ("bogus index"));
674 offset = msix->msix_table_offset + index * 16;
675 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
676 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
677 bus_write_4(msix->msix_table_res, offset + 8, data);
678
679 /* Enable MSI -> HT mapping. */
680 pci_ht_map_msi(dev, address);
681 }
682
683 void
684 pci_mask_msix(device_t dev, u_int index)
685 {
686 struct pci_devinfo *dinfo = device_get_ivars(dev);
687 struct pcicfg_msix *msix = &dinfo->cfg.msix;
688 uint32_t offset, val;
689
690 KASSERT(msix->msix_msgnum > index, ("bogus index"));
691 offset = msix->msix_table_offset + index * 16 + 12;
692 val = bus_read_4(msix->msix_table_res, offset);
693 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
694 val |= PCIM_MSIX_VCTRL_MASK;
695 bus_write_4(msix->msix_table_res, offset, val);
696 }
697 }
698
699 void
700 pci_unmask_msix(device_t dev, u_int index)
701 {
702 struct pci_devinfo *dinfo = device_get_ivars(dev);
703 struct pcicfg_msix *msix = &dinfo->cfg.msix;
704 uint32_t offset, val;
705
706 KASSERT(msix->msix_table_len > index, ("bogus index"));
707 offset = msix->msix_table_offset + index * 16 + 12;
708 val = bus_read_4(msix->msix_table_res, offset);
709 if (val & PCIM_MSIX_VCTRL_MASK) {
710 val &= ~PCIM_MSIX_VCTRL_MASK;
711 bus_write_4(msix->msix_table_res, offset, val);
712 }
713 }
714
715 int
716 pci_pending_msix(device_t dev, u_int index)
717 {
718 struct pci_devinfo *dinfo = device_get_ivars(dev);
719 struct pcicfg_msix *msix = &dinfo->cfg.msix;
720 uint32_t offset, bit;
721
722 KASSERT(msix->msix_table_len > index, ("bogus index"));
723 offset = msix->msix_pba_offset + (index / 32) * 4;
724 bit = 1 << index % 32;
725 return (bus_read_4(msix->msix_pba_res, offset) & bit);
726 }
727
728 /*
729 * Restore MSI-X registers and table during resume. If MSI-X is
730 * enabled then walk the virtual table to restore the actual MSI-X
731 * table.
732 */
733 static void
734 pci_resume_msix(device_t dev)
735 {
736 struct pci_devinfo *dinfo = device_get_ivars(dev);
737 struct pcicfg_msix *msix = &dinfo->cfg.msix;
738 struct msix_table_entry *mte;
739 struct msix_vector *mv;
740 int i;
741
742 if (msix->msix_alloc > 0) {
743 /* First, mask all vectors. */
744 for (i = 0; i < msix->msix_msgnum; i++)
745 pci_mask_msix(dev, i);
746
747 /* Second, program any messages with at least one handler. */
748 for (i = 0; i < msix->msix_table_len; i++) {
749 mte = &msix->msix_table[i];
750 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
751 continue;
752 mv = &msix->msix_vectors[mte->mte_vector - 1];
753 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
754 pci_unmask_msix(dev, i);
755 }
756 }
757 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
758 msix->msix_ctrl, 2);
759 }
760
761 /*
762 * Attempt to allocate *count MSI-X messages. The actual number allocated is
763 * returned in *count. After this function returns, each message will be
764 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
765 */
766 int
767 pci_alloc_msix_method(device_t dev, device_t child, int *count)
768 {
769 struct pci_devinfo *dinfo = device_get_ivars(child);
770 pcicfgregs *cfg = &dinfo->cfg;
771 struct resource_list_entry *rle;
772 int actual, error, i, irq, max;
773
774 /* Don't let count == 0 get us into trouble. */
775 if (*count == 0)
776 return (EINVAL);
777
778 /* If rid 0 is allocated, then fail. */
779 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
780 if (rle != NULL && rle->res != NULL)
781 return (ENXIO);
782
783 /* Already have allocated messages? */
784 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
785 return (ENXIO);
786
787 /* If MSI is blacklisted for this system, fail. */
788 if (pci_msi_blacklisted())
789 return (ENXIO);
790
791 /* MSI-X capability present? */
792 if (cfg->msix.msix_location == 0 || !pci_do_msix)
793 return (ENODEV);
794
795 /* Make sure the appropriate BARs are mapped. */
796 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
797 cfg->msix.msix_table_bar);
798 if (rle == NULL || rle->res == NULL ||
799 !(rman_get_flags(rle->res) & RF_ACTIVE))
800 return (ENXIO);
801 cfg->msix.msix_table_res = rle->res;
802 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
803 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
804 cfg->msix.msix_pba_bar);
805 if (rle == NULL || rle->res == NULL ||
806 !(rman_get_flags(rle->res) & RF_ACTIVE))
807 return (ENXIO);
808 }
809 cfg->msix.msix_pba_res = rle->res;
810
811 if (bootverbose)
812 device_printf(child,
813 "attempting to allocate %d MSI-X vectors (%d supported)\n",
814 *count, cfg->msix.msix_msgnum);
815 max = min(*count, cfg->msix.msix_msgnum);
816 for (i = 0; i < max; i++) {
817 /* Allocate a message. */
818 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
819 if (error)
820 break;
821 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
822 irq, 1);
823 }
824 actual = i;
825
826 if (bootverbose) {
827 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
828 if (actual == 1)
829 device_printf(child, "using IRQ %lu for MSI-X\n",
830 rle->start);
831 else {
832 int run;
833
834 /*
835 * Be fancy and try to print contiguous runs of
836 * IRQ values as ranges. 'irq' is the previous IRQ.
837 * 'run' is true if we are in a range.
838 */
839 device_printf(child, "using IRQs %lu", rle->start);
840 irq = rle->start;
841 run = 0;
842 for (i = 1; i < actual; i++) {
843 rle = resource_list_find(&dinfo->resources,
844 SYS_RES_IRQ, i + 1);
845
846 /* Still in a run? */
847 if (rle->start == irq + 1) {
848 run = 1;
849 irq++;
850 continue;
851 }
852
853 /* Finish previous range. */
854 if (run) {
855 printf("-%d", irq);
856 run = 0;
857 }
858
859 /* Start new range. */
860 printf(",%lu", rle->start);
861 irq = rle->start;
862 }
863
864 /* Unfinished range? */
865 if (run)
866 printf("-%d", irq);
867 printf(" for MSI-X\n");
868 }
869 }
870
871 /* Mask all vectors. */
872 for (i = 0; i < cfg->msix.msix_msgnum; i++)
873 pci_mask_msix(child, i);
874
875 /* Allocate and initialize vector data and virtual table. */
876 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
877 M_DEVBUF, M_WAITOK | M_ZERO);
878 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
879 M_DEVBUF, M_WAITOK | M_ZERO);
880 for (i = 0; i < actual; i++) {
881 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
882 cfg->msix.msix_vectors[i].mv_irq = rle->start;
883 cfg->msix.msix_table[i].mte_vector = i + 1;
884 }
885
886 /* Update control register to enable MSI-X. */
887 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
888 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
889 cfg->msix.msix_ctrl, 2);
890
891 /* Update counts of alloc'd messages. */
892 cfg->msix.msix_alloc = actual;
893 cfg->msix.msix_table_len = actual;
894 *count = actual;
895 return (0);
896 }
897
898 static int
899 pci_release_msix(device_t dev, device_t child)
900 {
901 struct pci_devinfo *dinfo = device_get_ivars(child);
902 struct pcicfg_msix *msix = &dinfo->cfg.msix;
903 struct resource_list_entry *rle;
904 int i;
905
906 /* Do we have any messages to release? */
907 if (msix->msix_alloc == 0)
908 return (ENODEV);
909
910 /* Make sure none of the resources are allocated. */
911 for (i = 0; i < msix->msix_table_len; i++) {
912 if (msix->msix_table[i].mte_vector == 0)
913 continue;
914 if (msix->msix_table[i].mte_handlers > 0)
915 return (EBUSY);
916 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
917 KASSERT(rle != NULL, ("missing resource"));
918 if (rle->res != NULL)
919 return (EBUSY);
920 }
921
922 /* Update control register to disable MSI-X. */
923 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
924 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
925 msix->msix_ctrl, 2);
926
927 /* Free the resource list entries. */
928 for (i = 0; i < msix->msix_table_len; i++) {
929 if (msix->msix_table[i].mte_vector == 0)
930 continue;
931 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
932 }
933 free(msix->msix_table, M_DEVBUF);
934 msix->msix_table_len = 0;
935
936 /* Release the IRQs. */
937 for (i = 0; i < msix->msix_alloc; i++)
938 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
939 msix->msix_vectors[i].mv_irq);
940 free(msix->msix_vectors, M_DEVBUF);
941 msix->msix_alloc = 0;
942 return (0);
943 }
944
945 /*
946 * Return the max supported MSI-X messages this device supports.
947 * Basically, assuming the MD code can alloc messages, this function
948 * should return the maximum value that pci_alloc_msix() can return.
949 * Thus, it is subject to the tunables, etc.
950 */
951 int
952 pci_msix_count_method(device_t dev, device_t child)
953 {
954 struct pci_devinfo *dinfo = device_get_ivars(child);
955 struct pcicfg_msix *msix = &dinfo->cfg.msix;
956
957 if (pci_do_msix && msix->msix_location != 0)
958 return (msix->msix_msgnum);
959 return (0);
960 }
961
962 /*
963 * HyperTransport MSI mapping control
964 */
965 void
966 pci_ht_map_msi(device_t dev, uint64_t addr)
967 {
968 struct pci_devinfo *dinfo = device_get_ivars(dev);
969 struct pcicfg_ht *ht = &dinfo->cfg.ht;
970
971 if (!ht->ht_msimap)
972 return;
973
974 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
975 ht->ht_msiaddr >> 20 == addr >> 20) {
976 /* Enable MSI -> HT mapping. */
977 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
978 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
979 ht->ht_msictrl, 2);
980 }
981
982 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
983 /* Disable MSI -> HT mapping. */
984 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
985 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
986 ht->ht_msictrl, 2);
987 }
988 }
989
990 /*
991 * Support for MSI message signalled interrupts.
992 */
993 void
994 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
995 {
996 struct pci_devinfo *dinfo = device_get_ivars(dev);
997 struct pcicfg_msi *msi = &dinfo->cfg.msi;
998
999 /* Write data and address values. */
1000 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1001 address & 0xffffffff, 4);
1002 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1003 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1004 address >> 32, 4);
1005 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1006 data, 2);
1007 } else
1008 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1009 2);
1010
1011 /* Enable MSI in the control register. */
1012 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1013 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1014 2);
1015
1016 /* Enable MSI -> HT mapping. */
1017 pci_ht_map_msi(dev, address);
1018 }
1019
1020 void
1021 pci_disable_msi(device_t dev)
1022 {
1023 struct pci_devinfo *dinfo = device_get_ivars(dev);
1024 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1025
1026 /* Disable MSI -> HT mapping. */
1027 pci_ht_map_msi(dev, 0);
1028
1029 /* Disable MSI in the control register. */
1030 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1031 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1032 2);
1033 }
1034
1035 /*
1036 * Restore MSI registers during resume. If MSI is enabled then
1037 * restore the data and address registers in addition to the control
1038 * register.
1039 */
1040 static void
1041 pci_resume_msi(device_t dev)
1042 {
1043 struct pci_devinfo *dinfo = device_get_ivars(dev);
1044 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1045 uint64_t address;
1046 uint16_t data;
1047
1048 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1049 address = msi->msi_addr;
1050 data = msi->msi_data;
1051 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1052 address & 0xffffffff, 4);
1053 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1054 pci_write_config(dev, msi->msi_location +
1055 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1056 pci_write_config(dev, msi->msi_location +
1057 PCIR_MSI_DATA_64BIT, data, 2);
1058 } else
1059 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1060 data, 2);
1061 }
1062 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1063 2);
1064 }
1065
1066 int
1067 pci_remap_msi_irq(device_t dev, u_int irq)
1068 {
1069 struct pci_devinfo *dinfo = device_get_ivars(dev);
1070 pcicfgregs *cfg = &dinfo->cfg;
1071 struct resource_list_entry *rle;
1072 struct msix_table_entry *mte;
1073 struct msix_vector *mv;
1074 device_t bus;
1075 uint64_t addr;
1076 uint32_t data;
1077 int error, i, j;
1078
1079 bus = device_get_parent(dev);
1080
1081 /*
1082 * Handle MSI first. We try to find this IRQ among our list
1083 * of MSI IRQs. If we find it, we request updated address and
1084 * data registers and apply the results.
1085 */
1086 if (cfg->msi.msi_alloc > 0) {
1087
1088 /* If we don't have any active handlers, nothing to do. */
1089 if (cfg->msi.msi_handlers == 0)
1090 return (0);
1091 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1092 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1093 i + 1);
1094 if (rle->start == irq) {
1095 error = PCIB_MAP_MSI(device_get_parent(bus),
1096 dev, irq, &addr, &data);
1097 if (error)
1098 return (error);
1099 pci_disable_msi(dev);
1100 dinfo->cfg.msi.msi_addr = addr;
1101 dinfo->cfg.msi.msi_data = data;
1102 pci_enable_msi(dev, addr, data);
1103 return (0);
1104 }
1105 }
1106 return (ENOENT);
1107 }
1108
1109 /*
1110 * For MSI-X, we check to see if we have this IRQ. If we do,
1111 * we request the updated mapping info. If that works, we go
1112 * through all the slots that use this IRQ and update them.
1113 */
1114 if (cfg->msix.msix_alloc > 0) {
1115 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1116 mv = &cfg->msix.msix_vectors[i];
1117 if (mv->mv_irq == irq) {
1118 error = PCIB_MAP_MSI(device_get_parent(bus),
1119 dev, irq, &addr, &data);
1120 if (error)
1121 return (error);
1122 mv->mv_address = addr;
1123 mv->mv_data = data;
1124 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1125 mte = &cfg->msix.msix_table[j];
1126 if (mte->mte_vector != i + 1)
1127 continue;
1128 if (mte->mte_handlers == 0)
1129 continue;
1130 pci_mask_msix(dev, j);
1131 pci_enable_msix(dev, j, addr, data);
1132 pci_unmask_msix(dev, j);
1133 }
1134 }
1135 }
1136 return (ENOENT);
1137 }
1138
1139 return (ENOENT);
1140 }
1141
1142 /*
1143 * Returns true if the specified device is blacklisted because MSI
1144 * doesn't work.
1145 */
1146 int
1147 pci_msi_device_blacklisted(device_t dev)
1148 {
1149 struct pci_quirk *q;
1150
1151 if (!pci_honor_msi_blacklist)
1152 return (0);
1153
1154 for (q = &pci_quirks[0]; q->devid; q++) {
1155 if (q->devid == pci_get_devid(dev) &&
1156 q->type == PCI_QUIRK_DISABLE_MSI)
1157 return (1);
1158 }
1159 return (0);
1160 }
1161
1162 /*
1163 * Determine if MSI is blacklisted globally on this sytem. Currently,
1164 * we just check for blacklisted chipsets as represented by the
1165 * host-PCI bridge at device 0:0:0. In the future, it may become
1166 * necessary to check other system attributes, such as the kenv values
1167 * that give the motherboard manufacturer and model number.
1168 */
1169 static int
1170 pci_msi_blacklisted(void)
1171 {
1172 device_t dev;
1173
1174 if (!pci_honor_msi_blacklist)
1175 return (0);
1176
1177 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1178 if (!(pcie_chipset || pcix_chipset))
1179 return (1);
1180
1181 dev = pci_find_bsf(0, 0, 0);
1182 if (dev != NULL)
1183 return (pci_msi_device_blacklisted(dev));
1184 return (0);
1185 }
1186
1187 /*
1188 * Attempt to allocate *count MSI messages. The actual number allocated is
1189 * returned in *count. After this function returns, each message will be
1190 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1191 */
1192 int
1193 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1194 {
1195 struct pci_devinfo *dinfo = device_get_ivars(child);
1196 pcicfgregs *cfg = &dinfo->cfg;
1197 struct resource_list_entry *rle;
1198 int actual, error, i, irqs[32];
1199 uint16_t ctrl;
1200
1201 /* Don't let count == 0 get us into trouble. */
1202 if (*count == 0)
1203 return (EINVAL);
1204
1205 /* If rid 0 is allocated, then fail. */
1206 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1207 if (rle != NULL && rle->res != NULL)
1208 return (ENXIO);
1209
1210 /* Already have allocated messages? */
1211 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1212 return (ENXIO);
1213
1214 /* If MSI is blacklisted for this system, fail. */
1215 if (pci_msi_blacklisted())
1216 return (ENXIO);
1217
1218 /* MSI capability present? */
1219 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1220 return (ENODEV);
1221
1222 if (bootverbose)
1223 device_printf(child,
1224 "attempting to allocate %d MSI vectors (%d supported)\n",
1225 *count, cfg->msi.msi_msgnum);
1226
1227 /* Don't ask for more than the device supports. */
1228 actual = min(*count, cfg->msi.msi_msgnum);
1229
1230 /* Don't ask for more than 32 messages. */
1231 actual = min(actual, 32);
1232
1233 /* MSI requires power of 2 number of messages. */
1234 if (!powerof2(actual))
1235 return (EINVAL);
1236
1237 for (;;) {
1238 /* Try to allocate N messages. */
1239 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1240 cfg->msi.msi_msgnum, irqs);
1241 if (error == 0)
1242 break;
1243 if (actual == 1)
1244 return (error);
1245
1246 /* Try N / 2. */
1247 actual >>= 1;
1248 }
1249
1250 /*
1251 * We now have N actual messages mapped onto SYS_RES_IRQ
1252 * resources in the irqs[] array, so add new resources
1253 * starting at rid 1.
1254 */
1255 for (i = 0; i < actual; i++)
1256 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1257 irqs[i], irqs[i], 1);
1258
1259 if (bootverbose) {
1260 if (actual == 1)
1261 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1262 else {
1263 int run;
1264
1265 /*
1266 * Be fancy and try to print contiguous runs
1267 * of IRQ values as ranges. 'run' is true if
1268 * we are in a range.
1269 */
1270 device_printf(child, "using IRQs %d", irqs[0]);
1271 run = 0;
1272 for (i = 1; i < actual; i++) {
1273
1274 /* Still in a run? */
1275 if (irqs[i] == irqs[i - 1] + 1) {
1276 run = 1;
1277 continue;
1278 }
1279
1280 /* Finish previous range. */
1281 if (run) {
1282 printf("-%d", irqs[i - 1]);
1283 run = 0;
1284 }
1285
1286 /* Start new range. */
1287 printf(",%d", irqs[i]);
1288 }
1289
1290 /* Unfinished range? */
1291 if (run)
1292 printf("-%d", irqs[actual - 1]);
1293 printf(" for MSI\n");
1294 }
1295 }
1296
1297 /* Update control register with actual count. */
1298 ctrl = cfg->msi.msi_ctrl;
1299 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1300 ctrl |= (ffs(actual) - 1) << 4;
1301 cfg->msi.msi_ctrl = ctrl;
1302 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1303
1304 /* Update counts of alloc'd messages. */
1305 cfg->msi.msi_alloc = actual;
1306 cfg->msi.msi_handlers = 0;
1307 *count = actual;
1308 return (0);
1309 }
1310
1311 /* Release the MSI messages associated with this device. */
1312 int
1313 pci_release_msi_method(device_t dev, device_t child)
1314 {
1315 struct pci_devinfo *dinfo = device_get_ivars(child);
1316 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1317 struct resource_list_entry *rle;
1318 int error, i, irqs[32];
1319
1320 /* Try MSI-X first. */
1321 error = pci_release_msix(dev, child);
1322 if (error != ENODEV)
1323 return (error);
1324
1325 /* Do we have any messages to release? */
1326 if (msi->msi_alloc == 0)
1327 return (ENODEV);
1328 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
1329
1330 /* Make sure none of the resources are allocated. */
1331 if (msi->msi_handlers > 0)
1332 return (EBUSY);
1333 for (i = 0; i < msi->msi_alloc; i++) {
1334 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1335 KASSERT(rle != NULL, ("missing MSI resource"));
1336 if (rle->res != NULL)
1337 return (EBUSY);
1338 irqs[i] = rle->start;
1339 }
1340
1341 /* Update control register with 0 count. */
1342 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
1343 ("%s: MSI still enabled", __func__));
1344 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
1345 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
1346 msi->msi_ctrl, 2);
1347
1348 /* Release the messages. */
1349 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
1350 for (i = 0; i < msi->msi_alloc; i++)
1351 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1352
1353 /* Update alloc count. */
1354 msi->msi_alloc = 0;
1355 msi->msi_addr = 0;
1356 msi->msi_data = 0;
1357 return (0);
1358 }
1359
1360 /*
1361 * Return the max supported MSI messages this device supports.
1362 * Basically, assuming the MD code can alloc messages, this function
1363 * should return the maximum value that pci_alloc_msi() can return.
1364 * Thus, it is subject to the tunables, etc.
1365 */
1366 int
1367 pci_msi_count_method(device_t dev, device_t child)
1368 {
1369 struct pci_devinfo *dinfo = device_get_ivars(child);
1370 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1371
1372 if (pci_do_msi && msi->msi_location != 0)
1373 return (msi->msi_msgnum);
1374 return (0);
1375 }
1376
1377 /* free pcicfgregs structure and all depending data structures */
1378
1379 int
1380 pci_freecfg(struct pci_devinfo *dinfo)
1381 {
1382 struct devlist *devlist_head;
1383
1384 devlist_head = &pci_devq;
1385
1386 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
1387 free(dinfo, M_DEVBUF);
1388
1389 /* increment the generation count */
1390 pci_generation++;
1391
1392 /* we're losing one device */
1393 pci_numdevs--;
1394 return (0);
1395 }
1396
1397 /*
1398 * PCI power manangement
1399 */
1400 int
1401 pci_set_powerstate_method(device_t dev, device_t child, int state)
1402 {
1403 struct pci_devinfo *dinfo = device_get_ivars(child);
1404 pcicfgregs *cfg = &dinfo->cfg;
1405 uint16_t status;
1406 int result, oldstate, highest, delay;
1407
1408 if (cfg->pp.pp_cap == 0)
1409 return (EOPNOTSUPP);
1410
1411 /*
1412 * Optimize a no state change request away. While it would be OK to
1413 * write to the hardware in theory, some devices have shown odd
1414 * behavior when going from D3 -> D3.
1415 */
1416 oldstate = pci_get_powerstate(child);
1417 if (oldstate == state)
1418 return (0);
1419
1420 /*
1421 * The PCI power management specification states that after a state
1422 * transition between PCI power states, system software must
1423 * guarantee a minimal delay before the function accesses the device.
1424 * Compute the worst case delay that we need to guarantee before we
1425 * access the device. Many devices will be responsive much more
1426 * quickly than this delay, but there are some that don't respond
1427 * instantly to state changes. Transitions to/from D3 state require
1428 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
1429 * is done below with DELAY rather than a sleeper function because
1430 * this function can be called from contexts where we cannot sleep.
1431 */
1432 highest = (oldstate > state) ? oldstate : state;
1433 if (highest == PCI_POWERSTATE_D3)
1434 delay = 10000;
1435 else if (highest == PCI_POWERSTATE_D2)
1436 delay = 200;
1437 else
1438 delay = 0;
1439 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
1440 & ~PCIM_PSTAT_DMASK;
1441 result = 0;
1442 switch (state) {
1443 case PCI_POWERSTATE_D0:
1444 status |= PCIM_PSTAT_D0;
1445 break;
1446 case PCI_POWERSTATE_D1:
1447 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
1448 return (EOPNOTSUPP);
1449 status |= PCIM_PSTAT_D1;
1450 break;
1451 case PCI_POWERSTATE_D2:
1452 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
1453 return (EOPNOTSUPP);
1454 status |= PCIM_PSTAT_D2;
1455 break;
1456 case PCI_POWERSTATE_D3:
1457 status |= PCIM_PSTAT_D3;
1458 break;
1459 default:
1460 return (EINVAL);
1461 }
1462
1463 if (bootverbose)
1464 printf(
1465 "pci%d:%d:%d: Transition from D%d to D%d\n",
1466 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func,
1467 oldstate, state);
1468
1469 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
1470 if (delay)
1471 DELAY(delay);
1472 return (0);
1473 }
1474
1475 int
1476 pci_get_powerstate_method(device_t dev, device_t child)
1477 {
1478 struct pci_devinfo *dinfo = device_get_ivars(child);
1479 pcicfgregs *cfg = &dinfo->cfg;
1480 uint16_t status;
1481 int result;
1482
1483 if (cfg->pp.pp_cap != 0) {
1484 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
1485 switch (status & PCIM_PSTAT_DMASK) {
1486 case PCIM_PSTAT_D0:
1487 result = PCI_POWERSTATE_D0;
1488 break;
1489 case PCIM_PSTAT_D1:
1490 result = PCI_POWERSTATE_D1;
1491 break;
1492 case PCIM_PSTAT_D2:
1493 result = PCI_POWERSTATE_D2;
1494 break;
1495 case PCIM_PSTAT_D3:
1496 result = PCI_POWERSTATE_D3;
1497 break;
1498 default:
1499 result = PCI_POWERSTATE_UNKNOWN;
1500 break;
1501 }
1502 } else {
1503 /* No support, device is always at D0 */
1504 result = PCI_POWERSTATE_D0;
1505 }
1506 return (result);
1507 }
1508
1509 /*
1510 * Some convenience functions for PCI device drivers.
1511 */
1512
1513 static __inline void
1514 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
1515 {
1516 uint16_t command;
1517
1518 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
1519 command |= bit;
1520 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
1521 }
1522
1523 static __inline void
1524 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
1525 {
1526 uint16_t command;
1527
1528 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
1529 command &= ~bit;
1530 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
1531 }
1532
1533 int
1534 pci_enable_busmaster_method(device_t dev, device_t child)
1535 {
1536 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
1537 return (0);
1538 }
1539
1540 int
1541 pci_disable_busmaster_method(device_t dev, device_t child)
1542 {
1543 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
1544 return (0);
1545 }
1546
1547 int
1548 pci_enable_io_method(device_t dev, device_t child, int space)
1549 {
1550 uint16_t command;
1551 uint16_t bit;
1552 char *error;
1553
1554 bit = 0;
1555 error = NULL;
1556
1557 switch(space) {
1558 case SYS_RES_IOPORT:
1559 bit = PCIM_CMD_PORTEN;
1560 error = "port";
1561 break;
1562 case SYS_RES_MEMORY:
1563 bit = PCIM_CMD_MEMEN;
1564 error = "memory";
1565 break;
1566 default:
1567 return (EINVAL);
1568 }
1569 pci_set_command_bit(dev, child, bit);
1570 /* Some devices seem to need a brief stall here, what do to? */
1571 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
1572 if (command & bit)
1573 return (0);
1574 device_printf(child, "failed to enable %s mapping!\n", error);
1575 return (ENXIO);
1576 }
1577
1578 int
1579 pci_disable_io_method(device_t dev, device_t child, int space)
1580 {
1581 uint16_t command;
1582 uint16_t bit;
1583 char *error;
1584
1585 bit = 0;
1586 error = NULL;
1587
1588 switch(space) {
1589 case SYS_RES_IOPORT:
1590 bit = PCIM_CMD_PORTEN;
1591 error = "port";
1592 break;
1593 case SYS_RES_MEMORY:
1594 bit = PCIM_CMD_MEMEN;
1595 error = "memory";
1596 break;
1597 default:
1598 return (EINVAL);
1599 }
1600 pci_clear_command_bit(dev, child, bit);
1601 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
1602 if (command & bit) {
1603 device_printf(child, "failed to disable %s mapping!\n", error);
1604 return (ENXIO);
1605 }
1606 return (0);
1607 }
1608
1609 /*
1610 * New style pci driver. Parent device is either a pci-host-bridge or a
1611 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1612 */
1613
1614 void
1615 pci_print_verbose(struct pci_devinfo *dinfo)
1616 {
1617 if (bootverbose) {
1618 pcicfgregs *cfg = &dinfo->cfg;
1619
1620 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1621 cfg->vendor, cfg->device, cfg->revid);
1622 printf("\tbus=%d, slot=%d, func=%d\n",
1623 cfg->bus, cfg->slot, cfg->func);
1624 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1625 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
1626 cfg->mfdev);
1627 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1628 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1629 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1630 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
1631 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1632 if (cfg->intpin > 0)
1633 printf("\tintpin=%c, irq=%d\n",
1634 cfg->intpin +'a' -1, cfg->intline);
1635 if (cfg->pp.pp_cap) {
1636 uint16_t status;
1637
1638 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
1639 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
1640 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
1641 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
1642 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
1643 status & PCIM_PSTAT_DMASK);
1644 }
1645 if (cfg->msi.msi_location) {
1646 int ctrl;
1647
1648 ctrl = cfg->msi.msi_ctrl;
1649 printf("\tMSI supports %d message%s%s%s\n",
1650 cfg->msi.msi_msgnum,
1651 (cfg->msi.msi_msgnum == 1) ? "" : "s",
1652 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
1653 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
1654 }
1655 if (cfg->msix.msix_location) {
1656 printf("\tMSI-X supports %d message%s ",
1657 cfg->msix.msix_msgnum,
1658 (cfg->msix.msix_msgnum == 1) ? "" : "s");
1659 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
1660 printf("in map 0x%x\n",
1661 cfg->msix.msix_table_bar);
1662 else
1663 printf("in maps 0x%x and 0x%x\n",
1664 cfg->msix.msix_table_bar,
1665 cfg->msix.msix_pba_bar);
1666 }
1667 }
1668 }
1669
1670 static int
1671 pci_porten(device_t pcib, int b, int s, int f)
1672 {
1673 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1674 & PCIM_CMD_PORTEN) != 0;
1675 }
1676
1677 static int
1678 pci_memen(device_t pcib, int b, int s, int f)
1679 {
1680 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1681 & PCIM_CMD_MEMEN) != 0;
1682 }
1683
1684 /*
1685 * Add a resource based on a pci map register. Return 1 if the map
1686 * register is a 32bit map register or 2 if it is a 64bit register.
1687 */
1688 static int
1689 pci_add_map(device_t pcib, device_t bus, device_t dev,
1690 int b, int s, int f, int reg, struct resource_list *rl, int force,
1691 int prefetch)
1692 {
1693 uint32_t map;
1694 uint64_t base;
1695 uint64_t start, end, count;
1696 uint8_t ln2size;
1697 uint8_t ln2range;
1698 uint32_t testval;
1699 uint16_t cmd;
1700 int type;
1701 int barlen;
1702 struct resource *res;
1703
1704 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1705 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1706 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1707 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1708
1709 if (pci_maptype(map) & PCI_MAPMEM) {
1710 type = SYS_RES_MEMORY;
1711 if (pci_maptype(map) & PCI_MAPMEMP)
1712 prefetch = 1;
1713 } else
1714 type = SYS_RES_IOPORT;
1715 ln2size = pci_mapsize(testval);
1716 ln2range = pci_maprange(testval);
1717 base = pci_mapbase(map);
1718 barlen = ln2range == 64 ? 2 : 1;
1719
1720 /*
1721 * For I/O registers, if bottom bit is set, and the next bit up
1722 * isn't clear, we know we have a BAR that doesn't conform to the
1723 * spec, so ignore it. Also, sanity check the size of the data
1724 * areas to the type of memory involved. Memory must be at least
1725 * 16 bytes in size, while I/O ranges must be at least 4.
1726 */
1727 if ((testval & 0x1) == 0x1 &&
1728 (testval & 0x2) != 0)
1729 return (barlen);
1730 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
1731 (type == SYS_RES_IOPORT && ln2size < 2))
1732 return (barlen);
1733
1734 if (ln2range == 64)
1735 /* Read the other half of a 64bit map register */
1736 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
1737
1738 if (bootverbose) {
1739 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
1740 reg, pci_maptype(map), ln2range,
1741 (unsigned int) base, ln2size);
1742 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1743 printf(", port disabled\n");
1744 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1745 printf(", memory disabled\n");
1746 else
1747 printf(", enabled\n");
1748 }
1749
1750 /*
1751 * If base is 0, then we have problems. It is best to ignore
1752 * such entries for the moment. These will be allocated later if
1753 * the driver specifically requests them. However, some
1754 * removable busses look better when all resources are allocated,
1755 * so allow '' to be overriden.
1756 *
1757 * Similarly treat maps whose values is the same as the test value
1758 * read back. These maps have had all f's written to them by the
1759 * BIOS in an attempt to disable the resources.
1760 */
1761 if (!force && (base == 0 || map == testval))
1762 return (barlen);
1763
1764 /*
1765 * This code theoretically does the right thing, but has
1766 * undesirable side effects in some cases where peripherals
1767 * respond oddly to having these bits enabled. Let the user
1768 * be able to turn them off (since pci_enable_io_modes is 1 by
1769 * default).
1770 */
1771 if (pci_enable_io_modes) {
1772 /* Turn on resources that have been left off by a lazy BIOS */
1773 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1774 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1775 cmd |= PCIM_CMD_PORTEN;
1776 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1777 }
1778 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1779 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1780 cmd |= PCIM_CMD_MEMEN;
1781 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1782 }
1783 } else {
1784 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1785 return (barlen);
1786 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1787 return (barlen);
1788 }
1789
1790 count = 1 << ln2size;
1791 if (base == 0 || base == pci_mapbase(testval)) {
1792 start = 0; /* Let the parent decide. */
1793 end = ~0ULL;
1794 } else {
1795 start = base;
1796 end = base + (1 << ln2size) - 1;
1797 }
1798 resource_list_add(rl, type, reg, start, end, count);
1799
1800 /*
1801 * Try to allocate the resource for this BAR from our parent
1802 * so that this resource range is already reserved. The
1803 * driver for this device will later inherit this resource in
1804 * pci_alloc_resource().
1805 */
1806 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
1807 prefetch ? RF_PREFETCHABLE : 0);
1808 if (res == NULL) {
1809 /*
1810 * If the allocation fails, clear the BAR and delete
1811 * the resource list entry to force
1812 * pci_alloc_resource() to allocate resources from the
1813 * parent.
1814 */
1815 resource_list_delete(rl, type, reg);
1816 start = 0;
1817 } else
1818 start = rman_get_start(res);
1819 pci_write_config(dev, reg, start, 4);
1820 if (ln2range == 64)
1821 pci_write_config(dev, reg + 4, start >> 32, 4);
1822 return (barlen);
1823 }
1824
1825 /*
1826 * For ATA devices we need to decide early what addressing mode to use.
1827 * Legacy demands that the primary and secondary ATA ports sits on the
1828 * same addresses that old ISA hardware did. This dictates that we use
1829 * those addresses and ignore the BAR's if we cannot set PCI native
1830 * addressing mode.
1831 */
1832 static void
1833 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
1834 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
1835 {
1836 int rid, type, progif;
1837 #if 0
1838 /* if this device supports PCI native addressing use it */
1839 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1840 if ((progif & 0x8a) == 0x8a) {
1841 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1842 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
1843 printf("Trying ATA native PCI addressing mode\n");
1844 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1845 }
1846 }
1847 #endif
1848 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1849 type = SYS_RES_IOPORT;
1850 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1851 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
1852 prefetchmask & (1 << 0));
1853 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
1854 prefetchmask & (1 << 1));
1855 } else {
1856 rid = PCIR_BAR(0);
1857 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1858 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1859 0);
1860 rid = PCIR_BAR(1);
1861 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1862 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1863 0);
1864 }
1865 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1866 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
1867 prefetchmask & (1 << 2));
1868 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
1869 prefetchmask & (1 << 3));
1870 } else {
1871 rid = PCIR_BAR(2);
1872 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1873 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1874 0);
1875 rid = PCIR_BAR(3);
1876 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1877 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1878 0);
1879 }
1880 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
1881 prefetchmask & (1 << 4));
1882 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
1883 prefetchmask & (1 << 5));
1884 }
1885
1886 static void
1887 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
1888 {
1889 struct pci_devinfo *dinfo = device_get_ivars(dev);
1890 pcicfgregs *cfg = &dinfo->cfg;
1891 char tunable_name[64];
1892 int irq;
1893
1894 /* Has to have an intpin to have an interrupt. */
1895 if (cfg->intpin == 0)
1896 return;
1897
1898 /* Let the user override the IRQ with a tunable. */
1899 irq = PCI_INVALID_IRQ;
1900 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq",
1901 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
1902 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
1903 irq = PCI_INVALID_IRQ;
1904
1905 /*
1906 * If we didn't get an IRQ via the tunable, then we either use the
1907 * IRQ value in the intline register or we ask the bus to route an
1908 * interrupt for us. If force_route is true, then we only use the
1909 * value in the intline register if the bus was unable to assign an
1910 * IRQ.
1911 */
1912 if (!PCI_INTERRUPT_VALID(irq)) {
1913 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
1914 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
1915 if (!PCI_INTERRUPT_VALID(irq))
1916 irq = cfg->intline;
1917 }
1918
1919 /* If after all that we don't have an IRQ, just bail. */
1920 if (!PCI_INTERRUPT_VALID(irq))
1921 return;
1922
1923 /* Update the config register if it changed. */
1924 if (irq != cfg->intline) {
1925 cfg->intline = irq;
1926 pci_write_config(dev, PCIR_INTLINE, irq, 1);
1927 }
1928
1929 /* Add this IRQ as rid 0 interrupt resource. */
1930 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
1931 }
1932
1933 void
1934 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
1935 {
1936 device_t pcib;
1937 struct pci_devinfo *dinfo = device_get_ivars(dev);
1938 pcicfgregs *cfg = &dinfo->cfg;
1939 struct resource_list *rl = &dinfo->resources;
1940 struct pci_quirk *q;
1941 int b, i, f, s;
1942
1943 pcib = device_get_parent(bus);
1944
1945 b = cfg->bus;
1946 s = cfg->slot;
1947 f = cfg->func;
1948
1949 /* ATA devices needs special map treatment */
1950 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1951 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
1952 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1953 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1954 !pci_read_config(dev, PCIR_BAR(2), 4))) )
1955 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
1956 else
1957 for (i = 0; i < cfg->nummaps;)
1958 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
1959 rl, force, prefetchmask & (1 << i));
1960
1961 /*
1962 * Add additional, quirked resources.
1963 */
1964 for (q = &pci_quirks[0]; q->devid; q++) {
1965 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1966 && q->type == PCI_QUIRK_MAP_REG)
1967 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
1968 force, 0);
1969 }
1970
1971 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1972 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \
1973 defined(__arm__) || defined(__alpha__)
1974 /*
1975 * Try to re-route interrupts. Sometimes the BIOS or
1976 * firmware may leave bogus values in these registers.
1977 * If the re-route fails, then just stick with what we
1978 * have.
1979 */
1980 pci_assign_interrupt(bus, dev, 1);
1981 #else
1982 pci_assign_interrupt(bus, dev, 0);
1983 #endif
1984 }
1985 }
1986
1987 void
1988 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1989 {
1990 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1991 device_t pcib = device_get_parent(dev);
1992 struct pci_devinfo *dinfo;
1993 int maxslots;
1994 int s, f, pcifunchigh;
1995 uint8_t hdrtype;
1996
1997 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
1998 ("dinfo_size too small"));
1999 maxslots = PCIB_MAXSLOTS(pcib);
2000 for (s = 0; s <= maxslots; s++) {
2001 pcifunchigh = 0;
2002 f = 0;
2003 DELAY(1);
2004 hdrtype = REG(PCIR_HDRTYPE, 1);
2005 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2006 continue;
2007 if (hdrtype & PCIM_MFDEV)
2008 pcifunchigh = PCI_FUNCMAX;
2009 for (f = 0; f <= pcifunchigh; f++) {
2010 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
2011 if (dinfo != NULL) {
2012 pci_add_child(dev, dinfo);
2013 }
2014 }
2015 }
2016 #undef REG
2017 }
2018
2019 void
2020 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2021 {
2022 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2023 device_set_ivars(dinfo->cfg.dev, dinfo);
2024 resource_list_init(&dinfo->resources);
2025 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2026 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2027 pci_print_verbose(dinfo);
2028 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
2029 }
2030
2031 static int
2032 pci_probe(device_t dev)
2033 {
2034
2035 device_set_desc(dev, "PCI bus");
2036
2037 /* Allow other subclasses to override this driver. */
2038 return (-1000);
2039 }
2040
2041 static int
2042 pci_attach(device_t dev)
2043 {
2044 int busno;
2045
2046 /*
2047 * Since there can be multiple independantly numbered PCI
2048 * busses on some large alpha systems, we can't use the unit
2049 * number to decide what bus we are probing. We ask the parent
2050 * pcib what our bus number is.
2051 */
2052 busno = pcib_get_bus(dev);
2053 if (bootverbose)
2054 device_printf(dev, "physical bus=%d\n", busno);
2055
2056 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
2057
2058 return (bus_generic_attach(dev));
2059 }
2060
2061 int
2062 pci_suspend(device_t dev)
2063 {
2064 int dstate, error, i, numdevs;
2065 device_t acpi_dev, child, *devlist;
2066 struct pci_devinfo *dinfo;
2067
2068 /*
2069 * Save the PCI configuration space for each child and set the
2070 * device in the appropriate power state for this sleep state.
2071 */
2072 acpi_dev = NULL;
2073 if (pci_do_power_resume)
2074 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2075 device_get_children(dev, &devlist, &numdevs);
2076 for (i = 0; i < numdevs; i++) {
2077 child = devlist[i];
2078 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2079 pci_cfg_save(child, dinfo, 0);
2080 }
2081
2082 /* Suspend devices before potentially powering them down. */
2083 error = bus_generic_suspend(dev);
2084 if (error) {
2085 free(devlist, M_TEMP);
2086 return (error);
2087 }
2088
2089 /*
2090 * Always set the device to D3. If ACPI suggests a different
2091 * power state, use it instead. If ACPI is not present, the
2092 * firmware is responsible for managing device power. Skip
2093 * children who aren't attached since they are powered down
2094 * separately. Only manage type 0 devices for now.
2095 */
2096 for (i = 0; acpi_dev && i < numdevs; i++) {
2097 child = devlist[i];
2098 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2099 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2100 dstate = PCI_POWERSTATE_D3;
2101 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2102 pci_set_powerstate(child, dstate);
2103 }
2104 }
2105 free(devlist, M_TEMP);
2106 return (0);
2107 }
2108
2109 int
2110 pci_resume(device_t dev)
2111 {
2112 int i, numdevs;
2113 device_t acpi_dev, child, *devlist;
2114 struct pci_devinfo *dinfo;
2115
2116 /*
2117 * Set each child to D0 and restore its PCI configuration space.
2118 */
2119 acpi_dev = NULL;
2120 if (pci_do_power_resume)
2121 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2122 device_get_children(dev, &devlist, &numdevs);
2123 for (i = 0; i < numdevs; i++) {
2124 /*
2125 * Notify ACPI we're going to D0 but ignore the result. If
2126 * ACPI is not present, the firmware is responsible for
2127 * managing device power. Only manage type 0 devices for now.
2128 */
2129 child = devlist[i];
2130 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2131 if (acpi_dev && device_is_attached(child) &&
2132 dinfo->cfg.hdrtype == 0) {
2133 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2134 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2135 }
2136
2137 /* Now the device is powered up, restore its config space. */
2138 pci_cfg_restore(child, dinfo);
2139 }
2140 free(devlist, M_TEMP);
2141 return (bus_generic_resume(dev));
2142 }
2143
2144 static void
2145 pci_load_vendor_data(void)
2146 {
2147 caddr_t vendordata, info;
2148
2149 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2150 info = preload_search_info(vendordata, MODINFO_ADDR);
2151 pci_vendordata = *(char **)info;
2152 info = preload_search_info(vendordata, MODINFO_SIZE);
2153 pci_vendordata_size = *(size_t *)info;
2154 /* terminate the database */
2155 pci_vendordata[pci_vendordata_size] = '\n';
2156 }
2157 }
2158
2159 void
2160 pci_driver_added(device_t dev, driver_t *driver)
2161 {
2162 int numdevs;
2163 device_t *devlist;
2164 device_t child;
2165 struct pci_devinfo *dinfo;
2166 int i;
2167
2168 if (bootverbose)
2169 device_printf(dev, "driver added\n");
2170 DEVICE_IDENTIFY(driver, dev);
2171 device_get_children(dev, &devlist, &numdevs);
2172 for (i = 0; i < numdevs; i++) {
2173 child = devlist[i];
2174 if (device_get_state(child) != DS_NOTPRESENT)
2175 continue;
2176 dinfo = device_get_ivars(child);
2177 pci_print_verbose(dinfo);
2178 if (bootverbose)
2179 printf("pci%d:%d:%d: reprobing on driver added\n",
2180 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
2181 pci_cfg_restore(child, dinfo);
2182 if (device_probe_and_attach(child) != 0)
2183 pci_cfg_save(child, dinfo, 1);
2184 }
2185 free(devlist, M_TEMP);
2186 }
2187
2188 int
2189 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2190 driver_intr_t *intr, void *arg, void **cookiep)
2191 {
2192 struct pci_devinfo *dinfo;
2193 struct msix_table_entry *mte;
2194 struct msix_vector *mv;
2195 uint64_t addr;
2196 uint32_t data;
2197 void *cookie;
2198 int error, rid;
2199
2200 error = bus_generic_setup_intr(dev, child, irq, flags, intr, arg,
2201 &cookie);
2202 if (error)
2203 return (error);
2204
2205 /*
2206 * If this is a direct child, check to see if the interrupt is
2207 * MSI or MSI-X. If so, ask our parent to map the MSI and give
2208 * us the address and data register values. If we fail for some
2209 * reason, teardown the interrupt handler.
2210 */
2211 rid = rman_get_rid(irq);
2212 if (device_get_parent(child) == dev && rid > 0) {
2213 dinfo = device_get_ivars(child);
2214 if (dinfo->cfg.msi.msi_alloc > 0) {
2215 if (dinfo->cfg.msi.msi_addr == 0) {
2216 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
2217 ("MSI has handlers, but vectors not mapped"));
2218 error = PCIB_MAP_MSI(device_get_parent(dev),
2219 child, rman_get_start(irq), &addr, &data);
2220 if (error)
2221 goto bad;
2222 dinfo->cfg.msi.msi_addr = addr;
2223 dinfo->cfg.msi.msi_data = data;
2224 }
2225 if (dinfo->cfg.msi.msi_handlers == 0)
2226 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
2227 dinfo->cfg.msi.msi_data);
2228 dinfo->cfg.msi.msi_handlers++;
2229 } else {
2230 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2231 ("No MSI or MSI-X interrupts allocated"));
2232 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2233 ("MSI-X index too high"));
2234 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2235 KASSERT(mte->mte_vector != 0, ("no message vector"));
2236 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
2237 KASSERT(mv->mv_irq == rman_get_start(irq),
2238 ("IRQ mismatch"));
2239 if (mv->mv_address == 0) {
2240 KASSERT(mte->mte_handlers == 0,
2241 ("MSI-X table entry has handlers, but vector not mapped"));
2242 error = PCIB_MAP_MSI(device_get_parent(dev),
2243 child, rman_get_start(irq), &addr, &data);
2244 if (error)
2245 goto bad;
2246 mv->mv_address = addr;
2247 mv->mv_data = data;
2248 }
2249 if (mte->mte_handlers == 0) {
2250 pci_enable_msix(child, rid - 1, mv->mv_address,
2251 mv->mv_data);
2252 pci_unmask_msix(child, rid - 1);
2253 }
2254 mte->mte_handlers++;
2255 }
2256 bad:
2257 if (error) {
2258 (void)bus_generic_teardown_intr(dev, child, irq,
2259 cookie);
2260 return (error);
2261 }
2262 }
2263 *cookiep = cookie;
2264 return (0);
2265 }
2266
2267 int
2268 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
2269 void *cookie)
2270 {
2271 struct msix_table_entry *mte;
2272 struct resource_list_entry *rle;
2273 struct pci_devinfo *dinfo;
2274 int error, rid;
2275
2276 /*
2277 * If this is a direct child, check to see if the interrupt is
2278 * MSI or MSI-X. If so, decrement the appropriate handlers
2279 * count and mask the MSI-X message, or disable MSI messages
2280 * if the count drops to 0.
2281 */
2282 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
2283 return (EINVAL);
2284 rid = rman_get_rid(irq);
2285 if (device_get_parent(child) == dev && rid > 0) {
2286 dinfo = device_get_ivars(child);
2287 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
2288 if (rle->res != irq)
2289 return (EINVAL);
2290 if (dinfo->cfg.msi.msi_alloc > 0) {
2291 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
2292 ("MSI-X index too high"));
2293 if (dinfo->cfg.msi.msi_handlers == 0)
2294 return (EINVAL);
2295 dinfo->cfg.msi.msi_handlers--;
2296 if (dinfo->cfg.msi.msi_handlers == 0)
2297 pci_disable_msi(child);
2298 } else {
2299 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2300 ("No MSI or MSI-X interrupts allocated"));
2301 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2302 ("MSI-X index too high"));
2303 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2304 if (mte->mte_handlers == 0)
2305 return (EINVAL);
2306 mte->mte_handlers--;
2307 if (mte->mte_handlers == 0)
2308 pci_mask_msix(child, rid - 1);
2309 }
2310 }
2311 error = bus_generic_teardown_intr(dev, child, irq, cookie);
2312 if (device_get_parent(child) == dev && rid > 0)
2313 KASSERT(error == 0,
2314 ("%s: generic teardown failed for MSI/MSI-X", __func__));
2315 return (error);
2316 }
2317
2318 int
2319 pci_print_child(device_t dev, device_t child)
2320 {
2321 struct pci_devinfo *dinfo;
2322 struct resource_list *rl;
2323 int retval = 0;
2324
2325 dinfo = device_get_ivars(child);
2326 rl = &dinfo->resources;
2327
2328 retval += bus_print_child_header(dev, child);
2329
2330 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
2331 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
2332 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
2333 if (device_get_flags(dev))
2334 retval += printf(" flags %#x", device_get_flags(dev));
2335
2336 retval += printf(" at device %d.%d", pci_get_slot(child),
2337 pci_get_function(child));
2338
2339 retval += bus_print_child_footer(dev, child);
2340
2341 return (retval);
2342 }
2343
2344 static struct
2345 {
2346 int class;
2347 int subclass;
2348 char *desc;
2349 } pci_nomatch_tab[] = {
2350 {PCIC_OLD, -1, "old"},
2351 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
2352 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
2353 {PCIC_STORAGE, -1, "mass storage"},
2354 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
2355 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
2356 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
2357 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
2358 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
2359 {PCIC_NETWORK, -1, "network"},
2360 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
2361 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
2362 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
2363 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
2364 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
2365 {PCIC_DISPLAY, -1, "display"},
2366 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
2367 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
2368 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
2369 {PCIC_MULTIMEDIA, -1, "multimedia"},
2370 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
2371 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
2372 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
2373 {PCIC_MEMORY, -1, "memory"},
2374 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
2375 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
2376 {PCIC_BRIDGE, -1, "bridge"},
2377 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
2378 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
2379 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
2380 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
2381 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
2382 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
2383 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
2384 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
2385 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
2386 {PCIC_SIMPLECOMM, -1, "simple comms"},
2387 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
2388 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
2389 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
2390 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
2391 {PCIC_BASEPERIPH, -1, "base peripheral"},
2392 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
2393 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
2394 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
2395 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
2396 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
2397 {PCIC_INPUTDEV, -1, "input device"},
2398 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
2399 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
2400 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
2401 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
2402 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
2403 {PCIC_DOCKING, -1, "docking station"},
2404 {PCIC_PROCESSOR, -1, "processor"},
2405 {PCIC_SERIALBUS, -1, "serial bus"},
2406 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
2407 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
2408 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
2409 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
2410 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
2411 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
2412 {PCIC_WIRELESS, -1, "wireless controller"},
2413 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
2414 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
2415 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
2416 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
2417 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
2418 {PCIC_SATCOM, -1, "satellite communication"},
2419 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
2420 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
2421 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
2422 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
2423 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
2424 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
2425 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
2426 {PCIC_DASP, -1, "dasp"},
2427 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
2428 {0, 0, NULL}
2429 };
2430
2431 void
2432 pci_probe_nomatch(device_t dev, device_t child)
2433 {
2434 int i;
2435 char *cp, *scp, *device;
2436
2437 /*
2438 * Look for a listing for this device in a loaded device database.
2439 */
2440 if ((device = pci_describe_device(child)) != NULL) {
2441 device_printf(dev, "<%s>", device);
2442 free(device, M_DEVBUF);
2443 } else {
2444 /*
2445 * Scan the class/subclass descriptions for a general
2446 * description.
2447 */
2448 cp = "unknown";
2449 scp = NULL;
2450 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
2451 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
2452 if (pci_nomatch_tab[i].subclass == -1) {
2453 cp = pci_nomatch_tab[i].desc;
2454 } else if (pci_nomatch_tab[i].subclass ==
2455 pci_get_subclass(child)) {
2456 scp = pci_nomatch_tab[i].desc;
2457 }
2458 }
2459 }
2460 device_printf(dev, "<%s%s%s>",
2461 cp ? cp : "",
2462 ((cp != NULL) && (scp != NULL)) ? ", " : "",
2463 scp ? scp : "");
2464 }
2465 printf(" at device %d.%d (no driver attached)\n",
2466 pci_get_slot(child), pci_get_function(child));
2467 if (pci_do_power_nodriver)
2468 pci_cfg_save(child,
2469 (struct pci_devinfo *) device_get_ivars(child), 1);
2470 return;
2471 }
2472
2473 /*
2474 * Parse the PCI device database, if loaded, and return a pointer to a
2475 * description of the device.
2476 *
2477 * The database is flat text formatted as follows:
2478 *
2479 * Any line not in a valid format is ignored.
2480 * Lines are terminated with newline '\n' characters.
2481 *
2482 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
2483 * the vendor name.
2484 *
2485 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
2486 * - devices cannot be listed without a corresponding VENDOR line.
2487 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
2488 * another TAB, then the device name.
2489 */
2490
2491 /*
2492 * Assuming (ptr) points to the beginning of a line in the database,
2493 * return the vendor or device and description of the next entry.
2494 * The value of (vendor) or (device) inappropriate for the entry type
2495 * is set to -1. Returns nonzero at the end of the database.
2496 *
2497 * Note that this is slightly unrobust in the face of corrupt data;
2498 * we attempt to safeguard against this by spamming the end of the
2499 * database with a newline when we initialise.
2500 */
2501 static int
2502 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
2503 {
2504 char *cp = *ptr;
2505 int left;
2506
2507 *device = -1;
2508 *vendor = -1;
2509 **desc = '\0';
2510 for (;;) {
2511 left = pci_vendordata_size - (cp - pci_vendordata);
2512 if (left <= 0) {
2513 *ptr = cp;
2514 return(1);
2515 }
2516
2517 /* vendor entry? */
2518 if (*cp != '\t' &&
2519 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
2520 break;
2521 /* device entry? */
2522 if (*cp == '\t' &&
2523 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
2524 break;
2525
2526 /* skip to next line */
2527 while (*cp != '\n' && left > 0) {
2528 cp++;
2529 left--;
2530 }
2531 if (*cp == '\n') {
2532 cp++;
2533 left--;
2534 }
2535 }
2536 /* skip to next line */
2537 while (*cp != '\n' && left > 0) {
2538 cp++;
2539 left--;
2540 }
2541 if (*cp == '\n' && left > 0)
2542 cp++;
2543 *ptr = cp;
2544 return(0);
2545 }
2546
2547 static char *
2548 pci_describe_device(device_t dev)
2549 {
2550 int vendor, device;
2551 char *desc, *vp, *dp, *line;
2552
2553 desc = vp = dp = NULL;
2554
2555 /*
2556 * If we have no vendor data, we can't do anything.
2557 */
2558 if (pci_vendordata == NULL)
2559 goto out;
2560
2561 /*
2562 * Scan the vendor data looking for this device
2563 */
2564 line = pci_vendordata;
2565 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
2566 goto out;
2567 for (;;) {
2568 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
2569 goto out;
2570 if (vendor == pci_get_vendor(dev))
2571 break;
2572 }
2573 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
2574 goto out;
2575 for (;;) {
2576 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
2577 *dp = 0;
2578 break;
2579 }
2580 if (vendor != -1) {
2581 *dp = 0;
2582 break;
2583 }
2584 if (device == pci_get_device(dev))
2585 break;
2586 }
2587 if (dp[0] == '\0')
2588 snprintf(dp, 80, "0x%x", pci_get_device(dev));
2589 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
2590 NULL)
2591 sprintf(desc, "%s, %s", vp, dp);
2592 out:
2593 if (vp != NULL)
2594 free(vp, M_DEVBUF);
2595 if (dp != NULL)
2596 free(dp, M_DEVBUF);
2597 return(desc);
2598 }
2599
2600 int
2601 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
2602 {
2603 struct pci_devinfo *dinfo;
2604 pcicfgregs *cfg;
2605
2606 dinfo = device_get_ivars(child);
2607 cfg = &dinfo->cfg;
2608
2609 switch (which) {
2610 case PCI_IVAR_ETHADDR:
2611 /*
2612 * The generic accessor doesn't deal with failure, so
2613 * we set the return value, then return an error.
2614 */
2615 *((uint8_t **) result) = NULL;
2616 return (EINVAL);
2617 case PCI_IVAR_SUBVENDOR:
2618 *result = cfg->subvendor;
2619 break;
2620 case PCI_IVAR_SUBDEVICE:
2621 *result = cfg->subdevice;
2622 break;
2623 case PCI_IVAR_VENDOR:
2624 *result = cfg->vendor;
2625 break;
2626 case PCI_IVAR_DEVICE:
2627 *result = cfg->device;
2628 break;
2629 case PCI_IVAR_DEVID:
2630 *result = (cfg->device << 16) | cfg->vendor;
2631 break;
2632 case PCI_IVAR_CLASS:
2633 *result = cfg->baseclass;
2634 break;
2635 case PCI_IVAR_SUBCLASS:
2636 *result = cfg->subclass;
2637 break;
2638 case PCI_IVAR_PROGIF:
2639 *result = cfg->progif;
2640 break;
2641 case PCI_IVAR_REVID:
2642 *result = cfg->revid;
2643 break;
2644 case PCI_IVAR_INTPIN:
2645 *result = cfg->intpin;
2646 break;
2647 case PCI_IVAR_IRQ:
2648 *result = cfg->intline;
2649 break;
2650 case PCI_IVAR_BUS:
2651 *result = cfg->bus;
2652 break;
2653 case PCI_IVAR_SLOT:
2654 *result = cfg->slot;
2655 break;
2656 case PCI_IVAR_FUNCTION:
2657 *result = cfg->func;
2658 break;
2659 case PCI_IVAR_CMDREG:
2660 *result = cfg->cmdreg;
2661 break;
2662 case PCI_IVAR_CACHELNSZ:
2663 *result = cfg->cachelnsz;
2664 break;
2665 case PCI_IVAR_MINGNT:
2666 *result = cfg->mingnt;
2667 break;
2668 case PCI_IVAR_MAXLAT:
2669 *result = cfg->maxlat;
2670 break;
2671 case PCI_IVAR_LATTIMER:
2672 *result = cfg->lattimer;
2673 break;
2674 default:
2675 return (ENOENT);
2676 }
2677 return (0);
2678 }
2679
2680 int
2681 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
2682 {
2683 struct pci_devinfo *dinfo;
2684
2685 dinfo = device_get_ivars(child);
2686
2687 switch (which) {
2688 case PCI_IVAR_INTPIN:
2689 dinfo->cfg.intpin = value;
2690 return (0);
2691 case PCI_IVAR_ETHADDR:
2692 case PCI_IVAR_SUBVENDOR:
2693 case PCI_IVAR_SUBDEVICE:
2694 case PCI_IVAR_VENDOR:
2695 case PCI_IVAR_DEVICE:
2696 case PCI_IVAR_DEVID:
2697 case PCI_IVAR_CLASS:
2698 case PCI_IVAR_SUBCLASS:
2699 case PCI_IVAR_PROGIF:
2700 case PCI_IVAR_REVID:
2701 case PCI_IVAR_IRQ:
2702 case PCI_IVAR_BUS:
2703 case PCI_IVAR_SLOT:
2704 case PCI_IVAR_FUNCTION:
2705 return (EINVAL); /* disallow for now */
2706
2707 default:
2708 return (ENOENT);
2709 }
2710 }
2711
2712
2713 #include "opt_ddb.h"
2714 #ifdef DDB
2715 #include <ddb/ddb.h>
2716 #include <sys/cons.h>
2717
2718 /*
2719 * List resources based on pci map registers, used for within ddb
2720 */
2721
2722 DB_SHOW_COMMAND(pciregs, db_pci_dump)
2723 {
2724 struct pci_devinfo *dinfo;
2725 struct devlist *devlist_head;
2726 struct pci_conf *p;
2727 const char *name;
2728 int i, error, none_count, quit;
2729
2730 none_count = 0;
2731 /* get the head of the device queue */
2732 devlist_head = &pci_devq;
2733
2734 /*
2735 * Go through the list of devices and print out devices
2736 */
2737 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
2738 for (error = 0, i = 0, quit = 0,
2739 dinfo = STAILQ_FIRST(devlist_head);
2740 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit;
2741 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
2742
2743 /* Populate pd_name and pd_unit */
2744 name = NULL;
2745 if (dinfo->cfg.dev)
2746 name = device_get_name(dinfo->cfg.dev);
2747
2748 p = &dinfo->conf;
2749 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x "
2750 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
2751 (name && *name) ? name : "none",
2752 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
2753 none_count++,
2754 p->pc_sel.pc_bus, p->pc_sel.pc_dev,
2755 p->pc_sel.pc_func, (p->pc_class << 16) |
2756 (p->pc_subclass << 8) | p->pc_progif,
2757 (p->pc_subdevice << 16) | p->pc_subvendor,
2758 (p->pc_device << 16) | p->pc_vendor,
2759 p->pc_revid, p->pc_hdr);
2760 }
2761 }
2762 #endif /* DDB */
2763
2764 static struct resource *
2765 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
2766 u_long start, u_long end, u_long count, u_int flags)
2767 {
2768 struct pci_devinfo *dinfo = device_get_ivars(child);
2769 struct resource_list *rl = &dinfo->resources;
2770 struct resource_list_entry *rle;
2771 struct resource *res;
2772 uint32_t map, testval;
2773 int mapsize;
2774
2775 /*
2776 * Weed out the bogons, and figure out how large the BAR/map
2777 * is. Bars that read back 0 here are bogus and unimplemented.
2778 * Note: atapci in legacy mode are special and handled elsewhere
2779 * in the code. If you have a atapci device in legacy mode and
2780 * it fails here, that other code is broken.
2781 */
2782 res = NULL;
2783 map = pci_read_config(child, *rid, 4);
2784 pci_write_config(child, *rid, 0xffffffff, 4);
2785 testval = pci_read_config(child, *rid, 4);
2786 if (pci_mapbase(testval) == 0)
2787 goto out;
2788 if (pci_maptype(testval) & PCI_MAPMEM) {
2789 if (type != SYS_RES_MEMORY) {
2790 if (bootverbose)
2791 device_printf(dev,
2792 "child %s requested type %d for rid %#x,"
2793 " but the BAR says it is an memio\n",
2794 device_get_nameunit(child), type, *rid);
2795 goto out;
2796 }
2797 } else {
2798 if (type != SYS_RES_IOPORT) {
2799 if (bootverbose)
2800 device_printf(dev,
2801 "child %s requested type %d for rid %#x,"
2802 " but the BAR says it is an ioport\n",
2803 device_get_nameunit(child), type, *rid);
2804 goto out;
2805 }
2806 }
2807 /*
2808 * For real BARs, we need to override the size that
2809 * the driver requests, because that's what the BAR
2810 * actually uses and we would otherwise have a
2811 * situation where we might allocate the excess to
2812 * another driver, which won't work.
2813 */
2814 mapsize = pci_mapsize(testval);
2815 count = 1 << mapsize;
2816 if (RF_ALIGNMENT(flags) < mapsize)
2817 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
2818 if (pci_maptype(testval) & PCI_MAPMEMP)
2819 flags |= RF_PREFETCHABLE;
2820
2821 /*
2822 * Allocate enough resource, and then write back the
2823 * appropriate bar for that resource.
2824 */
2825 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
2826 start, end, count, flags);
2827 if (res == NULL) {
2828 device_printf(child,
2829 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
2830 count, *rid, type, start, end);
2831 goto out;
2832 }
2833 resource_list_add(rl, type, *rid, start, end, count);
2834 rle = resource_list_find(rl, type, *rid);
2835 if (rle == NULL)
2836 panic("pci_alloc_map: unexpectedly can't find resource.");
2837 rle->res = res;
2838 rle->start = rman_get_start(res);
2839 rle->end = rman_get_end(res);
2840 rle->count = count;
2841 if (bootverbose)
2842 device_printf(child,
2843 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
2844 count, *rid, type, rman_get_start(res));
2845 map = rman_get_start(res);
2846 out:;
2847 pci_write_config(child, *rid, map, 4);
2848 return (res);
2849 }
2850
2851
2852 struct resource *
2853 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2854 u_long start, u_long end, u_long count, u_int flags)
2855 {
2856 struct pci_devinfo *dinfo = device_get_ivars(child);
2857 struct resource_list *rl = &dinfo->resources;
2858 struct resource_list_entry *rle;
2859 pcicfgregs *cfg = &dinfo->cfg;
2860
2861 /*
2862 * Perform lazy resource allocation
2863 */
2864 if (device_get_parent(child) == dev) {
2865 switch (type) {
2866 case SYS_RES_IRQ:
2867 /*
2868 * Can't alloc legacy interrupt once MSI messages
2869 * have been allocated.
2870 */
2871 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
2872 cfg->msix.msix_alloc > 0))
2873 return (NULL);
2874 /*
2875 * If the child device doesn't have an
2876 * interrupt routed and is deserving of an
2877 * interrupt, try to assign it one.
2878 */
2879 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
2880 (cfg->intpin != 0))
2881 pci_assign_interrupt(dev, child, 0);
2882 break;
2883 case SYS_RES_IOPORT:
2884 case SYS_RES_MEMORY:
2885 if (*rid < PCIR_BAR(cfg->nummaps)) {
2886 /*
2887 * Enable the I/O mode. We should
2888 * also be assigning resources too
2889 * when none are present. The
2890 * resource_list_alloc kind of sorta does
2891 * this...
2892 */
2893 if (PCI_ENABLE_IO(dev, child, type))
2894 return (NULL);
2895 }
2896 rle = resource_list_find(rl, type, *rid);
2897 if (rle == NULL)
2898 return (pci_alloc_map(dev, child, type, rid,
2899 start, end, count, flags));
2900 break;
2901 }
2902 /*
2903 * If we've already allocated the resource, then
2904 * return it now. But first we may need to activate
2905 * it, since we don't allocate the resource as active
2906 * above. Normally this would be done down in the
2907 * nexus, but since we short-circuit that path we have
2908 * to do its job here. Not sure if we should free the
2909 * resource if it fails to activate.
2910 */
2911 rle = resource_list_find(rl, type, *rid);
2912 if (rle != NULL && rle->res != NULL) {
2913 if (bootverbose)
2914 device_printf(child,
2915 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
2916 rman_get_size(rle->res), *rid, type,
2917 rman_get_start(rle->res));
2918 if ((flags & RF_ACTIVE) &&
2919 bus_generic_activate_resource(dev, child, type,
2920 *rid, rle->res) != 0)
2921 return NULL;
2922 return (rle->res);
2923 }
2924 }
2925 return (resource_list_alloc(rl, dev, child, type, rid,
2926 start, end, count, flags));
2927 }
2928
2929 void
2930 pci_delete_resource(device_t dev, device_t child, int type, int rid)
2931 {
2932 struct pci_devinfo *dinfo;
2933 struct resource_list *rl;
2934 struct resource_list_entry *rle;
2935
2936 if (device_get_parent(child) != dev)
2937 return;
2938
2939 dinfo = device_get_ivars(child);
2940 rl = &dinfo->resources;
2941 rle = resource_list_find(rl, type, rid);
2942 if (rle) {
2943 if (rle->res) {
2944 if (rman_get_device(rle->res) != dev ||
2945 rman_get_flags(rle->res) & RF_ACTIVE) {
2946 device_printf(dev, "delete_resource: "
2947 "Resource still owned by child, oops. "
2948 "(type=%d, rid=%d, addr=%lx)\n",
2949 rle->type, rle->rid,
2950 rman_get_start(rle->res));
2951 return;
2952 }
2953 bus_release_resource(dev, type, rid, rle->res);
2954 }
2955 resource_list_delete(rl, type, rid);
2956 }
2957 /*
2958 * Why do we turn off the PCI configuration BAR when we delete a
2959 * resource? -- imp
2960 */
2961 pci_write_config(child, rid, 0, 4);
2962 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
2963 }
2964
2965 struct resource_list *
2966 pci_get_resource_list (device_t dev, device_t child)
2967 {
2968 struct pci_devinfo *dinfo = device_get_ivars(child);
2969
2970 return (&dinfo->resources);
2971 }
2972
2973 uint32_t
2974 pci_read_config_method(device_t dev, device_t child, int reg, int width)
2975 {
2976 struct pci_devinfo *dinfo = device_get_ivars(child);
2977 pcicfgregs *cfg = &dinfo->cfg;
2978
2979 return (PCIB_READ_CONFIG(device_get_parent(dev),
2980 cfg->bus, cfg->slot, cfg->func, reg, width));
2981 }
2982
2983 void
2984 pci_write_config_method(device_t dev, device_t child, int reg,
2985 uint32_t val, int width)
2986 {
2987 struct pci_devinfo *dinfo = device_get_ivars(child);
2988 pcicfgregs *cfg = &dinfo->cfg;
2989
2990 PCIB_WRITE_CONFIG(device_get_parent(dev),
2991 cfg->bus, cfg->slot, cfg->func, reg, val, width);
2992 }
2993
2994 int
2995 pci_child_location_str_method(device_t dev, device_t child, char *buf,
2996 size_t buflen)
2997 {
2998
2999 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3000 pci_get_function(child));
3001 return (0);
3002 }
3003
3004 int
3005 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3006 size_t buflen)
3007 {
3008 struct pci_devinfo *dinfo;
3009 pcicfgregs *cfg;
3010
3011 dinfo = device_get_ivars(child);
3012 cfg = &dinfo->cfg;
3013 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3014 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3015 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3016 cfg->progif);
3017 return (0);
3018 }
3019
3020 int
3021 pci_assign_interrupt_method(device_t dev, device_t child)
3022 {
3023 struct pci_devinfo *dinfo = device_get_ivars(child);
3024 pcicfgregs *cfg = &dinfo->cfg;
3025
3026 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3027 cfg->intpin));
3028 }
3029
3030 static int
3031 pci_modevent(module_t mod, int what, void *arg)
3032 {
3033 static struct cdev *pci_cdev;
3034
3035 switch (what) {
3036 case MOD_LOAD:
3037 STAILQ_INIT(&pci_devq);
3038 pci_generation = 0;
3039 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
3040 "pci");
3041 pci_load_vendor_data();
3042 break;
3043
3044 case MOD_UNLOAD:
3045 destroy_dev(pci_cdev);
3046 break;
3047 }
3048
3049 return (0);
3050 }
3051
3052 void
3053 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3054 {
3055 int i;
3056
3057 /*
3058 * Only do header type 0 devices. Type 1 devices are bridges,
3059 * which we know need special treatment. Type 2 devices are
3060 * cardbus bridges which also require special treatment.
3061 * Other types are unknown, and we err on the side of safety
3062 * by ignoring them.
3063 */
3064 if (dinfo->cfg.hdrtype != 0)
3065 return;
3066
3067 /*
3068 * Restore the device to full power mode. We must do this
3069 * before we restore the registers because moving from D3 to
3070 * D0 will cause the chip's BARs and some other registers to
3071 * be reset to some unknown power on reset values. Cut down
3072 * the noise on boot by doing nothing if we are already in
3073 * state D0.
3074 */
3075 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3076 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3077 }
3078 for (i = 0; i < dinfo->cfg.nummaps; i++)
3079 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3080 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3081 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3082 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3083 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3084 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3085 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3086 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3087 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3088 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3089 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3090
3091 /* Restore MSI and MSI-X configurations if they are present. */
3092 if (dinfo->cfg.msi.msi_location != 0)
3093 pci_resume_msi(dev);
3094 if (dinfo->cfg.msix.msix_location != 0)
3095 pci_resume_msix(dev);
3096 }
3097
3098 void
3099 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3100 {
3101 int i;
3102 uint32_t cls;
3103 int ps;
3104
3105 /*
3106 * Only do header type 0 devices. Type 1 devices are bridges, which
3107 * we know need special treatment. Type 2 devices are cardbus bridges
3108 * which also require special treatment. Other types are unknown, and
3109 * we err on the side of safety by ignoring them. Powering down
3110 * bridges should not be undertaken lightly.
3111 */
3112 if (dinfo->cfg.hdrtype != 0)
3113 return;
3114 for (i = 0; i < dinfo->cfg.nummaps; i++)
3115 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3116 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3117
3118 /*
3119 * Some drivers apparently write to these registers w/o updating our
3120 * cached copy. No harm happens if we update the copy, so do so here
3121 * so we can restore them. The COMMAND register is modified by the
3122 * bus w/o updating the cache. This should represent the normally
3123 * writable portion of the 'defined' part of type 0 headers. In
3124 * theory we also need to save/restore the PCI capability structures
3125 * we know about, but apart from power we don't know any that are
3126 * writable.
3127 */
3128 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3129 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3130 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3131 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3132 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3133 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3134 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3135 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3136 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3137 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3138 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3139 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
3140 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
3141 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
3142 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
3143
3144 /*
3145 * don't set the state for display devices, base peripherals and
3146 * memory devices since bad things happen when they are powered down.
3147 * We should (a) have drivers that can easily detach and (b) use
3148 * generic drivers for these devices so that some device actually
3149 * attaches. We need to make sure that when we implement (a) we don't
3150 * power the device down on a reattach.
3151 */
3152 cls = pci_get_class(dev);
3153 if (!setstate)
3154 return;
3155 switch (pci_do_power_nodriver)
3156 {
3157 case 0: /* NO powerdown at all */
3158 return;
3159 case 1: /* Conservative about what to power down */
3160 if (cls == PCIC_STORAGE)
3161 return;
3162 /*FALLTHROUGH*/
3163 case 2: /* Agressive about what to power down */
3164 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
3165 cls == PCIC_BASEPERIPH)
3166 return;
3167 /*FALLTHROUGH*/
3168 case 3: /* Power down everything */
3169 break;
3170 }
3171 /*
3172 * PCI spec says we can only go into D3 state from D0 state.
3173 * Transition from D[12] into D0 before going to D3 state.
3174 */
3175 ps = pci_get_powerstate(dev);
3176 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
3177 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3178 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
3179 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
3180 }
Cache object: 13c67e0f1f24f54d5710ea211a4d730f
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