The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pci.c

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    1 /*-
    2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
    3  * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
    4  * Copyright (c) 2000, BSDi
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice unmodified, this list of conditions, and the following
   12  *    disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  */
   28 
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD: releng/7.3/sys/dev/pci/pci.c 197483 2009-09-25 14:58:30Z jhb $");
   31 
   32 #include "opt_bus.h"
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/malloc.h>
   37 #include <sys/module.h>
   38 #include <sys/linker.h>
   39 #include <sys/fcntl.h>
   40 #include <sys/conf.h>
   41 #include <sys/kernel.h>
   42 #include <sys/queue.h>
   43 #include <sys/sysctl.h>
   44 #include <sys/endian.h>
   45 
   46 #include <vm/vm.h>
   47 #include <vm/pmap.h>
   48 #include <vm/vm_extern.h>
   49 
   50 #include <sys/bus.h>
   51 #include <machine/bus.h>
   52 #include <sys/rman.h>
   53 #include <machine/resource.h>
   54 
   55 #if defined(__i386__) || defined(__amd64__)
   56 #include <machine/intr_machdep.h>
   57 #endif
   58 
   59 #include <sys/pciio.h>
   60 #include <dev/pci/pcireg.h>
   61 #include <dev/pci/pcivar.h>
   62 #include <dev/pci/pci_private.h>
   63 
   64 #include "pcib_if.h"
   65 #include "pci_if.h"
   66 
   67 #ifdef __HAVE_ACPI
   68 #include <contrib/dev/acpica/acpi.h>
   69 #include "acpi_if.h"
   70 #else
   71 #define ACPI_PWR_FOR_SLEEP(x, y, z)
   72 #endif
   73 
   74 static pci_addr_t       pci_mapbase(uint64_t mapreg);
   75 static const char       *pci_maptype(uint64_t mapreg);
   76 static int              pci_mapsize(uint64_t testval);
   77 static int              pci_maprange(uint64_t mapreg);
   78 static void             pci_fixancient(pcicfgregs *cfg);
   79 
   80 static int              pci_porten(device_t dev);
   81 static int              pci_memen(device_t dev);
   82 static void             pci_assign_interrupt(device_t bus, device_t dev,
   83                             int force_route);
   84 static int              pci_add_map(device_t bus, device_t dev, int reg,
   85                             struct resource_list *rl, int force, int prefetch);
   86 static int              pci_probe(device_t dev);
   87 static int              pci_attach(device_t dev);
   88 static void             pci_load_vendor_data(void);
   89 static int              pci_describe_parse_line(char **ptr, int *vendor,
   90                             int *device, char **desc);
   91 static char             *pci_describe_device(device_t dev);
   92 static int              pci_modevent(module_t mod, int what, void *arg);
   93 static void             pci_hdrtypedata(device_t pcib, int b, int s, int f,
   94                             pcicfgregs *cfg);
   95 static void             pci_read_extcap(device_t pcib, pcicfgregs *cfg);
   96 static int              pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
   97                             int reg, uint32_t *data);
   98 #if 0
   99 static int              pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
  100                             int reg, uint32_t data);
  101 #endif
  102 static void             pci_read_vpd(device_t pcib, pcicfgregs *cfg);
  103 static void             pci_disable_msi(device_t dev);
  104 static void             pci_enable_msi(device_t dev, uint64_t address,
  105                             uint16_t data);
  106 static void             pci_enable_msix(device_t dev, u_int index,
  107                             uint64_t address, uint32_t data);
  108 static void             pci_mask_msix(device_t dev, u_int index);
  109 static void             pci_unmask_msix(device_t dev, u_int index);
  110 static int              pci_msi_blacklisted(void);
  111 static void             pci_resume_msi(device_t dev);
  112 static void             pci_resume_msix(device_t dev);
  113 
  114 static device_method_t pci_methods[] = {
  115         /* Device interface */
  116         DEVMETHOD(device_probe,         pci_probe),
  117         DEVMETHOD(device_attach,        pci_attach),
  118         DEVMETHOD(device_detach,        bus_generic_detach),
  119         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  120         DEVMETHOD(device_suspend,       pci_suspend),
  121         DEVMETHOD(device_resume,        pci_resume),
  122 
  123         /* Bus interface */
  124         DEVMETHOD(bus_print_child,      pci_print_child),
  125         DEVMETHOD(bus_probe_nomatch,    pci_probe_nomatch),
  126         DEVMETHOD(bus_read_ivar,        pci_read_ivar),
  127         DEVMETHOD(bus_write_ivar,       pci_write_ivar),
  128         DEVMETHOD(bus_driver_added,     pci_driver_added),
  129         DEVMETHOD(bus_setup_intr,       pci_setup_intr),
  130         DEVMETHOD(bus_teardown_intr,    pci_teardown_intr),
  131 
  132         DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
  133         DEVMETHOD(bus_set_resource,     bus_generic_rl_set_resource),
  134         DEVMETHOD(bus_get_resource,     bus_generic_rl_get_resource),
  135         DEVMETHOD(bus_delete_resource,  pci_delete_resource),
  136         DEVMETHOD(bus_alloc_resource,   pci_alloc_resource),
  137         DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
  138         DEVMETHOD(bus_activate_resource, pci_activate_resource),
  139         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  140         DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
  141         DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
  142 
  143         /* PCI interface */
  144         DEVMETHOD(pci_read_config,      pci_read_config_method),
  145         DEVMETHOD(pci_write_config,     pci_write_config_method),
  146         DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
  147         DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
  148         DEVMETHOD(pci_enable_io,        pci_enable_io_method),
  149         DEVMETHOD(pci_disable_io,       pci_disable_io_method),
  150         DEVMETHOD(pci_get_vpd_ident,    pci_get_vpd_ident_method),
  151         DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
  152         DEVMETHOD(pci_get_powerstate,   pci_get_powerstate_method),
  153         DEVMETHOD(pci_set_powerstate,   pci_set_powerstate_method),
  154         DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
  155         DEVMETHOD(pci_find_extcap,      pci_find_extcap_method),
  156         DEVMETHOD(pci_alloc_msi,        pci_alloc_msi_method),
  157         DEVMETHOD(pci_alloc_msix,       pci_alloc_msix_method),
  158         DEVMETHOD(pci_remap_msix,       pci_remap_msix_method),
  159         DEVMETHOD(pci_release_msi,      pci_release_msi_method),
  160         DEVMETHOD(pci_msi_count,        pci_msi_count_method),
  161         DEVMETHOD(pci_msix_count,       pci_msix_count_method),
  162 
  163         { 0, 0 }
  164 };
  165 
  166 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
  167 
  168 static devclass_t pci_devclass;
  169 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
  170 MODULE_VERSION(pci, 1);
  171 
  172 static char     *pci_vendordata;
  173 static size_t   pci_vendordata_size;
  174 
  175 
  176 struct pci_quirk {
  177         uint32_t devid; /* Vendor/device of the card */
  178         int     type;
  179 #define PCI_QUIRK_MAP_REG       1 /* PCI map register in weird place */
  180 #define PCI_QUIRK_DISABLE_MSI   2 /* MSI/MSI-X doesn't work */
  181         int     arg1;
  182         int     arg2;
  183 };
  184 
  185 struct pci_quirk pci_quirks[] = {
  186         /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
  187         { 0x71138086, PCI_QUIRK_MAP_REG,        0x90,    0 },
  188         { 0x719b8086, PCI_QUIRK_MAP_REG,        0x90,    0 },
  189         /* As does the Serverworks OSB4 (the SMBus mapping register) */
  190         { 0x02001166, PCI_QUIRK_MAP_REG,        0x90,    0 },
  191 
  192         /*
  193          * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
  194          * or the CMIC-SL (AKA ServerWorks GC_LE).
  195          */
  196         { 0x00141166, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  197         { 0x00171166, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  198 
  199         /*
  200          * MSI doesn't work on earlier Intel chipsets including
  201          * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
  202          */
  203         { 0x25408086, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  204         { 0x254c8086, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  205         { 0x25508086, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  206         { 0x25608086, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  207         { 0x25708086, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  208         { 0x25788086, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  209         { 0x35808086, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  210 
  211         /*
  212          * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
  213          * bridge.
  214          */
  215         { 0x74501022, PCI_QUIRK_DISABLE_MSI,    0,      0 },
  216 
  217         { 0 }
  218 };
  219 
  220 /* map register information */
  221 #define PCI_MAPMEM      0x01    /* memory map */
  222 #define PCI_MAPMEMP     0x02    /* prefetchable memory map */
  223 #define PCI_MAPPORT     0x04    /* port map */
  224 
  225 struct devlist pci_devq;
  226 uint32_t pci_generation;
  227 uint32_t pci_numdevs = 0;
  228 static int pcie_chipset, pcix_chipset;
  229 
  230 /* sysctl vars */
  231 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
  232 
  233 static int pci_enable_io_modes = 1;
  234 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
  235 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
  236     &pci_enable_io_modes, 1,
  237     "Enable I/O and memory bits in the config register.  Some BIOSes do not\n\
  238 enable these bits correctly.  We'd like to do this all the time, but there\n\
  239 are some peripherals that this causes problems with.");
  240 
  241 static int pci_do_power_nodriver = 0;
  242 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
  243 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
  244     &pci_do_power_nodriver, 0,
  245   "Place a function into D3 state when no driver attaches to it.  0 means\n\
  246 disable.  1 means conservatively place devices into D3 state.  2 means\n\
  247 agressively place devices into D3 state.  3 means put absolutely everything\n\
  248 in D3 state.");
  249 
  250 static int pci_do_power_resume = 1;
  251 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
  252 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
  253     &pci_do_power_resume, 1,
  254   "Transition from D3 -> D0 on resume.");
  255 
  256 static int pci_do_msi = 1;
  257 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
  258 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
  259     "Enable support for MSI interrupts");
  260 
  261 static int pci_do_msix = 1;
  262 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
  263 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
  264     "Enable support for MSI-X interrupts");
  265 
  266 static int pci_honor_msi_blacklist = 1;
  267 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
  268 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
  269     &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
  270 
  271 /* Find a device_t by bus/slot/function in domain 0 */
  272 
  273 device_t
  274 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
  275 {
  276 
  277         return (pci_find_dbsf(0, bus, slot, func));
  278 }
  279 
  280 /* Find a device_t by domain/bus/slot/function */
  281 
  282 device_t
  283 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
  284 {
  285         struct pci_devinfo *dinfo;
  286 
  287         STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
  288                 if ((dinfo->cfg.domain == domain) &&
  289                     (dinfo->cfg.bus == bus) &&
  290                     (dinfo->cfg.slot == slot) &&
  291                     (dinfo->cfg.func == func)) {
  292                         return (dinfo->cfg.dev);
  293                 }
  294         }
  295 
  296         return (NULL);
  297 }
  298 
  299 /* Find a device_t by vendor/device ID */
  300 
  301 device_t
  302 pci_find_device(uint16_t vendor, uint16_t device)
  303 {
  304         struct pci_devinfo *dinfo;
  305 
  306         STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
  307                 if ((dinfo->cfg.vendor == vendor) &&
  308                     (dinfo->cfg.device == device)) {
  309                         return (dinfo->cfg.dev);
  310                 }
  311         }
  312 
  313         return (NULL);
  314 }
  315 
  316 /* return base address of memory or port map */
  317 
  318 static pci_addr_t
  319 pci_mapbase(uint64_t mapreg)
  320 {
  321 
  322         if (PCI_BAR_MEM(mapreg))
  323                 return (mapreg & PCIM_BAR_MEM_BASE);
  324         else
  325                 return (mapreg & PCIM_BAR_IO_BASE);
  326 }
  327 
  328 /* return map type of memory or port map */
  329 
  330 static const char *
  331 pci_maptype(uint64_t mapreg)
  332 {
  333 
  334         if (PCI_BAR_IO(mapreg))
  335                 return ("I/O Port");
  336         if (mapreg & PCIM_BAR_MEM_PREFETCH)
  337                 return ("Prefetchable Memory");
  338         return ("Memory");
  339 }
  340 
  341 /* return log2 of map size decoded for memory or port map */
  342 
  343 static int
  344 pci_mapsize(uint64_t testval)
  345 {
  346         int ln2size;
  347 
  348         testval = pci_mapbase(testval);
  349         ln2size = 0;
  350         if (testval != 0) {
  351                 while ((testval & 1) == 0)
  352                 {
  353                         ln2size++;
  354                         testval >>= 1;
  355                 }
  356         }
  357         return (ln2size);
  358 }
  359 
  360 /* return log2 of address range supported by map register */
  361 
  362 static int
  363 pci_maprange(uint64_t mapreg)
  364 {
  365         int ln2range = 0;
  366 
  367         if (PCI_BAR_IO(mapreg))
  368                 ln2range = 32;
  369         else
  370                 switch (mapreg & PCIM_BAR_MEM_TYPE) {
  371                 case PCIM_BAR_MEM_32:
  372                         ln2range = 32;
  373                         break;
  374                 case PCIM_BAR_MEM_1MB:
  375                         ln2range = 20;
  376                         break;
  377                 case PCIM_BAR_MEM_64:
  378                         ln2range = 64;
  379                         break;
  380                 }
  381         return (ln2range);
  382 }
  383 
  384 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
  385 
  386 static void
  387 pci_fixancient(pcicfgregs *cfg)
  388 {
  389         if (cfg->hdrtype != 0)
  390                 return;
  391 
  392         /* PCI to PCI bridges use header type 1 */
  393         if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
  394                 cfg->hdrtype = 1;
  395 }
  396 
  397 /* extract header type specific config data */
  398 
  399 static void
  400 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
  401 {
  402 #define REG(n, w)       PCIB_READ_CONFIG(pcib, b, s, f, n, w)
  403         switch (cfg->hdrtype) {
  404         case 0:
  405                 cfg->subvendor      = REG(PCIR_SUBVEND_0, 2);
  406                 cfg->subdevice      = REG(PCIR_SUBDEV_0, 2);
  407                 cfg->nummaps        = PCI_MAXMAPS_0;
  408                 break;
  409         case 1:
  410                 cfg->nummaps        = PCI_MAXMAPS_1;
  411                 break;
  412         case 2:
  413                 cfg->subvendor      = REG(PCIR_SUBVEND_2, 2);
  414                 cfg->subdevice      = REG(PCIR_SUBDEV_2, 2);
  415                 cfg->nummaps        = PCI_MAXMAPS_2;
  416                 break;
  417         }
  418 #undef REG
  419 }
  420 
  421 /* read configuration header into pcicfgregs structure */
  422 struct pci_devinfo *
  423 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
  424 {
  425 #define REG(n, w)       PCIB_READ_CONFIG(pcib, b, s, f, n, w)
  426         pcicfgregs *cfg = NULL;
  427         struct pci_devinfo *devlist_entry;
  428         struct devlist *devlist_head;
  429 
  430         devlist_head = &pci_devq;
  431 
  432         devlist_entry = NULL;
  433 
  434         if (REG(PCIR_DEVVENDOR, 4) != -1) {
  435                 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
  436                 if (devlist_entry == NULL)
  437                         return (NULL);
  438 
  439                 cfg = &devlist_entry->cfg;
  440 
  441                 cfg->domain             = d;
  442                 cfg->bus                = b;
  443                 cfg->slot               = s;
  444                 cfg->func               = f;
  445                 cfg->vendor             = REG(PCIR_VENDOR, 2);
  446                 cfg->device             = REG(PCIR_DEVICE, 2);
  447                 cfg->cmdreg             = REG(PCIR_COMMAND, 2);
  448                 cfg->statreg            = REG(PCIR_STATUS, 2);
  449                 cfg->baseclass          = REG(PCIR_CLASS, 1);
  450                 cfg->subclass           = REG(PCIR_SUBCLASS, 1);
  451                 cfg->progif             = REG(PCIR_PROGIF, 1);
  452                 cfg->revid              = REG(PCIR_REVID, 1);
  453                 cfg->hdrtype            = REG(PCIR_HDRTYPE, 1);
  454                 cfg->cachelnsz          = REG(PCIR_CACHELNSZ, 1);
  455                 cfg->lattimer           = REG(PCIR_LATTIMER, 1);
  456                 cfg->intpin             = REG(PCIR_INTPIN, 1);
  457                 cfg->intline            = REG(PCIR_INTLINE, 1);
  458 
  459                 cfg->mingnt             = REG(PCIR_MINGNT, 1);
  460                 cfg->maxlat             = REG(PCIR_MAXLAT, 1);
  461 
  462                 cfg->mfdev              = (cfg->hdrtype & PCIM_MFDEV) != 0;
  463                 cfg->hdrtype            &= ~PCIM_MFDEV;
  464 
  465                 pci_fixancient(cfg);
  466                 pci_hdrtypedata(pcib, b, s, f, cfg);
  467 
  468                 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
  469                         pci_read_extcap(pcib, cfg);
  470 
  471                 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
  472 
  473                 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
  474                 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
  475                 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
  476                 devlist_entry->conf.pc_sel.pc_func = cfg->func;
  477                 devlist_entry->conf.pc_hdr = cfg->hdrtype;
  478 
  479                 devlist_entry->conf.pc_subvendor = cfg->subvendor;
  480                 devlist_entry->conf.pc_subdevice = cfg->subdevice;
  481                 devlist_entry->conf.pc_vendor = cfg->vendor;
  482                 devlist_entry->conf.pc_device = cfg->device;
  483 
  484                 devlist_entry->conf.pc_class = cfg->baseclass;
  485                 devlist_entry->conf.pc_subclass = cfg->subclass;
  486                 devlist_entry->conf.pc_progif = cfg->progif;
  487                 devlist_entry->conf.pc_revid = cfg->revid;
  488 
  489                 pci_numdevs++;
  490                 pci_generation++;
  491         }
  492         return (devlist_entry);
  493 #undef REG
  494 }
  495 
  496 static void
  497 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
  498 {
  499 #define REG(n, w)       PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
  500 #define WREG(n, v, w)   PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
  501 #if defined(__i386__) || defined(__amd64__)
  502         uint64_t addr;
  503 #endif
  504         uint32_t val;
  505         int     ptr, nextptr, ptrptr;
  506 
  507         switch (cfg->hdrtype & PCIM_HDRTYPE) {
  508         case 0:
  509         case 1:
  510                 ptrptr = PCIR_CAP_PTR;
  511                 break;
  512         case 2:
  513                 ptrptr = PCIR_CAP_PTR_2;        /* cardbus capabilities ptr */
  514                 break;
  515         default:
  516                 return;         /* no extended capabilities support */
  517         }
  518         nextptr = REG(ptrptr, 1);       /* sanity check? */
  519 
  520         /*
  521          * Read capability entries.
  522          */
  523         while (nextptr != 0) {
  524                 /* Sanity check */
  525                 if (nextptr > 255) {
  526                         printf("illegal PCI extended capability offset %d\n",
  527                             nextptr);
  528                         return;
  529                 }
  530                 /* Find the next entry */
  531                 ptr = nextptr;
  532                 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
  533 
  534                 /* Process this entry */
  535                 switch (REG(ptr + PCICAP_ID, 1)) {
  536                 case PCIY_PMG:          /* PCI power management */
  537                         if (cfg->pp.pp_cap == 0) {
  538                                 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
  539                                 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
  540                                 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
  541                                 if ((nextptr - ptr) > PCIR_POWER_DATA)
  542                                         cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
  543                         }
  544                         break;
  545 #if defined(__i386__) || defined(__amd64__)
  546                 case PCIY_HT:           /* HyperTransport */
  547                         /* Determine HT-specific capability type. */
  548                         val = REG(ptr + PCIR_HT_COMMAND, 2);
  549                         switch (val & PCIM_HTCMD_CAP_MASK) {
  550                         case PCIM_HTCAP_MSI_MAPPING:
  551                                 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
  552                                         /* Sanity check the mapping window. */
  553                                         addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
  554                                             4);
  555                                         addr <<= 32;
  556                                         addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
  557                                             4);
  558                                         if (addr != MSI_INTEL_ADDR_BASE)
  559                                                 device_printf(pcib,
  560             "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
  561                                                     cfg->domain, cfg->bus,
  562                                                     cfg->slot, cfg->func,
  563                                                     (long long)addr);
  564                                 } else
  565                                         addr = MSI_INTEL_ADDR_BASE;
  566 
  567                                 cfg->ht.ht_msimap = ptr;
  568                                 cfg->ht.ht_msictrl = val;
  569                                 cfg->ht.ht_msiaddr = addr;
  570                                 break;
  571                         }
  572                         break;
  573 #endif
  574                 case PCIY_MSI:          /* PCI MSI */
  575                         cfg->msi.msi_location = ptr;
  576                         cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
  577                         cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
  578                                                      PCIM_MSICTRL_MMC_MASK)>>1);
  579                         break;
  580                 case PCIY_MSIX:         /* PCI MSI-X */
  581                         cfg->msix.msix_location = ptr;
  582                         cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
  583                         cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
  584                             PCIM_MSIXCTRL_TABLE_SIZE) + 1;
  585                         val = REG(ptr + PCIR_MSIX_TABLE, 4);
  586                         cfg->msix.msix_table_bar = PCIR_BAR(val &
  587                             PCIM_MSIX_BIR_MASK);
  588                         cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
  589                         val = REG(ptr + PCIR_MSIX_PBA, 4);
  590                         cfg->msix.msix_pba_bar = PCIR_BAR(val &
  591                             PCIM_MSIX_BIR_MASK);
  592                         cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
  593                         break;
  594                 case PCIY_VPD:          /* PCI Vital Product Data */
  595                         cfg->vpd.vpd_reg = ptr;
  596                         break;
  597                 case PCIY_SUBVENDOR:
  598                         /* Should always be true. */
  599                         if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
  600                                 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
  601                                 cfg->subvendor = val & 0xffff;
  602                                 cfg->subdevice = val >> 16;
  603                         }
  604                         break;
  605                 case PCIY_PCIX:         /* PCI-X */
  606                         /*
  607                          * Assume we have a PCI-X chipset if we have
  608                          * at least one PCI-PCI bridge with a PCI-X
  609                          * capability.  Note that some systems with
  610                          * PCI-express or HT chipsets might match on
  611                          * this check as well.
  612                          */
  613                         if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
  614                                 pcix_chipset = 1;
  615                         break;
  616                 case PCIY_EXPRESS:      /* PCI-express */
  617                         /*
  618                          * Assume we have a PCI-express chipset if we have
  619                          * at least one PCI-express device.
  620                          */
  621                         pcie_chipset = 1;
  622                         break;
  623                 default:
  624                         break;
  625                 }
  626         }
  627 /* REG and WREG use carry through to next functions */
  628 }
  629 
  630 /*
  631  * PCI Vital Product Data
  632  */
  633 
  634 #define PCI_VPD_TIMEOUT         1000000
  635 
  636 static int
  637 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
  638 {
  639         int count = PCI_VPD_TIMEOUT;
  640 
  641         KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
  642 
  643         WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
  644 
  645         while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
  646                 if (--count < 0)
  647                         return (ENXIO);
  648                 DELAY(1);       /* limit looping */
  649         }
  650         *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
  651 
  652         return (0);
  653 }
  654 
  655 #if 0
  656 static int
  657 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
  658 {
  659         int count = PCI_VPD_TIMEOUT;
  660 
  661         KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
  662 
  663         WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
  664         WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
  665         while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
  666                 if (--count < 0)
  667                         return (ENXIO);
  668                 DELAY(1);       /* limit looping */
  669         }
  670 
  671         return (0);
  672 }
  673 #endif
  674 
  675 #undef PCI_VPD_TIMEOUT
  676 
  677 struct vpd_readstate {
  678         device_t        pcib;
  679         pcicfgregs      *cfg;
  680         uint32_t        val;
  681         int             bytesinval;
  682         int             off;
  683         uint8_t         cksum;
  684 };
  685 
  686 static int
  687 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
  688 {
  689         uint32_t reg;
  690         uint8_t byte;
  691 
  692         if (vrs->bytesinval == 0) {
  693                 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg))
  694                         return (ENXIO);
  695                 vrs->val = le32toh(reg);
  696                 vrs->off += 4;
  697                 byte = vrs->val & 0xff;
  698                 vrs->bytesinval = 3;
  699         } else {
  700                 vrs->val = vrs->val >> 8;
  701                 byte = vrs->val & 0xff;
  702                 vrs->bytesinval--;
  703         }
  704 
  705         vrs->cksum += byte;
  706         *data = byte;
  707         return (0);
  708 }
  709 
  710 static void
  711 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
  712 {
  713         struct vpd_readstate vrs;
  714         int state;
  715         int name;
  716         int remain;
  717         int i;
  718         int alloc, off;         /* alloc/off for RO/W arrays */
  719         int cksumvalid;
  720         int dflen;
  721         uint8_t byte;
  722         uint8_t byte2;
  723 
  724         /* init vpd reader */
  725         vrs.bytesinval = 0;
  726         vrs.off = 0;
  727         vrs.pcib = pcib;
  728         vrs.cfg = cfg;
  729         vrs.cksum = 0;
  730 
  731         state = 0;
  732         name = remain = i = 0;  /* shut up stupid gcc */
  733         alloc = off = 0;        /* shut up stupid gcc */
  734         dflen = 0;              /* shut up stupid gcc */
  735         cksumvalid = -1;
  736         while (state >= 0) {
  737                 if (vpd_nextbyte(&vrs, &byte)) {
  738                         state = -2;
  739                         break;
  740                 }
  741 #if 0
  742                 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
  743                     "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
  744                     vrs.off, vrs.bytesinval, byte, state, remain, name, i);
  745 #endif
  746                 switch (state) {
  747                 case 0:         /* item name */
  748                         if (byte & 0x80) {
  749                                 if (vpd_nextbyte(&vrs, &byte2)) {
  750                                         state = -2;
  751                                         break;
  752                                 }
  753                                 remain = byte2;
  754                                 if (vpd_nextbyte(&vrs, &byte2)) {
  755                                         state = -2;
  756                                         break;
  757                                 }
  758                                 remain |= byte2 << 8;
  759                                 if (remain > (0x7f*4 - vrs.off)) {
  760                                         state = -1;
  761                                         printf(
  762                             "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
  763                                             cfg->domain, cfg->bus, cfg->slot,
  764                                             cfg->func, remain);
  765                                 }
  766                                 name = byte & 0x7f;
  767                         } else {
  768                                 remain = byte & 0x7;
  769                                 name = (byte >> 3) & 0xf;
  770                         }
  771                         switch (name) {
  772                         case 0x2:       /* String */
  773                                 cfg->vpd.vpd_ident = malloc(remain + 1,
  774                                     M_DEVBUF, M_WAITOK);
  775                                 i = 0;
  776                                 state = 1;
  777                                 break;
  778                         case 0xf:       /* End */
  779                                 state = -1;
  780                                 break;
  781                         case 0x10:      /* VPD-R */
  782                                 alloc = 8;
  783                                 off = 0;
  784                                 cfg->vpd.vpd_ros = malloc(alloc *
  785                                     sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
  786                                     M_WAITOK | M_ZERO);
  787                                 state = 2;
  788                                 break;
  789                         case 0x11:      /* VPD-W */
  790                                 alloc = 8;
  791                                 off = 0;
  792                                 cfg->vpd.vpd_w = malloc(alloc *
  793                                     sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
  794                                     M_WAITOK | M_ZERO);
  795                                 state = 5;
  796                                 break;
  797                         default:        /* Invalid data, abort */
  798                                 state = -1;
  799                                 break;
  800                         }
  801                         break;
  802 
  803                 case 1: /* Identifier String */
  804                         cfg->vpd.vpd_ident[i++] = byte;
  805                         remain--;
  806                         if (remain == 0)  {
  807                                 cfg->vpd.vpd_ident[i] = '\0';
  808                                 state = 0;
  809                         }
  810                         break;
  811 
  812                 case 2: /* VPD-R Keyword Header */
  813                         if (off == alloc) {
  814                                 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
  815                                     (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
  816                                     M_DEVBUF, M_WAITOK | M_ZERO);
  817                         }
  818                         cfg->vpd.vpd_ros[off].keyword[0] = byte;
  819                         if (vpd_nextbyte(&vrs, &byte2)) {
  820                                 state = -2;
  821                                 break;
  822                         }
  823                         cfg->vpd.vpd_ros[off].keyword[1] = byte2;
  824                         if (vpd_nextbyte(&vrs, &byte2)) {
  825                                 state = -2;
  826                                 break;
  827                         }
  828                         dflen = byte2;
  829                         if (dflen == 0 &&
  830                             strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
  831                             2) == 0) {
  832                                 /*
  833                                  * if this happens, we can't trust the rest
  834                                  * of the VPD.
  835                                  */
  836                                 printf(
  837                                     "pci%d:%d:%d:%d: bad keyword length: %d\n",
  838                                     cfg->domain, cfg->bus, cfg->slot,
  839                                     cfg->func, dflen);
  840                                 cksumvalid = 0;
  841                                 state = -1;
  842                                 break;
  843                         } else if (dflen == 0) {
  844                                 cfg->vpd.vpd_ros[off].value = malloc(1 *
  845                                     sizeof(*cfg->vpd.vpd_ros[off].value),
  846                                     M_DEVBUF, M_WAITOK);
  847                                 cfg->vpd.vpd_ros[off].value[0] = '\x00';
  848                         } else
  849                                 cfg->vpd.vpd_ros[off].value = malloc(
  850                                     (dflen + 1) *
  851                                     sizeof(*cfg->vpd.vpd_ros[off].value),
  852                                     M_DEVBUF, M_WAITOK);
  853                         remain -= 3;
  854                         i = 0;
  855                         /* keep in sync w/ state 3's transistions */
  856                         if (dflen == 0 && remain == 0)
  857                                 state = 0;
  858                         else if (dflen == 0)
  859                                 state = 2;
  860                         else
  861                                 state = 3;
  862                         break;
  863 
  864                 case 3: /* VPD-R Keyword Value */
  865                         cfg->vpd.vpd_ros[off].value[i++] = byte;
  866                         if (strncmp(cfg->vpd.vpd_ros[off].keyword,
  867                             "RV", 2) == 0 && cksumvalid == -1) {
  868                                 if (vrs.cksum == 0)
  869                                         cksumvalid = 1;
  870                                 else {
  871                                         if (bootverbose)
  872                                                 printf(
  873                                 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
  874                                                     cfg->domain, cfg->bus,
  875                                                     cfg->slot, cfg->func,
  876                                                     vrs.cksum);
  877                                         cksumvalid = 0;
  878                                         state = -1;
  879                                         break;
  880                                 }
  881                         }
  882                         dflen--;
  883                         remain--;
  884                         /* keep in sync w/ state 2's transistions */
  885                         if (dflen == 0)
  886                                 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
  887                         if (dflen == 0 && remain == 0) {
  888                                 cfg->vpd.vpd_rocnt = off;
  889                                 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
  890                                     off * sizeof(*cfg->vpd.vpd_ros),
  891                                     M_DEVBUF, M_WAITOK | M_ZERO);
  892                                 state = 0;
  893                         } else if (dflen == 0)
  894                                 state = 2;
  895                         break;
  896 
  897                 case 4:
  898                         remain--;
  899                         if (remain == 0)
  900                                 state = 0;
  901                         break;
  902 
  903                 case 5: /* VPD-W Keyword Header */
  904                         if (off == alloc) {
  905                                 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
  906                                     (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
  907                                     M_DEVBUF, M_WAITOK | M_ZERO);
  908                         }
  909                         cfg->vpd.vpd_w[off].keyword[0] = byte;
  910                         if (vpd_nextbyte(&vrs, &byte2)) {
  911                                 state = -2;
  912                                 break;
  913                         }
  914                         cfg->vpd.vpd_w[off].keyword[1] = byte2;
  915                         if (vpd_nextbyte(&vrs, &byte2)) {
  916                                 state = -2;
  917                                 break;
  918                         }
  919                         cfg->vpd.vpd_w[off].len = dflen = byte2;
  920                         cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
  921                         cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
  922                             sizeof(*cfg->vpd.vpd_w[off].value),
  923                             M_DEVBUF, M_WAITOK);
  924                         remain -= 3;
  925                         i = 0;
  926                         /* keep in sync w/ state 6's transistions */
  927                         if (dflen == 0 && remain == 0)
  928                                 state = 0;
  929                         else if (dflen == 0)
  930                                 state = 5;
  931                         else
  932                                 state = 6;
  933                         break;
  934 
  935                 case 6: /* VPD-W Keyword Value */
  936                         cfg->vpd.vpd_w[off].value[i++] = byte;
  937                         dflen--;
  938                         remain--;
  939                         /* keep in sync w/ state 5's transistions */
  940                         if (dflen == 0)
  941                                 cfg->vpd.vpd_w[off++].value[i++] = '\0';
  942                         if (dflen == 0 && remain == 0) {
  943                                 cfg->vpd.vpd_wcnt = off;
  944                                 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
  945                                     off * sizeof(*cfg->vpd.vpd_w),
  946                                     M_DEVBUF, M_WAITOK | M_ZERO);
  947                                 state = 0;
  948                         } else if (dflen == 0)
  949                                 state = 5;
  950                         break;
  951 
  952                 default:
  953                         printf("pci%d:%d:%d:%d: invalid state: %d\n",
  954                             cfg->domain, cfg->bus, cfg->slot, cfg->func,
  955                             state);
  956                         state = -1;
  957                         break;
  958                 }
  959         }
  960 
  961         if (cksumvalid == 0 || state < -1) {
  962                 /* read-only data bad, clean up */
  963                 if (cfg->vpd.vpd_ros != NULL) {
  964                         for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
  965                                 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
  966                         free(cfg->vpd.vpd_ros, M_DEVBUF);
  967                         cfg->vpd.vpd_ros = NULL;
  968                 }
  969         }
  970         if (state < -1) {
  971                 /* I/O error, clean up */
  972                 printf("pci%d:%d:%d:%d: failed to read VPD data.\n",
  973                     cfg->domain, cfg->bus, cfg->slot, cfg->func);
  974                 if (cfg->vpd.vpd_ident != NULL) {
  975                         free(cfg->vpd.vpd_ident, M_DEVBUF);
  976                         cfg->vpd.vpd_ident = NULL;
  977                 }
  978                 if (cfg->vpd.vpd_w != NULL) {
  979                         for (off = 0; cfg->vpd.vpd_w[off].value; off++)
  980                                 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
  981                         free(cfg->vpd.vpd_w, M_DEVBUF);
  982                         cfg->vpd.vpd_w = NULL;
  983                 }
  984         }
  985         cfg->vpd.vpd_cached = 1;
  986 #undef REG
  987 #undef WREG
  988 }
  989 
  990 int
  991 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
  992 {
  993         struct pci_devinfo *dinfo = device_get_ivars(child);
  994         pcicfgregs *cfg = &dinfo->cfg;
  995 
  996         if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
  997                 pci_read_vpd(device_get_parent(dev), cfg);
  998 
  999         *identptr = cfg->vpd.vpd_ident;
 1000 
 1001         if (*identptr == NULL)
 1002                 return (ENXIO);
 1003 
 1004         return (0);
 1005 }
 1006 
 1007 int
 1008 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
 1009         const char **vptr)
 1010 {
 1011         struct pci_devinfo *dinfo = device_get_ivars(child);
 1012         pcicfgregs *cfg = &dinfo->cfg;
 1013         int i;
 1014 
 1015         if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
 1016                 pci_read_vpd(device_get_parent(dev), cfg);
 1017 
 1018         for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
 1019                 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
 1020                     sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
 1021                         *vptr = cfg->vpd.vpd_ros[i].value;
 1022                 }
 1023 
 1024         if (i != cfg->vpd.vpd_rocnt)
 1025                 return (0);
 1026 
 1027         *vptr = NULL;
 1028         return (ENXIO);
 1029 }
 1030 
 1031 /*
 1032  * Return the offset in configuration space of the requested extended
 1033  * capability entry or 0 if the specified capability was not found.
 1034  */
 1035 int
 1036 pci_find_extcap_method(device_t dev, device_t child, int capability,
 1037     int *capreg)
 1038 {
 1039         struct pci_devinfo *dinfo = device_get_ivars(child);
 1040         pcicfgregs *cfg = &dinfo->cfg;
 1041         u_int32_t status;
 1042         u_int8_t ptr;
 1043 
 1044         /*
 1045          * Check the CAP_LIST bit of the PCI status register first.
 1046          */
 1047         status = pci_read_config(child, PCIR_STATUS, 2);
 1048         if (!(status & PCIM_STATUS_CAPPRESENT))
 1049                 return (ENXIO);
 1050 
 1051         /*
 1052          * Determine the start pointer of the capabilities list.
 1053          */
 1054         switch (cfg->hdrtype & PCIM_HDRTYPE) {
 1055         case 0:
 1056         case 1:
 1057                 ptr = PCIR_CAP_PTR;
 1058                 break;
 1059         case 2:
 1060                 ptr = PCIR_CAP_PTR_2;
 1061                 break;
 1062         default:
 1063                 /* XXX: panic? */
 1064                 return (ENXIO);         /* no extended capabilities support */
 1065         }
 1066         ptr = pci_read_config(child, ptr, 1);
 1067 
 1068         /*
 1069          * Traverse the capabilities list.
 1070          */
 1071         while (ptr != 0) {
 1072                 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
 1073                         if (capreg != NULL)
 1074                                 *capreg = ptr;
 1075                         return (0);
 1076                 }
 1077                 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
 1078         }
 1079 
 1080         return (ENOENT);
 1081 }
 1082 
 1083 /*
 1084  * Support for MSI-X message interrupts.
 1085  */
 1086 void
 1087 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
 1088 {
 1089         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1090         struct pcicfg_msix *msix = &dinfo->cfg.msix;
 1091         uint32_t offset;
 1092 
 1093         KASSERT(msix->msix_table_len > index, ("bogus index"));
 1094         offset = msix->msix_table_offset + index * 16;
 1095         bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
 1096         bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
 1097         bus_write_4(msix->msix_table_res, offset + 8, data);
 1098 
 1099         /* Enable MSI -> HT mapping. */
 1100         pci_ht_map_msi(dev, address);
 1101 }
 1102 
 1103 void
 1104 pci_mask_msix(device_t dev, u_int index)
 1105 {
 1106         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1107         struct pcicfg_msix *msix = &dinfo->cfg.msix;
 1108         uint32_t offset, val;
 1109 
 1110         KASSERT(msix->msix_msgnum > index, ("bogus index"));
 1111         offset = msix->msix_table_offset + index * 16 + 12;
 1112         val = bus_read_4(msix->msix_table_res, offset);
 1113         if (!(val & PCIM_MSIX_VCTRL_MASK)) {
 1114                 val |= PCIM_MSIX_VCTRL_MASK;
 1115                 bus_write_4(msix->msix_table_res, offset, val);
 1116         }
 1117 }
 1118 
 1119 void
 1120 pci_unmask_msix(device_t dev, u_int index)
 1121 {
 1122         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1123         struct pcicfg_msix *msix = &dinfo->cfg.msix;
 1124         uint32_t offset, val;
 1125 
 1126         KASSERT(msix->msix_table_len > index, ("bogus index"));
 1127         offset = msix->msix_table_offset + index * 16 + 12;
 1128         val = bus_read_4(msix->msix_table_res, offset);
 1129         if (val & PCIM_MSIX_VCTRL_MASK) {
 1130                 val &= ~PCIM_MSIX_VCTRL_MASK;
 1131                 bus_write_4(msix->msix_table_res, offset, val);
 1132         }
 1133 }
 1134 
 1135 int
 1136 pci_pending_msix(device_t dev, u_int index)
 1137 {
 1138         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1139         struct pcicfg_msix *msix = &dinfo->cfg.msix;
 1140         uint32_t offset, bit;
 1141 
 1142         KASSERT(msix->msix_table_len > index, ("bogus index"));
 1143         offset = msix->msix_pba_offset + (index / 32) * 4;
 1144         bit = 1 << index % 32;
 1145         return (bus_read_4(msix->msix_pba_res, offset) & bit);
 1146 }
 1147 
 1148 /*
 1149  * Restore MSI-X registers and table during resume.  If MSI-X is
 1150  * enabled then walk the virtual table to restore the actual MSI-X
 1151  * table.
 1152  */
 1153 static void
 1154 pci_resume_msix(device_t dev)
 1155 {
 1156         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1157         struct pcicfg_msix *msix = &dinfo->cfg.msix;
 1158         struct msix_table_entry *mte;
 1159         struct msix_vector *mv;
 1160         int i;
 1161 
 1162         if (msix->msix_alloc > 0) {
 1163                 /* First, mask all vectors. */
 1164                 for (i = 0; i < msix->msix_msgnum; i++)
 1165                         pci_mask_msix(dev, i);
 1166 
 1167                 /* Second, program any messages with at least one handler. */
 1168                 for (i = 0; i < msix->msix_table_len; i++) {
 1169                         mte = &msix->msix_table[i];
 1170                         if (mte->mte_vector == 0 || mte->mte_handlers == 0)
 1171                                 continue;
 1172                         mv = &msix->msix_vectors[mte->mte_vector - 1];
 1173                         pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
 1174                         pci_unmask_msix(dev, i);
 1175                 }
 1176         }
 1177         pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
 1178             msix->msix_ctrl, 2);
 1179 }
 1180 
 1181 /*
 1182  * Attempt to allocate *count MSI-X messages.  The actual number allocated is
 1183  * returned in *count.  After this function returns, each message will be
 1184  * available to the driver as SYS_RES_IRQ resources starting at rid 1.
 1185  */
 1186 int
 1187 pci_alloc_msix_method(device_t dev, device_t child, int *count)
 1188 {
 1189         struct pci_devinfo *dinfo = device_get_ivars(child);
 1190         pcicfgregs *cfg = &dinfo->cfg;
 1191         struct resource_list_entry *rle;
 1192         int actual, error, i, irq, max;
 1193 
 1194         /* Don't let count == 0 get us into trouble. */
 1195         if (*count == 0)
 1196                 return (EINVAL);
 1197 
 1198         /* If rid 0 is allocated, then fail. */
 1199         rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
 1200         if (rle != NULL && rle->res != NULL)
 1201                 return (ENXIO);
 1202 
 1203         /* Already have allocated messages? */
 1204         if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
 1205                 return (ENXIO);
 1206 
 1207         /* If MSI is blacklisted for this system, fail. */
 1208         if (pci_msi_blacklisted())
 1209                 return (ENXIO);
 1210 
 1211         /* MSI-X capability present? */
 1212         if (cfg->msix.msix_location == 0 || !pci_do_msix)
 1213                 return (ENODEV);
 1214 
 1215         /* Make sure the appropriate BARs are mapped. */
 1216         rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
 1217             cfg->msix.msix_table_bar);
 1218         if (rle == NULL || rle->res == NULL ||
 1219             !(rman_get_flags(rle->res) & RF_ACTIVE))
 1220                 return (ENXIO);
 1221         cfg->msix.msix_table_res = rle->res;
 1222         if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
 1223                 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
 1224                     cfg->msix.msix_pba_bar);
 1225                 if (rle == NULL || rle->res == NULL ||
 1226                     !(rman_get_flags(rle->res) & RF_ACTIVE))
 1227                         return (ENXIO);
 1228         }
 1229         cfg->msix.msix_pba_res = rle->res;
 1230 
 1231         if (bootverbose)
 1232                 device_printf(child,
 1233                     "attempting to allocate %d MSI-X vectors (%d supported)\n",
 1234                     *count, cfg->msix.msix_msgnum);
 1235         max = min(*count, cfg->msix.msix_msgnum);
 1236         for (i = 0; i < max; i++) {
 1237                 /* Allocate a message. */
 1238                 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
 1239                 if (error)
 1240                         break;
 1241                 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
 1242                     irq, 1);
 1243         }
 1244         actual = i;
 1245 
 1246         if (bootverbose) {
 1247                 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
 1248                 if (actual == 1)
 1249                         device_printf(child, "using IRQ %lu for MSI-X\n",
 1250                             rle->start);
 1251                 else {
 1252                         int run;
 1253 
 1254                         /*
 1255                          * Be fancy and try to print contiguous runs of
 1256                          * IRQ values as ranges.  'irq' is the previous IRQ.
 1257                          * 'run' is true if we are in a range.
 1258                          */
 1259                         device_printf(child, "using IRQs %lu", rle->start);
 1260                         irq = rle->start;
 1261                         run = 0;
 1262                         for (i = 1; i < actual; i++) {
 1263                                 rle = resource_list_find(&dinfo->resources,
 1264                                     SYS_RES_IRQ, i + 1);
 1265 
 1266                                 /* Still in a run? */
 1267                                 if (rle->start == irq + 1) {
 1268                                         run = 1;
 1269                                         irq++;
 1270                                         continue;
 1271                                 }
 1272 
 1273                                 /* Finish previous range. */
 1274                                 if (run) {
 1275                                         printf("-%d", irq);
 1276                                         run = 0;
 1277                                 }
 1278 
 1279                                 /* Start new range. */
 1280                                 printf(",%lu", rle->start);
 1281                                 irq = rle->start;
 1282                         }
 1283 
 1284                         /* Unfinished range? */
 1285                         if (run)
 1286                                 printf("-%d", irq);
 1287                         printf(" for MSI-X\n");
 1288                 }
 1289         }
 1290 
 1291         /* Mask all vectors. */
 1292         for (i = 0; i < cfg->msix.msix_msgnum; i++)
 1293                 pci_mask_msix(child, i);
 1294 
 1295         /* Allocate and initialize vector data and virtual table. */
 1296         cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
 1297             M_DEVBUF, M_WAITOK | M_ZERO);
 1298         cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
 1299             M_DEVBUF, M_WAITOK | M_ZERO);
 1300         for (i = 0; i < actual; i++) {
 1301                 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
 1302                 cfg->msix.msix_vectors[i].mv_irq = rle->start;
 1303                 cfg->msix.msix_table[i].mte_vector = i + 1;
 1304         }
 1305 
 1306         /* Update control register to enable MSI-X. */
 1307         cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
 1308         pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
 1309             cfg->msix.msix_ctrl, 2);
 1310 
 1311         /* Update counts of alloc'd messages. */
 1312         cfg->msix.msix_alloc = actual;
 1313         cfg->msix.msix_table_len = actual;
 1314         *count = actual;
 1315         return (0);
 1316 }
 1317 
 1318 /*
 1319  * By default, pci_alloc_msix() will assign the allocated IRQ
 1320  * resources consecutively to the first N messages in the MSI-X table.
 1321  * However, device drivers may want to use different layouts if they
 1322  * either receive fewer messages than they asked for, or they wish to
 1323  * populate the MSI-X table sparsely.  This method allows the driver
 1324  * to specify what layout it wants.  It must be called after a
 1325  * successful pci_alloc_msix() but before any of the associated
 1326  * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
 1327  *
 1328  * The 'vectors' array contains 'count' message vectors.  The array
 1329  * maps directly to the MSI-X table in that index 0 in the array
 1330  * specifies the vector for the first message in the MSI-X table, etc.
 1331  * The vector value in each array index can either be 0 to indicate
 1332  * that no vector should be assigned to a message slot, or it can be a
 1333  * number from 1 to N (where N is the count returned from a
 1334  * succcessful call to pci_alloc_msix()) to indicate which message
 1335  * vector (IRQ) to be used for the corresponding message.
 1336  *
 1337  * On successful return, each message with a non-zero vector will have
 1338  * an associated SYS_RES_IRQ whose rid is equal to the array index +
 1339  * 1.  Additionally, if any of the IRQs allocated via the previous
 1340  * call to pci_alloc_msix() are not used in the mapping, those IRQs
 1341  * will be freed back to the system automatically.
 1342  *
 1343  * For example, suppose a driver has a MSI-X table with 6 messages and
 1344  * asks for 6 messages, but pci_alloc_msix() only returns a count of
 1345  * 3.  Call the three vectors allocated by pci_alloc_msix() A, B, and
 1346  * C.  After the call to pci_alloc_msix(), the device will be setup to
 1347  * have an MSI-X table of ABC--- (where - means no vector assigned).
 1348  * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
 1349  * then the MSI-X table will look like A-AB-B, and the 'C' vector will
 1350  * be freed back to the system.  This device will also have valid
 1351  * SYS_RES_IRQ rids of 1, 3, 4, and 6.
 1352  *
 1353  * In any case, the SYS_RES_IRQ rid X will always map to the message
 1354  * at MSI-X table index X - 1 and will only be valid if a vector is
 1355  * assigned to that table entry.
 1356  */
 1357 int
 1358 pci_remap_msix_method(device_t dev, device_t child, int count,
 1359     const u_int *vectors)
 1360 {
 1361         struct pci_devinfo *dinfo = device_get_ivars(child);
 1362         struct pcicfg_msix *msix = &dinfo->cfg.msix;
 1363         struct resource_list_entry *rle;
 1364         int i, irq, j, *used;
 1365 
 1366         /*
 1367          * Have to have at least one message in the table but the
 1368          * table can't be bigger than the actual MSI-X table in the
 1369          * device.
 1370          */
 1371         if (count == 0 || count > msix->msix_msgnum)
 1372                 return (EINVAL);
 1373 
 1374         /* Sanity check the vectors. */
 1375         for (i = 0; i < count; i++)
 1376                 if (vectors[i] > msix->msix_alloc)
 1377                         return (EINVAL);
 1378 
 1379         /*
 1380          * Make sure there aren't any holes in the vectors to be used.
 1381          * It's a big pain to support it, and it doesn't really make
 1382          * sense anyway.  Also, at least one vector must be used.
 1383          */
 1384         used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
 1385             M_ZERO);
 1386         for (i = 0; i < count; i++)
 1387                 if (vectors[i] != 0)
 1388                         used[vectors[i] - 1] = 1;
 1389         for (i = 0; i < msix->msix_alloc - 1; i++)
 1390                 if (used[i] == 0 && used[i + 1] == 1) {
 1391                         free(used, M_DEVBUF);
 1392                         return (EINVAL);
 1393                 }
 1394         if (used[0] != 1) {
 1395                 free(used, M_DEVBUF);
 1396                 return (EINVAL);
 1397         }
 1398         
 1399         /* Make sure none of the resources are allocated. */
 1400         for (i = 0; i < msix->msix_table_len; i++) {
 1401                 if (msix->msix_table[i].mte_vector == 0)
 1402                         continue;
 1403                 if (msix->msix_table[i].mte_handlers > 0)
 1404                         return (EBUSY);
 1405                 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
 1406                 KASSERT(rle != NULL, ("missing resource"));
 1407                 if (rle->res != NULL)
 1408                         return (EBUSY);
 1409         }
 1410 
 1411         /* Free the existing resource list entries. */
 1412         for (i = 0; i < msix->msix_table_len; i++) {
 1413                 if (msix->msix_table[i].mte_vector == 0)
 1414                         continue;
 1415                 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
 1416         }
 1417 
 1418         /*
 1419          * Build the new virtual table keeping track of which vectors are
 1420          * used.
 1421          */
 1422         free(msix->msix_table, M_DEVBUF);
 1423         msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
 1424             M_DEVBUF, M_WAITOK | M_ZERO);
 1425         for (i = 0; i < count; i++)
 1426                 msix->msix_table[i].mte_vector = vectors[i];
 1427         msix->msix_table_len = count;
 1428 
 1429         /* Free any unused IRQs and resize the vectors array if necessary. */
 1430         j = msix->msix_alloc - 1;
 1431         if (used[j] == 0) {
 1432                 struct msix_vector *vec;
 1433 
 1434                 while (used[j] == 0) {
 1435                         PCIB_RELEASE_MSIX(device_get_parent(dev), child,
 1436                             msix->msix_vectors[j].mv_irq);
 1437                         j--;
 1438                 }
 1439                 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
 1440                     M_WAITOK);
 1441                 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
 1442                     (j + 1));
 1443                 free(msix->msix_vectors, M_DEVBUF);
 1444                 msix->msix_vectors = vec;
 1445                 msix->msix_alloc = j + 1;
 1446         }
 1447         free(used, M_DEVBUF);
 1448 
 1449         /* Map the IRQs onto the rids. */
 1450         for (i = 0; i < count; i++) {
 1451                 if (vectors[i] == 0)
 1452                         continue;
 1453                 irq = msix->msix_vectors[vectors[i]].mv_irq;
 1454                 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
 1455                     irq, 1);
 1456         }
 1457 
 1458         if (bootverbose) {
 1459                 device_printf(child, "Remapped MSI-X IRQs as: ");
 1460                 for (i = 0; i < count; i++) {
 1461                         if (i != 0)
 1462                                 printf(", ");
 1463                         if (vectors[i] == 0)
 1464                                 printf("---");
 1465                         else
 1466                                 printf("%d",
 1467                                     msix->msix_vectors[vectors[i]].mv_irq);
 1468                 }
 1469                 printf("\n");
 1470         }
 1471 
 1472         return (0);
 1473 }
 1474 
 1475 static int
 1476 pci_release_msix(device_t dev, device_t child)
 1477 {
 1478         struct pci_devinfo *dinfo = device_get_ivars(child);
 1479         struct pcicfg_msix *msix = &dinfo->cfg.msix;
 1480         struct resource_list_entry *rle;
 1481         int i;
 1482 
 1483         /* Do we have any messages to release? */
 1484         if (msix->msix_alloc == 0)
 1485                 return (ENODEV);
 1486 
 1487         /* Make sure none of the resources are allocated. */
 1488         for (i = 0; i < msix->msix_table_len; i++) {
 1489                 if (msix->msix_table[i].mte_vector == 0)
 1490                         continue;
 1491                 if (msix->msix_table[i].mte_handlers > 0)
 1492                         return (EBUSY);
 1493                 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
 1494                 KASSERT(rle != NULL, ("missing resource"));
 1495                 if (rle->res != NULL)
 1496                         return (EBUSY);
 1497         }
 1498 
 1499         /* Update control register to disable MSI-X. */
 1500         msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
 1501         pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
 1502             msix->msix_ctrl, 2);
 1503 
 1504         /* Free the resource list entries. */
 1505         for (i = 0; i < msix->msix_table_len; i++) {
 1506                 if (msix->msix_table[i].mte_vector == 0)
 1507                         continue;
 1508                 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
 1509         }
 1510         free(msix->msix_table, M_DEVBUF);
 1511         msix->msix_table_len = 0;
 1512 
 1513         /* Release the IRQs. */
 1514         for (i = 0; i < msix->msix_alloc; i++)
 1515                 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
 1516                     msix->msix_vectors[i].mv_irq);
 1517         free(msix->msix_vectors, M_DEVBUF);
 1518         msix->msix_alloc = 0;
 1519         return (0);
 1520 }
 1521 
 1522 /*
 1523  * Return the max supported MSI-X messages this device supports.
 1524  * Basically, assuming the MD code can alloc messages, this function
 1525  * should return the maximum value that pci_alloc_msix() can return.
 1526  * Thus, it is subject to the tunables, etc.
 1527  */
 1528 int
 1529 pci_msix_count_method(device_t dev, device_t child)
 1530 {
 1531         struct pci_devinfo *dinfo = device_get_ivars(child);
 1532         struct pcicfg_msix *msix = &dinfo->cfg.msix;
 1533 
 1534         if (pci_do_msix && msix->msix_location != 0)
 1535                 return (msix->msix_msgnum);
 1536         return (0);
 1537 }
 1538 
 1539 /*
 1540  * HyperTransport MSI mapping control
 1541  */
 1542 void
 1543 pci_ht_map_msi(device_t dev, uint64_t addr)
 1544 {
 1545         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1546         struct pcicfg_ht *ht = &dinfo->cfg.ht;
 1547 
 1548         if (!ht->ht_msimap)
 1549                 return;
 1550 
 1551         if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
 1552             ht->ht_msiaddr >> 20 == addr >> 20) {
 1553                 /* Enable MSI -> HT mapping. */
 1554                 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
 1555                 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
 1556                     ht->ht_msictrl, 2);
 1557         }
 1558 
 1559         if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
 1560                 /* Disable MSI -> HT mapping. */
 1561                 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
 1562                 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
 1563                     ht->ht_msictrl, 2);
 1564         }
 1565 }
 1566 
 1567 /*
 1568  * Support for MSI message signalled interrupts.
 1569  */
 1570 void
 1571 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
 1572 {
 1573         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1574         struct pcicfg_msi *msi = &dinfo->cfg.msi;
 1575 
 1576         /* Write data and address values. */
 1577         pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
 1578             address & 0xffffffff, 4);
 1579         if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
 1580                 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
 1581                     address >> 32, 4);
 1582                 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
 1583                     data, 2);
 1584         } else
 1585                 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
 1586                     2);
 1587 
 1588         /* Enable MSI in the control register. */
 1589         msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
 1590         pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
 1591             2);
 1592 
 1593         /* Enable MSI -> HT mapping. */
 1594         pci_ht_map_msi(dev, address);
 1595 }
 1596 
 1597 void
 1598 pci_disable_msi(device_t dev)
 1599 {
 1600         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1601         struct pcicfg_msi *msi = &dinfo->cfg.msi;
 1602 
 1603         /* Disable MSI -> HT mapping. */
 1604         pci_ht_map_msi(dev, 0);
 1605 
 1606         /* Disable MSI in the control register. */
 1607         msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
 1608         pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
 1609             2);
 1610 }
 1611 
 1612 /*
 1613  * Restore MSI registers during resume.  If MSI is enabled then
 1614  * restore the data and address registers in addition to the control
 1615  * register.
 1616  */
 1617 static void
 1618 pci_resume_msi(device_t dev)
 1619 {
 1620         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1621         struct pcicfg_msi *msi = &dinfo->cfg.msi;
 1622         uint64_t address;
 1623         uint16_t data;
 1624 
 1625         if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
 1626                 address = msi->msi_addr;
 1627                 data = msi->msi_data;
 1628                 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
 1629                     address & 0xffffffff, 4);
 1630                 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
 1631                         pci_write_config(dev, msi->msi_location +
 1632                             PCIR_MSI_ADDR_HIGH, address >> 32, 4);
 1633                         pci_write_config(dev, msi->msi_location +
 1634                             PCIR_MSI_DATA_64BIT, data, 2);
 1635                 } else
 1636                         pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
 1637                             data, 2);
 1638         }
 1639         pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
 1640             2);
 1641 }
 1642 
 1643 int
 1644 pci_remap_msi_irq(device_t dev, u_int irq)
 1645 {
 1646         struct pci_devinfo *dinfo = device_get_ivars(dev);
 1647         pcicfgregs *cfg = &dinfo->cfg;
 1648         struct resource_list_entry *rle;
 1649         struct msix_table_entry *mte;
 1650         struct msix_vector *mv;
 1651         device_t bus;
 1652         uint64_t addr;
 1653         uint32_t data;  
 1654         int error, i, j;
 1655 
 1656         bus = device_get_parent(dev);
 1657 
 1658         /*
 1659          * Handle MSI first.  We try to find this IRQ among our list
 1660          * of MSI IRQs.  If we find it, we request updated address and
 1661          * data registers and apply the results.
 1662          */
 1663         if (cfg->msi.msi_alloc > 0) {
 1664 
 1665                 /* If we don't have any active handlers, nothing to do. */
 1666                 if (cfg->msi.msi_handlers == 0)
 1667                         return (0);
 1668                 for (i = 0; i < cfg->msi.msi_alloc; i++) {
 1669                         rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
 1670                             i + 1);
 1671                         if (rle->start == irq) {
 1672                                 error = PCIB_MAP_MSI(device_get_parent(bus),
 1673                                     dev, irq, &addr, &data);
 1674                                 if (error)
 1675                                         return (error);
 1676                                 pci_disable_msi(dev);
 1677                                 dinfo->cfg.msi.msi_addr = addr;
 1678                                 dinfo->cfg.msi.msi_data = data;
 1679                                 pci_enable_msi(dev, addr, data);
 1680                                 return (0);
 1681                         }
 1682                 }
 1683                 return (ENOENT);
 1684         }
 1685 
 1686         /*
 1687          * For MSI-X, we check to see if we have this IRQ.  If we do,
 1688          * we request the updated mapping info.  If that works, we go
 1689          * through all the slots that use this IRQ and update them.
 1690          */
 1691         if (cfg->msix.msix_alloc > 0) {
 1692                 for (i = 0; i < cfg->msix.msix_alloc; i++) {
 1693                         mv = &cfg->msix.msix_vectors[i];
 1694                         if (mv->mv_irq == irq) {
 1695                                 error = PCIB_MAP_MSI(device_get_parent(bus),
 1696                                     dev, irq, &addr, &data);
 1697                                 if (error)
 1698                                         return (error);
 1699                                 mv->mv_address = addr;
 1700                                 mv->mv_data = data;
 1701                                 for (j = 0; j < cfg->msix.msix_table_len; j++) {
 1702                                         mte = &cfg->msix.msix_table[j];
 1703                                         if (mte->mte_vector != i + 1)
 1704                                                 continue;
 1705                                         if (mte->mte_handlers == 0)
 1706                                                 continue;
 1707                                         pci_mask_msix(dev, j);
 1708                                         pci_enable_msix(dev, j, addr, data);
 1709                                         pci_unmask_msix(dev, j);
 1710                                 }
 1711                         }
 1712                 }
 1713                 return (ENOENT);
 1714         }
 1715 
 1716         return (ENOENT);
 1717 }
 1718 
 1719 /*
 1720  * Returns true if the specified device is blacklisted because MSI
 1721  * doesn't work.
 1722  */
 1723 int
 1724 pci_msi_device_blacklisted(device_t dev)
 1725 {
 1726         struct pci_quirk *q;
 1727 
 1728         if (!pci_honor_msi_blacklist)
 1729                 return (0);
 1730 
 1731         for (q = &pci_quirks[0]; q->devid; q++) {
 1732                 if (q->devid == pci_get_devid(dev) &&
 1733                     q->type == PCI_QUIRK_DISABLE_MSI)
 1734                         return (1);
 1735         }
 1736         return (0);
 1737 }
 1738 
 1739 /*
 1740  * Determine if MSI is blacklisted globally on this sytem.  Currently,
 1741  * we just check for blacklisted chipsets as represented by the
 1742  * host-PCI bridge at device 0:0:0.  In the future, it may become
 1743  * necessary to check other system attributes, such as the kenv values
 1744  * that give the motherboard manufacturer and model number.
 1745  */
 1746 static int
 1747 pci_msi_blacklisted(void)
 1748 {
 1749         device_t dev;
 1750 
 1751         if (!pci_honor_msi_blacklist)
 1752                 return (0);
 1753 
 1754         /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
 1755         if (!(pcie_chipset || pcix_chipset))
 1756                 return (1);
 1757 
 1758         dev = pci_find_bsf(0, 0, 0);
 1759         if (dev != NULL)
 1760                 return (pci_msi_device_blacklisted(dev));
 1761         return (0);
 1762 }
 1763 
 1764 /*
 1765  * Attempt to allocate *count MSI messages.  The actual number allocated is
 1766  * returned in *count.  After this function returns, each message will be
 1767  * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
 1768  */
 1769 int
 1770 pci_alloc_msi_method(device_t dev, device_t child, int *count)
 1771 {
 1772         struct pci_devinfo *dinfo = device_get_ivars(child);
 1773         pcicfgregs *cfg = &dinfo->cfg;
 1774         struct resource_list_entry *rle;
 1775         int actual, error, i, irqs[32];
 1776         uint16_t ctrl;
 1777 
 1778         /* Don't let count == 0 get us into trouble. */
 1779         if (*count == 0)
 1780                 return (EINVAL);
 1781 
 1782         /* If rid 0 is allocated, then fail. */
 1783         rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
 1784         if (rle != NULL && rle->res != NULL)
 1785                 return (ENXIO);
 1786 
 1787         /* Already have allocated messages? */
 1788         if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
 1789                 return (ENXIO);
 1790 
 1791         /* If MSI is blacklisted for this system, fail. */
 1792         if (pci_msi_blacklisted())
 1793                 return (ENXIO);
 1794 
 1795         /* MSI capability present? */
 1796         if (cfg->msi.msi_location == 0 || !pci_do_msi)
 1797                 return (ENODEV);
 1798 
 1799         if (bootverbose)
 1800                 device_printf(child,
 1801                     "attempting to allocate %d MSI vectors (%d supported)\n",
 1802                     *count, cfg->msi.msi_msgnum);
 1803 
 1804         /* Don't ask for more than the device supports. */
 1805         actual = min(*count, cfg->msi.msi_msgnum);
 1806 
 1807         /* Don't ask for more than 32 messages. */
 1808         actual = min(actual, 32);
 1809 
 1810         /* MSI requires power of 2 number of messages. */
 1811         if (!powerof2(actual))
 1812                 return (EINVAL);
 1813 
 1814         for (;;) {
 1815                 /* Try to allocate N messages. */
 1816                 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
 1817                     cfg->msi.msi_msgnum, irqs);
 1818                 if (error == 0)
 1819                         break;
 1820                 if (actual == 1)
 1821                         return (error);
 1822 
 1823                 /* Try N / 2. */
 1824                 actual >>= 1;
 1825         }
 1826 
 1827         /*
 1828          * We now have N actual messages mapped onto SYS_RES_IRQ
 1829          * resources in the irqs[] array, so add new resources
 1830          * starting at rid 1.
 1831          */
 1832         for (i = 0; i < actual; i++)
 1833                 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
 1834                     irqs[i], irqs[i], 1);
 1835 
 1836         if (bootverbose) {
 1837                 if (actual == 1)
 1838                         device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
 1839                 else {
 1840                         int run;
 1841 
 1842                         /*
 1843                          * Be fancy and try to print contiguous runs
 1844                          * of IRQ values as ranges.  'run' is true if
 1845                          * we are in a range.
 1846                          */
 1847                         device_printf(child, "using IRQs %d", irqs[0]);
 1848                         run = 0;
 1849                         for (i = 1; i < actual; i++) {
 1850 
 1851                                 /* Still in a run? */
 1852                                 if (irqs[i] == irqs[i - 1] + 1) {
 1853                                         run = 1;
 1854                                         continue;
 1855                                 }
 1856 
 1857                                 /* Finish previous range. */
 1858                                 if (run) {
 1859                                         printf("-%d", irqs[i - 1]);
 1860                                         run = 0;
 1861                                 }
 1862 
 1863                                 /* Start new range. */
 1864                                 printf(",%d", irqs[i]);
 1865                         }
 1866 
 1867                         /* Unfinished range? */
 1868                         if (run)
 1869                                 printf("-%d", irqs[actual - 1]);
 1870                         printf(" for MSI\n");
 1871                 }
 1872         }
 1873 
 1874         /* Update control register with actual count. */
 1875         ctrl = cfg->msi.msi_ctrl;
 1876         ctrl &= ~PCIM_MSICTRL_MME_MASK;
 1877         ctrl |= (ffs(actual) - 1) << 4;
 1878         cfg->msi.msi_ctrl = ctrl;
 1879         pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
 1880 
 1881         /* Update counts of alloc'd messages. */
 1882         cfg->msi.msi_alloc = actual;
 1883         cfg->msi.msi_handlers = 0;
 1884         *count = actual;
 1885         return (0);
 1886 }
 1887 
 1888 /* Release the MSI messages associated with this device. */
 1889 int
 1890 pci_release_msi_method(device_t dev, device_t child)
 1891 {
 1892         struct pci_devinfo *dinfo = device_get_ivars(child);
 1893         struct pcicfg_msi *msi = &dinfo->cfg.msi;
 1894         struct resource_list_entry *rle;
 1895         int error, i, irqs[32];
 1896 
 1897         /* Try MSI-X first. */
 1898         error = pci_release_msix(dev, child);
 1899         if (error != ENODEV)
 1900                 return (error);
 1901 
 1902         /* Do we have any messages to release? */
 1903         if (msi->msi_alloc == 0)
 1904                 return (ENODEV);
 1905         KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
 1906 
 1907         /* Make sure none of the resources are allocated. */
 1908         if (msi->msi_handlers > 0)
 1909                 return (EBUSY);
 1910         for (i = 0; i < msi->msi_alloc; i++) {
 1911                 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
 1912                 KASSERT(rle != NULL, ("missing MSI resource"));
 1913                 if (rle->res != NULL)
 1914                         return (EBUSY);
 1915                 irqs[i] = rle->start;
 1916         }
 1917 
 1918         /* Update control register with 0 count. */
 1919         KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
 1920             ("%s: MSI still enabled", __func__));
 1921         msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
 1922         pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
 1923             msi->msi_ctrl, 2);
 1924 
 1925         /* Release the messages. */
 1926         PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
 1927         for (i = 0; i < msi->msi_alloc; i++)
 1928                 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
 1929 
 1930         /* Update alloc count. */
 1931         msi->msi_alloc = 0;
 1932         msi->msi_addr = 0;
 1933         msi->msi_data = 0;
 1934         return (0);
 1935 }
 1936 
 1937 /*
 1938  * Return the max supported MSI messages this device supports.
 1939  * Basically, assuming the MD code can alloc messages, this function
 1940  * should return the maximum value that pci_alloc_msi() can return.
 1941  * Thus, it is subject to the tunables, etc.
 1942  */
 1943 int
 1944 pci_msi_count_method(device_t dev, device_t child)
 1945 {
 1946         struct pci_devinfo *dinfo = device_get_ivars(child);
 1947         struct pcicfg_msi *msi = &dinfo->cfg.msi;
 1948 
 1949         if (pci_do_msi && msi->msi_location != 0)
 1950                 return (msi->msi_msgnum);
 1951         return (0);
 1952 }
 1953 
 1954 /* free pcicfgregs structure and all depending data structures */
 1955 
 1956 int
 1957 pci_freecfg(struct pci_devinfo *dinfo)
 1958 {
 1959         struct devlist *devlist_head;
 1960         int i;
 1961 
 1962         devlist_head = &pci_devq;
 1963 
 1964         if (dinfo->cfg.vpd.vpd_reg) {
 1965                 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
 1966                 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
 1967                         free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
 1968                 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
 1969                 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
 1970                         free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
 1971                 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
 1972         }
 1973         STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
 1974         free(dinfo, M_DEVBUF);
 1975 
 1976         /* increment the generation count */
 1977         pci_generation++;
 1978 
 1979         /* we're losing one device */
 1980         pci_numdevs--;
 1981         return (0);
 1982 }
 1983 
 1984 /*
 1985  * PCI power manangement
 1986  */
 1987 int
 1988 pci_set_powerstate_method(device_t dev, device_t child, int state)
 1989 {
 1990         struct pci_devinfo *dinfo = device_get_ivars(child);
 1991         pcicfgregs *cfg = &dinfo->cfg;
 1992         uint16_t status;
 1993         int result, oldstate, highest, delay;
 1994 
 1995         if (cfg->pp.pp_cap == 0)
 1996                 return (EOPNOTSUPP);
 1997 
 1998         /*
 1999          * Optimize a no state change request away.  While it would be OK to
 2000          * write to the hardware in theory, some devices have shown odd
 2001          * behavior when going from D3 -> D3.
 2002          */
 2003         oldstate = pci_get_powerstate(child);
 2004         if (oldstate == state)
 2005                 return (0);
 2006 
 2007         /*
 2008          * The PCI power management specification states that after a state
 2009          * transition between PCI power states, system software must
 2010          * guarantee a minimal delay before the function accesses the device.
 2011          * Compute the worst case delay that we need to guarantee before we
 2012          * access the device.  Many devices will be responsive much more
 2013          * quickly than this delay, but there are some that don't respond
 2014          * instantly to state changes.  Transitions to/from D3 state require
 2015          * 10ms, while D2 requires 200us, and D0/1 require none.  The delay
 2016          * is done below with DELAY rather than a sleeper function because
 2017          * this function can be called from contexts where we cannot sleep.
 2018          */
 2019         highest = (oldstate > state) ? oldstate : state;
 2020         if (highest == PCI_POWERSTATE_D3)
 2021             delay = 10000;
 2022         else if (highest == PCI_POWERSTATE_D2)
 2023             delay = 200;
 2024         else
 2025             delay = 0;
 2026         status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
 2027             & ~PCIM_PSTAT_DMASK;
 2028         result = 0;
 2029         switch (state) {
 2030         case PCI_POWERSTATE_D0:
 2031                 status |= PCIM_PSTAT_D0;
 2032                 break;
 2033         case PCI_POWERSTATE_D1:
 2034                 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
 2035                         return (EOPNOTSUPP);
 2036                 status |= PCIM_PSTAT_D1;
 2037                 break;
 2038         case PCI_POWERSTATE_D2:
 2039                 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
 2040                         return (EOPNOTSUPP);
 2041                 status |= PCIM_PSTAT_D2;
 2042                 break;
 2043         case PCI_POWERSTATE_D3:
 2044                 status |= PCIM_PSTAT_D3;
 2045                 break;
 2046         default:
 2047                 return (EINVAL);
 2048         }
 2049 
 2050         if (bootverbose)
 2051                 printf(
 2052                     "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
 2053                     dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
 2054                     dinfo->cfg.func, oldstate, state);
 2055 
 2056         PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
 2057         if (delay)
 2058                 DELAY(delay);
 2059         return (0);
 2060 }
 2061 
 2062 int
 2063 pci_get_powerstate_method(device_t dev, device_t child)
 2064 {
 2065         struct pci_devinfo *dinfo = device_get_ivars(child);
 2066         pcicfgregs *cfg = &dinfo->cfg;
 2067         uint16_t status;
 2068         int result;
 2069 
 2070         if (cfg->pp.pp_cap != 0) {
 2071                 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
 2072                 switch (status & PCIM_PSTAT_DMASK) {
 2073                 case PCIM_PSTAT_D0:
 2074                         result = PCI_POWERSTATE_D0;
 2075                         break;
 2076                 case PCIM_PSTAT_D1:
 2077                         result = PCI_POWERSTATE_D1;
 2078                         break;
 2079                 case PCIM_PSTAT_D2:
 2080                         result = PCI_POWERSTATE_D2;
 2081                         break;
 2082                 case PCIM_PSTAT_D3:
 2083                         result = PCI_POWERSTATE_D3;
 2084                         break;
 2085                 default:
 2086                         result = PCI_POWERSTATE_UNKNOWN;
 2087                         break;
 2088                 }
 2089         } else {
 2090                 /* No support, device is always at D0 */
 2091                 result = PCI_POWERSTATE_D0;
 2092         }
 2093         return (result);
 2094 }
 2095 
 2096 /*
 2097  * Some convenience functions for PCI device drivers.
 2098  */
 2099 
 2100 static __inline void
 2101 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
 2102 {
 2103         uint16_t        command;
 2104 
 2105         command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
 2106         command |= bit;
 2107         PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
 2108 }
 2109 
 2110 static __inline void
 2111 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
 2112 {
 2113         uint16_t        command;
 2114 
 2115         command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
 2116         command &= ~bit;
 2117         PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
 2118 }
 2119 
 2120 int
 2121 pci_enable_busmaster_method(device_t dev, device_t child)
 2122 {
 2123         pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
 2124         return (0);
 2125 }
 2126 
 2127 int
 2128 pci_disable_busmaster_method(device_t dev, device_t child)
 2129 {
 2130         pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
 2131         return (0);
 2132 }
 2133 
 2134 int
 2135 pci_enable_io_method(device_t dev, device_t child, int space)
 2136 {
 2137         uint16_t bit;
 2138 
 2139         switch(space) {
 2140         case SYS_RES_IOPORT:
 2141                 bit = PCIM_CMD_PORTEN;
 2142                 break;
 2143         case SYS_RES_MEMORY:
 2144                 bit = PCIM_CMD_MEMEN;
 2145                 break;
 2146         default:
 2147                 return (EINVAL);
 2148         }
 2149         pci_set_command_bit(dev, child, bit);
 2150         return (0);
 2151 }
 2152 
 2153 int
 2154 pci_disable_io_method(device_t dev, device_t child, int space)
 2155 {
 2156         uint16_t bit;
 2157 
 2158         switch(space) {
 2159         case SYS_RES_IOPORT:
 2160                 bit = PCIM_CMD_PORTEN;
 2161                 break;
 2162         case SYS_RES_MEMORY:
 2163                 bit = PCIM_CMD_MEMEN;
 2164                 break;
 2165         default:
 2166                 return (EINVAL);
 2167         }
 2168         pci_clear_command_bit(dev, child, bit);
 2169         return (0);
 2170 }
 2171 
 2172 /*
 2173  * New style pci driver.  Parent device is either a pci-host-bridge or a
 2174  * pci-pci-bridge.  Both kinds are represented by instances of pcib.
 2175  */
 2176 
 2177 void
 2178 pci_print_verbose(struct pci_devinfo *dinfo)
 2179 {
 2180 
 2181         if (bootverbose) {
 2182                 pcicfgregs *cfg = &dinfo->cfg;
 2183 
 2184                 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
 2185                     cfg->vendor, cfg->device, cfg->revid);
 2186                 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
 2187                     cfg->domain, cfg->bus, cfg->slot, cfg->func);
 2188                 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
 2189                     cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
 2190                     cfg->mfdev);
 2191                 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
 2192                     cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
 2193                 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
 2194                     cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
 2195                     cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
 2196                 if (cfg->intpin > 0)
 2197                         printf("\tintpin=%c, irq=%d\n",
 2198                             cfg->intpin +'a' -1, cfg->intline);
 2199                 if (cfg->pp.pp_cap) {
 2200                         uint16_t status;
 2201 
 2202                         status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
 2203                         printf("\tpowerspec %d  supports D0%s%s D3  current D%d\n",
 2204                             cfg->pp.pp_cap & PCIM_PCAP_SPEC,
 2205                             cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
 2206                             cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
 2207                             status & PCIM_PSTAT_DMASK);
 2208                 }
 2209                 if (cfg->msi.msi_location) {
 2210                         int ctrl;
 2211 
 2212                         ctrl = cfg->msi.msi_ctrl;
 2213                         printf("\tMSI supports %d message%s%s%s\n",
 2214                             cfg->msi.msi_msgnum,
 2215                             (cfg->msi.msi_msgnum == 1) ? "" : "s",
 2216                             (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
 2217                             (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
 2218                 }
 2219                 if (cfg->msix.msix_location) {
 2220                         printf("\tMSI-X supports %d message%s ",
 2221                             cfg->msix.msix_msgnum,
 2222                             (cfg->msix.msix_msgnum == 1) ? "" : "s");
 2223                         if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
 2224                                 printf("in map 0x%x\n",
 2225                                     cfg->msix.msix_table_bar);
 2226                         else
 2227                                 printf("in maps 0x%x and 0x%x\n",
 2228                                     cfg->msix.msix_table_bar,
 2229                                     cfg->msix.msix_pba_bar);
 2230                 }
 2231         }
 2232 }
 2233 
 2234 static int
 2235 pci_porten(device_t dev)
 2236 {
 2237         return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
 2238 }
 2239 
 2240 static int
 2241 pci_memen(device_t dev)
 2242 {
 2243         return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
 2244 }
 2245 
 2246 static void
 2247 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
 2248 {
 2249         pci_addr_t map, testval;
 2250         int ln2range;
 2251         uint16_t cmd;
 2252 
 2253         map = pci_read_config(dev, reg, 4);
 2254         ln2range = pci_maprange(map);
 2255         if (ln2range == 64)
 2256                 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
 2257 
 2258         /*
 2259          * Disable decoding via the command register before
 2260          * determining the BAR's length since we will be placing it in
 2261          * a weird state.
 2262          */
 2263         cmd = pci_read_config(dev, PCIR_COMMAND, 2);
 2264         pci_write_config(dev, PCIR_COMMAND,
 2265             cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
 2266 
 2267         /*
 2268          * Determine the BAR's length by writing all 1's.  The bottom
 2269          * log_2(size) bits of the BAR will stick as 0 when we read
 2270          * the value back.
 2271          */
 2272         pci_write_config(dev, reg, 0xffffffff, 4);
 2273         testval = pci_read_config(dev, reg, 4);
 2274         if (ln2range == 64) {
 2275                 pci_write_config(dev, reg + 4, 0xffffffff, 4);
 2276                 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
 2277         }
 2278 
 2279         /*
 2280          * Restore the original value of the BAR.  We may have reprogrammed
 2281          * the BAR of the low-level console device and when booting verbose,
 2282          * we need the console device addressable.
 2283          */
 2284         pci_write_config(dev, reg, map, 4);
 2285         if (ln2range == 64)
 2286                 pci_write_config(dev, reg + 4, map >> 32, 4);
 2287         pci_write_config(dev, PCIR_COMMAND, cmd, 2);
 2288 
 2289         *mapp = map;
 2290         *testvalp = testval;
 2291 }
 2292 
 2293 static void
 2294 pci_write_bar(device_t dev, int reg, pci_addr_t base)
 2295 {
 2296         pci_addr_t map;
 2297         int ln2range;
 2298 
 2299         map = pci_read_config(dev, reg, 4);
 2300         ln2range = pci_maprange(map);
 2301         pci_write_config(dev, reg, base, 4);
 2302         if (ln2range == 64)
 2303                 pci_write_config(dev, reg + 4, base >> 32, 4);
 2304 }
 2305 
 2306 /*
 2307  * Add a resource based on a pci map register. Return 1 if the map
 2308  * register is a 32bit map register or 2 if it is a 64bit register.
 2309  */
 2310 static int
 2311 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
 2312     int force, int prefetch)
 2313 {
 2314         pci_addr_t base, map, testval;
 2315         pci_addr_t start, end, count;
 2316         int barlen, basezero, maprange, mapsize, type;
 2317         uint16_t cmd;
 2318         struct resource *res;
 2319 
 2320         pci_read_bar(dev, reg, &map, &testval);
 2321         if (PCI_BAR_MEM(map)) {
 2322                 type = SYS_RES_MEMORY;
 2323                 if (map & PCIM_BAR_MEM_PREFETCH)
 2324                         prefetch = 1;
 2325         } else
 2326                 type = SYS_RES_IOPORT;
 2327         mapsize = pci_mapsize(testval);
 2328         base = pci_mapbase(map);
 2329 #ifdef __PCI_BAR_ZERO_VALID
 2330         basezero = 0;
 2331 #else
 2332         basezero = base == 0;
 2333 #endif
 2334         maprange = pci_maprange(map);
 2335         barlen = maprange == 64 ? 2 : 1;
 2336 
 2337         /*
 2338          * For I/O registers, if bottom bit is set, and the next bit up
 2339          * isn't clear, we know we have a BAR that doesn't conform to the
 2340          * spec, so ignore it.  Also, sanity check the size of the data
 2341          * areas to the type of memory involved.  Memory must be at least
 2342          * 16 bytes in size, while I/O ranges must be at least 4.
 2343          */
 2344         if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
 2345                 return (barlen);
 2346         if ((type == SYS_RES_MEMORY && mapsize < 4) ||
 2347             (type == SYS_RES_IOPORT && mapsize < 2))
 2348                 return (barlen);
 2349 
 2350         if (bootverbose) {
 2351                 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
 2352                     reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
 2353                 if (type == SYS_RES_IOPORT && !pci_porten(dev))
 2354                         printf(", port disabled\n");
 2355                 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
 2356                         printf(", memory disabled\n");
 2357                 else
 2358                         printf(", enabled\n");
 2359         }
 2360 
 2361         /*
 2362          * If base is 0, then we have problems if this architecture does
 2363          * not allow that.  It is best to ignore such entries for the
 2364          * moment.  These will be allocated later if the driver specifically
 2365          * requests them.  However, some removable busses look better when
 2366          * all resources are allocated, so allow '' to be overriden.
 2367          *
 2368          * Similarly treat maps whose values is the same as the test value
 2369          * read back.  These maps have had all f's written to them by the
 2370          * BIOS in an attempt to disable the resources.
 2371          */
 2372         if (!force && (basezero || map == testval))
 2373                 return (barlen);
 2374         if ((u_long)base != base) {
 2375                 device_printf(bus,
 2376                     "pci%d:%d:%d:%d bar %#x too many address bits",
 2377                     pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
 2378                     pci_get_function(dev), reg);
 2379                 return (barlen);
 2380         }
 2381 
 2382         /*
 2383          * This code theoretically does the right thing, but has
 2384          * undesirable side effects in some cases where peripherals
 2385          * respond oddly to having these bits enabled.  Let the user
 2386          * be able to turn them off (since pci_enable_io_modes is 1 by
 2387          * default).
 2388          */
 2389         if (pci_enable_io_modes) {
 2390                 /* Turn on resources that have been left off by a lazy BIOS */
 2391                 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
 2392                         cmd = pci_read_config(dev, PCIR_COMMAND, 2);
 2393                         cmd |= PCIM_CMD_PORTEN;
 2394                         pci_write_config(dev, PCIR_COMMAND, cmd, 2);
 2395                 }
 2396                 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
 2397                         cmd = pci_read_config(dev, PCIR_COMMAND, 2);
 2398                         cmd |= PCIM_CMD_MEMEN;
 2399                         pci_write_config(dev, PCIR_COMMAND, cmd, 2);
 2400                 }
 2401         } else {
 2402                 if (type == SYS_RES_IOPORT && !pci_porten(dev))
 2403                         return (barlen);
 2404                 if (type == SYS_RES_MEMORY && !pci_memen(dev))
 2405                         return (barlen);
 2406         }
 2407 
 2408         count = 1 << mapsize;
 2409         if (basezero || base == pci_mapbase(testval)) {
 2410                 start = 0;      /* Let the parent decide. */
 2411                 end = ~0ULL;
 2412         } else {
 2413                 start = base;
 2414                 end = base + (1 << mapsize) - 1;
 2415         }
 2416         resource_list_add(rl, type, reg, start, end, count);
 2417 
 2418         /*
 2419          * Try to allocate the resource for this BAR from our parent
 2420          * so that this resource range is already reserved.  The
 2421          * driver for this device will later inherit this resource in
 2422          * pci_alloc_resource().
 2423          */
 2424         res = resource_list_alloc(rl, bus, dev, type, &reg, start, end, count,
 2425             prefetch ? RF_PREFETCHABLE : 0);
 2426         if (res == NULL) {
 2427                 /*
 2428                  * If the allocation fails, clear the BAR and delete
 2429                  * the resource list entry to force
 2430                  * pci_alloc_resource() to allocate resources from the
 2431                  * parent.
 2432                  */
 2433                 resource_list_delete(rl, type, reg);
 2434                 start = 0;
 2435         } else {
 2436                 start = rman_get_start(res);
 2437                 rman_set_device(res, bus);
 2438         }
 2439         pci_write_bar(dev, reg, start);
 2440         return (barlen);
 2441 }
 2442 
 2443 /*
 2444  * For ATA devices we need to decide early what addressing mode to use.
 2445  * Legacy demands that the primary and secondary ATA ports sits on the
 2446  * same addresses that old ISA hardware did. This dictates that we use
 2447  * those addresses and ignore the BAR's if we cannot set PCI native
 2448  * addressing mode.
 2449  */
 2450 static void
 2451 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
 2452     uint32_t prefetchmask)
 2453 {
 2454         struct resource *r;
 2455         int rid, type, progif;
 2456 #if 0
 2457         /* if this device supports PCI native addressing use it */
 2458         progif = pci_read_config(dev, PCIR_PROGIF, 1);
 2459         if ((progif & 0x8a) == 0x8a) {
 2460                 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
 2461                     pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
 2462                         printf("Trying ATA native PCI addressing mode\n");
 2463                         pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
 2464                 }
 2465         }
 2466 #endif
 2467         progif = pci_read_config(dev, PCIR_PROGIF, 1);
 2468         type = SYS_RES_IOPORT;
 2469         if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
 2470                 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
 2471                     prefetchmask & (1 << 0));
 2472                 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
 2473                     prefetchmask & (1 << 1));
 2474         } else {
 2475                 rid = PCIR_BAR(0);
 2476                 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
 2477                 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,
 2478                     8, 0);
 2479                 rman_set_device(r, bus);
 2480                 rid = PCIR_BAR(1);
 2481                 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
 2482                 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,
 2483                     1, 0);
 2484                 rman_set_device(r, bus);
 2485         }
 2486         if (progif & PCIP_STORAGE_IDE_MODESEC) {
 2487                 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
 2488                     prefetchmask & (1 << 2));
 2489                 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
 2490                     prefetchmask & (1 << 3));
 2491         } else {
 2492                 rid = PCIR_BAR(2);
 2493                 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
 2494                 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,
 2495                     8, 0);
 2496                 rman_set_device(r, bus);
 2497                 rid = PCIR_BAR(3);
 2498                 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
 2499                 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,
 2500                     1, 0);
 2501                 rman_set_device(r, bus);
 2502         }
 2503         pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
 2504             prefetchmask & (1 << 4));
 2505         pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
 2506             prefetchmask & (1 << 5));
 2507 }
 2508 
 2509 static void
 2510 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
 2511 {
 2512         struct pci_devinfo *dinfo = device_get_ivars(dev);
 2513         pcicfgregs *cfg = &dinfo->cfg;
 2514         char tunable_name[64];
 2515         int irq;
 2516 
 2517         /* Has to have an intpin to have an interrupt. */
 2518         if (cfg->intpin == 0)
 2519                 return;
 2520 
 2521         /* Let the user override the IRQ with a tunable. */
 2522         irq = PCI_INVALID_IRQ;
 2523         snprintf(tunable_name, sizeof(tunable_name),
 2524             "hw.pci%d.%d.%d.INT%c.irq",
 2525             cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
 2526         if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
 2527                 irq = PCI_INVALID_IRQ;
 2528 
 2529         /*
 2530          * If we didn't get an IRQ via the tunable, then we either use the
 2531          * IRQ value in the intline register or we ask the bus to route an
 2532          * interrupt for us.  If force_route is true, then we only use the
 2533          * value in the intline register if the bus was unable to assign an
 2534          * IRQ.
 2535          */
 2536         if (!PCI_INTERRUPT_VALID(irq)) {
 2537                 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
 2538                         irq = PCI_ASSIGN_INTERRUPT(bus, dev);
 2539                 if (!PCI_INTERRUPT_VALID(irq))
 2540                         irq = cfg->intline;
 2541         }
 2542 
 2543         /* If after all that we don't have an IRQ, just bail. */
 2544         if (!PCI_INTERRUPT_VALID(irq))
 2545                 return;
 2546 
 2547         /* Update the config register if it changed. */
 2548         if (irq != cfg->intline) {
 2549                 cfg->intline = irq;
 2550                 pci_write_config(dev, PCIR_INTLINE, irq, 1);
 2551         }
 2552 
 2553         /* Add this IRQ as rid 0 interrupt resource. */
 2554         resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
 2555 }
 2556 
 2557 void
 2558 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
 2559 {
 2560         struct pci_devinfo *dinfo = device_get_ivars(dev);
 2561         pcicfgregs *cfg = &dinfo->cfg;
 2562         struct resource_list *rl = &dinfo->resources;
 2563         struct pci_quirk *q;
 2564         int i;
 2565 
 2566         /* ATA devices needs special map treatment */
 2567         if ((pci_get_class(dev) == PCIC_STORAGE) &&
 2568             (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
 2569             ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
 2570              (!pci_read_config(dev, PCIR_BAR(0), 4) &&
 2571               !pci_read_config(dev, PCIR_BAR(2), 4))) )
 2572                 pci_ata_maps(bus, dev, rl, force, prefetchmask);
 2573         else
 2574                 for (i = 0; i < cfg->nummaps;)
 2575                         i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
 2576                             prefetchmask & (1 << i));
 2577 
 2578         /*
 2579          * Add additional, quirked resources.
 2580          */
 2581         for (q = &pci_quirks[0]; q->devid; q++) {
 2582                 if (q->devid == ((cfg->device << 16) | cfg->vendor)
 2583                     && q->type == PCI_QUIRK_MAP_REG)
 2584                         pci_add_map(bus, dev, q->arg1, rl, force, 0);
 2585         }
 2586 
 2587         if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
 2588 #ifdef __PCI_REROUTE_INTERRUPT
 2589                 /*
 2590                  * Try to re-route interrupts. Sometimes the BIOS or
 2591                  * firmware may leave bogus values in these registers.
 2592                  * If the re-route fails, then just stick with what we
 2593                  * have.
 2594                  */
 2595                 pci_assign_interrupt(bus, dev, 1);
 2596 #else
 2597                 pci_assign_interrupt(bus, dev, 0);
 2598 #endif
 2599         }
 2600 }
 2601 
 2602 void
 2603 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
 2604 {
 2605 #define REG(n, w)       PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
 2606         device_t pcib = device_get_parent(dev);
 2607         struct pci_devinfo *dinfo;
 2608         int maxslots;
 2609         int s, f, pcifunchigh;
 2610         uint8_t hdrtype;
 2611 
 2612         KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
 2613             ("dinfo_size too small"));
 2614         maxslots = PCIB_MAXSLOTS(pcib);
 2615         for (s = 0; s <= maxslots; s++) {
 2616                 pcifunchigh = 0;
 2617                 f = 0;
 2618                 DELAY(1);
 2619                 hdrtype = REG(PCIR_HDRTYPE, 1);
 2620                 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
 2621                         continue;
 2622                 if (hdrtype & PCIM_MFDEV)
 2623                         pcifunchigh = PCI_FUNCMAX;
 2624                 for (f = 0; f <= pcifunchigh; f++) {
 2625                         dinfo = pci_read_device(pcib, domain, busno, s, f,
 2626                             dinfo_size);
 2627                         if (dinfo != NULL) {
 2628                                 pci_add_child(dev, dinfo);
 2629                         }
 2630                 }
 2631         }
 2632 #undef REG
 2633 }
 2634 
 2635 void
 2636 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
 2637 {
 2638         dinfo->cfg.dev = device_add_child(bus, NULL, -1);
 2639         device_set_ivars(dinfo->cfg.dev, dinfo);
 2640         resource_list_init(&dinfo->resources);
 2641         pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
 2642         pci_cfg_restore(dinfo->cfg.dev, dinfo);
 2643         pci_print_verbose(dinfo);
 2644         pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
 2645 }
 2646 
 2647 static int
 2648 pci_probe(device_t dev)
 2649 {
 2650 
 2651         device_set_desc(dev, "PCI bus");
 2652 
 2653         /* Allow other subclasses to override this driver. */
 2654         return (-1000);
 2655 }
 2656 
 2657 static int
 2658 pci_attach(device_t dev)
 2659 {
 2660         int busno, domain;
 2661 
 2662         /*
 2663          * Since there can be multiple independantly numbered PCI
 2664          * busses on systems with multiple PCI domains, we can't use
 2665          * the unit number to decide which bus we are probing. We ask
 2666          * the parent pcib what our domain and bus numbers are.
 2667          */
 2668         domain = pcib_get_domain(dev);
 2669         busno = pcib_get_bus(dev);
 2670         if (bootverbose)
 2671                 device_printf(dev, "domain=%d, physical bus=%d\n",
 2672                     domain, busno);
 2673 
 2674         pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
 2675 
 2676         return (bus_generic_attach(dev));
 2677 }
 2678 
 2679 int
 2680 pci_suspend(device_t dev)
 2681 {
 2682         int dstate, error, i, numdevs;
 2683         device_t acpi_dev, child, *devlist;
 2684         struct pci_devinfo *dinfo;
 2685 
 2686         /*
 2687          * Save the PCI configuration space for each child and set the
 2688          * device in the appropriate power state for this sleep state.
 2689          */
 2690         acpi_dev = NULL;
 2691         if (pci_do_power_resume)
 2692                 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
 2693         device_get_children(dev, &devlist, &numdevs);
 2694         for (i = 0; i < numdevs; i++) {
 2695                 child = devlist[i];
 2696                 dinfo = (struct pci_devinfo *) device_get_ivars(child);
 2697                 pci_cfg_save(child, dinfo, 0);
 2698         }
 2699 
 2700         /* Suspend devices before potentially powering them down. */
 2701         error = bus_generic_suspend(dev);
 2702         if (error) {
 2703                 free(devlist, M_TEMP);
 2704                 return (error);
 2705         }
 2706 
 2707         /*
 2708          * Always set the device to D3.  If ACPI suggests a different
 2709          * power state, use it instead.  If ACPI is not present, the
 2710          * firmware is responsible for managing device power.  Skip
 2711          * children who aren't attached since they are powered down
 2712          * separately.  Only manage type 0 devices for now.
 2713          */
 2714         for (i = 0; acpi_dev && i < numdevs; i++) {
 2715                 child = devlist[i];
 2716                 dinfo = (struct pci_devinfo *) device_get_ivars(child);
 2717                 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
 2718                         dstate = PCI_POWERSTATE_D3;
 2719                         ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
 2720                         pci_set_powerstate(child, dstate);
 2721                 }
 2722         }
 2723         free(devlist, M_TEMP);
 2724         return (0);
 2725 }
 2726 
 2727 int
 2728 pci_resume(device_t dev)
 2729 {
 2730         int i, numdevs;
 2731         device_t acpi_dev, child, *devlist;
 2732         struct pci_devinfo *dinfo;
 2733 
 2734         /*
 2735          * Set each child to D0 and restore its PCI configuration space.
 2736          */
 2737         acpi_dev = NULL;
 2738         if (pci_do_power_resume)
 2739                 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
 2740         device_get_children(dev, &devlist, &numdevs);
 2741         for (i = 0; i < numdevs; i++) {
 2742                 /*
 2743                  * Notify ACPI we're going to D0 but ignore the result.  If
 2744                  * ACPI is not present, the firmware is responsible for
 2745                  * managing device power.  Only manage type 0 devices for now.
 2746                  */
 2747                 child = devlist[i];
 2748                 dinfo = (struct pci_devinfo *) device_get_ivars(child);
 2749                 if (acpi_dev && device_is_attached(child) &&
 2750                     dinfo->cfg.hdrtype == 0) {
 2751                         ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
 2752                         pci_set_powerstate(child, PCI_POWERSTATE_D0);
 2753                 }
 2754 
 2755                 /* Now the device is powered up, restore its config space. */
 2756                 pci_cfg_restore(child, dinfo);
 2757         }
 2758         free(devlist, M_TEMP);
 2759         return (bus_generic_resume(dev));
 2760 }
 2761 
 2762 static void
 2763 pci_load_vendor_data(void)
 2764 {
 2765         caddr_t vendordata, info;
 2766 
 2767         if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
 2768                 info = preload_search_info(vendordata, MODINFO_ADDR);
 2769                 pci_vendordata = *(char **)info;
 2770                 info = preload_search_info(vendordata, MODINFO_SIZE);
 2771                 pci_vendordata_size = *(size_t *)info;
 2772                 /* terminate the database */
 2773                 pci_vendordata[pci_vendordata_size] = '\n';
 2774         }
 2775 }
 2776 
 2777 void
 2778 pci_driver_added(device_t dev, driver_t *driver)
 2779 {
 2780         int numdevs;
 2781         device_t *devlist;
 2782         device_t child;
 2783         struct pci_devinfo *dinfo;
 2784         int i;
 2785 
 2786         if (bootverbose)
 2787                 device_printf(dev, "driver added\n");
 2788         DEVICE_IDENTIFY(driver, dev);
 2789         device_get_children(dev, &devlist, &numdevs);
 2790         for (i = 0; i < numdevs; i++) {
 2791                 child = devlist[i];
 2792                 if (device_get_state(child) != DS_NOTPRESENT)
 2793                         continue;
 2794                 dinfo = device_get_ivars(child);
 2795                 pci_print_verbose(dinfo);
 2796                 if (bootverbose)
 2797                         printf("pci%d:%d:%d:%d: reprobing on driver added\n",
 2798                             dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
 2799                             dinfo->cfg.func);
 2800                 pci_cfg_restore(child, dinfo);
 2801                 if (device_probe_and_attach(child) != 0)
 2802                         pci_cfg_save(child, dinfo, 1);
 2803         }
 2804         free(devlist, M_TEMP);
 2805 }
 2806 
 2807 int
 2808 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
 2809     driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
 2810 {
 2811         struct pci_devinfo *dinfo;
 2812         struct msix_table_entry *mte;
 2813         struct msix_vector *mv;
 2814         uint64_t addr;
 2815         uint32_t data;
 2816         void *cookie;
 2817         int error, rid;
 2818 
 2819         error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
 2820             arg, &cookie);
 2821         if (error)
 2822                 return (error);
 2823 
 2824         /* If this is not a direct child, just bail out. */
 2825         if (device_get_parent(child) != dev) {
 2826                 *cookiep = cookie;
 2827                 return(0);
 2828         }
 2829 
 2830         rid = rman_get_rid(irq);
 2831         if (rid == 0) {
 2832                 /* Make sure that INTx is enabled */
 2833                 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
 2834         } else {
 2835                 /*
 2836                  * Check to see if the interrupt is MSI or MSI-X.
 2837                  * Ask our parent to map the MSI and give
 2838                  * us the address and data register values.
 2839                  * If we fail for some reason, teardown the
 2840                  * interrupt handler.
 2841                  */
 2842                 dinfo = device_get_ivars(child);
 2843                 if (dinfo->cfg.msi.msi_alloc > 0) {
 2844                         if (dinfo->cfg.msi.msi_addr == 0) {
 2845                                 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
 2846                             ("MSI has handlers, but vectors not mapped"));
 2847                                 error = PCIB_MAP_MSI(device_get_parent(dev),
 2848                                     child, rman_get_start(irq), &addr, &data);
 2849                                 if (error)
 2850                                         goto bad;
 2851                                 dinfo->cfg.msi.msi_addr = addr;
 2852                                 dinfo->cfg.msi.msi_data = data;
 2853                         }
 2854                         if (dinfo->cfg.msi.msi_handlers == 0)
 2855                                 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
 2856                                     dinfo->cfg.msi.msi_data);
 2857                         dinfo->cfg.msi.msi_handlers++;
 2858                 } else {
 2859                         KASSERT(dinfo->cfg.msix.msix_alloc > 0,
 2860                             ("No MSI or MSI-X interrupts allocated"));
 2861                         KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
 2862                             ("MSI-X index too high"));
 2863                         mte = &dinfo->cfg.msix.msix_table[rid - 1];
 2864                         KASSERT(mte->mte_vector != 0, ("no message vector"));
 2865                         mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
 2866                         KASSERT(mv->mv_irq == rman_get_start(irq),
 2867                             ("IRQ mismatch"));
 2868                         if (mv->mv_address == 0) {
 2869                                 KASSERT(mte->mte_handlers == 0,
 2870                     ("MSI-X table entry has handlers, but vector not mapped"));
 2871                                 error = PCIB_MAP_MSI(device_get_parent(dev),
 2872                                     child, rman_get_start(irq), &addr, &data);
 2873                                 if (error)
 2874                                         goto bad;
 2875                                 mv->mv_address = addr;
 2876                                 mv->mv_data = data;
 2877                         }
 2878                         if (mte->mte_handlers == 0) {
 2879                                 pci_enable_msix(child, rid - 1, mv->mv_address,
 2880                                     mv->mv_data);
 2881                                 pci_unmask_msix(child, rid - 1);
 2882                         }
 2883                         mte->mte_handlers++;
 2884                 }
 2885 
 2886                 /* Make sure that INTx is disabled if we are using MSI/MSIX */
 2887                 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
 2888         bad:
 2889                 if (error) {
 2890                         (void)bus_generic_teardown_intr(dev, child, irq,
 2891                             cookie);
 2892                         return (error);
 2893                 }
 2894         }
 2895         *cookiep = cookie;
 2896         return (0);
 2897 }
 2898 
 2899 int
 2900 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
 2901     void *cookie)
 2902 {
 2903         struct msix_table_entry *mte;
 2904         struct resource_list_entry *rle;
 2905         struct pci_devinfo *dinfo;
 2906         int error, rid;
 2907 
 2908         if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
 2909                 return (EINVAL);
 2910 
 2911         /* If this isn't a direct child, just bail out */
 2912         if (device_get_parent(child) != dev)
 2913                 return(bus_generic_teardown_intr(dev, child, irq, cookie));
 2914 
 2915         rid = rman_get_rid(irq);
 2916         if (rid == 0) {
 2917                 /* Mask INTx */
 2918                 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
 2919         } else {
 2920                 /*
 2921                  * Check to see if the interrupt is MSI or MSI-X.  If so,
 2922                  * decrement the appropriate handlers count and mask the
 2923                  * MSI-X message, or disable MSI messages if the count
 2924                  * drops to 0.
 2925                  */
 2926                 dinfo = device_get_ivars(child);
 2927                 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
 2928                 if (rle->res != irq)
 2929                         return (EINVAL);
 2930                 if (dinfo->cfg.msi.msi_alloc > 0) {
 2931                         KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
 2932                             ("MSI-X index too high"));
 2933                         if (dinfo->cfg.msi.msi_handlers == 0)
 2934                                 return (EINVAL);
 2935                         dinfo->cfg.msi.msi_handlers--;
 2936                         if (dinfo->cfg.msi.msi_handlers == 0)
 2937                                 pci_disable_msi(child);
 2938                 } else {
 2939                         KASSERT(dinfo->cfg.msix.msix_alloc > 0,
 2940                             ("No MSI or MSI-X interrupts allocated"));
 2941                         KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
 2942                             ("MSI-X index too high"));
 2943                         mte = &dinfo->cfg.msix.msix_table[rid - 1];
 2944                         if (mte->mte_handlers == 0)
 2945                                 return (EINVAL);
 2946                         mte->mte_handlers--;
 2947                         if (mte->mte_handlers == 0)
 2948                                 pci_mask_msix(child, rid - 1);
 2949                 }
 2950         }
 2951         error = bus_generic_teardown_intr(dev, child, irq, cookie);
 2952         if (rid > 0)
 2953                 KASSERT(error == 0,
 2954                     ("%s: generic teardown failed for MSI/MSI-X", __func__));
 2955         return (error);
 2956 }
 2957 
 2958 int
 2959 pci_print_child(device_t dev, device_t child)
 2960 {
 2961         struct pci_devinfo *dinfo;
 2962         struct resource_list *rl;
 2963         int retval = 0;
 2964 
 2965         dinfo = device_get_ivars(child);
 2966         rl = &dinfo->resources;
 2967 
 2968         retval += bus_print_child_header(dev, child);
 2969 
 2970         retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
 2971         retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
 2972         retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
 2973         if (device_get_flags(dev))
 2974                 retval += printf(" flags %#x", device_get_flags(dev));
 2975 
 2976         retval += printf(" at device %d.%d", pci_get_slot(child),
 2977             pci_get_function(child));
 2978 
 2979         retval += bus_print_child_footer(dev, child);
 2980 
 2981         return (retval);
 2982 }
 2983 
 2984 static struct
 2985 {
 2986         int     class;
 2987         int     subclass;
 2988         char    *desc;
 2989 } pci_nomatch_tab[] = {
 2990         {PCIC_OLD,              -1,                     "old"},
 2991         {PCIC_OLD,              PCIS_OLD_NONVGA,        "non-VGA display device"},
 2992         {PCIC_OLD,              PCIS_OLD_VGA,           "VGA-compatible display device"},
 2993         {PCIC_STORAGE,          -1,                     "mass storage"},
 2994         {PCIC_STORAGE,          PCIS_STORAGE_SCSI,      "SCSI"},
 2995         {PCIC_STORAGE,          PCIS_STORAGE_IDE,       "ATA"},
 2996         {PCIC_STORAGE,          PCIS_STORAGE_FLOPPY,    "floppy disk"},
 2997         {PCIC_STORAGE,          PCIS_STORAGE_IPI,       "IPI"},
 2998         {PCIC_STORAGE,          PCIS_STORAGE_RAID,      "RAID"},
 2999         {PCIC_STORAGE,          PCIS_STORAGE_ATA_ADMA,  "ATA (ADMA)"},
 3000         {PCIC_STORAGE,          PCIS_STORAGE_SATA,      "SATA"},
 3001         {PCIC_STORAGE,          PCIS_STORAGE_SAS,       "SAS"},
 3002         {PCIC_NETWORK,          -1,                     "network"},
 3003         {PCIC_NETWORK,          PCIS_NETWORK_ETHERNET,  "ethernet"},
 3004         {PCIC_NETWORK,          PCIS_NETWORK_TOKENRING, "token ring"},
 3005         {PCIC_NETWORK,          PCIS_NETWORK_FDDI,      "fddi"},
 3006         {PCIC_NETWORK,          PCIS_NETWORK_ATM,       "ATM"},
 3007         {PCIC_NETWORK,          PCIS_NETWORK_ISDN,      "ISDN"},
 3008         {PCIC_DISPLAY,          -1,                     "display"},
 3009         {PCIC_DISPLAY,          PCIS_DISPLAY_VGA,       "VGA"},
 3010         {PCIC_DISPLAY,          PCIS_DISPLAY_XGA,       "XGA"},
 3011         {PCIC_DISPLAY,          PCIS_DISPLAY_3D,        "3D"},
 3012         {PCIC_MULTIMEDIA,       -1,                     "multimedia"},
 3013         {PCIC_MULTIMEDIA,       PCIS_MULTIMEDIA_VIDEO,  "video"},
 3014         {PCIC_MULTIMEDIA,       PCIS_MULTIMEDIA_AUDIO,  "audio"},
 3015         {PCIC_MULTIMEDIA,       PCIS_MULTIMEDIA_TELE,   "telephony"},
 3016         {PCIC_MULTIMEDIA,       PCIS_MULTIMEDIA_HDA,    "HDA"},
 3017         {PCIC_MEMORY,           -1,                     "memory"},
 3018         {PCIC_MEMORY,           PCIS_MEMORY_RAM,        "RAM"},
 3019         {PCIC_MEMORY,           PCIS_MEMORY_FLASH,      "flash"},
 3020         {PCIC_BRIDGE,           -1,                     "bridge"},
 3021         {PCIC_BRIDGE,           PCIS_BRIDGE_HOST,       "HOST-PCI"},
 3022         {PCIC_BRIDGE,           PCIS_BRIDGE_ISA,        "PCI-ISA"},
 3023         {PCIC_BRIDGE,           PCIS_BRIDGE_EISA,       "PCI-EISA"},
 3024         {PCIC_BRIDGE,           PCIS_BRIDGE_MCA,        "PCI-MCA"},
 3025         {PCIC_BRIDGE,           PCIS_BRIDGE_PCI,        "PCI-PCI"},
 3026         {PCIC_BRIDGE,           PCIS_BRIDGE_PCMCIA,     "PCI-PCMCIA"},
 3027         {PCIC_BRIDGE,           PCIS_BRIDGE_NUBUS,      "PCI-NuBus"},
 3028         {PCIC_BRIDGE,           PCIS_BRIDGE_CARDBUS,    "PCI-CardBus"},
 3029         {PCIC_BRIDGE,           PCIS_BRIDGE_RACEWAY,    "PCI-RACEway"},
 3030         {PCIC_SIMPLECOMM,       -1,                     "simple comms"},
 3031         {PCIC_SIMPLECOMM,       PCIS_SIMPLECOMM_UART,   "UART"},        /* could detect 16550 */
 3032         {PCIC_SIMPLECOMM,       PCIS_SIMPLECOMM_PAR,    "parallel port"},
 3033         {PCIC_SIMPLECOMM,       PCIS_SIMPLECOMM_MULSER, "multiport serial"},
 3034         {PCIC_SIMPLECOMM,       PCIS_SIMPLECOMM_MODEM,  "generic modem"},
 3035         {PCIC_BASEPERIPH,       -1,                     "base peripheral"},
 3036         {PCIC_BASEPERIPH,       PCIS_BASEPERIPH_PIC,    "interrupt controller"},
 3037         {PCIC_BASEPERIPH,       PCIS_BASEPERIPH_DMA,    "DMA controller"},
 3038         {PCIC_BASEPERIPH,       PCIS_BASEPERIPH_TIMER,  "timer"},
 3039         {PCIC_BASEPERIPH,       PCIS_BASEPERIPH_RTC,    "realtime clock"},
 3040         {PCIC_BASEPERIPH,       PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
 3041         {PCIC_BASEPERIPH,       PCIS_BASEPERIPH_SDHC,   "SD host controller"},
 3042         {PCIC_INPUTDEV,         -1,                     "input device"},
 3043         {PCIC_INPUTDEV,         PCIS_INPUTDEV_KEYBOARD, "keyboard"},
 3044         {PCIC_INPUTDEV,         PCIS_INPUTDEV_DIGITIZER,"digitizer"},
 3045         {PCIC_INPUTDEV,         PCIS_INPUTDEV_MOUSE,    "mouse"},
 3046         {PCIC_INPUTDEV,         PCIS_INPUTDEV_SCANNER,  "scanner"},
 3047         {PCIC_INPUTDEV,         PCIS_INPUTDEV_GAMEPORT, "gameport"},
 3048         {PCIC_DOCKING,          -1,                     "docking station"},
 3049         {PCIC_PROCESSOR,        -1,                     "processor"},
 3050         {PCIC_SERIALBUS,        -1,                     "serial bus"},
 3051         {PCIC_SERIALBUS,        PCIS_SERIALBUS_FW,      "FireWire"},
 3052         {PCIC_SERIALBUS,        PCIS_SERIALBUS_ACCESS,  "AccessBus"},
 3053         {PCIC_SERIALBUS,        PCIS_SERIALBUS_SSA,     "SSA"},
 3054         {PCIC_SERIALBUS,        PCIS_SERIALBUS_USB,     "USB"},
 3055         {PCIC_SERIALBUS,        PCIS_SERIALBUS_FC,      "Fibre Channel"},
 3056         {PCIC_SERIALBUS,        PCIS_SERIALBUS_SMBUS,   "SMBus"},
 3057         {PCIC_WIRELESS,         -1,                     "wireless controller"},
 3058         {PCIC_WIRELESS,         PCIS_WIRELESS_IRDA,     "iRDA"},
 3059         {PCIC_WIRELESS,         PCIS_WIRELESS_IR,       "IR"},
 3060         {PCIC_WIRELESS,         PCIS_WIRELESS_RF,       "RF"},
 3061         {PCIC_INTELLIIO,        -1,                     "intelligent I/O controller"},
 3062         {PCIC_INTELLIIO,        PCIS_INTELLIIO_I2O,     "I2O"},
 3063         {PCIC_SATCOM,           -1,                     "satellite communication"},
 3064         {PCIC_SATCOM,           PCIS_SATCOM_TV,         "sat TV"},
 3065         {PCIC_SATCOM,           PCIS_SATCOM_AUDIO,      "sat audio"},
 3066         {PCIC_SATCOM,           PCIS_SATCOM_VOICE,      "sat voice"},
 3067         {PCIC_SATCOM,           PCIS_SATCOM_DATA,       "sat data"},
 3068         {PCIC_CRYPTO,           -1,                     "encrypt/decrypt"},
 3069         {PCIC_CRYPTO,           PCIS_CRYPTO_NETCOMP,    "network/computer crypto"},
 3070         {PCIC_CRYPTO,           PCIS_CRYPTO_ENTERTAIN,  "entertainment crypto"},
 3071         {PCIC_DASP,             -1,                     "dasp"},
 3072         {PCIC_DASP,             PCIS_DASP_DPIO,         "DPIO module"},
 3073         {0, 0,          NULL}
 3074 };
 3075 
 3076 void
 3077 pci_probe_nomatch(device_t dev, device_t child)
 3078 {
 3079         int     i;
 3080         char    *cp, *scp, *device;
 3081 
 3082         /*
 3083          * Look for a listing for this device in a loaded device database.
 3084          */
 3085         if ((device = pci_describe_device(child)) != NULL) {
 3086                 device_printf(dev, "<%s>", device);
 3087                 free(device, M_DEVBUF);
 3088         } else {
 3089                 /*
 3090                  * Scan the class/subclass descriptions for a general
 3091                  * description.
 3092                  */
 3093                 cp = "unknown";
 3094                 scp = NULL;
 3095                 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
 3096                         if (pci_nomatch_tab[i].class == pci_get_class(child)) {
 3097                                 if (pci_nomatch_tab[i].subclass == -1) {
 3098                                         cp = pci_nomatch_tab[i].desc;
 3099                                 } else if (pci_nomatch_tab[i].subclass ==
 3100                                     pci_get_subclass(child)) {
 3101                                         scp = pci_nomatch_tab[i].desc;
 3102                                 }
 3103                         }
 3104                 }
 3105                 device_printf(dev, "<%s%s%s>",
 3106                     cp ? cp : "",
 3107                     ((cp != NULL) && (scp != NULL)) ? ", " : "",
 3108                     scp ? scp : "");
 3109         }
 3110         printf(" at device %d.%d (no driver attached)\n",
 3111             pci_get_slot(child), pci_get_function(child));
 3112         pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
 3113         return;
 3114 }
 3115 
 3116 /*
 3117  * Parse the PCI device database, if loaded, and return a pointer to a
 3118  * description of the device.
 3119  *
 3120  * The database is flat text formatted as follows:
 3121  *
 3122  * Any line not in a valid format is ignored.
 3123  * Lines are terminated with newline '\n' characters.
 3124  *
 3125  * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
 3126  * the vendor name.
 3127  *
 3128  * A DEVICE line is entered immediately below the corresponding VENDOR ID.
 3129  * - devices cannot be listed without a corresponding VENDOR line.
 3130  * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
 3131  * another TAB, then the device name.
 3132  */
 3133 
 3134 /*
 3135  * Assuming (ptr) points to the beginning of a line in the database,
 3136  * return the vendor or device and description of the next entry.
 3137  * The value of (vendor) or (device) inappropriate for the entry type
 3138  * is set to -1.  Returns nonzero at the end of the database.
 3139  *
 3140  * Note that this is slightly unrobust in the face of corrupt data;
 3141  * we attempt to safeguard against this by spamming the end of the
 3142  * database with a newline when we initialise.
 3143  */
 3144 static int
 3145 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
 3146 {
 3147         char    *cp = *ptr;
 3148         int     left;
 3149 
 3150         *device = -1;
 3151         *vendor = -1;
 3152         **desc = '\0';
 3153         for (;;) {
 3154                 left = pci_vendordata_size - (cp - pci_vendordata);
 3155                 if (left <= 0) {
 3156                         *ptr = cp;
 3157                         return(1);
 3158                 }
 3159 
 3160                 /* vendor entry? */
 3161                 if (*cp != '\t' &&
 3162                     sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
 3163                         break;
 3164                 /* device entry? */
 3165                 if (*cp == '\t' &&
 3166                     sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
 3167                         break;
 3168 
 3169                 /* skip to next line */
 3170                 while (*cp != '\n' && left > 0) {
 3171                         cp++;
 3172                         left--;
 3173                 }
 3174                 if (*cp == '\n') {
 3175                         cp++;
 3176                         left--;
 3177                 }
 3178         }
 3179         /* skip to next line */
 3180         while (*cp != '\n' && left > 0) {
 3181                 cp++;
 3182                 left--;
 3183         }
 3184         if (*cp == '\n' && left > 0)
 3185                 cp++;
 3186         *ptr = cp;
 3187         return(0);
 3188 }
 3189 
 3190 static char *
 3191 pci_describe_device(device_t dev)
 3192 {
 3193         int     vendor, device;
 3194         char    *desc, *vp, *dp, *line;
 3195 
 3196         desc = vp = dp = NULL;
 3197 
 3198         /*
 3199          * If we have no vendor data, we can't do anything.
 3200          */
 3201         if (pci_vendordata == NULL)
 3202                 goto out;
 3203 
 3204         /*
 3205          * Scan the vendor data looking for this device
 3206          */
 3207         line = pci_vendordata;
 3208         if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
 3209                 goto out;
 3210         for (;;) {
 3211                 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
 3212                         goto out;
 3213                 if (vendor == pci_get_vendor(dev))
 3214                         break;
 3215         }
 3216         if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
 3217                 goto out;
 3218         for (;;) {
 3219                 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
 3220                         *dp = 0;
 3221                         break;
 3222                 }
 3223                 if (vendor != -1) {
 3224                         *dp = 0;
 3225                         break;
 3226                 }
 3227                 if (device == pci_get_device(dev))
 3228                         break;
 3229         }
 3230         if (dp[0] == '\0')
 3231                 snprintf(dp, 80, "0x%x", pci_get_device(dev));
 3232         if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
 3233             NULL)
 3234                 sprintf(desc, "%s, %s", vp, dp);
 3235  out:
 3236         if (vp != NULL)
 3237                 free(vp, M_DEVBUF);
 3238         if (dp != NULL)
 3239                 free(dp, M_DEVBUF);
 3240         return(desc);
 3241 }
 3242 
 3243 int
 3244 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 3245 {
 3246         struct pci_devinfo *dinfo;
 3247         pcicfgregs *cfg;
 3248 
 3249         dinfo = device_get_ivars(child);
 3250         cfg = &dinfo->cfg;
 3251 
 3252         switch (which) {
 3253         case PCI_IVAR_ETHADDR:
 3254                 /*
 3255                  * The generic accessor doesn't deal with failure, so
 3256                  * we set the return value, then return an error.
 3257                  */
 3258                 *((uint8_t **) result) = NULL;
 3259                 return (EINVAL);
 3260         case PCI_IVAR_SUBVENDOR:
 3261                 *result = cfg->subvendor;
 3262                 break;
 3263         case PCI_IVAR_SUBDEVICE:
 3264                 *result = cfg->subdevice;
 3265                 break;
 3266         case PCI_IVAR_VENDOR:
 3267                 *result = cfg->vendor;
 3268                 break;
 3269         case PCI_IVAR_DEVICE:
 3270                 *result = cfg->device;
 3271                 break;
 3272         case PCI_IVAR_DEVID:
 3273                 *result = (cfg->device << 16) | cfg->vendor;
 3274                 break;
 3275         case PCI_IVAR_CLASS:
 3276                 *result = cfg->baseclass;
 3277                 break;
 3278         case PCI_IVAR_SUBCLASS:
 3279                 *result = cfg->subclass;
 3280                 break;
 3281         case PCI_IVAR_PROGIF:
 3282                 *result = cfg->progif;
 3283                 break;
 3284         case PCI_IVAR_REVID:
 3285                 *result = cfg->revid;
 3286                 break;
 3287         case PCI_IVAR_INTPIN:
 3288                 *result = cfg->intpin;
 3289                 break;
 3290         case PCI_IVAR_IRQ:
 3291                 *result = cfg->intline;
 3292                 break;
 3293         case PCI_IVAR_DOMAIN:
 3294                 *result = cfg->domain;
 3295                 break;
 3296         case PCI_IVAR_BUS:
 3297                 *result = cfg->bus;
 3298                 break;
 3299         case PCI_IVAR_SLOT:
 3300                 *result = cfg->slot;
 3301                 break;
 3302         case PCI_IVAR_FUNCTION:
 3303                 *result = cfg->func;
 3304                 break;
 3305         case PCI_IVAR_CMDREG:
 3306                 *result = cfg->cmdreg;
 3307                 break;
 3308         case PCI_IVAR_CACHELNSZ:
 3309                 *result = cfg->cachelnsz;
 3310                 break;
 3311         case PCI_IVAR_MINGNT:
 3312                 *result = cfg->mingnt;
 3313                 break;
 3314         case PCI_IVAR_MAXLAT:
 3315                 *result = cfg->maxlat;
 3316                 break;
 3317         case PCI_IVAR_LATTIMER:
 3318                 *result = cfg->lattimer;
 3319                 break;
 3320         default:
 3321                 return (ENOENT);
 3322         }
 3323         return (0);
 3324 }
 3325 
 3326 int
 3327 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
 3328 {
 3329         struct pci_devinfo *dinfo;
 3330 
 3331         dinfo = device_get_ivars(child);
 3332 
 3333         switch (which) {
 3334         case PCI_IVAR_INTPIN:
 3335                 dinfo->cfg.intpin = value;
 3336                 return (0);
 3337         case PCI_IVAR_ETHADDR:
 3338         case PCI_IVAR_SUBVENDOR:
 3339         case PCI_IVAR_SUBDEVICE:
 3340         case PCI_IVAR_VENDOR:
 3341         case PCI_IVAR_DEVICE:
 3342         case PCI_IVAR_DEVID:
 3343         case PCI_IVAR_CLASS:
 3344         case PCI_IVAR_SUBCLASS:
 3345         case PCI_IVAR_PROGIF:
 3346         case PCI_IVAR_REVID:
 3347         case PCI_IVAR_IRQ:
 3348         case PCI_IVAR_DOMAIN:
 3349         case PCI_IVAR_BUS:
 3350         case PCI_IVAR_SLOT:
 3351         case PCI_IVAR_FUNCTION:
 3352                 return (EINVAL);        /* disallow for now */
 3353 
 3354         default:
 3355                 return (ENOENT);
 3356         }
 3357 }
 3358 
 3359 
 3360 #include "opt_ddb.h"
 3361 #ifdef DDB
 3362 #include <ddb/ddb.h>
 3363 #include <sys/cons.h>
 3364 
 3365 /*
 3366  * List resources based on pci map registers, used for within ddb
 3367  */
 3368 
 3369 DB_SHOW_COMMAND(pciregs, db_pci_dump)
 3370 {
 3371         struct pci_devinfo *dinfo;
 3372         struct devlist *devlist_head;
 3373         struct pci_conf *p;
 3374         const char *name;
 3375         int i, error, none_count;
 3376 
 3377         none_count = 0;
 3378         /* get the head of the device queue */
 3379         devlist_head = &pci_devq;
 3380 
 3381         /*
 3382          * Go through the list of devices and print out devices
 3383          */
 3384         for (error = 0, i = 0,
 3385              dinfo = STAILQ_FIRST(devlist_head);
 3386              (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
 3387              dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
 3388 
 3389                 /* Populate pd_name and pd_unit */
 3390                 name = NULL;
 3391                 if (dinfo->cfg.dev)
 3392                         name = device_get_name(dinfo->cfg.dev);
 3393 
 3394                 p = &dinfo->conf;
 3395                 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
 3396                         "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
 3397                         (name && *name) ? name : "none",
 3398                         (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
 3399                         none_count++,
 3400                         p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
 3401                         p->pc_sel.pc_func, (p->pc_class << 16) |
 3402                         (p->pc_subclass << 8) | p->pc_progif,
 3403                         (p->pc_subdevice << 16) | p->pc_subvendor,
 3404                         (p->pc_device << 16) | p->pc_vendor,
 3405                         p->pc_revid, p->pc_hdr);
 3406         }
 3407 }
 3408 #endif /* DDB */
 3409 
 3410 static struct resource *
 3411 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
 3412     u_long start, u_long end, u_long count, u_int flags)
 3413 {
 3414         struct pci_devinfo *dinfo = device_get_ivars(child);
 3415         struct resource_list *rl = &dinfo->resources;
 3416         struct resource_list_entry *rle;
 3417         struct resource *res;
 3418         pci_addr_t map, testval;
 3419         int mapsize;
 3420 
 3421         /*
 3422          * Weed out the bogons, and figure out how large the BAR/map
 3423          * is.  Bars that read back 0 here are bogus and unimplemented.
 3424          * Note: atapci in legacy mode are special and handled elsewhere
 3425          * in the code.  If you have a atapci device in legacy mode and
 3426          * it fails here, that other code is broken.
 3427          */
 3428         res = NULL;
 3429         pci_read_bar(child, *rid, &map, &testval);
 3430 
 3431         /* Ignore a BAR with a base of 0. */
 3432         if (pci_mapbase(testval) == 0)
 3433                 goto out;
 3434 
 3435         if (PCI_BAR_MEM(testval)) {
 3436                 if (type != SYS_RES_MEMORY) {
 3437                         if (bootverbose)
 3438                                 device_printf(dev,
 3439                                     "child %s requested type %d for rid %#x,"
 3440                                     " but the BAR says it is an memio\n",
 3441                                     device_get_nameunit(child), type, *rid);
 3442                         goto out;
 3443                 }
 3444         } else {
 3445                 if (type != SYS_RES_IOPORT) {
 3446                         if (bootverbose)
 3447                                 device_printf(dev,
 3448                                     "child %s requested type %d for rid %#x,"
 3449                                     " but the BAR says it is an ioport\n",
 3450                                     device_get_nameunit(child), type, *rid);
 3451                         goto out;
 3452                 }
 3453         }
 3454 
 3455         /*
 3456          * For real BARs, we need to override the size that
 3457          * the driver requests, because that's what the BAR
 3458          * actually uses and we would otherwise have a
 3459          * situation where we might allocate the excess to
 3460          * another driver, which won't work.
 3461          */
 3462         mapsize = pci_mapsize(testval);
 3463         count = 1UL << mapsize;
 3464         if (RF_ALIGNMENT(flags) < mapsize)
 3465                 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
 3466         if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
 3467                 flags |= RF_PREFETCHABLE;
 3468 
 3469         /*
 3470          * Allocate enough resource, and then write back the
 3471          * appropriate bar for that resource.
 3472          */
 3473         res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
 3474             start, end, count, flags & ~RF_ACTIVE);
 3475         if (res == NULL) {
 3476                 device_printf(child,
 3477                     "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
 3478                     count, *rid, type, start, end);
 3479                 goto out;
 3480         }
 3481         rman_set_device(res, dev);
 3482         resource_list_add(rl, type, *rid, start, end, count);
 3483         rle = resource_list_find(rl, type, *rid);
 3484         if (rle == NULL)
 3485                 panic("pci_alloc_map: unexpectedly can't find resource.");
 3486         rle->res = res;
 3487         rle->start = rman_get_start(res);
 3488         rle->end = rman_get_end(res);
 3489         rle->count = count;
 3490         if (bootverbose)
 3491                 device_printf(child,
 3492                     "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
 3493                     count, *rid, type, rman_get_start(res));
 3494         map = rman_get_start(res);
 3495         pci_write_bar(child, *rid, map);
 3496 out:;
 3497         return (res);
 3498 }
 3499 
 3500 
 3501 struct resource *
 3502 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
 3503                    u_long start, u_long end, u_long count, u_int flags)
 3504 {
 3505         struct pci_devinfo *dinfo = device_get_ivars(child);
 3506         struct resource_list *rl = &dinfo->resources;
 3507         struct resource_list_entry *rle;
 3508         struct resource *res;
 3509         pcicfgregs *cfg = &dinfo->cfg;
 3510 
 3511         if (device_get_parent(child) != dev)
 3512                 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
 3513                     type, rid, start, end, count, flags));
 3514 
 3515         /*
 3516          * Perform lazy resource allocation
 3517          */
 3518         switch (type) {
 3519         case SYS_RES_IRQ:
 3520                 /*
 3521                  * Can't alloc legacy interrupt once MSI messages have
 3522                  * been allocated.
 3523                  */
 3524                 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
 3525                     cfg->msix.msix_alloc > 0))
 3526                         return (NULL);
 3527 
 3528                 /*
 3529                  * If the child device doesn't have an interrupt
 3530                  * routed and is deserving of an interrupt, try to
 3531                  * assign it one.
 3532                  */
 3533                 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
 3534                     (cfg->intpin != 0))
 3535                         pci_assign_interrupt(dev, child, 0);
 3536                 break;
 3537         case SYS_RES_IOPORT:
 3538         case SYS_RES_MEMORY:
 3539                 /* Allocate resources for this BAR if needed. */
 3540                 rle = resource_list_find(rl, type, *rid);
 3541                 if (rle == NULL) {
 3542                         res = pci_alloc_map(dev, child, type, rid, start, end,
 3543                             count, flags);
 3544                         if (res == NULL)
 3545                                 return (NULL);
 3546                         rle = resource_list_find(rl, type, *rid);
 3547                 }
 3548 
 3549                 /*
 3550                  * If the resource belongs to the bus, then give it to
 3551                  * the child.  We need to activate it if requested
 3552                  * since the bus always allocates inactive resources.
 3553                  */
 3554                 if (rle != NULL && rle->res != NULL &&
 3555                     rman_get_device(rle->res) == dev) {
 3556                         if (bootverbose)
 3557                                 device_printf(child,
 3558                             "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
 3559                                     rman_get_size(rle->res), *rid, type,
 3560                                     rman_get_start(rle->res));
 3561                         rman_set_device(rle->res, child);
 3562                         if ((flags & RF_ACTIVE) &&
 3563                             bus_activate_resource(child, type, *rid,
 3564                             rle->res) != 0)
 3565                                 return (NULL);
 3566                         return (rle->res);
 3567                 }
 3568         }
 3569         return (resource_list_alloc(rl, dev, child, type, rid,
 3570             start, end, count, flags));
 3571 }
 3572 
 3573 int
 3574 pci_release_resource(device_t dev, device_t child, int type, int rid,
 3575     struct resource *r)
 3576 {
 3577         int error;
 3578 
 3579         if (device_get_parent(child) != dev)
 3580                 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
 3581                     type, rid, r));
 3582 
 3583         /*
 3584          * For BARs we don't actually want to release the resource.
 3585          * Instead, we deactivate the resource if needed and then give
 3586          * ownership of the BAR back to the bus.
 3587          */
 3588         switch (type) {
 3589         case SYS_RES_IOPORT:
 3590         case SYS_RES_MEMORY:
 3591                 if (rman_get_device(r) != child)
 3592                         return (EINVAL);
 3593                 if (rman_get_flags(r) & RF_ACTIVE) {
 3594                         error = bus_deactivate_resource(child, type, rid, r);
 3595                         if (error)
 3596                                 return (error);
 3597                 }
 3598                 rman_set_device(r, dev);
 3599                 return (0);
 3600         }
 3601         return (bus_generic_rl_release_resource(dev, child, type, rid, r));
 3602 }
 3603 
 3604 int
 3605 pci_activate_resource(device_t dev, device_t child, int type, int rid,
 3606     struct resource *r)
 3607 {
 3608         int error;
 3609 
 3610         error = bus_generic_activate_resource(dev, child, type, rid, r);
 3611         if (error)
 3612                 return (error);
 3613 
 3614         /* Enable decoding in the command register when activating BARs. */
 3615         if (device_get_parent(child) == dev) {
 3616                 switch (type) {
 3617                 case SYS_RES_IOPORT:
 3618                 case SYS_RES_MEMORY:
 3619                         error = PCI_ENABLE_IO(dev, child, type);
 3620                         break;
 3621                 }
 3622         }
 3623         return (error);
 3624 }
 3625 
 3626 void
 3627 pci_delete_resource(device_t dev, device_t child, int type, int rid)
 3628 {
 3629         struct pci_devinfo *dinfo;
 3630         struct resource_list *rl;
 3631         struct resource_list_entry *rle;
 3632 
 3633         if (device_get_parent(child) != dev)
 3634                 return;
 3635 
 3636         dinfo = device_get_ivars(child);
 3637         rl = &dinfo->resources;
 3638         rle = resource_list_find(rl, type, rid);
 3639         if (rle == NULL)
 3640                 return;
 3641 
 3642         if (rle->res) {
 3643                 if (rman_get_device(rle->res) != dev ||
 3644                     rman_get_flags(rle->res) & RF_ACTIVE) {
 3645                         device_printf(dev, "delete_resource: "
 3646                             "Resource still owned by child, oops. "
 3647                             "(type=%d, rid=%d, addr=%lx)\n",
 3648                             rle->type, rle->rid,
 3649                             rman_get_start(rle->res));
 3650                         return;
 3651                 }
 3652 
 3653 #ifndef __PCI_BAR_ZERO_VALID
 3654                 /*
 3655                  * If this is a BAR, clear the BAR so it stops
 3656                  * decoding before releasing the resource.
 3657                  */
 3658                 switch (type) {
 3659                 case SYS_RES_IOPORT:
 3660                 case SYS_RES_MEMORY:
 3661                         pci_write_bar(child, rid, 0);
 3662                         break;
 3663                 }
 3664 #endif
 3665                 bus_release_resource(dev, type, rid, rle->res);
 3666         }
 3667         resource_list_delete(rl, type, rid);
 3668 }
 3669 
 3670 struct resource_list *
 3671 pci_get_resource_list (device_t dev, device_t child)
 3672 {
 3673         struct pci_devinfo *dinfo = device_get_ivars(child);
 3674 
 3675         return (&dinfo->resources);
 3676 }
 3677 
 3678 uint32_t
 3679 pci_read_config_method(device_t dev, device_t child, int reg, int width)
 3680 {
 3681         struct pci_devinfo *dinfo = device_get_ivars(child);
 3682         pcicfgregs *cfg = &dinfo->cfg;
 3683 
 3684         return (PCIB_READ_CONFIG(device_get_parent(dev),
 3685             cfg->bus, cfg->slot, cfg->func, reg, width));
 3686 }
 3687 
 3688 void
 3689 pci_write_config_method(device_t dev, device_t child, int reg,
 3690     uint32_t val, int width)
 3691 {
 3692         struct pci_devinfo *dinfo = device_get_ivars(child);
 3693         pcicfgregs *cfg = &dinfo->cfg;
 3694 
 3695         PCIB_WRITE_CONFIG(device_get_parent(dev),
 3696             cfg->bus, cfg->slot, cfg->func, reg, val, width);
 3697 }
 3698 
 3699 int
 3700 pci_child_location_str_method(device_t dev, device_t child, char *buf,
 3701     size_t buflen)
 3702 {
 3703 
 3704         snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
 3705             pci_get_function(child));
 3706         return (0);
 3707 }
 3708 
 3709 int
 3710 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
 3711     size_t buflen)
 3712 {
 3713         struct pci_devinfo *dinfo;
 3714         pcicfgregs *cfg;
 3715 
 3716         dinfo = device_get_ivars(child);
 3717         cfg = &dinfo->cfg;
 3718         snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
 3719             "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
 3720             cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
 3721             cfg->progif);
 3722         return (0);
 3723 }
 3724 
 3725 int
 3726 pci_assign_interrupt_method(device_t dev, device_t child)
 3727 {
 3728         struct pci_devinfo *dinfo = device_get_ivars(child);
 3729         pcicfgregs *cfg = &dinfo->cfg;
 3730 
 3731         return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
 3732             cfg->intpin));
 3733 }
 3734 
 3735 static int
 3736 pci_modevent(module_t mod, int what, void *arg)
 3737 {
 3738         static struct cdev *pci_cdev;
 3739 
 3740         switch (what) {
 3741         case MOD_LOAD:
 3742                 STAILQ_INIT(&pci_devq);
 3743                 pci_generation = 0;
 3744                 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
 3745                     "pci");
 3746                 pci_load_vendor_data();
 3747                 break;
 3748 
 3749         case MOD_UNLOAD:
 3750                 destroy_dev(pci_cdev);
 3751                 break;
 3752         }
 3753 
 3754         return (0);
 3755 }
 3756 
 3757 void
 3758 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
 3759 {
 3760         int i;
 3761 
 3762         /*
 3763          * Only do header type 0 devices.  Type 1 devices are bridges,
 3764          * which we know need special treatment.  Type 2 devices are
 3765          * cardbus bridges which also require special treatment.
 3766          * Other types are unknown, and we err on the side of safety
 3767          * by ignoring them.
 3768          */
 3769         if (dinfo->cfg.hdrtype != 0)
 3770                 return;
 3771 
 3772         /*
 3773          * Restore the device to full power mode.  We must do this
 3774          * before we restore the registers because moving from D3 to
 3775          * D0 will cause the chip's BARs and some other registers to
 3776          * be reset to some unknown power on reset values.  Cut down
 3777          * the noise on boot by doing nothing if we are already in
 3778          * state D0.
 3779          */
 3780         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 3781                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 3782         }
 3783         for (i = 0; i < dinfo->cfg.nummaps; i++)
 3784                 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
 3785         pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
 3786         pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
 3787         pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
 3788         pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
 3789         pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
 3790         pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
 3791         pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
 3792         pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
 3793         pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
 3794         pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
 3795 
 3796         /* Restore MSI and MSI-X configurations if they are present. */
 3797         if (dinfo->cfg.msi.msi_location != 0)
 3798                 pci_resume_msi(dev);
 3799         if (dinfo->cfg.msix.msix_location != 0)
 3800                 pci_resume_msix(dev);
 3801 }
 3802 
 3803 void
 3804 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
 3805 {
 3806         int i;
 3807         uint32_t cls;
 3808         int ps;
 3809 
 3810         /*
 3811          * Only do header type 0 devices.  Type 1 devices are bridges, which
 3812          * we know need special treatment.  Type 2 devices are cardbus bridges
 3813          * which also require special treatment.  Other types are unknown, and
 3814          * we err on the side of safety by ignoring them.  Powering down
 3815          * bridges should not be undertaken lightly.
 3816          */
 3817         if (dinfo->cfg.hdrtype != 0)
 3818                 return;
 3819         for (i = 0; i < dinfo->cfg.nummaps; i++)
 3820                 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
 3821         dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
 3822 
 3823         /*
 3824          * Some drivers apparently write to these registers w/o updating our
 3825          * cached copy.  No harm happens if we update the copy, so do so here
 3826          * so we can restore them.  The COMMAND register is modified by the
 3827          * bus w/o updating the cache.  This should represent the normally
 3828          * writable portion of the 'defined' part of type 0 headers.  In
 3829          * theory we also need to save/restore the PCI capability structures
 3830          * we know about, but apart from power we don't know any that are
 3831          * writable.
 3832          */
 3833         dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 3834         dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 3835         dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
 3836         dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
 3837         dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
 3838         dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
 3839         dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
 3840         dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
 3841         dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
 3842         dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 3843         dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
 3844         dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
 3845         dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
 3846         dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
 3847         dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
 3848 
 3849         /*
 3850          * don't set the state for display devices, base peripherals and
 3851          * memory devices since bad things happen when they are powered down.
 3852          * We should (a) have drivers that can easily detach and (b) use
 3853          * generic drivers for these devices so that some device actually
 3854          * attaches.  We need to make sure that when we implement (a) we don't
 3855          * power the device down on a reattach.
 3856          */
 3857         cls = pci_get_class(dev);
 3858         if (!setstate)
 3859                 return;
 3860         switch (pci_do_power_nodriver)
 3861         {
 3862                 case 0:         /* NO powerdown at all */
 3863                         return;
 3864                 case 1:         /* Conservative about what to power down */
 3865                         if (cls == PCIC_STORAGE)
 3866                                 return;
 3867                         /*FALLTHROUGH*/
 3868                 case 2:         /* Agressive about what to power down */
 3869                         if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
 3870                             cls == PCIC_BASEPERIPH)
 3871                                 return;
 3872                         /*FALLTHROUGH*/
 3873                 case 3:         /* Power down everything */
 3874                         break;
 3875         }
 3876         /*
 3877          * PCI spec says we can only go into D3 state from D0 state.
 3878          * Transition from D[12] into D0 before going to D3 state.
 3879          */
 3880         ps = pci_get_powerstate(dev);
 3881         if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
 3882                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 3883         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
 3884                 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
 3885 }

Cache object: 89534c5dc74d97da27f5e311f3347259


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