Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/pci/pci.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD: releng/8.2/sys/dev/pci/pci.c 215064 2010-11-09 22:18:20Z mav $"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 #include <machine/stdarg.h> 55 56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 57 #include <machine/intr_machdep.h> 58 #endif 59 60 #include <sys/pciio.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pci_private.h> 64 65 #include <dev/usb/controller/ehcireg.h> 66 #include <dev/usb/controller/ohcireg.h> 67 #include <dev/usb/controller/uhcireg.h> 68 69 #include "pcib_if.h" 70 #include "pci_if.h" 71 72 #ifdef __HAVE_ACPI 73 #include <contrib/dev/acpica/include/acpi.h> 74 #include "acpi_if.h" 75 #else 76 #define ACPI_PWR_FOR_SLEEP(x, y, z) 77 #endif 78 79 static pci_addr_t pci_mapbase(uint64_t mapreg); 80 static const char *pci_maptype(uint64_t mapreg); 81 static int pci_mapsize(uint64_t testval); 82 static int pci_maprange(uint64_t mapreg); 83 static void pci_fixancient(pcicfgregs *cfg); 84 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 85 86 static int pci_porten(device_t dev); 87 static int pci_memen(device_t dev); 88 static void pci_assign_interrupt(device_t bus, device_t dev, 89 int force_route); 90 static int pci_add_map(device_t bus, device_t dev, int reg, 91 struct resource_list *rl, int force, int prefetch); 92 static int pci_probe(device_t dev); 93 static int pci_attach(device_t dev); 94 static void pci_load_vendor_data(void); 95 static int pci_describe_parse_line(char **ptr, int *vendor, 96 int *device, char **desc); 97 static char *pci_describe_device(device_t dev); 98 static int pci_modevent(module_t mod, int what, void *arg); 99 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 100 pcicfgregs *cfg); 101 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 102 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 103 int reg, uint32_t *data); 104 #if 0 105 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 106 int reg, uint32_t data); 107 #endif 108 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 109 static void pci_disable_msi(device_t dev); 110 static void pci_enable_msi(device_t dev, uint64_t address, 111 uint16_t data); 112 static void pci_enable_msix(device_t dev, u_int index, 113 uint64_t address, uint32_t data); 114 static void pci_mask_msix(device_t dev, u_int index); 115 static void pci_unmask_msix(device_t dev, u_int index); 116 static int pci_msi_blacklisted(void); 117 static void pci_resume_msi(device_t dev); 118 static void pci_resume_msix(device_t dev); 119 static int pci_remap_intr_method(device_t bus, device_t dev, 120 u_int irq); 121 122 static device_method_t pci_methods[] = { 123 /* Device interface */ 124 DEVMETHOD(device_probe, pci_probe), 125 DEVMETHOD(device_attach, pci_attach), 126 DEVMETHOD(device_detach, bus_generic_detach), 127 DEVMETHOD(device_shutdown, bus_generic_shutdown), 128 DEVMETHOD(device_suspend, pci_suspend), 129 DEVMETHOD(device_resume, pci_resume), 130 131 /* Bus interface */ 132 DEVMETHOD(bus_print_child, pci_print_child), 133 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 134 DEVMETHOD(bus_read_ivar, pci_read_ivar), 135 DEVMETHOD(bus_write_ivar, pci_write_ivar), 136 DEVMETHOD(bus_driver_added, pci_driver_added), 137 DEVMETHOD(bus_setup_intr, pci_setup_intr), 138 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 139 140 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 141 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 142 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 143 DEVMETHOD(bus_delete_resource, pci_delete_resource), 144 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 145 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 146 DEVMETHOD(bus_activate_resource, pci_activate_resource), 147 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 148 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 149 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 150 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 151 152 /* PCI interface */ 153 DEVMETHOD(pci_read_config, pci_read_config_method), 154 DEVMETHOD(pci_write_config, pci_write_config_method), 155 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 156 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 157 DEVMETHOD(pci_enable_io, pci_enable_io_method), 158 DEVMETHOD(pci_disable_io, pci_disable_io_method), 159 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 160 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 161 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 162 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 163 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 164 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 165 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 166 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 167 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 168 DEVMETHOD(pci_release_msi, pci_release_msi_method), 169 DEVMETHOD(pci_msi_count, pci_msi_count_method), 170 DEVMETHOD(pci_msix_count, pci_msix_count_method), 171 172 { 0, 0 } 173 }; 174 175 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 176 177 static devclass_t pci_devclass; 178 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 179 MODULE_VERSION(pci, 1); 180 181 static char *pci_vendordata; 182 static size_t pci_vendordata_size; 183 184 185 struct pci_quirk { 186 uint32_t devid; /* Vendor/device of the card */ 187 int type; 188 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 189 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */ 190 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 191 int arg1; 192 int arg2; 193 }; 194 195 struct pci_quirk pci_quirks[] = { 196 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 197 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 198 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 199 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 200 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 201 202 /* 203 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 204 * or the CMIC-SL (AKA ServerWorks GC_LE). 205 */ 206 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 207 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 208 209 /* 210 * MSI doesn't work on earlier Intel chipsets including 211 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 212 */ 213 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 214 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 215 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 216 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 217 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 218 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 219 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 220 221 /* 222 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 223 * bridge. 224 */ 225 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 226 227 /* 228 * Some virtualization environments emulate an older chipset 229 * but support MSI just fine. QEMU uses the Intel 82440. 230 */ 231 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 232 233 { 0 } 234 }; 235 236 /* map register information */ 237 #define PCI_MAPMEM 0x01 /* memory map */ 238 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 239 #define PCI_MAPPORT 0x04 /* port map */ 240 241 struct devlist pci_devq; 242 uint32_t pci_generation; 243 uint32_t pci_numdevs = 0; 244 static int pcie_chipset, pcix_chipset; 245 246 /* sysctl vars */ 247 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 248 249 static int pci_enable_io_modes = 1; 250 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 251 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 252 &pci_enable_io_modes, 1, 253 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 254 enable these bits correctly. We'd like to do this all the time, but there\n\ 255 are some peripherals that this causes problems with."); 256 257 static int pci_do_power_nodriver = 0; 258 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 259 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 260 &pci_do_power_nodriver, 0, 261 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 262 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 263 agressively place devices into D3 state. 3 means put absolutely everything\n\ 264 in D3 state."); 265 266 static int pci_do_power_resume = 1; 267 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 268 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 269 &pci_do_power_resume, 1, 270 "Transition from D3 -> D0 on resume."); 271 272 static int pci_do_msi = 1; 273 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 274 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 275 "Enable support for MSI interrupts"); 276 277 static int pci_do_msix = 1; 278 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 279 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 280 "Enable support for MSI-X interrupts"); 281 282 static int pci_honor_msi_blacklist = 1; 283 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist); 284 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD, 285 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI"); 286 287 #if defined(__i386__) || defined(__amd64__) 288 static int pci_usb_takeover = 1; 289 #else 290 static int pci_usb_takeover = 0; 291 #endif 292 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover); 293 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RD | CTLFLAG_TUN, 294 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\ 295 Disable this if you depend on BIOS emulation of USB devices, that is\n\ 296 you use USB devices (like keyboard or mouse) but do not load USB drivers"); 297 298 /* Find a device_t by bus/slot/function in domain 0 */ 299 300 device_t 301 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 302 { 303 304 return (pci_find_dbsf(0, bus, slot, func)); 305 } 306 307 /* Find a device_t by domain/bus/slot/function */ 308 309 device_t 310 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 311 { 312 struct pci_devinfo *dinfo; 313 314 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 315 if ((dinfo->cfg.domain == domain) && 316 (dinfo->cfg.bus == bus) && 317 (dinfo->cfg.slot == slot) && 318 (dinfo->cfg.func == func)) { 319 return (dinfo->cfg.dev); 320 } 321 } 322 323 return (NULL); 324 } 325 326 /* Find a device_t by vendor/device ID */ 327 328 device_t 329 pci_find_device(uint16_t vendor, uint16_t device) 330 { 331 struct pci_devinfo *dinfo; 332 333 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 334 if ((dinfo->cfg.vendor == vendor) && 335 (dinfo->cfg.device == device)) { 336 return (dinfo->cfg.dev); 337 } 338 } 339 340 return (NULL); 341 } 342 343 static int 344 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 345 { 346 va_list ap; 347 int retval; 348 349 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 350 cfg->func); 351 va_start(ap, fmt); 352 retval += vprintf(fmt, ap); 353 va_end(ap); 354 return (retval); 355 } 356 357 /* return base address of memory or port map */ 358 359 static pci_addr_t 360 pci_mapbase(uint64_t mapreg) 361 { 362 363 if (PCI_BAR_MEM(mapreg)) 364 return (mapreg & PCIM_BAR_MEM_BASE); 365 else 366 return (mapreg & PCIM_BAR_IO_BASE); 367 } 368 369 /* return map type of memory or port map */ 370 371 static const char * 372 pci_maptype(uint64_t mapreg) 373 { 374 375 if (PCI_BAR_IO(mapreg)) 376 return ("I/O Port"); 377 if (mapreg & PCIM_BAR_MEM_PREFETCH) 378 return ("Prefetchable Memory"); 379 return ("Memory"); 380 } 381 382 /* return log2 of map size decoded for memory or port map */ 383 384 static int 385 pci_mapsize(uint64_t testval) 386 { 387 int ln2size; 388 389 testval = pci_mapbase(testval); 390 ln2size = 0; 391 if (testval != 0) { 392 while ((testval & 1) == 0) 393 { 394 ln2size++; 395 testval >>= 1; 396 } 397 } 398 return (ln2size); 399 } 400 401 /* return log2 of address range supported by map register */ 402 403 static int 404 pci_maprange(uint64_t mapreg) 405 { 406 int ln2range = 0; 407 408 if (PCI_BAR_IO(mapreg)) 409 ln2range = 32; 410 else 411 switch (mapreg & PCIM_BAR_MEM_TYPE) { 412 case PCIM_BAR_MEM_32: 413 ln2range = 32; 414 break; 415 case PCIM_BAR_MEM_1MB: 416 ln2range = 20; 417 break; 418 case PCIM_BAR_MEM_64: 419 ln2range = 64; 420 break; 421 } 422 return (ln2range); 423 } 424 425 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 426 427 static void 428 pci_fixancient(pcicfgregs *cfg) 429 { 430 if (cfg->hdrtype != 0) 431 return; 432 433 /* PCI to PCI bridges use header type 1 */ 434 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 435 cfg->hdrtype = 1; 436 } 437 438 /* extract header type specific config data */ 439 440 static void 441 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 442 { 443 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 444 switch (cfg->hdrtype) { 445 case 0: 446 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 447 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 448 cfg->nummaps = PCI_MAXMAPS_0; 449 break; 450 case 1: 451 cfg->nummaps = PCI_MAXMAPS_1; 452 break; 453 case 2: 454 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 455 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 456 cfg->nummaps = PCI_MAXMAPS_2; 457 break; 458 } 459 #undef REG 460 } 461 462 /* read configuration header into pcicfgregs structure */ 463 struct pci_devinfo * 464 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size) 465 { 466 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 467 pcicfgregs *cfg = NULL; 468 struct pci_devinfo *devlist_entry; 469 struct devlist *devlist_head; 470 471 devlist_head = &pci_devq; 472 473 devlist_entry = NULL; 474 475 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) { 476 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 477 if (devlist_entry == NULL) 478 return (NULL); 479 480 cfg = &devlist_entry->cfg; 481 482 cfg->domain = d; 483 cfg->bus = b; 484 cfg->slot = s; 485 cfg->func = f; 486 cfg->vendor = REG(PCIR_VENDOR, 2); 487 cfg->device = REG(PCIR_DEVICE, 2); 488 cfg->cmdreg = REG(PCIR_COMMAND, 2); 489 cfg->statreg = REG(PCIR_STATUS, 2); 490 cfg->baseclass = REG(PCIR_CLASS, 1); 491 cfg->subclass = REG(PCIR_SUBCLASS, 1); 492 cfg->progif = REG(PCIR_PROGIF, 1); 493 cfg->revid = REG(PCIR_REVID, 1); 494 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 495 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 496 cfg->lattimer = REG(PCIR_LATTIMER, 1); 497 cfg->intpin = REG(PCIR_INTPIN, 1); 498 cfg->intline = REG(PCIR_INTLINE, 1); 499 500 cfg->mingnt = REG(PCIR_MINGNT, 1); 501 cfg->maxlat = REG(PCIR_MAXLAT, 1); 502 503 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 504 cfg->hdrtype &= ~PCIM_MFDEV; 505 506 pci_fixancient(cfg); 507 pci_hdrtypedata(pcib, b, s, f, cfg); 508 509 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 510 pci_read_extcap(pcib, cfg); 511 512 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 513 514 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 515 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 516 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 517 devlist_entry->conf.pc_sel.pc_func = cfg->func; 518 devlist_entry->conf.pc_hdr = cfg->hdrtype; 519 520 devlist_entry->conf.pc_subvendor = cfg->subvendor; 521 devlist_entry->conf.pc_subdevice = cfg->subdevice; 522 devlist_entry->conf.pc_vendor = cfg->vendor; 523 devlist_entry->conf.pc_device = cfg->device; 524 525 devlist_entry->conf.pc_class = cfg->baseclass; 526 devlist_entry->conf.pc_subclass = cfg->subclass; 527 devlist_entry->conf.pc_progif = cfg->progif; 528 devlist_entry->conf.pc_revid = cfg->revid; 529 530 pci_numdevs++; 531 pci_generation++; 532 } 533 return (devlist_entry); 534 #undef REG 535 } 536 537 static void 538 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 539 { 540 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 541 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 542 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 543 uint64_t addr; 544 #endif 545 uint32_t val; 546 int ptr, nextptr, ptrptr; 547 548 switch (cfg->hdrtype & PCIM_HDRTYPE) { 549 case 0: 550 case 1: 551 ptrptr = PCIR_CAP_PTR; 552 break; 553 case 2: 554 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 555 break; 556 default: 557 return; /* no extended capabilities support */ 558 } 559 nextptr = REG(ptrptr, 1); /* sanity check? */ 560 561 /* 562 * Read capability entries. 563 */ 564 while (nextptr != 0) { 565 /* Sanity check */ 566 if (nextptr > 255) { 567 printf("illegal PCI extended capability offset %d\n", 568 nextptr); 569 return; 570 } 571 /* Find the next entry */ 572 ptr = nextptr; 573 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 574 575 /* Process this entry */ 576 switch (REG(ptr + PCICAP_ID, 1)) { 577 case PCIY_PMG: /* PCI power management */ 578 if (cfg->pp.pp_cap == 0) { 579 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 580 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 581 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 582 if ((nextptr - ptr) > PCIR_POWER_DATA) 583 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 584 } 585 break; 586 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 587 case PCIY_HT: /* HyperTransport */ 588 /* Determine HT-specific capability type. */ 589 val = REG(ptr + PCIR_HT_COMMAND, 2); 590 switch (val & PCIM_HTCMD_CAP_MASK) { 591 case PCIM_HTCAP_MSI_MAPPING: 592 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 593 /* Sanity check the mapping window. */ 594 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 595 4); 596 addr <<= 32; 597 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 598 4); 599 if (addr != MSI_INTEL_ADDR_BASE) 600 device_printf(pcib, 601 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 602 cfg->domain, cfg->bus, 603 cfg->slot, cfg->func, 604 (long long)addr); 605 } else 606 addr = MSI_INTEL_ADDR_BASE; 607 608 cfg->ht.ht_msimap = ptr; 609 cfg->ht.ht_msictrl = val; 610 cfg->ht.ht_msiaddr = addr; 611 break; 612 } 613 break; 614 #endif 615 case PCIY_MSI: /* PCI MSI */ 616 cfg->msi.msi_location = ptr; 617 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 618 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 619 PCIM_MSICTRL_MMC_MASK)>>1); 620 break; 621 case PCIY_MSIX: /* PCI MSI-X */ 622 cfg->msix.msix_location = ptr; 623 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 624 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 625 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 626 val = REG(ptr + PCIR_MSIX_TABLE, 4); 627 cfg->msix.msix_table_bar = PCIR_BAR(val & 628 PCIM_MSIX_BIR_MASK); 629 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 630 val = REG(ptr + PCIR_MSIX_PBA, 4); 631 cfg->msix.msix_pba_bar = PCIR_BAR(val & 632 PCIM_MSIX_BIR_MASK); 633 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 634 break; 635 case PCIY_VPD: /* PCI Vital Product Data */ 636 cfg->vpd.vpd_reg = ptr; 637 break; 638 case PCIY_SUBVENDOR: 639 /* Should always be true. */ 640 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) { 641 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 642 cfg->subvendor = val & 0xffff; 643 cfg->subdevice = val >> 16; 644 } 645 break; 646 case PCIY_PCIX: /* PCI-X */ 647 /* 648 * Assume we have a PCI-X chipset if we have 649 * at least one PCI-PCI bridge with a PCI-X 650 * capability. Note that some systems with 651 * PCI-express or HT chipsets might match on 652 * this check as well. 653 */ 654 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) 655 pcix_chipset = 1; 656 break; 657 case PCIY_EXPRESS: /* PCI-express */ 658 /* 659 * Assume we have a PCI-express chipset if we have 660 * at least one PCI-express device. 661 */ 662 pcie_chipset = 1; 663 break; 664 default: 665 break; 666 } 667 } 668 /* REG and WREG use carry through to next functions */ 669 } 670 671 /* 672 * PCI Vital Product Data 673 */ 674 675 #define PCI_VPD_TIMEOUT 1000000 676 677 static int 678 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 679 { 680 int count = PCI_VPD_TIMEOUT; 681 682 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 683 684 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 685 686 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 687 if (--count < 0) 688 return (ENXIO); 689 DELAY(1); /* limit looping */ 690 } 691 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 692 693 return (0); 694 } 695 696 #if 0 697 static int 698 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 699 { 700 int count = PCI_VPD_TIMEOUT; 701 702 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 703 704 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 705 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 706 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 707 if (--count < 0) 708 return (ENXIO); 709 DELAY(1); /* limit looping */ 710 } 711 712 return (0); 713 } 714 #endif 715 716 #undef PCI_VPD_TIMEOUT 717 718 struct vpd_readstate { 719 device_t pcib; 720 pcicfgregs *cfg; 721 uint32_t val; 722 int bytesinval; 723 int off; 724 uint8_t cksum; 725 }; 726 727 static int 728 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 729 { 730 uint32_t reg; 731 uint8_t byte; 732 733 if (vrs->bytesinval == 0) { 734 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 735 return (ENXIO); 736 vrs->val = le32toh(reg); 737 vrs->off += 4; 738 byte = vrs->val & 0xff; 739 vrs->bytesinval = 3; 740 } else { 741 vrs->val = vrs->val >> 8; 742 byte = vrs->val & 0xff; 743 vrs->bytesinval--; 744 } 745 746 vrs->cksum += byte; 747 *data = byte; 748 return (0); 749 } 750 751 static void 752 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 753 { 754 struct vpd_readstate vrs; 755 int state; 756 int name; 757 int remain; 758 int i; 759 int alloc, off; /* alloc/off for RO/W arrays */ 760 int cksumvalid; 761 int dflen; 762 uint8_t byte; 763 uint8_t byte2; 764 765 /* init vpd reader */ 766 vrs.bytesinval = 0; 767 vrs.off = 0; 768 vrs.pcib = pcib; 769 vrs.cfg = cfg; 770 vrs.cksum = 0; 771 772 state = 0; 773 name = remain = i = 0; /* shut up stupid gcc */ 774 alloc = off = 0; /* shut up stupid gcc */ 775 dflen = 0; /* shut up stupid gcc */ 776 cksumvalid = -1; 777 while (state >= 0) { 778 if (vpd_nextbyte(&vrs, &byte)) { 779 state = -2; 780 break; 781 } 782 #if 0 783 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 784 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 785 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 786 #endif 787 switch (state) { 788 case 0: /* item name */ 789 if (byte & 0x80) { 790 if (vpd_nextbyte(&vrs, &byte2)) { 791 state = -2; 792 break; 793 } 794 remain = byte2; 795 if (vpd_nextbyte(&vrs, &byte2)) { 796 state = -2; 797 break; 798 } 799 remain |= byte2 << 8; 800 if (remain > (0x7f*4 - vrs.off)) { 801 state = -1; 802 printf( 803 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n", 804 cfg->domain, cfg->bus, cfg->slot, 805 cfg->func, remain); 806 } 807 name = byte & 0x7f; 808 } else { 809 remain = byte & 0x7; 810 name = (byte >> 3) & 0xf; 811 } 812 switch (name) { 813 case 0x2: /* String */ 814 cfg->vpd.vpd_ident = malloc(remain + 1, 815 M_DEVBUF, M_WAITOK); 816 i = 0; 817 state = 1; 818 break; 819 case 0xf: /* End */ 820 state = -1; 821 break; 822 case 0x10: /* VPD-R */ 823 alloc = 8; 824 off = 0; 825 cfg->vpd.vpd_ros = malloc(alloc * 826 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 827 M_WAITOK | M_ZERO); 828 state = 2; 829 break; 830 case 0x11: /* VPD-W */ 831 alloc = 8; 832 off = 0; 833 cfg->vpd.vpd_w = malloc(alloc * 834 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 835 M_WAITOK | M_ZERO); 836 state = 5; 837 break; 838 default: /* Invalid data, abort */ 839 state = -1; 840 break; 841 } 842 break; 843 844 case 1: /* Identifier String */ 845 cfg->vpd.vpd_ident[i++] = byte; 846 remain--; 847 if (remain == 0) { 848 cfg->vpd.vpd_ident[i] = '\0'; 849 state = 0; 850 } 851 break; 852 853 case 2: /* VPD-R Keyword Header */ 854 if (off == alloc) { 855 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 856 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 857 M_DEVBUF, M_WAITOK | M_ZERO); 858 } 859 cfg->vpd.vpd_ros[off].keyword[0] = byte; 860 if (vpd_nextbyte(&vrs, &byte2)) { 861 state = -2; 862 break; 863 } 864 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 865 if (vpd_nextbyte(&vrs, &byte2)) { 866 state = -2; 867 break; 868 } 869 dflen = byte2; 870 if (dflen == 0 && 871 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 872 2) == 0) { 873 /* 874 * if this happens, we can't trust the rest 875 * of the VPD. 876 */ 877 printf( 878 "pci%d:%d:%d:%d: bad keyword length: %d\n", 879 cfg->domain, cfg->bus, cfg->slot, 880 cfg->func, dflen); 881 cksumvalid = 0; 882 state = -1; 883 break; 884 } else if (dflen == 0) { 885 cfg->vpd.vpd_ros[off].value = malloc(1 * 886 sizeof(*cfg->vpd.vpd_ros[off].value), 887 M_DEVBUF, M_WAITOK); 888 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 889 } else 890 cfg->vpd.vpd_ros[off].value = malloc( 891 (dflen + 1) * 892 sizeof(*cfg->vpd.vpd_ros[off].value), 893 M_DEVBUF, M_WAITOK); 894 remain -= 3; 895 i = 0; 896 /* keep in sync w/ state 3's transistions */ 897 if (dflen == 0 && remain == 0) 898 state = 0; 899 else if (dflen == 0) 900 state = 2; 901 else 902 state = 3; 903 break; 904 905 case 3: /* VPD-R Keyword Value */ 906 cfg->vpd.vpd_ros[off].value[i++] = byte; 907 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 908 "RV", 2) == 0 && cksumvalid == -1) { 909 if (vrs.cksum == 0) 910 cksumvalid = 1; 911 else { 912 if (bootverbose) 913 printf( 914 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n", 915 cfg->domain, cfg->bus, 916 cfg->slot, cfg->func, 917 vrs.cksum); 918 cksumvalid = 0; 919 state = -1; 920 break; 921 } 922 } 923 dflen--; 924 remain--; 925 /* keep in sync w/ state 2's transistions */ 926 if (dflen == 0) 927 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 928 if (dflen == 0 && remain == 0) { 929 cfg->vpd.vpd_rocnt = off; 930 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 931 off * sizeof(*cfg->vpd.vpd_ros), 932 M_DEVBUF, M_WAITOK | M_ZERO); 933 state = 0; 934 } else if (dflen == 0) 935 state = 2; 936 break; 937 938 case 4: 939 remain--; 940 if (remain == 0) 941 state = 0; 942 break; 943 944 case 5: /* VPD-W Keyword Header */ 945 if (off == alloc) { 946 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 947 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 948 M_DEVBUF, M_WAITOK | M_ZERO); 949 } 950 cfg->vpd.vpd_w[off].keyword[0] = byte; 951 if (vpd_nextbyte(&vrs, &byte2)) { 952 state = -2; 953 break; 954 } 955 cfg->vpd.vpd_w[off].keyword[1] = byte2; 956 if (vpd_nextbyte(&vrs, &byte2)) { 957 state = -2; 958 break; 959 } 960 cfg->vpd.vpd_w[off].len = dflen = byte2; 961 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 962 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 963 sizeof(*cfg->vpd.vpd_w[off].value), 964 M_DEVBUF, M_WAITOK); 965 remain -= 3; 966 i = 0; 967 /* keep in sync w/ state 6's transistions */ 968 if (dflen == 0 && remain == 0) 969 state = 0; 970 else if (dflen == 0) 971 state = 5; 972 else 973 state = 6; 974 break; 975 976 case 6: /* VPD-W Keyword Value */ 977 cfg->vpd.vpd_w[off].value[i++] = byte; 978 dflen--; 979 remain--; 980 /* keep in sync w/ state 5's transistions */ 981 if (dflen == 0) 982 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 983 if (dflen == 0 && remain == 0) { 984 cfg->vpd.vpd_wcnt = off; 985 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 986 off * sizeof(*cfg->vpd.vpd_w), 987 M_DEVBUF, M_WAITOK | M_ZERO); 988 state = 0; 989 } else if (dflen == 0) 990 state = 5; 991 break; 992 993 default: 994 printf("pci%d:%d:%d:%d: invalid state: %d\n", 995 cfg->domain, cfg->bus, cfg->slot, cfg->func, 996 state); 997 state = -1; 998 break; 999 } 1000 } 1001 1002 if (cksumvalid == 0 || state < -1) { 1003 /* read-only data bad, clean up */ 1004 if (cfg->vpd.vpd_ros != NULL) { 1005 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1006 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1007 free(cfg->vpd.vpd_ros, M_DEVBUF); 1008 cfg->vpd.vpd_ros = NULL; 1009 } 1010 } 1011 if (state < -1) { 1012 /* I/O error, clean up */ 1013 printf("pci%d:%d:%d:%d: failed to read VPD data.\n", 1014 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1015 if (cfg->vpd.vpd_ident != NULL) { 1016 free(cfg->vpd.vpd_ident, M_DEVBUF); 1017 cfg->vpd.vpd_ident = NULL; 1018 } 1019 if (cfg->vpd.vpd_w != NULL) { 1020 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1021 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1022 free(cfg->vpd.vpd_w, M_DEVBUF); 1023 cfg->vpd.vpd_w = NULL; 1024 } 1025 } 1026 cfg->vpd.vpd_cached = 1; 1027 #undef REG 1028 #undef WREG 1029 } 1030 1031 int 1032 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1033 { 1034 struct pci_devinfo *dinfo = device_get_ivars(child); 1035 pcicfgregs *cfg = &dinfo->cfg; 1036 1037 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1038 pci_read_vpd(device_get_parent(dev), cfg); 1039 1040 *identptr = cfg->vpd.vpd_ident; 1041 1042 if (*identptr == NULL) 1043 return (ENXIO); 1044 1045 return (0); 1046 } 1047 1048 int 1049 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1050 const char **vptr) 1051 { 1052 struct pci_devinfo *dinfo = device_get_ivars(child); 1053 pcicfgregs *cfg = &dinfo->cfg; 1054 int i; 1055 1056 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1057 pci_read_vpd(device_get_parent(dev), cfg); 1058 1059 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1060 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1061 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1062 *vptr = cfg->vpd.vpd_ros[i].value; 1063 } 1064 1065 if (i != cfg->vpd.vpd_rocnt) 1066 return (0); 1067 1068 *vptr = NULL; 1069 return (ENXIO); 1070 } 1071 1072 /* 1073 * Find the requested extended capability and return the offset in 1074 * configuration space via the pointer provided. The function returns 1075 * 0 on success and error code otherwise. 1076 */ 1077 int 1078 pci_find_extcap_method(device_t dev, device_t child, int capability, 1079 int *capreg) 1080 { 1081 struct pci_devinfo *dinfo = device_get_ivars(child); 1082 pcicfgregs *cfg = &dinfo->cfg; 1083 u_int32_t status; 1084 u_int8_t ptr; 1085 1086 /* 1087 * Check the CAP_LIST bit of the PCI status register first. 1088 */ 1089 status = pci_read_config(child, PCIR_STATUS, 2); 1090 if (!(status & PCIM_STATUS_CAPPRESENT)) 1091 return (ENXIO); 1092 1093 /* 1094 * Determine the start pointer of the capabilities list. 1095 */ 1096 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1097 case 0: 1098 case 1: 1099 ptr = PCIR_CAP_PTR; 1100 break; 1101 case 2: 1102 ptr = PCIR_CAP_PTR_2; 1103 break; 1104 default: 1105 /* XXX: panic? */ 1106 return (ENXIO); /* no extended capabilities support */ 1107 } 1108 ptr = pci_read_config(child, ptr, 1); 1109 1110 /* 1111 * Traverse the capabilities list. 1112 */ 1113 while (ptr != 0) { 1114 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1115 if (capreg != NULL) 1116 *capreg = ptr; 1117 return (0); 1118 } 1119 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1120 } 1121 1122 return (ENOENT); 1123 } 1124 1125 /* 1126 * Support for MSI-X message interrupts. 1127 */ 1128 void 1129 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 1130 { 1131 struct pci_devinfo *dinfo = device_get_ivars(dev); 1132 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1133 uint32_t offset; 1134 1135 KASSERT(msix->msix_table_len > index, ("bogus index")); 1136 offset = msix->msix_table_offset + index * 16; 1137 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1138 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1139 bus_write_4(msix->msix_table_res, offset + 8, data); 1140 1141 /* Enable MSI -> HT mapping. */ 1142 pci_ht_map_msi(dev, address); 1143 } 1144 1145 void 1146 pci_mask_msix(device_t dev, u_int index) 1147 { 1148 struct pci_devinfo *dinfo = device_get_ivars(dev); 1149 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1150 uint32_t offset, val; 1151 1152 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1153 offset = msix->msix_table_offset + index * 16 + 12; 1154 val = bus_read_4(msix->msix_table_res, offset); 1155 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 1156 val |= PCIM_MSIX_VCTRL_MASK; 1157 bus_write_4(msix->msix_table_res, offset, val); 1158 } 1159 } 1160 1161 void 1162 pci_unmask_msix(device_t dev, u_int index) 1163 { 1164 struct pci_devinfo *dinfo = device_get_ivars(dev); 1165 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1166 uint32_t offset, val; 1167 1168 KASSERT(msix->msix_table_len > index, ("bogus index")); 1169 offset = msix->msix_table_offset + index * 16 + 12; 1170 val = bus_read_4(msix->msix_table_res, offset); 1171 if (val & PCIM_MSIX_VCTRL_MASK) { 1172 val &= ~PCIM_MSIX_VCTRL_MASK; 1173 bus_write_4(msix->msix_table_res, offset, val); 1174 } 1175 } 1176 1177 int 1178 pci_pending_msix(device_t dev, u_int index) 1179 { 1180 struct pci_devinfo *dinfo = device_get_ivars(dev); 1181 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1182 uint32_t offset, bit; 1183 1184 KASSERT(msix->msix_table_len > index, ("bogus index")); 1185 offset = msix->msix_pba_offset + (index / 32) * 4; 1186 bit = 1 << index % 32; 1187 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1188 } 1189 1190 /* 1191 * Restore MSI-X registers and table during resume. If MSI-X is 1192 * enabled then walk the virtual table to restore the actual MSI-X 1193 * table. 1194 */ 1195 static void 1196 pci_resume_msix(device_t dev) 1197 { 1198 struct pci_devinfo *dinfo = device_get_ivars(dev); 1199 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1200 struct msix_table_entry *mte; 1201 struct msix_vector *mv; 1202 int i; 1203 1204 if (msix->msix_alloc > 0) { 1205 /* First, mask all vectors. */ 1206 for (i = 0; i < msix->msix_msgnum; i++) 1207 pci_mask_msix(dev, i); 1208 1209 /* Second, program any messages with at least one handler. */ 1210 for (i = 0; i < msix->msix_table_len; i++) { 1211 mte = &msix->msix_table[i]; 1212 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1213 continue; 1214 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1215 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data); 1216 pci_unmask_msix(dev, i); 1217 } 1218 } 1219 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1220 msix->msix_ctrl, 2); 1221 } 1222 1223 /* 1224 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1225 * returned in *count. After this function returns, each message will be 1226 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1227 */ 1228 int 1229 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1230 { 1231 struct pci_devinfo *dinfo = device_get_ivars(child); 1232 pcicfgregs *cfg = &dinfo->cfg; 1233 struct resource_list_entry *rle; 1234 int actual, error, i, irq, max; 1235 1236 /* Don't let count == 0 get us into trouble. */ 1237 if (*count == 0) 1238 return (EINVAL); 1239 1240 /* If rid 0 is allocated, then fail. */ 1241 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1242 if (rle != NULL && rle->res != NULL) 1243 return (ENXIO); 1244 1245 /* Already have allocated messages? */ 1246 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1247 return (ENXIO); 1248 1249 /* If MSI is blacklisted for this system, fail. */ 1250 if (pci_msi_blacklisted()) 1251 return (ENXIO); 1252 1253 /* MSI-X capability present? */ 1254 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1255 return (ENODEV); 1256 1257 /* Make sure the appropriate BARs are mapped. */ 1258 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1259 cfg->msix.msix_table_bar); 1260 if (rle == NULL || rle->res == NULL || 1261 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1262 return (ENXIO); 1263 cfg->msix.msix_table_res = rle->res; 1264 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1265 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1266 cfg->msix.msix_pba_bar); 1267 if (rle == NULL || rle->res == NULL || 1268 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1269 return (ENXIO); 1270 } 1271 cfg->msix.msix_pba_res = rle->res; 1272 1273 if (bootverbose) 1274 device_printf(child, 1275 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1276 *count, cfg->msix.msix_msgnum); 1277 max = min(*count, cfg->msix.msix_msgnum); 1278 for (i = 0; i < max; i++) { 1279 /* Allocate a message. */ 1280 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1281 if (error) 1282 break; 1283 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1284 irq, 1); 1285 } 1286 actual = i; 1287 1288 if (bootverbose) { 1289 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1290 if (actual == 1) 1291 device_printf(child, "using IRQ %lu for MSI-X\n", 1292 rle->start); 1293 else { 1294 int run; 1295 1296 /* 1297 * Be fancy and try to print contiguous runs of 1298 * IRQ values as ranges. 'irq' is the previous IRQ. 1299 * 'run' is true if we are in a range. 1300 */ 1301 device_printf(child, "using IRQs %lu", rle->start); 1302 irq = rle->start; 1303 run = 0; 1304 for (i = 1; i < actual; i++) { 1305 rle = resource_list_find(&dinfo->resources, 1306 SYS_RES_IRQ, i + 1); 1307 1308 /* Still in a run? */ 1309 if (rle->start == irq + 1) { 1310 run = 1; 1311 irq++; 1312 continue; 1313 } 1314 1315 /* Finish previous range. */ 1316 if (run) { 1317 printf("-%d", irq); 1318 run = 0; 1319 } 1320 1321 /* Start new range. */ 1322 printf(",%lu", rle->start); 1323 irq = rle->start; 1324 } 1325 1326 /* Unfinished range? */ 1327 if (run) 1328 printf("-%d", irq); 1329 printf(" for MSI-X\n"); 1330 } 1331 } 1332 1333 /* Mask all vectors. */ 1334 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1335 pci_mask_msix(child, i); 1336 1337 /* Allocate and initialize vector data and virtual table. */ 1338 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1339 M_DEVBUF, M_WAITOK | M_ZERO); 1340 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1341 M_DEVBUF, M_WAITOK | M_ZERO); 1342 for (i = 0; i < actual; i++) { 1343 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1344 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1345 cfg->msix.msix_table[i].mte_vector = i + 1; 1346 } 1347 1348 /* Update control register to enable MSI-X. */ 1349 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1350 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1351 cfg->msix.msix_ctrl, 2); 1352 1353 /* Update counts of alloc'd messages. */ 1354 cfg->msix.msix_alloc = actual; 1355 cfg->msix.msix_table_len = actual; 1356 *count = actual; 1357 return (0); 1358 } 1359 1360 /* 1361 * By default, pci_alloc_msix() will assign the allocated IRQ 1362 * resources consecutively to the first N messages in the MSI-X table. 1363 * However, device drivers may want to use different layouts if they 1364 * either receive fewer messages than they asked for, or they wish to 1365 * populate the MSI-X table sparsely. This method allows the driver 1366 * to specify what layout it wants. It must be called after a 1367 * successful pci_alloc_msix() but before any of the associated 1368 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1369 * 1370 * The 'vectors' array contains 'count' message vectors. The array 1371 * maps directly to the MSI-X table in that index 0 in the array 1372 * specifies the vector for the first message in the MSI-X table, etc. 1373 * The vector value in each array index can either be 0 to indicate 1374 * that no vector should be assigned to a message slot, or it can be a 1375 * number from 1 to N (where N is the count returned from a 1376 * succcessful call to pci_alloc_msix()) to indicate which message 1377 * vector (IRQ) to be used for the corresponding message. 1378 * 1379 * On successful return, each message with a non-zero vector will have 1380 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1381 * 1. Additionally, if any of the IRQs allocated via the previous 1382 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1383 * will be freed back to the system automatically. 1384 * 1385 * For example, suppose a driver has a MSI-X table with 6 messages and 1386 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1387 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1388 * C. After the call to pci_alloc_msix(), the device will be setup to 1389 * have an MSI-X table of ABC--- (where - means no vector assigned). 1390 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1391 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1392 * be freed back to the system. This device will also have valid 1393 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1394 * 1395 * In any case, the SYS_RES_IRQ rid X will always map to the message 1396 * at MSI-X table index X - 1 and will only be valid if a vector is 1397 * assigned to that table entry. 1398 */ 1399 int 1400 pci_remap_msix_method(device_t dev, device_t child, int count, 1401 const u_int *vectors) 1402 { 1403 struct pci_devinfo *dinfo = device_get_ivars(child); 1404 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1405 struct resource_list_entry *rle; 1406 int i, irq, j, *used; 1407 1408 /* 1409 * Have to have at least one message in the table but the 1410 * table can't be bigger than the actual MSI-X table in the 1411 * device. 1412 */ 1413 if (count == 0 || count > msix->msix_msgnum) 1414 return (EINVAL); 1415 1416 /* Sanity check the vectors. */ 1417 for (i = 0; i < count; i++) 1418 if (vectors[i] > msix->msix_alloc) 1419 return (EINVAL); 1420 1421 /* 1422 * Make sure there aren't any holes in the vectors to be used. 1423 * It's a big pain to support it, and it doesn't really make 1424 * sense anyway. Also, at least one vector must be used. 1425 */ 1426 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1427 M_ZERO); 1428 for (i = 0; i < count; i++) 1429 if (vectors[i] != 0) 1430 used[vectors[i] - 1] = 1; 1431 for (i = 0; i < msix->msix_alloc - 1; i++) 1432 if (used[i] == 0 && used[i + 1] == 1) { 1433 free(used, M_DEVBUF); 1434 return (EINVAL); 1435 } 1436 if (used[0] != 1) { 1437 free(used, M_DEVBUF); 1438 return (EINVAL); 1439 } 1440 1441 /* Make sure none of the resources are allocated. */ 1442 for (i = 0; i < msix->msix_table_len; i++) { 1443 if (msix->msix_table[i].mte_vector == 0) 1444 continue; 1445 if (msix->msix_table[i].mte_handlers > 0) 1446 return (EBUSY); 1447 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1448 KASSERT(rle != NULL, ("missing resource")); 1449 if (rle->res != NULL) 1450 return (EBUSY); 1451 } 1452 1453 /* Free the existing resource list entries. */ 1454 for (i = 0; i < msix->msix_table_len; i++) { 1455 if (msix->msix_table[i].mte_vector == 0) 1456 continue; 1457 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1458 } 1459 1460 /* 1461 * Build the new virtual table keeping track of which vectors are 1462 * used. 1463 */ 1464 free(msix->msix_table, M_DEVBUF); 1465 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1466 M_DEVBUF, M_WAITOK | M_ZERO); 1467 for (i = 0; i < count; i++) 1468 msix->msix_table[i].mte_vector = vectors[i]; 1469 msix->msix_table_len = count; 1470 1471 /* Free any unused IRQs and resize the vectors array if necessary. */ 1472 j = msix->msix_alloc - 1; 1473 if (used[j] == 0) { 1474 struct msix_vector *vec; 1475 1476 while (used[j] == 0) { 1477 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1478 msix->msix_vectors[j].mv_irq); 1479 j--; 1480 } 1481 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 1482 M_WAITOK); 1483 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 1484 (j + 1)); 1485 free(msix->msix_vectors, M_DEVBUF); 1486 msix->msix_vectors = vec; 1487 msix->msix_alloc = j + 1; 1488 } 1489 free(used, M_DEVBUF); 1490 1491 /* Map the IRQs onto the rids. */ 1492 for (i = 0; i < count; i++) { 1493 if (vectors[i] == 0) 1494 continue; 1495 irq = msix->msix_vectors[vectors[i]].mv_irq; 1496 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1497 irq, 1); 1498 } 1499 1500 if (bootverbose) { 1501 device_printf(child, "Remapped MSI-X IRQs as: "); 1502 for (i = 0; i < count; i++) { 1503 if (i != 0) 1504 printf(", "); 1505 if (vectors[i] == 0) 1506 printf("---"); 1507 else 1508 printf("%d", 1509 msix->msix_vectors[vectors[i]].mv_irq); 1510 } 1511 printf("\n"); 1512 } 1513 1514 return (0); 1515 } 1516 1517 static int 1518 pci_release_msix(device_t dev, device_t child) 1519 { 1520 struct pci_devinfo *dinfo = device_get_ivars(child); 1521 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1522 struct resource_list_entry *rle; 1523 int i; 1524 1525 /* Do we have any messages to release? */ 1526 if (msix->msix_alloc == 0) 1527 return (ENODEV); 1528 1529 /* Make sure none of the resources are allocated. */ 1530 for (i = 0; i < msix->msix_table_len; i++) { 1531 if (msix->msix_table[i].mte_vector == 0) 1532 continue; 1533 if (msix->msix_table[i].mte_handlers > 0) 1534 return (EBUSY); 1535 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1536 KASSERT(rle != NULL, ("missing resource")); 1537 if (rle->res != NULL) 1538 return (EBUSY); 1539 } 1540 1541 /* Update control register to disable MSI-X. */ 1542 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1543 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 1544 msix->msix_ctrl, 2); 1545 1546 /* Free the resource list entries. */ 1547 for (i = 0; i < msix->msix_table_len; i++) { 1548 if (msix->msix_table[i].mte_vector == 0) 1549 continue; 1550 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1551 } 1552 free(msix->msix_table, M_DEVBUF); 1553 msix->msix_table_len = 0; 1554 1555 /* Release the IRQs. */ 1556 for (i = 0; i < msix->msix_alloc; i++) 1557 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1558 msix->msix_vectors[i].mv_irq); 1559 free(msix->msix_vectors, M_DEVBUF); 1560 msix->msix_alloc = 0; 1561 return (0); 1562 } 1563 1564 /* 1565 * Return the max supported MSI-X messages this device supports. 1566 * Basically, assuming the MD code can alloc messages, this function 1567 * should return the maximum value that pci_alloc_msix() can return. 1568 * Thus, it is subject to the tunables, etc. 1569 */ 1570 int 1571 pci_msix_count_method(device_t dev, device_t child) 1572 { 1573 struct pci_devinfo *dinfo = device_get_ivars(child); 1574 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1575 1576 if (pci_do_msix && msix->msix_location != 0) 1577 return (msix->msix_msgnum); 1578 return (0); 1579 } 1580 1581 /* 1582 * HyperTransport MSI mapping control 1583 */ 1584 void 1585 pci_ht_map_msi(device_t dev, uint64_t addr) 1586 { 1587 struct pci_devinfo *dinfo = device_get_ivars(dev); 1588 struct pcicfg_ht *ht = &dinfo->cfg.ht; 1589 1590 if (!ht->ht_msimap) 1591 return; 1592 1593 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 1594 ht->ht_msiaddr >> 20 == addr >> 20) { 1595 /* Enable MSI -> HT mapping. */ 1596 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1597 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1598 ht->ht_msictrl, 2); 1599 } 1600 1601 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 1602 /* Disable MSI -> HT mapping. */ 1603 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 1604 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1605 ht->ht_msictrl, 2); 1606 } 1607 } 1608 1609 int 1610 pci_get_max_read_req(device_t dev) 1611 { 1612 int cap; 1613 uint16_t val; 1614 1615 if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) != 0) 1616 return (0); 1617 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2); 1618 val &= PCIM_EXP_CTL_MAX_READ_REQUEST; 1619 val >>= 12; 1620 return (1 << (val + 7)); 1621 } 1622 1623 int 1624 pci_set_max_read_req(device_t dev, int size) 1625 { 1626 int cap; 1627 uint16_t val; 1628 1629 if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) != 0) 1630 return (0); 1631 if (size < 128) 1632 size = 128; 1633 if (size > 4096) 1634 size = 4096; 1635 size = (1 << (fls(size) - 1)); 1636 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2); 1637 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 1638 val |= (fls(size) - 8) << 12; 1639 pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2); 1640 return (size); 1641 } 1642 1643 /* 1644 * Support for MSI message signalled interrupts. 1645 */ 1646 void 1647 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1648 { 1649 struct pci_devinfo *dinfo = device_get_ivars(dev); 1650 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1651 1652 /* Write data and address values. */ 1653 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1654 address & 0xffffffff, 4); 1655 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1656 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH, 1657 address >> 32, 4); 1658 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT, 1659 data, 2); 1660 } else 1661 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data, 1662 2); 1663 1664 /* Enable MSI in the control register. */ 1665 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1666 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1667 2); 1668 1669 /* Enable MSI -> HT mapping. */ 1670 pci_ht_map_msi(dev, address); 1671 } 1672 1673 void 1674 pci_disable_msi(device_t dev) 1675 { 1676 struct pci_devinfo *dinfo = device_get_ivars(dev); 1677 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1678 1679 /* Disable MSI -> HT mapping. */ 1680 pci_ht_map_msi(dev, 0); 1681 1682 /* Disable MSI in the control register. */ 1683 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 1684 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1685 2); 1686 } 1687 1688 /* 1689 * Restore MSI registers during resume. If MSI is enabled then 1690 * restore the data and address registers in addition to the control 1691 * register. 1692 */ 1693 static void 1694 pci_resume_msi(device_t dev) 1695 { 1696 struct pci_devinfo *dinfo = device_get_ivars(dev); 1697 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1698 uint64_t address; 1699 uint16_t data; 1700 1701 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1702 address = msi->msi_addr; 1703 data = msi->msi_data; 1704 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1705 address & 0xffffffff, 4); 1706 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1707 pci_write_config(dev, msi->msi_location + 1708 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1709 pci_write_config(dev, msi->msi_location + 1710 PCIR_MSI_DATA_64BIT, data, 2); 1711 } else 1712 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 1713 data, 2); 1714 } 1715 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1716 2); 1717 } 1718 1719 static int 1720 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 1721 { 1722 struct pci_devinfo *dinfo = device_get_ivars(dev); 1723 pcicfgregs *cfg = &dinfo->cfg; 1724 struct resource_list_entry *rle; 1725 struct msix_table_entry *mte; 1726 struct msix_vector *mv; 1727 uint64_t addr; 1728 uint32_t data; 1729 int error, i, j; 1730 1731 /* 1732 * Handle MSI first. We try to find this IRQ among our list 1733 * of MSI IRQs. If we find it, we request updated address and 1734 * data registers and apply the results. 1735 */ 1736 if (cfg->msi.msi_alloc > 0) { 1737 1738 /* If we don't have any active handlers, nothing to do. */ 1739 if (cfg->msi.msi_handlers == 0) 1740 return (0); 1741 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1742 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1743 i + 1); 1744 if (rle->start == irq) { 1745 error = PCIB_MAP_MSI(device_get_parent(bus), 1746 dev, irq, &addr, &data); 1747 if (error) 1748 return (error); 1749 pci_disable_msi(dev); 1750 dinfo->cfg.msi.msi_addr = addr; 1751 dinfo->cfg.msi.msi_data = data; 1752 pci_enable_msi(dev, addr, data); 1753 return (0); 1754 } 1755 } 1756 return (ENOENT); 1757 } 1758 1759 /* 1760 * For MSI-X, we check to see if we have this IRQ. If we do, 1761 * we request the updated mapping info. If that works, we go 1762 * through all the slots that use this IRQ and update them. 1763 */ 1764 if (cfg->msix.msix_alloc > 0) { 1765 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1766 mv = &cfg->msix.msix_vectors[i]; 1767 if (mv->mv_irq == irq) { 1768 error = PCIB_MAP_MSI(device_get_parent(bus), 1769 dev, irq, &addr, &data); 1770 if (error) 1771 return (error); 1772 mv->mv_address = addr; 1773 mv->mv_data = data; 1774 for (j = 0; j < cfg->msix.msix_table_len; j++) { 1775 mte = &cfg->msix.msix_table[j]; 1776 if (mte->mte_vector != i + 1) 1777 continue; 1778 if (mte->mte_handlers == 0) 1779 continue; 1780 pci_mask_msix(dev, j); 1781 pci_enable_msix(dev, j, addr, data); 1782 pci_unmask_msix(dev, j); 1783 } 1784 } 1785 } 1786 return (ENOENT); 1787 } 1788 1789 return (ENOENT); 1790 } 1791 1792 /* 1793 * Returns true if the specified device is blacklisted because MSI 1794 * doesn't work. 1795 */ 1796 int 1797 pci_msi_device_blacklisted(device_t dev) 1798 { 1799 struct pci_quirk *q; 1800 1801 if (!pci_honor_msi_blacklist) 1802 return (0); 1803 1804 for (q = &pci_quirks[0]; q->devid; q++) { 1805 if (q->devid == pci_get_devid(dev) && 1806 q->type == PCI_QUIRK_DISABLE_MSI) 1807 return (1); 1808 } 1809 return (0); 1810 } 1811 1812 /* 1813 * Returns true if a specified chipset supports MSI when it is 1814 * emulated hardware in a virtual machine. 1815 */ 1816 static int 1817 pci_msi_vm_chipset(device_t dev) 1818 { 1819 struct pci_quirk *q; 1820 1821 for (q = &pci_quirks[0]; q->devid; q++) { 1822 if (q->devid == pci_get_devid(dev) && 1823 q->type == PCI_QUIRK_ENABLE_MSI_VM) 1824 return (1); 1825 } 1826 return (0); 1827 } 1828 1829 /* 1830 * Determine if MSI is blacklisted globally on this sytem. Currently, 1831 * we just check for blacklisted chipsets as represented by the 1832 * host-PCI bridge at device 0:0:0. In the future, it may become 1833 * necessary to check other system attributes, such as the kenv values 1834 * that give the motherboard manufacturer and model number. 1835 */ 1836 static int 1837 pci_msi_blacklisted(void) 1838 { 1839 device_t dev; 1840 1841 if (!pci_honor_msi_blacklist) 1842 return (0); 1843 1844 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 1845 if (!(pcie_chipset || pcix_chipset)) { 1846 if (vm_guest != VM_GUEST_NO) { 1847 dev = pci_find_bsf(0, 0, 0); 1848 if (dev != NULL) 1849 return (pci_msi_vm_chipset(dev) == 0); 1850 } 1851 return (1); 1852 } 1853 1854 dev = pci_find_bsf(0, 0, 0); 1855 if (dev != NULL) 1856 return (pci_msi_device_blacklisted(dev)); 1857 return (0); 1858 } 1859 1860 /* 1861 * Attempt to allocate *count MSI messages. The actual number allocated is 1862 * returned in *count. After this function returns, each message will be 1863 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 1864 */ 1865 int 1866 pci_alloc_msi_method(device_t dev, device_t child, int *count) 1867 { 1868 struct pci_devinfo *dinfo = device_get_ivars(child); 1869 pcicfgregs *cfg = &dinfo->cfg; 1870 struct resource_list_entry *rle; 1871 int actual, error, i, irqs[32]; 1872 uint16_t ctrl; 1873 1874 /* Don't let count == 0 get us into trouble. */ 1875 if (*count == 0) 1876 return (EINVAL); 1877 1878 /* If rid 0 is allocated, then fail. */ 1879 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1880 if (rle != NULL && rle->res != NULL) 1881 return (ENXIO); 1882 1883 /* Already have allocated messages? */ 1884 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1885 return (ENXIO); 1886 1887 /* If MSI is blacklisted for this system, fail. */ 1888 if (pci_msi_blacklisted()) 1889 return (ENXIO); 1890 1891 /* MSI capability present? */ 1892 if (cfg->msi.msi_location == 0 || !pci_do_msi) 1893 return (ENODEV); 1894 1895 if (bootverbose) 1896 device_printf(child, 1897 "attempting to allocate %d MSI vectors (%d supported)\n", 1898 *count, cfg->msi.msi_msgnum); 1899 1900 /* Don't ask for more than the device supports. */ 1901 actual = min(*count, cfg->msi.msi_msgnum); 1902 1903 /* Don't ask for more than 32 messages. */ 1904 actual = min(actual, 32); 1905 1906 /* MSI requires power of 2 number of messages. */ 1907 if (!powerof2(actual)) 1908 return (EINVAL); 1909 1910 for (;;) { 1911 /* Try to allocate N messages. */ 1912 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 1913 cfg->msi.msi_msgnum, irqs); 1914 if (error == 0) 1915 break; 1916 if (actual == 1) 1917 return (error); 1918 1919 /* Try N / 2. */ 1920 actual >>= 1; 1921 } 1922 1923 /* 1924 * We now have N actual messages mapped onto SYS_RES_IRQ 1925 * resources in the irqs[] array, so add new resources 1926 * starting at rid 1. 1927 */ 1928 for (i = 0; i < actual; i++) 1929 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 1930 irqs[i], irqs[i], 1); 1931 1932 if (bootverbose) { 1933 if (actual == 1) 1934 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 1935 else { 1936 int run; 1937 1938 /* 1939 * Be fancy and try to print contiguous runs 1940 * of IRQ values as ranges. 'run' is true if 1941 * we are in a range. 1942 */ 1943 device_printf(child, "using IRQs %d", irqs[0]); 1944 run = 0; 1945 for (i = 1; i < actual; i++) { 1946 1947 /* Still in a run? */ 1948 if (irqs[i] == irqs[i - 1] + 1) { 1949 run = 1; 1950 continue; 1951 } 1952 1953 /* Finish previous range. */ 1954 if (run) { 1955 printf("-%d", irqs[i - 1]); 1956 run = 0; 1957 } 1958 1959 /* Start new range. */ 1960 printf(",%d", irqs[i]); 1961 } 1962 1963 /* Unfinished range? */ 1964 if (run) 1965 printf("-%d", irqs[actual - 1]); 1966 printf(" for MSI\n"); 1967 } 1968 } 1969 1970 /* Update control register with actual count. */ 1971 ctrl = cfg->msi.msi_ctrl; 1972 ctrl &= ~PCIM_MSICTRL_MME_MASK; 1973 ctrl |= (ffs(actual) - 1) << 4; 1974 cfg->msi.msi_ctrl = ctrl; 1975 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 1976 1977 /* Update counts of alloc'd messages. */ 1978 cfg->msi.msi_alloc = actual; 1979 cfg->msi.msi_handlers = 0; 1980 *count = actual; 1981 return (0); 1982 } 1983 1984 /* Release the MSI messages associated with this device. */ 1985 int 1986 pci_release_msi_method(device_t dev, device_t child) 1987 { 1988 struct pci_devinfo *dinfo = device_get_ivars(child); 1989 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1990 struct resource_list_entry *rle; 1991 int error, i, irqs[32]; 1992 1993 /* Try MSI-X first. */ 1994 error = pci_release_msix(dev, child); 1995 if (error != ENODEV) 1996 return (error); 1997 1998 /* Do we have any messages to release? */ 1999 if (msi->msi_alloc == 0) 2000 return (ENODEV); 2001 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2002 2003 /* Make sure none of the resources are allocated. */ 2004 if (msi->msi_handlers > 0) 2005 return (EBUSY); 2006 for (i = 0; i < msi->msi_alloc; i++) { 2007 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2008 KASSERT(rle != NULL, ("missing MSI resource")); 2009 if (rle->res != NULL) 2010 return (EBUSY); 2011 irqs[i] = rle->start; 2012 } 2013 2014 /* Update control register with 0 count. */ 2015 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2016 ("%s: MSI still enabled", __func__)); 2017 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2018 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2019 msi->msi_ctrl, 2); 2020 2021 /* Release the messages. */ 2022 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2023 for (i = 0; i < msi->msi_alloc; i++) 2024 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2025 2026 /* Update alloc count. */ 2027 msi->msi_alloc = 0; 2028 msi->msi_addr = 0; 2029 msi->msi_data = 0; 2030 return (0); 2031 } 2032 2033 /* 2034 * Return the max supported MSI messages this device supports. 2035 * Basically, assuming the MD code can alloc messages, this function 2036 * should return the maximum value that pci_alloc_msi() can return. 2037 * Thus, it is subject to the tunables, etc. 2038 */ 2039 int 2040 pci_msi_count_method(device_t dev, device_t child) 2041 { 2042 struct pci_devinfo *dinfo = device_get_ivars(child); 2043 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2044 2045 if (pci_do_msi && msi->msi_location != 0) 2046 return (msi->msi_msgnum); 2047 return (0); 2048 } 2049 2050 /* free pcicfgregs structure and all depending data structures */ 2051 2052 int 2053 pci_freecfg(struct pci_devinfo *dinfo) 2054 { 2055 struct devlist *devlist_head; 2056 int i; 2057 2058 devlist_head = &pci_devq; 2059 2060 if (dinfo->cfg.vpd.vpd_reg) { 2061 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2062 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2063 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2064 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2065 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2066 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2067 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2068 } 2069 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2070 free(dinfo, M_DEVBUF); 2071 2072 /* increment the generation count */ 2073 pci_generation++; 2074 2075 /* we're losing one device */ 2076 pci_numdevs--; 2077 return (0); 2078 } 2079 2080 /* 2081 * PCI power manangement 2082 */ 2083 int 2084 pci_set_powerstate_method(device_t dev, device_t child, int state) 2085 { 2086 struct pci_devinfo *dinfo = device_get_ivars(child); 2087 pcicfgregs *cfg = &dinfo->cfg; 2088 uint16_t status; 2089 int result, oldstate, highest, delay; 2090 2091 if (cfg->pp.pp_cap == 0) 2092 return (EOPNOTSUPP); 2093 2094 /* 2095 * Optimize a no state change request away. While it would be OK to 2096 * write to the hardware in theory, some devices have shown odd 2097 * behavior when going from D3 -> D3. 2098 */ 2099 oldstate = pci_get_powerstate(child); 2100 if (oldstate == state) 2101 return (0); 2102 2103 /* 2104 * The PCI power management specification states that after a state 2105 * transition between PCI power states, system software must 2106 * guarantee a minimal delay before the function accesses the device. 2107 * Compute the worst case delay that we need to guarantee before we 2108 * access the device. Many devices will be responsive much more 2109 * quickly than this delay, but there are some that don't respond 2110 * instantly to state changes. Transitions to/from D3 state require 2111 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2112 * is done below with DELAY rather than a sleeper function because 2113 * this function can be called from contexts where we cannot sleep. 2114 */ 2115 highest = (oldstate > state) ? oldstate : state; 2116 if (highest == PCI_POWERSTATE_D3) 2117 delay = 10000; 2118 else if (highest == PCI_POWERSTATE_D2) 2119 delay = 200; 2120 else 2121 delay = 0; 2122 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2123 & ~PCIM_PSTAT_DMASK; 2124 result = 0; 2125 switch (state) { 2126 case PCI_POWERSTATE_D0: 2127 status |= PCIM_PSTAT_D0; 2128 break; 2129 case PCI_POWERSTATE_D1: 2130 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2131 return (EOPNOTSUPP); 2132 status |= PCIM_PSTAT_D1; 2133 break; 2134 case PCI_POWERSTATE_D2: 2135 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2136 return (EOPNOTSUPP); 2137 status |= PCIM_PSTAT_D2; 2138 break; 2139 case PCI_POWERSTATE_D3: 2140 status |= PCIM_PSTAT_D3; 2141 break; 2142 default: 2143 return (EINVAL); 2144 } 2145 2146 if (bootverbose) 2147 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2148 state); 2149 2150 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2151 if (delay) 2152 DELAY(delay); 2153 return (0); 2154 } 2155 2156 int 2157 pci_get_powerstate_method(device_t dev, device_t child) 2158 { 2159 struct pci_devinfo *dinfo = device_get_ivars(child); 2160 pcicfgregs *cfg = &dinfo->cfg; 2161 uint16_t status; 2162 int result; 2163 2164 if (cfg->pp.pp_cap != 0) { 2165 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2166 switch (status & PCIM_PSTAT_DMASK) { 2167 case PCIM_PSTAT_D0: 2168 result = PCI_POWERSTATE_D0; 2169 break; 2170 case PCIM_PSTAT_D1: 2171 result = PCI_POWERSTATE_D1; 2172 break; 2173 case PCIM_PSTAT_D2: 2174 result = PCI_POWERSTATE_D2; 2175 break; 2176 case PCIM_PSTAT_D3: 2177 result = PCI_POWERSTATE_D3; 2178 break; 2179 default: 2180 result = PCI_POWERSTATE_UNKNOWN; 2181 break; 2182 } 2183 } else { 2184 /* No support, device is always at D0 */ 2185 result = PCI_POWERSTATE_D0; 2186 } 2187 return (result); 2188 } 2189 2190 /* 2191 * Some convenience functions for PCI device drivers. 2192 */ 2193 2194 static __inline void 2195 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2196 { 2197 uint16_t command; 2198 2199 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2200 command |= bit; 2201 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2202 } 2203 2204 static __inline void 2205 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2206 { 2207 uint16_t command; 2208 2209 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2210 command &= ~bit; 2211 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2212 } 2213 2214 int 2215 pci_enable_busmaster_method(device_t dev, device_t child) 2216 { 2217 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2218 return (0); 2219 } 2220 2221 int 2222 pci_disable_busmaster_method(device_t dev, device_t child) 2223 { 2224 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2225 return (0); 2226 } 2227 2228 int 2229 pci_enable_io_method(device_t dev, device_t child, int space) 2230 { 2231 uint16_t bit; 2232 2233 switch(space) { 2234 case SYS_RES_IOPORT: 2235 bit = PCIM_CMD_PORTEN; 2236 break; 2237 case SYS_RES_MEMORY: 2238 bit = PCIM_CMD_MEMEN; 2239 break; 2240 default: 2241 return (EINVAL); 2242 } 2243 pci_set_command_bit(dev, child, bit); 2244 return (0); 2245 } 2246 2247 int 2248 pci_disable_io_method(device_t dev, device_t child, int space) 2249 { 2250 uint16_t bit; 2251 2252 switch(space) { 2253 case SYS_RES_IOPORT: 2254 bit = PCIM_CMD_PORTEN; 2255 break; 2256 case SYS_RES_MEMORY: 2257 bit = PCIM_CMD_MEMEN; 2258 break; 2259 default: 2260 return (EINVAL); 2261 } 2262 pci_clear_command_bit(dev, child, bit); 2263 return (0); 2264 } 2265 2266 /* 2267 * New style pci driver. Parent device is either a pci-host-bridge or a 2268 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2269 */ 2270 2271 void 2272 pci_print_verbose(struct pci_devinfo *dinfo) 2273 { 2274 2275 if (bootverbose) { 2276 pcicfgregs *cfg = &dinfo->cfg; 2277 2278 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2279 cfg->vendor, cfg->device, cfg->revid); 2280 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2281 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2282 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2283 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2284 cfg->mfdev); 2285 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2286 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2287 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2288 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2289 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2290 if (cfg->intpin > 0) 2291 printf("\tintpin=%c, irq=%d\n", 2292 cfg->intpin +'a' -1, cfg->intline); 2293 if (cfg->pp.pp_cap) { 2294 uint16_t status; 2295 2296 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2297 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2298 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2299 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2300 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2301 status & PCIM_PSTAT_DMASK); 2302 } 2303 if (cfg->msi.msi_location) { 2304 int ctrl; 2305 2306 ctrl = cfg->msi.msi_ctrl; 2307 printf("\tMSI supports %d message%s%s%s\n", 2308 cfg->msi.msi_msgnum, 2309 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2310 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2311 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2312 } 2313 if (cfg->msix.msix_location) { 2314 printf("\tMSI-X supports %d message%s ", 2315 cfg->msix.msix_msgnum, 2316 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2317 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2318 printf("in map 0x%x\n", 2319 cfg->msix.msix_table_bar); 2320 else 2321 printf("in maps 0x%x and 0x%x\n", 2322 cfg->msix.msix_table_bar, 2323 cfg->msix.msix_pba_bar); 2324 } 2325 } 2326 } 2327 2328 static int 2329 pci_porten(device_t dev) 2330 { 2331 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2332 } 2333 2334 static int 2335 pci_memen(device_t dev) 2336 { 2337 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2338 } 2339 2340 static void 2341 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp) 2342 { 2343 pci_addr_t map, testval; 2344 int ln2range; 2345 uint16_t cmd; 2346 2347 map = pci_read_config(dev, reg, 4); 2348 ln2range = pci_maprange(map); 2349 if (ln2range == 64) 2350 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2351 2352 /* 2353 * Disable decoding via the command register before 2354 * determining the BAR's length since we will be placing it in 2355 * a weird state. 2356 */ 2357 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2358 pci_write_config(dev, PCIR_COMMAND, 2359 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 2360 2361 /* 2362 * Determine the BAR's length by writing all 1's. The bottom 2363 * log_2(size) bits of the BAR will stick as 0 when we read 2364 * the value back. 2365 */ 2366 pci_write_config(dev, reg, 0xffffffff, 4); 2367 testval = pci_read_config(dev, reg, 4); 2368 if (ln2range == 64) { 2369 pci_write_config(dev, reg + 4, 0xffffffff, 4); 2370 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2371 } 2372 2373 /* 2374 * Restore the original value of the BAR. We may have reprogrammed 2375 * the BAR of the low-level console device and when booting verbose, 2376 * we need the console device addressable. 2377 */ 2378 pci_write_config(dev, reg, map, 4); 2379 if (ln2range == 64) 2380 pci_write_config(dev, reg + 4, map >> 32, 4); 2381 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2382 2383 *mapp = map; 2384 *testvalp = testval; 2385 } 2386 2387 static void 2388 pci_write_bar(device_t dev, int reg, pci_addr_t base) 2389 { 2390 pci_addr_t map; 2391 int ln2range; 2392 2393 map = pci_read_config(dev, reg, 4); 2394 ln2range = pci_maprange(map); 2395 pci_write_config(dev, reg, base, 4); 2396 if (ln2range == 64) 2397 pci_write_config(dev, reg + 4, base >> 32, 4); 2398 } 2399 2400 /* 2401 * Add a resource based on a pci map register. Return 1 if the map 2402 * register is a 32bit map register or 2 if it is a 64bit register. 2403 */ 2404 static int 2405 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 2406 int force, int prefetch) 2407 { 2408 pci_addr_t base, map, testval; 2409 pci_addr_t start, end, count; 2410 int barlen, basezero, maprange, mapsize, type; 2411 uint16_t cmd; 2412 struct resource *res; 2413 2414 pci_read_bar(dev, reg, &map, &testval); 2415 if (PCI_BAR_MEM(map)) { 2416 type = SYS_RES_MEMORY; 2417 if (map & PCIM_BAR_MEM_PREFETCH) 2418 prefetch = 1; 2419 } else 2420 type = SYS_RES_IOPORT; 2421 mapsize = pci_mapsize(testval); 2422 base = pci_mapbase(map); 2423 #ifdef __PCI_BAR_ZERO_VALID 2424 basezero = 0; 2425 #else 2426 basezero = base == 0; 2427 #endif 2428 maprange = pci_maprange(map); 2429 barlen = maprange == 64 ? 2 : 1; 2430 2431 /* 2432 * For I/O registers, if bottom bit is set, and the next bit up 2433 * isn't clear, we know we have a BAR that doesn't conform to the 2434 * spec, so ignore it. Also, sanity check the size of the data 2435 * areas to the type of memory involved. Memory must be at least 2436 * 16 bytes in size, while I/O ranges must be at least 4. 2437 */ 2438 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 2439 return (barlen); 2440 if ((type == SYS_RES_MEMORY && mapsize < 4) || 2441 (type == SYS_RES_IOPORT && mapsize < 2)) 2442 return (barlen); 2443 2444 if (bootverbose) { 2445 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 2446 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 2447 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2448 printf(", port disabled\n"); 2449 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2450 printf(", memory disabled\n"); 2451 else 2452 printf(", enabled\n"); 2453 } 2454 2455 /* 2456 * If base is 0, then we have problems if this architecture does 2457 * not allow that. It is best to ignore such entries for the 2458 * moment. These will be allocated later if the driver specifically 2459 * requests them. However, some removable busses look better when 2460 * all resources are allocated, so allow '' to be overriden. 2461 * 2462 * Similarly treat maps whose values is the same as the test value 2463 * read back. These maps have had all f's written to them by the 2464 * BIOS in an attempt to disable the resources. 2465 */ 2466 if (!force && (basezero || map == testval)) 2467 return (barlen); 2468 if ((u_long)base != base) { 2469 device_printf(bus, 2470 "pci%d:%d:%d:%d bar %#x too many address bits", 2471 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 2472 pci_get_function(dev), reg); 2473 return (barlen); 2474 } 2475 2476 /* 2477 * This code theoretically does the right thing, but has 2478 * undesirable side effects in some cases where peripherals 2479 * respond oddly to having these bits enabled. Let the user 2480 * be able to turn them off (since pci_enable_io_modes is 1 by 2481 * default). 2482 */ 2483 if (pci_enable_io_modes) { 2484 /* Turn on resources that have been left off by a lazy BIOS */ 2485 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 2486 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2487 cmd |= PCIM_CMD_PORTEN; 2488 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2489 } 2490 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 2491 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2492 cmd |= PCIM_CMD_MEMEN; 2493 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2494 } 2495 } else { 2496 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2497 return (barlen); 2498 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2499 return (barlen); 2500 } 2501 2502 count = 1 << mapsize; 2503 if (basezero || base == pci_mapbase(testval)) { 2504 start = 0; /* Let the parent decide. */ 2505 end = ~0ULL; 2506 } else { 2507 start = base; 2508 end = base + (1 << mapsize) - 1; 2509 } 2510 resource_list_add(rl, type, reg, start, end, count); 2511 2512 /* 2513 * Try to allocate the resource for this BAR from our parent 2514 * so that this resource range is already reserved. The 2515 * driver for this device will later inherit this resource in 2516 * pci_alloc_resource(). 2517 */ 2518 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 2519 prefetch ? RF_PREFETCHABLE : 0); 2520 if (res == NULL) { 2521 /* 2522 * If the allocation fails, clear the BAR and delete 2523 * the resource list entry to force 2524 * pci_alloc_resource() to allocate resources from the 2525 * parent. 2526 */ 2527 resource_list_delete(rl, type, reg); 2528 start = 0; 2529 } else { 2530 start = rman_get_start(res); 2531 rman_set_device(res, bus); 2532 } 2533 pci_write_bar(dev, reg, start); 2534 return (barlen); 2535 } 2536 2537 /* 2538 * For ATA devices we need to decide early what addressing mode to use. 2539 * Legacy demands that the primary and secondary ATA ports sits on the 2540 * same addresses that old ISA hardware did. This dictates that we use 2541 * those addresses and ignore the BAR's if we cannot set PCI native 2542 * addressing mode. 2543 */ 2544 static void 2545 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 2546 uint32_t prefetchmask) 2547 { 2548 struct resource *r; 2549 int rid, type, progif; 2550 #if 0 2551 /* if this device supports PCI native addressing use it */ 2552 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2553 if ((progif & 0x8a) == 0x8a) { 2554 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 2555 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 2556 printf("Trying ATA native PCI addressing mode\n"); 2557 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 2558 } 2559 } 2560 #endif 2561 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2562 type = SYS_RES_IOPORT; 2563 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 2564 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 2565 prefetchmask & (1 << 0)); 2566 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 2567 prefetchmask & (1 << 1)); 2568 } else { 2569 rid = PCIR_BAR(0); 2570 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 2571 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 2572 8, 0); 2573 rman_set_device(r, bus); 2574 rid = PCIR_BAR(1); 2575 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 2576 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 2577 1, 0); 2578 rman_set_device(r, bus); 2579 } 2580 if (progif & PCIP_STORAGE_IDE_MODESEC) { 2581 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 2582 prefetchmask & (1 << 2)); 2583 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 2584 prefetchmask & (1 << 3)); 2585 } else { 2586 rid = PCIR_BAR(2); 2587 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 2588 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 2589 8, 0); 2590 rman_set_device(r, bus); 2591 rid = PCIR_BAR(3); 2592 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 2593 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 2594 1, 0); 2595 rman_set_device(r, bus); 2596 } 2597 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 2598 prefetchmask & (1 << 4)); 2599 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 2600 prefetchmask & (1 << 5)); 2601 } 2602 2603 static void 2604 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 2605 { 2606 struct pci_devinfo *dinfo = device_get_ivars(dev); 2607 pcicfgregs *cfg = &dinfo->cfg; 2608 char tunable_name[64]; 2609 int irq; 2610 2611 /* Has to have an intpin to have an interrupt. */ 2612 if (cfg->intpin == 0) 2613 return; 2614 2615 /* Let the user override the IRQ with a tunable. */ 2616 irq = PCI_INVALID_IRQ; 2617 snprintf(tunable_name, sizeof(tunable_name), 2618 "hw.pci%d.%d.%d.INT%c.irq", 2619 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 2620 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 2621 irq = PCI_INVALID_IRQ; 2622 2623 /* 2624 * If we didn't get an IRQ via the tunable, then we either use the 2625 * IRQ value in the intline register or we ask the bus to route an 2626 * interrupt for us. If force_route is true, then we only use the 2627 * value in the intline register if the bus was unable to assign an 2628 * IRQ. 2629 */ 2630 if (!PCI_INTERRUPT_VALID(irq)) { 2631 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 2632 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 2633 if (!PCI_INTERRUPT_VALID(irq)) 2634 irq = cfg->intline; 2635 } 2636 2637 /* If after all that we don't have an IRQ, just bail. */ 2638 if (!PCI_INTERRUPT_VALID(irq)) 2639 return; 2640 2641 /* Update the config register if it changed. */ 2642 if (irq != cfg->intline) { 2643 cfg->intline = irq; 2644 pci_write_config(dev, PCIR_INTLINE, irq, 1); 2645 } 2646 2647 /* Add this IRQ as rid 0 interrupt resource. */ 2648 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 2649 } 2650 2651 /* Perform early OHCI takeover from SMM. */ 2652 static void 2653 ohci_early_takeover(device_t self) 2654 { 2655 struct resource *res; 2656 uint32_t ctl; 2657 int rid; 2658 int i; 2659 2660 rid = PCIR_BAR(0); 2661 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 2662 if (res == NULL) 2663 return; 2664 2665 ctl = bus_read_4(res, OHCI_CONTROL); 2666 if (ctl & OHCI_IR) { 2667 if (bootverbose) 2668 printf("ohci early: " 2669 "SMM active, request owner change\n"); 2670 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 2671 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 2672 DELAY(1000); 2673 ctl = bus_read_4(res, OHCI_CONTROL); 2674 } 2675 if (ctl & OHCI_IR) { 2676 if (bootverbose) 2677 printf("ohci early: " 2678 "SMM does not respond, resetting\n"); 2679 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 2680 } 2681 /* Disable interrupts */ 2682 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 2683 } 2684 2685 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 2686 } 2687 2688 /* Perform early UHCI takeover from SMM. */ 2689 static void 2690 uhci_early_takeover(device_t self) 2691 { 2692 struct resource *res; 2693 int rid; 2694 2695 /* 2696 * Set the PIRQD enable bit and switch off all the others. We don't 2697 * want legacy support to interfere with us XXX Does this also mean 2698 * that the BIOS won't touch the keyboard anymore if it is connected 2699 * to the ports of the root hub? 2700 */ 2701 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 2702 2703 /* Disable interrupts */ 2704 rid = PCI_UHCI_BASE_REG; 2705 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 2706 if (res != NULL) { 2707 bus_write_2(res, UHCI_INTR, 0); 2708 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 2709 } 2710 } 2711 2712 /* Perform early EHCI takeover from SMM. */ 2713 static void 2714 ehci_early_takeover(device_t self) 2715 { 2716 struct resource *res; 2717 uint32_t cparams; 2718 uint32_t eec; 2719 uint8_t eecp; 2720 uint8_t bios_sem; 2721 uint8_t offs; 2722 int rid; 2723 int i; 2724 2725 rid = PCIR_BAR(0); 2726 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 2727 if (res == NULL) 2728 return; 2729 2730 cparams = bus_read_4(res, EHCI_HCCPARAMS); 2731 2732 /* Synchronise with the BIOS if it owns the controller. */ 2733 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 2734 eecp = EHCI_EECP_NEXT(eec)) { 2735 eec = pci_read_config(self, eecp, 4); 2736 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 2737 continue; 2738 } 2739 bios_sem = pci_read_config(self, eecp + 2740 EHCI_LEGSUP_BIOS_SEM, 1); 2741 if (bios_sem == 0) { 2742 continue; 2743 } 2744 if (bootverbose) 2745 printf("ehci early: " 2746 "SMM active, request owner change\n"); 2747 2748 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 2749 2750 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 2751 DELAY(1000); 2752 bios_sem = pci_read_config(self, eecp + 2753 EHCI_LEGSUP_BIOS_SEM, 1); 2754 } 2755 2756 if (bios_sem != 0) { 2757 if (bootverbose) 2758 printf("ehci early: " 2759 "SMM does not respond\n"); 2760 } 2761 /* Disable interrupts */ 2762 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 2763 bus_write_4(res, offs + EHCI_USBINTR, 0); 2764 } 2765 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 2766 } 2767 2768 void 2769 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 2770 { 2771 struct pci_devinfo *dinfo = device_get_ivars(dev); 2772 pcicfgregs *cfg = &dinfo->cfg; 2773 struct resource_list *rl = &dinfo->resources; 2774 struct pci_quirk *q; 2775 int i; 2776 2777 /* ATA devices needs special map treatment */ 2778 if ((pci_get_class(dev) == PCIC_STORAGE) && 2779 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 2780 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 2781 (!pci_read_config(dev, PCIR_BAR(0), 4) && 2782 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 2783 pci_ata_maps(bus, dev, rl, force, prefetchmask); 2784 else 2785 for (i = 0; i < cfg->nummaps;) 2786 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 2787 prefetchmask & (1 << i)); 2788 2789 /* 2790 * Add additional, quirked resources. 2791 */ 2792 for (q = &pci_quirks[0]; q->devid; q++) { 2793 if (q->devid == ((cfg->device << 16) | cfg->vendor) 2794 && q->type == PCI_QUIRK_MAP_REG) 2795 pci_add_map(bus, dev, q->arg1, rl, force, 0); 2796 } 2797 2798 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 2799 #ifdef __PCI_REROUTE_INTERRUPT 2800 /* 2801 * Try to re-route interrupts. Sometimes the BIOS or 2802 * firmware may leave bogus values in these registers. 2803 * If the re-route fails, then just stick with what we 2804 * have. 2805 */ 2806 pci_assign_interrupt(bus, dev, 1); 2807 #else 2808 pci_assign_interrupt(bus, dev, 0); 2809 #endif 2810 } 2811 2812 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 2813 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 2814 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 2815 ehci_early_takeover(dev); 2816 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 2817 ohci_early_takeover(dev); 2818 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 2819 uhci_early_takeover(dev); 2820 } 2821 } 2822 2823 void 2824 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size) 2825 { 2826 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 2827 device_t pcib = device_get_parent(dev); 2828 struct pci_devinfo *dinfo; 2829 int maxslots; 2830 int s, f, pcifunchigh; 2831 uint8_t hdrtype; 2832 2833 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 2834 ("dinfo_size too small")); 2835 maxslots = PCIB_MAXSLOTS(pcib); 2836 for (s = 0; s <= maxslots; s++) { 2837 pcifunchigh = 0; 2838 f = 0; 2839 DELAY(1); 2840 hdrtype = REG(PCIR_HDRTYPE, 1); 2841 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 2842 continue; 2843 if (hdrtype & PCIM_MFDEV) 2844 pcifunchigh = PCI_FUNCMAX; 2845 for (f = 0; f <= pcifunchigh; f++) { 2846 dinfo = pci_read_device(pcib, domain, busno, s, f, 2847 dinfo_size); 2848 if (dinfo != NULL) { 2849 pci_add_child(dev, dinfo); 2850 } 2851 } 2852 } 2853 #undef REG 2854 } 2855 2856 void 2857 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 2858 { 2859 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 2860 device_set_ivars(dinfo->cfg.dev, dinfo); 2861 resource_list_init(&dinfo->resources); 2862 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 2863 pci_cfg_restore(dinfo->cfg.dev, dinfo); 2864 pci_print_verbose(dinfo); 2865 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 2866 } 2867 2868 static int 2869 pci_probe(device_t dev) 2870 { 2871 2872 device_set_desc(dev, "PCI bus"); 2873 2874 /* Allow other subclasses to override this driver. */ 2875 return (BUS_PROBE_GENERIC); 2876 } 2877 2878 static int 2879 pci_attach(device_t dev) 2880 { 2881 int busno, domain; 2882 2883 /* 2884 * Since there can be multiple independantly numbered PCI 2885 * busses on systems with multiple PCI domains, we can't use 2886 * the unit number to decide which bus we are probing. We ask 2887 * the parent pcib what our domain and bus numbers are. 2888 */ 2889 domain = pcib_get_domain(dev); 2890 busno = pcib_get_bus(dev); 2891 if (bootverbose) 2892 device_printf(dev, "domain=%d, physical bus=%d\n", 2893 domain, busno); 2894 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo)); 2895 return (bus_generic_attach(dev)); 2896 } 2897 2898 int 2899 pci_suspend(device_t dev) 2900 { 2901 int dstate, error, i, numdevs; 2902 device_t acpi_dev, child, *devlist; 2903 struct pci_devinfo *dinfo; 2904 2905 /* 2906 * Save the PCI configuration space for each child and set the 2907 * device in the appropriate power state for this sleep state. 2908 */ 2909 acpi_dev = NULL; 2910 if (pci_do_power_resume) 2911 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2912 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 2913 return (error); 2914 for (i = 0; i < numdevs; i++) { 2915 child = devlist[i]; 2916 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2917 pci_cfg_save(child, dinfo, 0); 2918 } 2919 2920 /* Suspend devices before potentially powering them down. */ 2921 error = bus_generic_suspend(dev); 2922 if (error) { 2923 free(devlist, M_TEMP); 2924 return (error); 2925 } 2926 2927 /* 2928 * Always set the device to D3. If ACPI suggests a different 2929 * power state, use it instead. If ACPI is not present, the 2930 * firmware is responsible for managing device power. Skip 2931 * children who aren't attached since they are powered down 2932 * separately. Only manage type 0 devices for now. 2933 */ 2934 for (i = 0; acpi_dev && i < numdevs; i++) { 2935 child = devlist[i]; 2936 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2937 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 2938 dstate = PCI_POWERSTATE_D3; 2939 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 2940 pci_set_powerstate(child, dstate); 2941 } 2942 } 2943 free(devlist, M_TEMP); 2944 return (0); 2945 } 2946 2947 int 2948 pci_resume(device_t dev) 2949 { 2950 int i, numdevs, error; 2951 device_t acpi_dev, child, *devlist; 2952 struct pci_devinfo *dinfo; 2953 2954 /* 2955 * Set each child to D0 and restore its PCI configuration space. 2956 */ 2957 acpi_dev = NULL; 2958 if (pci_do_power_resume) 2959 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2960 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 2961 return (error); 2962 for (i = 0; i < numdevs; i++) { 2963 /* 2964 * Notify ACPI we're going to D0 but ignore the result. If 2965 * ACPI is not present, the firmware is responsible for 2966 * managing device power. Only manage type 0 devices for now. 2967 */ 2968 child = devlist[i]; 2969 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2970 if (acpi_dev && device_is_attached(child) && 2971 dinfo->cfg.hdrtype == 0) { 2972 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 2973 pci_set_powerstate(child, PCI_POWERSTATE_D0); 2974 } 2975 2976 /* Now the device is powered up, restore its config space. */ 2977 pci_cfg_restore(child, dinfo); 2978 } 2979 free(devlist, M_TEMP); 2980 return (bus_generic_resume(dev)); 2981 } 2982 2983 static void 2984 pci_load_vendor_data(void) 2985 { 2986 caddr_t vendordata, info; 2987 2988 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 2989 info = preload_search_info(vendordata, MODINFO_ADDR); 2990 pci_vendordata = *(char **)info; 2991 info = preload_search_info(vendordata, MODINFO_SIZE); 2992 pci_vendordata_size = *(size_t *)info; 2993 /* terminate the database */ 2994 pci_vendordata[pci_vendordata_size] = '\n'; 2995 } 2996 } 2997 2998 void 2999 pci_driver_added(device_t dev, driver_t *driver) 3000 { 3001 int numdevs; 3002 device_t *devlist; 3003 device_t child; 3004 struct pci_devinfo *dinfo; 3005 int i; 3006 3007 if (bootverbose) 3008 device_printf(dev, "driver added\n"); 3009 DEVICE_IDENTIFY(driver, dev); 3010 if (device_get_children(dev, &devlist, &numdevs) != 0) 3011 return; 3012 for (i = 0; i < numdevs; i++) { 3013 child = devlist[i]; 3014 if (device_get_state(child) != DS_NOTPRESENT) 3015 continue; 3016 dinfo = device_get_ivars(child); 3017 pci_print_verbose(dinfo); 3018 if (bootverbose) 3019 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 3020 pci_cfg_restore(child, dinfo); 3021 if (device_probe_and_attach(child) != 0) 3022 pci_cfg_save(child, dinfo, 1); 3023 } 3024 free(devlist, M_TEMP); 3025 } 3026 3027 int 3028 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 3029 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 3030 { 3031 struct pci_devinfo *dinfo; 3032 struct msix_table_entry *mte; 3033 struct msix_vector *mv; 3034 uint64_t addr; 3035 uint32_t data; 3036 void *cookie; 3037 int error, rid; 3038 3039 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 3040 arg, &cookie); 3041 if (error) 3042 return (error); 3043 3044 /* If this is not a direct child, just bail out. */ 3045 if (device_get_parent(child) != dev) { 3046 *cookiep = cookie; 3047 return(0); 3048 } 3049 3050 rid = rman_get_rid(irq); 3051 if (rid == 0) { 3052 /* Make sure that INTx is enabled */ 3053 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 3054 } else { 3055 /* 3056 * Check to see if the interrupt is MSI or MSI-X. 3057 * Ask our parent to map the MSI and give 3058 * us the address and data register values. 3059 * If we fail for some reason, teardown the 3060 * interrupt handler. 3061 */ 3062 dinfo = device_get_ivars(child); 3063 if (dinfo->cfg.msi.msi_alloc > 0) { 3064 if (dinfo->cfg.msi.msi_addr == 0) { 3065 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 3066 ("MSI has handlers, but vectors not mapped")); 3067 error = PCIB_MAP_MSI(device_get_parent(dev), 3068 child, rman_get_start(irq), &addr, &data); 3069 if (error) 3070 goto bad; 3071 dinfo->cfg.msi.msi_addr = addr; 3072 dinfo->cfg.msi.msi_data = data; 3073 } 3074 if (dinfo->cfg.msi.msi_handlers == 0) 3075 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 3076 dinfo->cfg.msi.msi_data); 3077 dinfo->cfg.msi.msi_handlers++; 3078 } else { 3079 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3080 ("No MSI or MSI-X interrupts allocated")); 3081 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3082 ("MSI-X index too high")); 3083 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3084 KASSERT(mte->mte_vector != 0, ("no message vector")); 3085 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 3086 KASSERT(mv->mv_irq == rman_get_start(irq), 3087 ("IRQ mismatch")); 3088 if (mv->mv_address == 0) { 3089 KASSERT(mte->mte_handlers == 0, 3090 ("MSI-X table entry has handlers, but vector not mapped")); 3091 error = PCIB_MAP_MSI(device_get_parent(dev), 3092 child, rman_get_start(irq), &addr, &data); 3093 if (error) 3094 goto bad; 3095 mv->mv_address = addr; 3096 mv->mv_data = data; 3097 } 3098 if (mte->mte_handlers == 0) { 3099 pci_enable_msix(child, rid - 1, mv->mv_address, 3100 mv->mv_data); 3101 pci_unmask_msix(child, rid - 1); 3102 } 3103 mte->mte_handlers++; 3104 } 3105 3106 /* Make sure that INTx is disabled if we are using MSI/MSIX */ 3107 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3108 bad: 3109 if (error) { 3110 (void)bus_generic_teardown_intr(dev, child, irq, 3111 cookie); 3112 return (error); 3113 } 3114 } 3115 *cookiep = cookie; 3116 return (0); 3117 } 3118 3119 int 3120 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 3121 void *cookie) 3122 { 3123 struct msix_table_entry *mte; 3124 struct resource_list_entry *rle; 3125 struct pci_devinfo *dinfo; 3126 int error, rid; 3127 3128 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 3129 return (EINVAL); 3130 3131 /* If this isn't a direct child, just bail out */ 3132 if (device_get_parent(child) != dev) 3133 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 3134 3135 rid = rman_get_rid(irq); 3136 if (rid == 0) { 3137 /* Mask INTx */ 3138 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3139 } else { 3140 /* 3141 * Check to see if the interrupt is MSI or MSI-X. If so, 3142 * decrement the appropriate handlers count and mask the 3143 * MSI-X message, or disable MSI messages if the count 3144 * drops to 0. 3145 */ 3146 dinfo = device_get_ivars(child); 3147 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 3148 if (rle->res != irq) 3149 return (EINVAL); 3150 if (dinfo->cfg.msi.msi_alloc > 0) { 3151 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 3152 ("MSI-X index too high")); 3153 if (dinfo->cfg.msi.msi_handlers == 0) 3154 return (EINVAL); 3155 dinfo->cfg.msi.msi_handlers--; 3156 if (dinfo->cfg.msi.msi_handlers == 0) 3157 pci_disable_msi(child); 3158 } else { 3159 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3160 ("No MSI or MSI-X interrupts allocated")); 3161 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3162 ("MSI-X index too high")); 3163 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3164 if (mte->mte_handlers == 0) 3165 return (EINVAL); 3166 mte->mte_handlers--; 3167 if (mte->mte_handlers == 0) 3168 pci_mask_msix(child, rid - 1); 3169 } 3170 } 3171 error = bus_generic_teardown_intr(dev, child, irq, cookie); 3172 if (rid > 0) 3173 KASSERT(error == 0, 3174 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 3175 return (error); 3176 } 3177 3178 int 3179 pci_print_child(device_t dev, device_t child) 3180 { 3181 struct pci_devinfo *dinfo; 3182 struct resource_list *rl; 3183 int retval = 0; 3184 3185 dinfo = device_get_ivars(child); 3186 rl = &dinfo->resources; 3187 3188 retval += bus_print_child_header(dev, child); 3189 3190 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 3191 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 3192 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 3193 if (device_get_flags(dev)) 3194 retval += printf(" flags %#x", device_get_flags(dev)); 3195 3196 retval += printf(" at device %d.%d", pci_get_slot(child), 3197 pci_get_function(child)); 3198 3199 retval += bus_print_child_footer(dev, child); 3200 3201 return (retval); 3202 } 3203 3204 static struct 3205 { 3206 int class; 3207 int subclass; 3208 char *desc; 3209 } pci_nomatch_tab[] = { 3210 {PCIC_OLD, -1, "old"}, 3211 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 3212 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 3213 {PCIC_STORAGE, -1, "mass storage"}, 3214 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 3215 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 3216 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 3217 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 3218 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 3219 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"}, 3220 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"}, 3221 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"}, 3222 {PCIC_NETWORK, -1, "network"}, 3223 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 3224 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 3225 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 3226 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 3227 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 3228 {PCIC_DISPLAY, -1, "display"}, 3229 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 3230 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 3231 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 3232 {PCIC_MULTIMEDIA, -1, "multimedia"}, 3233 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 3234 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 3235 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 3236 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"}, 3237 {PCIC_MEMORY, -1, "memory"}, 3238 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 3239 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 3240 {PCIC_BRIDGE, -1, "bridge"}, 3241 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 3242 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 3243 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 3244 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 3245 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 3246 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 3247 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 3248 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 3249 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 3250 {PCIC_SIMPLECOMM, -1, "simple comms"}, 3251 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 3252 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 3253 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 3254 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 3255 {PCIC_BASEPERIPH, -1, "base peripheral"}, 3256 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 3257 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 3258 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 3259 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 3260 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 3261 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"}, 3262 {PCIC_INPUTDEV, -1, "input device"}, 3263 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 3264 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 3265 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 3266 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 3267 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 3268 {PCIC_DOCKING, -1, "docking station"}, 3269 {PCIC_PROCESSOR, -1, "processor"}, 3270 {PCIC_SERIALBUS, -1, "serial bus"}, 3271 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 3272 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 3273 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 3274 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 3275 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 3276 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 3277 {PCIC_WIRELESS, -1, "wireless controller"}, 3278 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 3279 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 3280 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 3281 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 3282 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 3283 {PCIC_SATCOM, -1, "satellite communication"}, 3284 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 3285 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 3286 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 3287 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 3288 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 3289 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 3290 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 3291 {PCIC_DASP, -1, "dasp"}, 3292 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 3293 {0, 0, NULL} 3294 }; 3295 3296 void 3297 pci_probe_nomatch(device_t dev, device_t child) 3298 { 3299 int i; 3300 char *cp, *scp, *device; 3301 3302 /* 3303 * Look for a listing for this device in a loaded device database. 3304 */ 3305 if ((device = pci_describe_device(child)) != NULL) { 3306 device_printf(dev, "<%s>", device); 3307 free(device, M_DEVBUF); 3308 } else { 3309 /* 3310 * Scan the class/subclass descriptions for a general 3311 * description. 3312 */ 3313 cp = "unknown"; 3314 scp = NULL; 3315 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 3316 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 3317 if (pci_nomatch_tab[i].subclass == -1) { 3318 cp = pci_nomatch_tab[i].desc; 3319 } else if (pci_nomatch_tab[i].subclass == 3320 pci_get_subclass(child)) { 3321 scp = pci_nomatch_tab[i].desc; 3322 } 3323 } 3324 } 3325 device_printf(dev, "<%s%s%s>", 3326 cp ? cp : "", 3327 ((cp != NULL) && (scp != NULL)) ? ", " : "", 3328 scp ? scp : ""); 3329 } 3330 printf(" at device %d.%d (no driver attached)\n", 3331 pci_get_slot(child), pci_get_function(child)); 3332 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1); 3333 return; 3334 } 3335 3336 /* 3337 * Parse the PCI device database, if loaded, and return a pointer to a 3338 * description of the device. 3339 * 3340 * The database is flat text formatted as follows: 3341 * 3342 * Any line not in a valid format is ignored. 3343 * Lines are terminated with newline '\n' characters. 3344 * 3345 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 3346 * the vendor name. 3347 * 3348 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 3349 * - devices cannot be listed without a corresponding VENDOR line. 3350 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 3351 * another TAB, then the device name. 3352 */ 3353 3354 /* 3355 * Assuming (ptr) points to the beginning of a line in the database, 3356 * return the vendor or device and description of the next entry. 3357 * The value of (vendor) or (device) inappropriate for the entry type 3358 * is set to -1. Returns nonzero at the end of the database. 3359 * 3360 * Note that this is slightly unrobust in the face of corrupt data; 3361 * we attempt to safeguard against this by spamming the end of the 3362 * database with a newline when we initialise. 3363 */ 3364 static int 3365 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 3366 { 3367 char *cp = *ptr; 3368 int left; 3369 3370 *device = -1; 3371 *vendor = -1; 3372 **desc = '\0'; 3373 for (;;) { 3374 left = pci_vendordata_size - (cp - pci_vendordata); 3375 if (left <= 0) { 3376 *ptr = cp; 3377 return(1); 3378 } 3379 3380 /* vendor entry? */ 3381 if (*cp != '\t' && 3382 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 3383 break; 3384 /* device entry? */ 3385 if (*cp == '\t' && 3386 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 3387 break; 3388 3389 /* skip to next line */ 3390 while (*cp != '\n' && left > 0) { 3391 cp++; 3392 left--; 3393 } 3394 if (*cp == '\n') { 3395 cp++; 3396 left--; 3397 } 3398 } 3399 /* skip to next line */ 3400 while (*cp != '\n' && left > 0) { 3401 cp++; 3402 left--; 3403 } 3404 if (*cp == '\n' && left > 0) 3405 cp++; 3406 *ptr = cp; 3407 return(0); 3408 } 3409 3410 static char * 3411 pci_describe_device(device_t dev) 3412 { 3413 int vendor, device; 3414 char *desc, *vp, *dp, *line; 3415 3416 desc = vp = dp = NULL; 3417 3418 /* 3419 * If we have no vendor data, we can't do anything. 3420 */ 3421 if (pci_vendordata == NULL) 3422 goto out; 3423 3424 /* 3425 * Scan the vendor data looking for this device 3426 */ 3427 line = pci_vendordata; 3428 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 3429 goto out; 3430 for (;;) { 3431 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 3432 goto out; 3433 if (vendor == pci_get_vendor(dev)) 3434 break; 3435 } 3436 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 3437 goto out; 3438 for (;;) { 3439 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 3440 *dp = 0; 3441 break; 3442 } 3443 if (vendor != -1) { 3444 *dp = 0; 3445 break; 3446 } 3447 if (device == pci_get_device(dev)) 3448 break; 3449 } 3450 if (dp[0] == '\0') 3451 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 3452 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 3453 NULL) 3454 sprintf(desc, "%s, %s", vp, dp); 3455 out: 3456 if (vp != NULL) 3457 free(vp, M_DEVBUF); 3458 if (dp != NULL) 3459 free(dp, M_DEVBUF); 3460 return(desc); 3461 } 3462 3463 int 3464 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 3465 { 3466 struct pci_devinfo *dinfo; 3467 pcicfgregs *cfg; 3468 3469 dinfo = device_get_ivars(child); 3470 cfg = &dinfo->cfg; 3471 3472 switch (which) { 3473 case PCI_IVAR_ETHADDR: 3474 /* 3475 * The generic accessor doesn't deal with failure, so 3476 * we set the return value, then return an error. 3477 */ 3478 *((uint8_t **) result) = NULL; 3479 return (EINVAL); 3480 case PCI_IVAR_SUBVENDOR: 3481 *result = cfg->subvendor; 3482 break; 3483 case PCI_IVAR_SUBDEVICE: 3484 *result = cfg->subdevice; 3485 break; 3486 case PCI_IVAR_VENDOR: 3487 *result = cfg->vendor; 3488 break; 3489 case PCI_IVAR_DEVICE: 3490 *result = cfg->device; 3491 break; 3492 case PCI_IVAR_DEVID: 3493 *result = (cfg->device << 16) | cfg->vendor; 3494 break; 3495 case PCI_IVAR_CLASS: 3496 *result = cfg->baseclass; 3497 break; 3498 case PCI_IVAR_SUBCLASS: 3499 *result = cfg->subclass; 3500 break; 3501 case PCI_IVAR_PROGIF: 3502 *result = cfg->progif; 3503 break; 3504 case PCI_IVAR_REVID: 3505 *result = cfg->revid; 3506 break; 3507 case PCI_IVAR_INTPIN: 3508 *result = cfg->intpin; 3509 break; 3510 case PCI_IVAR_IRQ: 3511 *result = cfg->intline; 3512 break; 3513 case PCI_IVAR_DOMAIN: 3514 *result = cfg->domain; 3515 break; 3516 case PCI_IVAR_BUS: 3517 *result = cfg->bus; 3518 break; 3519 case PCI_IVAR_SLOT: 3520 *result = cfg->slot; 3521 break; 3522 case PCI_IVAR_FUNCTION: 3523 *result = cfg->func; 3524 break; 3525 case PCI_IVAR_CMDREG: 3526 *result = cfg->cmdreg; 3527 break; 3528 case PCI_IVAR_CACHELNSZ: 3529 *result = cfg->cachelnsz; 3530 break; 3531 case PCI_IVAR_MINGNT: 3532 *result = cfg->mingnt; 3533 break; 3534 case PCI_IVAR_MAXLAT: 3535 *result = cfg->maxlat; 3536 break; 3537 case PCI_IVAR_LATTIMER: 3538 *result = cfg->lattimer; 3539 break; 3540 default: 3541 return (ENOENT); 3542 } 3543 return (0); 3544 } 3545 3546 int 3547 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 3548 { 3549 struct pci_devinfo *dinfo; 3550 3551 dinfo = device_get_ivars(child); 3552 3553 switch (which) { 3554 case PCI_IVAR_INTPIN: 3555 dinfo->cfg.intpin = value; 3556 return (0); 3557 case PCI_IVAR_ETHADDR: 3558 case PCI_IVAR_SUBVENDOR: 3559 case PCI_IVAR_SUBDEVICE: 3560 case PCI_IVAR_VENDOR: 3561 case PCI_IVAR_DEVICE: 3562 case PCI_IVAR_DEVID: 3563 case PCI_IVAR_CLASS: 3564 case PCI_IVAR_SUBCLASS: 3565 case PCI_IVAR_PROGIF: 3566 case PCI_IVAR_REVID: 3567 case PCI_IVAR_IRQ: 3568 case PCI_IVAR_DOMAIN: 3569 case PCI_IVAR_BUS: 3570 case PCI_IVAR_SLOT: 3571 case PCI_IVAR_FUNCTION: 3572 return (EINVAL); /* disallow for now */ 3573 3574 default: 3575 return (ENOENT); 3576 } 3577 } 3578 3579 3580 #include "opt_ddb.h" 3581 #ifdef DDB 3582 #include <ddb/ddb.h> 3583 #include <sys/cons.h> 3584 3585 /* 3586 * List resources based on pci map registers, used for within ddb 3587 */ 3588 3589 DB_SHOW_COMMAND(pciregs, db_pci_dump) 3590 { 3591 struct pci_devinfo *dinfo; 3592 struct devlist *devlist_head; 3593 struct pci_conf *p; 3594 const char *name; 3595 int i, error, none_count; 3596 3597 none_count = 0; 3598 /* get the head of the device queue */ 3599 devlist_head = &pci_devq; 3600 3601 /* 3602 * Go through the list of devices and print out devices 3603 */ 3604 for (error = 0, i = 0, 3605 dinfo = STAILQ_FIRST(devlist_head); 3606 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 3607 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 3608 3609 /* Populate pd_name and pd_unit */ 3610 name = NULL; 3611 if (dinfo->cfg.dev) 3612 name = device_get_name(dinfo->cfg.dev); 3613 3614 p = &dinfo->conf; 3615 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 3616 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 3617 (name && *name) ? name : "none", 3618 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 3619 none_count++, 3620 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 3621 p->pc_sel.pc_func, (p->pc_class << 16) | 3622 (p->pc_subclass << 8) | p->pc_progif, 3623 (p->pc_subdevice << 16) | p->pc_subvendor, 3624 (p->pc_device << 16) | p->pc_vendor, 3625 p->pc_revid, p->pc_hdr); 3626 } 3627 } 3628 #endif /* DDB */ 3629 3630 static struct resource * 3631 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 3632 u_long start, u_long end, u_long count, u_int flags) 3633 { 3634 struct pci_devinfo *dinfo = device_get_ivars(child); 3635 struct resource_list *rl = &dinfo->resources; 3636 struct resource_list_entry *rle; 3637 struct resource *res; 3638 pci_addr_t map, testval; 3639 int mapsize; 3640 3641 /* 3642 * Weed out the bogons, and figure out how large the BAR/map 3643 * is. Bars that read back 0 here are bogus and unimplemented. 3644 * Note: atapci in legacy mode are special and handled elsewhere 3645 * in the code. If you have a atapci device in legacy mode and 3646 * it fails here, that other code is broken. 3647 */ 3648 res = NULL; 3649 pci_read_bar(child, *rid, &map, &testval); 3650 3651 /* Ignore a BAR with a base of 0. */ 3652 if (pci_mapbase(testval) == 0) 3653 goto out; 3654 3655 if (PCI_BAR_MEM(testval)) { 3656 if (type != SYS_RES_MEMORY) { 3657 if (bootverbose) 3658 device_printf(dev, 3659 "child %s requested type %d for rid %#x," 3660 " but the BAR says it is an memio\n", 3661 device_get_nameunit(child), type, *rid); 3662 goto out; 3663 } 3664 } else { 3665 if (type != SYS_RES_IOPORT) { 3666 if (bootverbose) 3667 device_printf(dev, 3668 "child %s requested type %d for rid %#x," 3669 " but the BAR says it is an ioport\n", 3670 device_get_nameunit(child), type, *rid); 3671 goto out; 3672 } 3673 } 3674 3675 /* 3676 * For real BARs, we need to override the size that 3677 * the driver requests, because that's what the BAR 3678 * actually uses and we would otherwise have a 3679 * situation where we might allocate the excess to 3680 * another driver, which won't work. 3681 */ 3682 mapsize = pci_mapsize(testval); 3683 count = 1UL << mapsize; 3684 if (RF_ALIGNMENT(flags) < mapsize) 3685 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 3686 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH)) 3687 flags |= RF_PREFETCHABLE; 3688 3689 /* 3690 * Allocate enough resource, and then write back the 3691 * appropriate bar for that resource. 3692 */ 3693 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 3694 start, end, count, flags & ~RF_ACTIVE); 3695 if (res == NULL) { 3696 device_printf(child, 3697 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 3698 count, *rid, type, start, end); 3699 goto out; 3700 } 3701 rman_set_device(res, dev); 3702 resource_list_add(rl, type, *rid, start, end, count); 3703 rle = resource_list_find(rl, type, *rid); 3704 if (rle == NULL) 3705 panic("pci_alloc_map: unexpectedly can't find resource."); 3706 rle->res = res; 3707 rle->start = rman_get_start(res); 3708 rle->end = rman_get_end(res); 3709 rle->count = count; 3710 if (bootverbose) 3711 device_printf(child, 3712 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 3713 count, *rid, type, rman_get_start(res)); 3714 map = rman_get_start(res); 3715 pci_write_bar(child, *rid, map); 3716 out:; 3717 return (res); 3718 } 3719 3720 3721 struct resource * 3722 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 3723 u_long start, u_long end, u_long count, u_int flags) 3724 { 3725 struct pci_devinfo *dinfo = device_get_ivars(child); 3726 struct resource_list *rl = &dinfo->resources; 3727 struct resource_list_entry *rle; 3728 struct resource *res; 3729 pcicfgregs *cfg = &dinfo->cfg; 3730 3731 if (device_get_parent(child) != dev) 3732 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 3733 type, rid, start, end, count, flags)); 3734 3735 /* 3736 * Perform lazy resource allocation 3737 */ 3738 switch (type) { 3739 case SYS_RES_IRQ: 3740 /* 3741 * Can't alloc legacy interrupt once MSI messages have 3742 * been allocated. 3743 */ 3744 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 3745 cfg->msix.msix_alloc > 0)) 3746 return (NULL); 3747 3748 /* 3749 * If the child device doesn't have an interrupt 3750 * routed and is deserving of an interrupt, try to 3751 * assign it one. 3752 */ 3753 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 3754 (cfg->intpin != 0)) 3755 pci_assign_interrupt(dev, child, 0); 3756 break; 3757 case SYS_RES_IOPORT: 3758 case SYS_RES_MEMORY: 3759 /* Allocate resources for this BAR if needed. */ 3760 rle = resource_list_find(rl, type, *rid); 3761 if (rle == NULL) { 3762 res = pci_alloc_map(dev, child, type, rid, start, end, 3763 count, flags); 3764 if (res == NULL) 3765 return (NULL); 3766 rle = resource_list_find(rl, type, *rid); 3767 } 3768 3769 /* 3770 * If the resource belongs to the bus, then give it to 3771 * the child. We need to activate it if requested 3772 * since the bus always allocates inactive resources. 3773 */ 3774 if (rle != NULL && rle->res != NULL && 3775 rman_get_device(rle->res) == dev) { 3776 if (bootverbose) 3777 device_printf(child, 3778 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 3779 rman_get_size(rle->res), *rid, type, 3780 rman_get_start(rle->res)); 3781 rman_set_device(rle->res, child); 3782 if ((flags & RF_ACTIVE) && 3783 bus_activate_resource(child, type, *rid, 3784 rle->res) != 0) 3785 return (NULL); 3786 return (rle->res); 3787 } 3788 } 3789 return (resource_list_alloc(rl, dev, child, type, rid, 3790 start, end, count, flags)); 3791 } 3792 3793 int 3794 pci_release_resource(device_t dev, device_t child, int type, int rid, 3795 struct resource *r) 3796 { 3797 int error; 3798 3799 if (device_get_parent(child) != dev) 3800 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 3801 type, rid, r)); 3802 3803 /* 3804 * For BARs we don't actually want to release the resource. 3805 * Instead, we deactivate the resource if needed and then give 3806 * ownership of the BAR back to the bus. 3807 */ 3808 switch (type) { 3809 case SYS_RES_IOPORT: 3810 case SYS_RES_MEMORY: 3811 if (rman_get_device(r) != child) 3812 return (EINVAL); 3813 if (rman_get_flags(r) & RF_ACTIVE) { 3814 error = bus_deactivate_resource(child, type, rid, r); 3815 if (error) 3816 return (error); 3817 } 3818 rman_set_device(r, dev); 3819 return (0); 3820 } 3821 return (bus_generic_rl_release_resource(dev, child, type, rid, r)); 3822 } 3823 3824 int 3825 pci_activate_resource(device_t dev, device_t child, int type, int rid, 3826 struct resource *r) 3827 { 3828 int error; 3829 3830 error = bus_generic_activate_resource(dev, child, type, rid, r); 3831 if (error) 3832 return (error); 3833 3834 /* Enable decoding in the command register when activating BARs. */ 3835 if (device_get_parent(child) == dev) { 3836 switch (type) { 3837 case SYS_RES_IOPORT: 3838 case SYS_RES_MEMORY: 3839 error = PCI_ENABLE_IO(dev, child, type); 3840 break; 3841 } 3842 } 3843 return (error); 3844 } 3845 3846 void 3847 pci_delete_resource(device_t dev, device_t child, int type, int rid) 3848 { 3849 struct pci_devinfo *dinfo; 3850 struct resource_list *rl; 3851 struct resource_list_entry *rle; 3852 3853 if (device_get_parent(child) != dev) 3854 return; 3855 3856 dinfo = device_get_ivars(child); 3857 rl = &dinfo->resources; 3858 rle = resource_list_find(rl, type, rid); 3859 if (rle == NULL) 3860 return; 3861 3862 if (rle->res) { 3863 if (rman_get_device(rle->res) != dev || 3864 rman_get_flags(rle->res) & RF_ACTIVE) { 3865 device_printf(dev, "delete_resource: " 3866 "Resource still owned by child, oops. " 3867 "(type=%d, rid=%d, addr=%lx)\n", 3868 rle->type, rle->rid, 3869 rman_get_start(rle->res)); 3870 return; 3871 } 3872 3873 #ifndef __PCI_BAR_ZERO_VALID 3874 /* 3875 * If this is a BAR, clear the BAR so it stops 3876 * decoding before releasing the resource. 3877 */ 3878 switch (type) { 3879 case SYS_RES_IOPORT: 3880 case SYS_RES_MEMORY: 3881 pci_write_bar(child, rid, 0); 3882 break; 3883 } 3884 #endif 3885 bus_release_resource(dev, type, rid, rle->res); 3886 } 3887 resource_list_delete(rl, type, rid); 3888 } 3889 3890 struct resource_list * 3891 pci_get_resource_list (device_t dev, device_t child) 3892 { 3893 struct pci_devinfo *dinfo = device_get_ivars(child); 3894 3895 return (&dinfo->resources); 3896 } 3897 3898 uint32_t 3899 pci_read_config_method(device_t dev, device_t child, int reg, int width) 3900 { 3901 struct pci_devinfo *dinfo = device_get_ivars(child); 3902 pcicfgregs *cfg = &dinfo->cfg; 3903 3904 return (PCIB_READ_CONFIG(device_get_parent(dev), 3905 cfg->bus, cfg->slot, cfg->func, reg, width)); 3906 } 3907 3908 void 3909 pci_write_config_method(device_t dev, device_t child, int reg, 3910 uint32_t val, int width) 3911 { 3912 struct pci_devinfo *dinfo = device_get_ivars(child); 3913 pcicfgregs *cfg = &dinfo->cfg; 3914 3915 PCIB_WRITE_CONFIG(device_get_parent(dev), 3916 cfg->bus, cfg->slot, cfg->func, reg, val, width); 3917 } 3918 3919 int 3920 pci_child_location_str_method(device_t dev, device_t child, char *buf, 3921 size_t buflen) 3922 { 3923 3924 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 3925 pci_get_function(child)); 3926 return (0); 3927 } 3928 3929 int 3930 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 3931 size_t buflen) 3932 { 3933 struct pci_devinfo *dinfo; 3934 pcicfgregs *cfg; 3935 3936 dinfo = device_get_ivars(child); 3937 cfg = &dinfo->cfg; 3938 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 3939 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 3940 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 3941 cfg->progif); 3942 return (0); 3943 } 3944 3945 int 3946 pci_assign_interrupt_method(device_t dev, device_t child) 3947 { 3948 struct pci_devinfo *dinfo = device_get_ivars(child); 3949 pcicfgregs *cfg = &dinfo->cfg; 3950 3951 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 3952 cfg->intpin)); 3953 } 3954 3955 static int 3956 pci_modevent(module_t mod, int what, void *arg) 3957 { 3958 static struct cdev *pci_cdev; 3959 3960 switch (what) { 3961 case MOD_LOAD: 3962 STAILQ_INIT(&pci_devq); 3963 pci_generation = 0; 3964 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 3965 "pci"); 3966 pci_load_vendor_data(); 3967 break; 3968 3969 case MOD_UNLOAD: 3970 destroy_dev(pci_cdev); 3971 break; 3972 } 3973 3974 return (0); 3975 } 3976 3977 void 3978 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 3979 { 3980 int i; 3981 3982 /* 3983 * Only do header type 0 devices. Type 1 devices are bridges, 3984 * which we know need special treatment. Type 2 devices are 3985 * cardbus bridges which also require special treatment. 3986 * Other types are unknown, and we err on the side of safety 3987 * by ignoring them. 3988 */ 3989 if (dinfo->cfg.hdrtype != 0) 3990 return; 3991 3992 /* 3993 * Restore the device to full power mode. We must do this 3994 * before we restore the registers because moving from D3 to 3995 * D0 will cause the chip's BARs and some other registers to 3996 * be reset to some unknown power on reset values. Cut down 3997 * the noise on boot by doing nothing if we are already in 3998 * state D0. 3999 */ 4000 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 4001 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 4002 } 4003 for (i = 0; i < dinfo->cfg.nummaps; i++) 4004 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 4005 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 4006 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 4007 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 4008 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 4009 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 4010 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 4011 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 4012 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 4013 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 4014 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 4015 4016 /* Restore MSI and MSI-X configurations if they are present. */ 4017 if (dinfo->cfg.msi.msi_location != 0) 4018 pci_resume_msi(dev); 4019 if (dinfo->cfg.msix.msix_location != 0) 4020 pci_resume_msix(dev); 4021 } 4022 4023 void 4024 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 4025 { 4026 int i; 4027 uint32_t cls; 4028 int ps; 4029 4030 /* 4031 * Only do header type 0 devices. Type 1 devices are bridges, which 4032 * we know need special treatment. Type 2 devices are cardbus bridges 4033 * which also require special treatment. Other types are unknown, and 4034 * we err on the side of safety by ignoring them. Powering down 4035 * bridges should not be undertaken lightly. 4036 */ 4037 if (dinfo->cfg.hdrtype != 0) 4038 return; 4039 for (i = 0; i < dinfo->cfg.nummaps; i++) 4040 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 4041 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 4042 4043 /* 4044 * Some drivers apparently write to these registers w/o updating our 4045 * cached copy. No harm happens if we update the copy, so do so here 4046 * so we can restore them. The COMMAND register is modified by the 4047 * bus w/o updating the cache. This should represent the normally 4048 * writable portion of the 'defined' part of type 0 headers. In 4049 * theory we also need to save/restore the PCI capability structures 4050 * we know about, but apart from power we don't know any that are 4051 * writable. 4052 */ 4053 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 4054 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4055 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 4056 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 4057 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 4058 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 4059 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 4060 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 4061 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 4062 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 4063 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 4064 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 4065 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 4066 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 4067 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 4068 4069 /* 4070 * don't set the state for display devices, base peripherals and 4071 * memory devices since bad things happen when they are powered down. 4072 * We should (a) have drivers that can easily detach and (b) use 4073 * generic drivers for these devices so that some device actually 4074 * attaches. We need to make sure that when we implement (a) we don't 4075 * power the device down on a reattach. 4076 */ 4077 cls = pci_get_class(dev); 4078 if (!setstate) 4079 return; 4080 switch (pci_do_power_nodriver) 4081 { 4082 case 0: /* NO powerdown at all */ 4083 return; 4084 case 1: /* Conservative about what to power down */ 4085 if (cls == PCIC_STORAGE) 4086 return; 4087 /*FALLTHROUGH*/ 4088 case 2: /* Agressive about what to power down */ 4089 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 4090 cls == PCIC_BASEPERIPH) 4091 return; 4092 /*FALLTHROUGH*/ 4093 case 3: /* Power down everything */ 4094 break; 4095 } 4096 /* 4097 * PCI spec says we can only go into D3 state from D0 state. 4098 * Transition from D[12] into D0 before going to D3 state. 4099 */ 4100 ps = pci_get_powerstate(dev); 4101 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 4102 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 4103 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 4104 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 4105 }
Cache object: fac914a23f2062a59c8a863d9caf961c
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]