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sys/dev/pci/pci.c
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1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD: releng/8.3/sys/dev/pci/pci.c 232093 2012-02-24 00:48:27Z marius $"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 #include <machine/stdarg.h> 55 56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 57 #include <machine/intr_machdep.h> 58 #endif 59 60 #include <sys/pciio.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pci_private.h> 64 65 #include <dev/usb/controller/ehcireg.h> 66 #include <dev/usb/controller/ohcireg.h> 67 #include <dev/usb/controller/uhcireg.h> 68 69 #include "pcib_if.h" 70 #include "pci_if.h" 71 72 #ifdef __HAVE_ACPI 73 #include <contrib/dev/acpica/include/acpi.h> 74 #include "acpi_if.h" 75 #else 76 #define ACPI_PWR_FOR_SLEEP(x, y, z) 77 #endif 78 79 static pci_addr_t pci_mapbase(uint64_t mapreg); 80 static const char *pci_maptype(uint64_t mapreg); 81 static int pci_mapsize(uint64_t testval); 82 static int pci_maprange(uint64_t mapreg); 83 static void pci_fixancient(pcicfgregs *cfg); 84 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 85 86 static int pci_porten(device_t dev); 87 static int pci_memen(device_t dev); 88 static void pci_assign_interrupt(device_t bus, device_t dev, 89 int force_route); 90 static int pci_add_map(device_t bus, device_t dev, int reg, 91 struct resource_list *rl, int force, int prefetch); 92 static int pci_probe(device_t dev); 93 static int pci_attach(device_t dev); 94 static void pci_load_vendor_data(void); 95 static int pci_describe_parse_line(char **ptr, int *vendor, 96 int *device, char **desc); 97 static char *pci_describe_device(device_t dev); 98 static int pci_modevent(module_t mod, int what, void *arg); 99 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 100 pcicfgregs *cfg); 101 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 102 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 103 int reg, uint32_t *data); 104 #if 0 105 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 106 int reg, uint32_t data); 107 #endif 108 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 109 static void pci_disable_msi(device_t dev); 110 static void pci_enable_msi(device_t dev, uint64_t address, 111 uint16_t data); 112 static void pci_enable_msix(device_t dev, u_int index, 113 uint64_t address, uint32_t data); 114 static void pci_mask_msix(device_t dev, u_int index); 115 static void pci_unmask_msix(device_t dev, u_int index); 116 static int pci_msi_blacklisted(void); 117 static void pci_resume_msi(device_t dev); 118 static void pci_resume_msix(device_t dev); 119 static int pci_remap_intr_method(device_t bus, device_t dev, 120 u_int irq); 121 122 static device_method_t pci_methods[] = { 123 /* Device interface */ 124 DEVMETHOD(device_probe, pci_probe), 125 DEVMETHOD(device_attach, pci_attach), 126 DEVMETHOD(device_detach, bus_generic_detach), 127 DEVMETHOD(device_shutdown, bus_generic_shutdown), 128 DEVMETHOD(device_suspend, pci_suspend), 129 DEVMETHOD(device_resume, pci_resume), 130 131 /* Bus interface */ 132 DEVMETHOD(bus_print_child, pci_print_child), 133 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 134 DEVMETHOD(bus_read_ivar, pci_read_ivar), 135 DEVMETHOD(bus_write_ivar, pci_write_ivar), 136 DEVMETHOD(bus_driver_added, pci_driver_added), 137 DEVMETHOD(bus_setup_intr, pci_setup_intr), 138 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 139 140 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 141 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 142 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 143 DEVMETHOD(bus_delete_resource, pci_delete_resource), 144 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 145 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 146 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 147 DEVMETHOD(bus_activate_resource, pci_activate_resource), 148 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 149 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 150 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 151 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 152 153 /* PCI interface */ 154 DEVMETHOD(pci_read_config, pci_read_config_method), 155 DEVMETHOD(pci_write_config, pci_write_config_method), 156 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 157 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 158 DEVMETHOD(pci_enable_io, pci_enable_io_method), 159 DEVMETHOD(pci_disable_io, pci_disable_io_method), 160 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 161 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 162 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 163 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 164 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 165 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 166 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 167 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 168 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 169 DEVMETHOD(pci_release_msi, pci_release_msi_method), 170 DEVMETHOD(pci_msi_count, pci_msi_count_method), 171 DEVMETHOD(pci_msix_count, pci_msix_count_method), 172 173 DEVMETHOD_END 174 }; 175 176 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 177 178 static devclass_t pci_devclass; 179 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 180 MODULE_VERSION(pci, 1); 181 182 static char *pci_vendordata; 183 static size_t pci_vendordata_size; 184 185 struct pci_quirk { 186 uint32_t devid; /* Vendor/device of the card */ 187 int type; 188 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 189 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */ 190 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 191 int arg1; 192 int arg2; 193 }; 194 195 static const struct pci_quirk const pci_quirks[] = { 196 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 197 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 198 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 199 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 200 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 201 202 /* 203 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 204 * or the CMIC-SL (AKA ServerWorks GC_LE). 205 */ 206 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 207 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 208 209 /* 210 * MSI doesn't work on earlier Intel chipsets including 211 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 212 */ 213 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 214 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 215 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 216 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 217 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 218 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 219 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 220 221 /* 222 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 223 * bridge. 224 */ 225 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 226 227 /* 228 * MSI-X doesn't work with at least LSI SAS1068E passed through by 229 * VMware. 230 */ 231 { 0x079015ad, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 232 233 /* 234 * Some virtualization environments emulate an older chipset 235 * but support MSI just fine. QEMU uses the Intel 82440. 236 */ 237 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 238 239 { 0 } 240 }; 241 242 /* map register information */ 243 #define PCI_MAPMEM 0x01 /* memory map */ 244 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 245 #define PCI_MAPPORT 0x04 /* port map */ 246 247 struct devlist pci_devq; 248 uint32_t pci_generation; 249 uint32_t pci_numdevs = 0; 250 static int pcie_chipset, pcix_chipset; 251 252 /* sysctl vars */ 253 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 254 255 static int pci_enable_io_modes = 1; 256 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 257 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 258 &pci_enable_io_modes, 1, 259 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 260 enable these bits correctly. We'd like to do this all the time, but there\n\ 261 are some peripherals that this causes problems with."); 262 263 static int pci_do_power_nodriver = 0; 264 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 265 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 266 &pci_do_power_nodriver, 0, 267 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 268 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 269 agressively place devices into D3 state. 3 means put absolutely everything\n\ 270 in D3 state."); 271 272 static int pci_do_power_resume = 1; 273 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 274 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 275 &pci_do_power_resume, 1, 276 "Transition from D3 -> D0 on resume."); 277 278 static int pci_do_msi = 1; 279 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 280 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 281 "Enable support for MSI interrupts"); 282 283 static int pci_do_msix = 1; 284 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 285 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 286 "Enable support for MSI-X interrupts"); 287 288 static int pci_honor_msi_blacklist = 1; 289 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist); 290 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD, 291 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI"); 292 293 #if defined(__i386__) || defined(__amd64__) 294 static int pci_usb_takeover = 1; 295 #else 296 static int pci_usb_takeover = 0; 297 #endif 298 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover); 299 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RD | CTLFLAG_TUN, 300 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\ 301 Disable this if you depend on BIOS emulation of USB devices, that is\n\ 302 you use USB devices (like keyboard or mouse) but do not load USB drivers"); 303 304 /* Find a device_t by bus/slot/function in domain 0 */ 305 306 device_t 307 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 308 { 309 310 return (pci_find_dbsf(0, bus, slot, func)); 311 } 312 313 /* Find a device_t by domain/bus/slot/function */ 314 315 device_t 316 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 317 { 318 struct pci_devinfo *dinfo; 319 320 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 321 if ((dinfo->cfg.domain == domain) && 322 (dinfo->cfg.bus == bus) && 323 (dinfo->cfg.slot == slot) && 324 (dinfo->cfg.func == func)) { 325 return (dinfo->cfg.dev); 326 } 327 } 328 329 return (NULL); 330 } 331 332 /* Find a device_t by vendor/device ID */ 333 334 device_t 335 pci_find_device(uint16_t vendor, uint16_t device) 336 { 337 struct pci_devinfo *dinfo; 338 339 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 340 if ((dinfo->cfg.vendor == vendor) && 341 (dinfo->cfg.device == device)) { 342 return (dinfo->cfg.dev); 343 } 344 } 345 346 return (NULL); 347 } 348 349 device_t 350 pci_find_class(uint8_t class, uint8_t subclass) 351 { 352 struct pci_devinfo *dinfo; 353 354 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 355 if (dinfo->cfg.baseclass == class && 356 dinfo->cfg.subclass == subclass) { 357 return (dinfo->cfg.dev); 358 } 359 } 360 361 return (NULL); 362 } 363 364 static int 365 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 366 { 367 va_list ap; 368 int retval; 369 370 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 371 cfg->func); 372 va_start(ap, fmt); 373 retval += vprintf(fmt, ap); 374 va_end(ap); 375 return (retval); 376 } 377 378 /* return base address of memory or port map */ 379 380 static pci_addr_t 381 pci_mapbase(uint64_t mapreg) 382 { 383 384 if (PCI_BAR_MEM(mapreg)) 385 return (mapreg & PCIM_BAR_MEM_BASE); 386 else 387 return (mapreg & PCIM_BAR_IO_BASE); 388 } 389 390 /* return map type of memory or port map */ 391 392 static const char * 393 pci_maptype(uint64_t mapreg) 394 { 395 396 if (PCI_BAR_IO(mapreg)) 397 return ("I/O Port"); 398 if (mapreg & PCIM_BAR_MEM_PREFETCH) 399 return ("Prefetchable Memory"); 400 return ("Memory"); 401 } 402 403 /* return log2 of map size decoded for memory or port map */ 404 405 static int 406 pci_mapsize(uint64_t testval) 407 { 408 int ln2size; 409 410 testval = pci_mapbase(testval); 411 ln2size = 0; 412 if (testval != 0) { 413 while ((testval & 1) == 0) 414 { 415 ln2size++; 416 testval >>= 1; 417 } 418 } 419 return (ln2size); 420 } 421 422 /* return log2 of address range supported by map register */ 423 424 static int 425 pci_maprange(uint64_t mapreg) 426 { 427 int ln2range = 0; 428 429 if (PCI_BAR_IO(mapreg)) 430 ln2range = 32; 431 else 432 switch (mapreg & PCIM_BAR_MEM_TYPE) { 433 case PCIM_BAR_MEM_32: 434 ln2range = 32; 435 break; 436 case PCIM_BAR_MEM_1MB: 437 ln2range = 20; 438 break; 439 case PCIM_BAR_MEM_64: 440 ln2range = 64; 441 break; 442 } 443 return (ln2range); 444 } 445 446 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 447 448 static void 449 pci_fixancient(pcicfgregs *cfg) 450 { 451 if (cfg->hdrtype != 0) 452 return; 453 454 /* PCI to PCI bridges use header type 1 */ 455 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 456 cfg->hdrtype = 1; 457 } 458 459 /* extract header type specific config data */ 460 461 static void 462 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 463 { 464 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 465 switch (cfg->hdrtype) { 466 case 0: 467 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 468 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 469 cfg->nummaps = PCI_MAXMAPS_0; 470 break; 471 case 1: 472 cfg->nummaps = PCI_MAXMAPS_1; 473 break; 474 case 2: 475 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 476 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 477 cfg->nummaps = PCI_MAXMAPS_2; 478 break; 479 } 480 #undef REG 481 } 482 483 /* read configuration header into pcicfgregs structure */ 484 struct pci_devinfo * 485 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size) 486 { 487 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 488 pcicfgregs *cfg = NULL; 489 struct pci_devinfo *devlist_entry; 490 struct devlist *devlist_head; 491 492 devlist_head = &pci_devq; 493 494 devlist_entry = NULL; 495 496 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) { 497 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 498 if (devlist_entry == NULL) 499 return (NULL); 500 501 cfg = &devlist_entry->cfg; 502 503 cfg->domain = d; 504 cfg->bus = b; 505 cfg->slot = s; 506 cfg->func = f; 507 cfg->vendor = REG(PCIR_VENDOR, 2); 508 cfg->device = REG(PCIR_DEVICE, 2); 509 cfg->cmdreg = REG(PCIR_COMMAND, 2); 510 cfg->statreg = REG(PCIR_STATUS, 2); 511 cfg->baseclass = REG(PCIR_CLASS, 1); 512 cfg->subclass = REG(PCIR_SUBCLASS, 1); 513 cfg->progif = REG(PCIR_PROGIF, 1); 514 cfg->revid = REG(PCIR_REVID, 1); 515 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 516 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 517 cfg->lattimer = REG(PCIR_LATTIMER, 1); 518 cfg->intpin = REG(PCIR_INTPIN, 1); 519 cfg->intline = REG(PCIR_INTLINE, 1); 520 521 cfg->mingnt = REG(PCIR_MINGNT, 1); 522 cfg->maxlat = REG(PCIR_MAXLAT, 1); 523 524 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 525 cfg->hdrtype &= ~PCIM_MFDEV; 526 527 pci_fixancient(cfg); 528 pci_hdrtypedata(pcib, b, s, f, cfg); 529 530 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 531 pci_read_cap(pcib, cfg); 532 533 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 534 535 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 536 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 537 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 538 devlist_entry->conf.pc_sel.pc_func = cfg->func; 539 devlist_entry->conf.pc_hdr = cfg->hdrtype; 540 541 devlist_entry->conf.pc_subvendor = cfg->subvendor; 542 devlist_entry->conf.pc_subdevice = cfg->subdevice; 543 devlist_entry->conf.pc_vendor = cfg->vendor; 544 devlist_entry->conf.pc_device = cfg->device; 545 546 devlist_entry->conf.pc_class = cfg->baseclass; 547 devlist_entry->conf.pc_subclass = cfg->subclass; 548 devlist_entry->conf.pc_progif = cfg->progif; 549 devlist_entry->conf.pc_revid = cfg->revid; 550 551 pci_numdevs++; 552 pci_generation++; 553 } 554 return (devlist_entry); 555 #undef REG 556 } 557 558 static void 559 pci_read_cap(device_t pcib, pcicfgregs *cfg) 560 { 561 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 562 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 563 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 564 uint64_t addr; 565 #endif 566 uint32_t val; 567 int ptr, nextptr, ptrptr; 568 569 switch (cfg->hdrtype & PCIM_HDRTYPE) { 570 case 0: 571 case 1: 572 ptrptr = PCIR_CAP_PTR; 573 break; 574 case 2: 575 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 576 break; 577 default: 578 return; /* no extended capabilities support */ 579 } 580 nextptr = REG(ptrptr, 1); /* sanity check? */ 581 582 /* 583 * Read capability entries. 584 */ 585 while (nextptr != 0) { 586 /* Sanity check */ 587 if (nextptr > 255) { 588 printf("illegal PCI extended capability offset %d\n", 589 nextptr); 590 return; 591 } 592 /* Find the next entry */ 593 ptr = nextptr; 594 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 595 596 /* Process this entry */ 597 switch (REG(ptr + PCICAP_ID, 1)) { 598 case PCIY_PMG: /* PCI power management */ 599 if (cfg->pp.pp_cap == 0) { 600 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 601 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 602 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 603 if ((nextptr - ptr) > PCIR_POWER_DATA) 604 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 605 } 606 break; 607 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 608 case PCIY_HT: /* HyperTransport */ 609 /* Determine HT-specific capability type. */ 610 val = REG(ptr + PCIR_HT_COMMAND, 2); 611 switch (val & PCIM_HTCMD_CAP_MASK) { 612 case PCIM_HTCAP_MSI_MAPPING: 613 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 614 /* Sanity check the mapping window. */ 615 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 616 4); 617 addr <<= 32; 618 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 619 4); 620 if (addr != MSI_INTEL_ADDR_BASE) 621 device_printf(pcib, 622 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 623 cfg->domain, cfg->bus, 624 cfg->slot, cfg->func, 625 (long long)addr); 626 } else 627 addr = MSI_INTEL_ADDR_BASE; 628 629 cfg->ht.ht_msimap = ptr; 630 cfg->ht.ht_msictrl = val; 631 cfg->ht.ht_msiaddr = addr; 632 break; 633 } 634 break; 635 #endif 636 case PCIY_MSI: /* PCI MSI */ 637 cfg->msi.msi_location = ptr; 638 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 639 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 640 PCIM_MSICTRL_MMC_MASK)>>1); 641 break; 642 case PCIY_MSIX: /* PCI MSI-X */ 643 cfg->msix.msix_location = ptr; 644 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 645 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 646 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 647 val = REG(ptr + PCIR_MSIX_TABLE, 4); 648 cfg->msix.msix_table_bar = PCIR_BAR(val & 649 PCIM_MSIX_BIR_MASK); 650 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 651 val = REG(ptr + PCIR_MSIX_PBA, 4); 652 cfg->msix.msix_pba_bar = PCIR_BAR(val & 653 PCIM_MSIX_BIR_MASK); 654 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 655 break; 656 case PCIY_VPD: /* PCI Vital Product Data */ 657 cfg->vpd.vpd_reg = ptr; 658 break; 659 case PCIY_SUBVENDOR: 660 /* Should always be true. */ 661 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) { 662 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 663 cfg->subvendor = val & 0xffff; 664 cfg->subdevice = val >> 16; 665 } 666 break; 667 case PCIY_PCIX: /* PCI-X */ 668 /* 669 * Assume we have a PCI-X chipset if we have 670 * at least one PCI-PCI bridge with a PCI-X 671 * capability. Note that some systems with 672 * PCI-express or HT chipsets might match on 673 * this check as well. 674 */ 675 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) 676 pcix_chipset = 1; 677 break; 678 case PCIY_EXPRESS: /* PCI-express */ 679 /* 680 * Assume we have a PCI-express chipset if we have 681 * at least one PCI-express device. 682 */ 683 pcie_chipset = 1; 684 break; 685 default: 686 break; 687 } 688 } 689 /* REG and WREG use carry through to next functions */ 690 } 691 692 /* 693 * PCI Vital Product Data 694 */ 695 696 #define PCI_VPD_TIMEOUT 1000000 697 698 static int 699 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 700 { 701 int count = PCI_VPD_TIMEOUT; 702 703 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 704 705 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 706 707 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 708 if (--count < 0) 709 return (ENXIO); 710 DELAY(1); /* limit looping */ 711 } 712 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 713 714 return (0); 715 } 716 717 #if 0 718 static int 719 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 720 { 721 int count = PCI_VPD_TIMEOUT; 722 723 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 724 725 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 726 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 727 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 728 if (--count < 0) 729 return (ENXIO); 730 DELAY(1); /* limit looping */ 731 } 732 733 return (0); 734 } 735 #endif 736 737 #undef PCI_VPD_TIMEOUT 738 739 struct vpd_readstate { 740 device_t pcib; 741 pcicfgregs *cfg; 742 uint32_t val; 743 int bytesinval; 744 int off; 745 uint8_t cksum; 746 }; 747 748 static int 749 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 750 { 751 uint32_t reg; 752 uint8_t byte; 753 754 if (vrs->bytesinval == 0) { 755 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 756 return (ENXIO); 757 vrs->val = le32toh(reg); 758 vrs->off += 4; 759 byte = vrs->val & 0xff; 760 vrs->bytesinval = 3; 761 } else { 762 vrs->val = vrs->val >> 8; 763 byte = vrs->val & 0xff; 764 vrs->bytesinval--; 765 } 766 767 vrs->cksum += byte; 768 *data = byte; 769 return (0); 770 } 771 772 static void 773 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 774 { 775 struct vpd_readstate vrs; 776 int state; 777 int name; 778 int remain; 779 int i; 780 int alloc, off; /* alloc/off for RO/W arrays */ 781 int cksumvalid; 782 int dflen; 783 uint8_t byte; 784 uint8_t byte2; 785 786 /* init vpd reader */ 787 vrs.bytesinval = 0; 788 vrs.off = 0; 789 vrs.pcib = pcib; 790 vrs.cfg = cfg; 791 vrs.cksum = 0; 792 793 state = 0; 794 name = remain = i = 0; /* shut up stupid gcc */ 795 alloc = off = 0; /* shut up stupid gcc */ 796 dflen = 0; /* shut up stupid gcc */ 797 cksumvalid = -1; 798 while (state >= 0) { 799 if (vpd_nextbyte(&vrs, &byte)) { 800 state = -2; 801 break; 802 } 803 #if 0 804 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 805 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 806 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 807 #endif 808 switch (state) { 809 case 0: /* item name */ 810 if (byte & 0x80) { 811 if (vpd_nextbyte(&vrs, &byte2)) { 812 state = -2; 813 break; 814 } 815 remain = byte2; 816 if (vpd_nextbyte(&vrs, &byte2)) { 817 state = -2; 818 break; 819 } 820 remain |= byte2 << 8; 821 if (remain > (0x7f*4 - vrs.off)) { 822 state = -1; 823 printf( 824 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n", 825 cfg->domain, cfg->bus, cfg->slot, 826 cfg->func, remain); 827 } 828 name = byte & 0x7f; 829 } else { 830 remain = byte & 0x7; 831 name = (byte >> 3) & 0xf; 832 } 833 switch (name) { 834 case 0x2: /* String */ 835 cfg->vpd.vpd_ident = malloc(remain + 1, 836 M_DEVBUF, M_WAITOK); 837 i = 0; 838 state = 1; 839 break; 840 case 0xf: /* End */ 841 state = -1; 842 break; 843 case 0x10: /* VPD-R */ 844 alloc = 8; 845 off = 0; 846 cfg->vpd.vpd_ros = malloc(alloc * 847 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 848 M_WAITOK | M_ZERO); 849 state = 2; 850 break; 851 case 0x11: /* VPD-W */ 852 alloc = 8; 853 off = 0; 854 cfg->vpd.vpd_w = malloc(alloc * 855 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 856 M_WAITOK | M_ZERO); 857 state = 5; 858 break; 859 default: /* Invalid data, abort */ 860 state = -1; 861 break; 862 } 863 break; 864 865 case 1: /* Identifier String */ 866 cfg->vpd.vpd_ident[i++] = byte; 867 remain--; 868 if (remain == 0) { 869 cfg->vpd.vpd_ident[i] = '\0'; 870 state = 0; 871 } 872 break; 873 874 case 2: /* VPD-R Keyword Header */ 875 if (off == alloc) { 876 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 877 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 878 M_DEVBUF, M_WAITOK | M_ZERO); 879 } 880 cfg->vpd.vpd_ros[off].keyword[0] = byte; 881 if (vpd_nextbyte(&vrs, &byte2)) { 882 state = -2; 883 break; 884 } 885 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 886 if (vpd_nextbyte(&vrs, &byte2)) { 887 state = -2; 888 break; 889 } 890 dflen = byte2; 891 if (dflen == 0 && 892 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 893 2) == 0) { 894 /* 895 * if this happens, we can't trust the rest 896 * of the VPD. 897 */ 898 printf( 899 "pci%d:%d:%d:%d: bad keyword length: %d\n", 900 cfg->domain, cfg->bus, cfg->slot, 901 cfg->func, dflen); 902 cksumvalid = 0; 903 state = -1; 904 break; 905 } else if (dflen == 0) { 906 cfg->vpd.vpd_ros[off].value = malloc(1 * 907 sizeof(*cfg->vpd.vpd_ros[off].value), 908 M_DEVBUF, M_WAITOK); 909 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 910 } else 911 cfg->vpd.vpd_ros[off].value = malloc( 912 (dflen + 1) * 913 sizeof(*cfg->vpd.vpd_ros[off].value), 914 M_DEVBUF, M_WAITOK); 915 remain -= 3; 916 i = 0; 917 /* keep in sync w/ state 3's transistions */ 918 if (dflen == 0 && remain == 0) 919 state = 0; 920 else if (dflen == 0) 921 state = 2; 922 else 923 state = 3; 924 break; 925 926 case 3: /* VPD-R Keyword Value */ 927 cfg->vpd.vpd_ros[off].value[i++] = byte; 928 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 929 "RV", 2) == 0 && cksumvalid == -1) { 930 if (vrs.cksum == 0) 931 cksumvalid = 1; 932 else { 933 if (bootverbose) 934 printf( 935 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n", 936 cfg->domain, cfg->bus, 937 cfg->slot, cfg->func, 938 vrs.cksum); 939 cksumvalid = 0; 940 state = -1; 941 break; 942 } 943 } 944 dflen--; 945 remain--; 946 /* keep in sync w/ state 2's transistions */ 947 if (dflen == 0) 948 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 949 if (dflen == 0 && remain == 0) { 950 cfg->vpd.vpd_rocnt = off; 951 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 952 off * sizeof(*cfg->vpd.vpd_ros), 953 M_DEVBUF, M_WAITOK | M_ZERO); 954 state = 0; 955 } else if (dflen == 0) 956 state = 2; 957 break; 958 959 case 4: 960 remain--; 961 if (remain == 0) 962 state = 0; 963 break; 964 965 case 5: /* VPD-W Keyword Header */ 966 if (off == alloc) { 967 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 968 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 969 M_DEVBUF, M_WAITOK | M_ZERO); 970 } 971 cfg->vpd.vpd_w[off].keyword[0] = byte; 972 if (vpd_nextbyte(&vrs, &byte2)) { 973 state = -2; 974 break; 975 } 976 cfg->vpd.vpd_w[off].keyword[1] = byte2; 977 if (vpd_nextbyte(&vrs, &byte2)) { 978 state = -2; 979 break; 980 } 981 cfg->vpd.vpd_w[off].len = dflen = byte2; 982 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 983 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 984 sizeof(*cfg->vpd.vpd_w[off].value), 985 M_DEVBUF, M_WAITOK); 986 remain -= 3; 987 i = 0; 988 /* keep in sync w/ state 6's transistions */ 989 if (dflen == 0 && remain == 0) 990 state = 0; 991 else if (dflen == 0) 992 state = 5; 993 else 994 state = 6; 995 break; 996 997 case 6: /* VPD-W Keyword Value */ 998 cfg->vpd.vpd_w[off].value[i++] = byte; 999 dflen--; 1000 remain--; 1001 /* keep in sync w/ state 5's transistions */ 1002 if (dflen == 0) 1003 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1004 if (dflen == 0 && remain == 0) { 1005 cfg->vpd.vpd_wcnt = off; 1006 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1007 off * sizeof(*cfg->vpd.vpd_w), 1008 M_DEVBUF, M_WAITOK | M_ZERO); 1009 state = 0; 1010 } else if (dflen == 0) 1011 state = 5; 1012 break; 1013 1014 default: 1015 printf("pci%d:%d:%d:%d: invalid state: %d\n", 1016 cfg->domain, cfg->bus, cfg->slot, cfg->func, 1017 state); 1018 state = -1; 1019 break; 1020 } 1021 } 1022 1023 if (cksumvalid == 0 || state < -1) { 1024 /* read-only data bad, clean up */ 1025 if (cfg->vpd.vpd_ros != NULL) { 1026 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1027 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1028 free(cfg->vpd.vpd_ros, M_DEVBUF); 1029 cfg->vpd.vpd_ros = NULL; 1030 } 1031 } 1032 if (state < -1) { 1033 /* I/O error, clean up */ 1034 printf("pci%d:%d:%d:%d: failed to read VPD data.\n", 1035 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1036 if (cfg->vpd.vpd_ident != NULL) { 1037 free(cfg->vpd.vpd_ident, M_DEVBUF); 1038 cfg->vpd.vpd_ident = NULL; 1039 } 1040 if (cfg->vpd.vpd_w != NULL) { 1041 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1042 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1043 free(cfg->vpd.vpd_w, M_DEVBUF); 1044 cfg->vpd.vpd_w = NULL; 1045 } 1046 } 1047 cfg->vpd.vpd_cached = 1; 1048 #undef REG 1049 #undef WREG 1050 } 1051 1052 int 1053 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1054 { 1055 struct pci_devinfo *dinfo = device_get_ivars(child); 1056 pcicfgregs *cfg = &dinfo->cfg; 1057 1058 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1059 pci_read_vpd(device_get_parent(dev), cfg); 1060 1061 *identptr = cfg->vpd.vpd_ident; 1062 1063 if (*identptr == NULL) 1064 return (ENXIO); 1065 1066 return (0); 1067 } 1068 1069 int 1070 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1071 const char **vptr) 1072 { 1073 struct pci_devinfo *dinfo = device_get_ivars(child); 1074 pcicfgregs *cfg = &dinfo->cfg; 1075 int i; 1076 1077 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1078 pci_read_vpd(device_get_parent(dev), cfg); 1079 1080 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1081 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1082 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1083 *vptr = cfg->vpd.vpd_ros[i].value; 1084 return (0); 1085 } 1086 1087 *vptr = NULL; 1088 return (ENXIO); 1089 } 1090 1091 /* 1092 * Find the requested extended capability and return the offset in 1093 * configuration space via the pointer provided. The function returns 1094 * 0 on success and error code otherwise. 1095 */ 1096 int 1097 pci_find_extcap_method(device_t dev, device_t child, int capability, 1098 int *capreg) 1099 { 1100 struct pci_devinfo *dinfo = device_get_ivars(child); 1101 pcicfgregs *cfg = &dinfo->cfg; 1102 u_int32_t status; 1103 u_int8_t ptr; 1104 1105 /* 1106 * Check the CAP_LIST bit of the PCI status register first. 1107 */ 1108 status = pci_read_config(child, PCIR_STATUS, 2); 1109 if (!(status & PCIM_STATUS_CAPPRESENT)) 1110 return (ENXIO); 1111 1112 /* 1113 * Determine the start pointer of the capabilities list. 1114 */ 1115 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1116 case 0: 1117 case 1: 1118 ptr = PCIR_CAP_PTR; 1119 break; 1120 case 2: 1121 ptr = PCIR_CAP_PTR_2; 1122 break; 1123 default: 1124 /* XXX: panic? */ 1125 return (ENXIO); /* no extended capabilities support */ 1126 } 1127 ptr = pci_read_config(child, ptr, 1); 1128 1129 /* 1130 * Traverse the capabilities list. 1131 */ 1132 while (ptr != 0) { 1133 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1134 if (capreg != NULL) 1135 *capreg = ptr; 1136 return (0); 1137 } 1138 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1139 } 1140 1141 return (ENOENT); 1142 } 1143 1144 /* 1145 * Support for MSI-X message interrupts. 1146 */ 1147 void 1148 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 1149 { 1150 struct pci_devinfo *dinfo = device_get_ivars(dev); 1151 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1152 uint32_t offset; 1153 1154 KASSERT(msix->msix_table_len > index, ("bogus index")); 1155 offset = msix->msix_table_offset + index * 16; 1156 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1157 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1158 bus_write_4(msix->msix_table_res, offset + 8, data); 1159 1160 /* Enable MSI -> HT mapping. */ 1161 pci_ht_map_msi(dev, address); 1162 } 1163 1164 void 1165 pci_mask_msix(device_t dev, u_int index) 1166 { 1167 struct pci_devinfo *dinfo = device_get_ivars(dev); 1168 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1169 uint32_t offset, val; 1170 1171 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1172 offset = msix->msix_table_offset + index * 16 + 12; 1173 val = bus_read_4(msix->msix_table_res, offset); 1174 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 1175 val |= PCIM_MSIX_VCTRL_MASK; 1176 bus_write_4(msix->msix_table_res, offset, val); 1177 } 1178 } 1179 1180 void 1181 pci_unmask_msix(device_t dev, u_int index) 1182 { 1183 struct pci_devinfo *dinfo = device_get_ivars(dev); 1184 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1185 uint32_t offset, val; 1186 1187 KASSERT(msix->msix_table_len > index, ("bogus index")); 1188 offset = msix->msix_table_offset + index * 16 + 12; 1189 val = bus_read_4(msix->msix_table_res, offset); 1190 if (val & PCIM_MSIX_VCTRL_MASK) { 1191 val &= ~PCIM_MSIX_VCTRL_MASK; 1192 bus_write_4(msix->msix_table_res, offset, val); 1193 } 1194 } 1195 1196 int 1197 pci_pending_msix(device_t dev, u_int index) 1198 { 1199 struct pci_devinfo *dinfo = device_get_ivars(dev); 1200 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1201 uint32_t offset, bit; 1202 1203 KASSERT(msix->msix_table_len > index, ("bogus index")); 1204 offset = msix->msix_pba_offset + (index / 32) * 4; 1205 bit = 1 << index % 32; 1206 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1207 } 1208 1209 /* 1210 * Restore MSI-X registers and table during resume. If MSI-X is 1211 * enabled then walk the virtual table to restore the actual MSI-X 1212 * table. 1213 */ 1214 static void 1215 pci_resume_msix(device_t dev) 1216 { 1217 struct pci_devinfo *dinfo = device_get_ivars(dev); 1218 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1219 struct msix_table_entry *mte; 1220 struct msix_vector *mv; 1221 int i; 1222 1223 if (msix->msix_alloc > 0) { 1224 /* First, mask all vectors. */ 1225 for (i = 0; i < msix->msix_msgnum; i++) 1226 pci_mask_msix(dev, i); 1227 1228 /* Second, program any messages with at least one handler. */ 1229 for (i = 0; i < msix->msix_table_len; i++) { 1230 mte = &msix->msix_table[i]; 1231 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1232 continue; 1233 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1234 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data); 1235 pci_unmask_msix(dev, i); 1236 } 1237 } 1238 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1239 msix->msix_ctrl, 2); 1240 } 1241 1242 /* 1243 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1244 * returned in *count. After this function returns, each message will be 1245 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1246 */ 1247 int 1248 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1249 { 1250 struct pci_devinfo *dinfo = device_get_ivars(child); 1251 pcicfgregs *cfg = &dinfo->cfg; 1252 struct resource_list_entry *rle; 1253 int actual, error, i, irq, max; 1254 1255 /* Don't let count == 0 get us into trouble. */ 1256 if (*count == 0) 1257 return (EINVAL); 1258 1259 /* If rid 0 is allocated, then fail. */ 1260 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1261 if (rle != NULL && rle->res != NULL) 1262 return (ENXIO); 1263 1264 /* Already have allocated messages? */ 1265 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1266 return (ENXIO); 1267 1268 /* If MSI is blacklisted for this system, fail. */ 1269 if (pci_msi_blacklisted()) 1270 return (ENXIO); 1271 1272 /* MSI-X capability present? */ 1273 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1274 return (ENODEV); 1275 1276 /* Make sure the appropriate BARs are mapped. */ 1277 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1278 cfg->msix.msix_table_bar); 1279 if (rle == NULL || rle->res == NULL || 1280 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1281 return (ENXIO); 1282 cfg->msix.msix_table_res = rle->res; 1283 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1284 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1285 cfg->msix.msix_pba_bar); 1286 if (rle == NULL || rle->res == NULL || 1287 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1288 return (ENXIO); 1289 } 1290 cfg->msix.msix_pba_res = rle->res; 1291 1292 if (bootverbose) 1293 device_printf(child, 1294 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1295 *count, cfg->msix.msix_msgnum); 1296 max = min(*count, cfg->msix.msix_msgnum); 1297 for (i = 0; i < max; i++) { 1298 /* Allocate a message. */ 1299 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1300 if (error) { 1301 if (i == 0) 1302 return (error); 1303 break; 1304 } 1305 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1306 irq, 1); 1307 } 1308 actual = i; 1309 1310 if (bootverbose) { 1311 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1312 if (actual == 1) 1313 device_printf(child, "using IRQ %lu for MSI-X\n", 1314 rle->start); 1315 else { 1316 int run; 1317 1318 /* 1319 * Be fancy and try to print contiguous runs of 1320 * IRQ values as ranges. 'irq' is the previous IRQ. 1321 * 'run' is true if we are in a range. 1322 */ 1323 device_printf(child, "using IRQs %lu", rle->start); 1324 irq = rle->start; 1325 run = 0; 1326 for (i = 1; i < actual; i++) { 1327 rle = resource_list_find(&dinfo->resources, 1328 SYS_RES_IRQ, i + 1); 1329 1330 /* Still in a run? */ 1331 if (rle->start == irq + 1) { 1332 run = 1; 1333 irq++; 1334 continue; 1335 } 1336 1337 /* Finish previous range. */ 1338 if (run) { 1339 printf("-%d", irq); 1340 run = 0; 1341 } 1342 1343 /* Start new range. */ 1344 printf(",%lu", rle->start); 1345 irq = rle->start; 1346 } 1347 1348 /* Unfinished range? */ 1349 if (run) 1350 printf("-%d", irq); 1351 printf(" for MSI-X\n"); 1352 } 1353 } 1354 1355 /* Mask all vectors. */ 1356 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1357 pci_mask_msix(child, i); 1358 1359 /* Allocate and initialize vector data and virtual table. */ 1360 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1361 M_DEVBUF, M_WAITOK | M_ZERO); 1362 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1363 M_DEVBUF, M_WAITOK | M_ZERO); 1364 for (i = 0; i < actual; i++) { 1365 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1366 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1367 cfg->msix.msix_table[i].mte_vector = i + 1; 1368 } 1369 1370 /* Update control register to enable MSI-X. */ 1371 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1372 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1373 cfg->msix.msix_ctrl, 2); 1374 1375 /* Update counts of alloc'd messages. */ 1376 cfg->msix.msix_alloc = actual; 1377 cfg->msix.msix_table_len = actual; 1378 *count = actual; 1379 return (0); 1380 } 1381 1382 /* 1383 * By default, pci_alloc_msix() will assign the allocated IRQ 1384 * resources consecutively to the first N messages in the MSI-X table. 1385 * However, device drivers may want to use different layouts if they 1386 * either receive fewer messages than they asked for, or they wish to 1387 * populate the MSI-X table sparsely. This method allows the driver 1388 * to specify what layout it wants. It must be called after a 1389 * successful pci_alloc_msix() but before any of the associated 1390 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1391 * 1392 * The 'vectors' array contains 'count' message vectors. The array 1393 * maps directly to the MSI-X table in that index 0 in the array 1394 * specifies the vector for the first message in the MSI-X table, etc. 1395 * The vector value in each array index can either be 0 to indicate 1396 * that no vector should be assigned to a message slot, or it can be a 1397 * number from 1 to N (where N is the count returned from a 1398 * succcessful call to pci_alloc_msix()) to indicate which message 1399 * vector (IRQ) to be used for the corresponding message. 1400 * 1401 * On successful return, each message with a non-zero vector will have 1402 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1403 * 1. Additionally, if any of the IRQs allocated via the previous 1404 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1405 * will be freed back to the system automatically. 1406 * 1407 * For example, suppose a driver has a MSI-X table with 6 messages and 1408 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1409 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1410 * C. After the call to pci_alloc_msix(), the device will be setup to 1411 * have an MSI-X table of ABC--- (where - means no vector assigned). 1412 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1413 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1414 * be freed back to the system. This device will also have valid 1415 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1416 * 1417 * In any case, the SYS_RES_IRQ rid X will always map to the message 1418 * at MSI-X table index X - 1 and will only be valid if a vector is 1419 * assigned to that table entry. 1420 */ 1421 int 1422 pci_remap_msix_method(device_t dev, device_t child, int count, 1423 const u_int *vectors) 1424 { 1425 struct pci_devinfo *dinfo = device_get_ivars(child); 1426 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1427 struct resource_list_entry *rle; 1428 int i, irq, j, *used; 1429 1430 /* 1431 * Have to have at least one message in the table but the 1432 * table can't be bigger than the actual MSI-X table in the 1433 * device. 1434 */ 1435 if (count == 0 || count > msix->msix_msgnum) 1436 return (EINVAL); 1437 1438 /* Sanity check the vectors. */ 1439 for (i = 0; i < count; i++) 1440 if (vectors[i] > msix->msix_alloc) 1441 return (EINVAL); 1442 1443 /* 1444 * Make sure there aren't any holes in the vectors to be used. 1445 * It's a big pain to support it, and it doesn't really make 1446 * sense anyway. Also, at least one vector must be used. 1447 */ 1448 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1449 M_ZERO); 1450 for (i = 0; i < count; i++) 1451 if (vectors[i] != 0) 1452 used[vectors[i] - 1] = 1; 1453 for (i = 0; i < msix->msix_alloc - 1; i++) 1454 if (used[i] == 0 && used[i + 1] == 1) { 1455 free(used, M_DEVBUF); 1456 return (EINVAL); 1457 } 1458 if (used[0] != 1) { 1459 free(used, M_DEVBUF); 1460 return (EINVAL); 1461 } 1462 1463 /* Make sure none of the resources are allocated. */ 1464 for (i = 0; i < msix->msix_table_len; i++) { 1465 if (msix->msix_table[i].mte_vector == 0) 1466 continue; 1467 if (msix->msix_table[i].mte_handlers > 0) 1468 return (EBUSY); 1469 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1470 KASSERT(rle != NULL, ("missing resource")); 1471 if (rle->res != NULL) 1472 return (EBUSY); 1473 } 1474 1475 /* Free the existing resource list entries. */ 1476 for (i = 0; i < msix->msix_table_len; i++) { 1477 if (msix->msix_table[i].mte_vector == 0) 1478 continue; 1479 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1480 } 1481 1482 /* 1483 * Build the new virtual table keeping track of which vectors are 1484 * used. 1485 */ 1486 free(msix->msix_table, M_DEVBUF); 1487 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1488 M_DEVBUF, M_WAITOK | M_ZERO); 1489 for (i = 0; i < count; i++) 1490 msix->msix_table[i].mte_vector = vectors[i]; 1491 msix->msix_table_len = count; 1492 1493 /* Free any unused IRQs and resize the vectors array if necessary. */ 1494 j = msix->msix_alloc - 1; 1495 if (used[j] == 0) { 1496 struct msix_vector *vec; 1497 1498 while (used[j] == 0) { 1499 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1500 msix->msix_vectors[j].mv_irq); 1501 j--; 1502 } 1503 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 1504 M_WAITOK); 1505 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 1506 (j + 1)); 1507 free(msix->msix_vectors, M_DEVBUF); 1508 msix->msix_vectors = vec; 1509 msix->msix_alloc = j + 1; 1510 } 1511 free(used, M_DEVBUF); 1512 1513 /* Map the IRQs onto the rids. */ 1514 for (i = 0; i < count; i++) { 1515 if (vectors[i] == 0) 1516 continue; 1517 irq = msix->msix_vectors[vectors[i]].mv_irq; 1518 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1519 irq, 1); 1520 } 1521 1522 if (bootverbose) { 1523 device_printf(child, "Remapped MSI-X IRQs as: "); 1524 for (i = 0; i < count; i++) { 1525 if (i != 0) 1526 printf(", "); 1527 if (vectors[i] == 0) 1528 printf("---"); 1529 else 1530 printf("%d", 1531 msix->msix_vectors[vectors[i]].mv_irq); 1532 } 1533 printf("\n"); 1534 } 1535 1536 return (0); 1537 } 1538 1539 static int 1540 pci_release_msix(device_t dev, device_t child) 1541 { 1542 struct pci_devinfo *dinfo = device_get_ivars(child); 1543 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1544 struct resource_list_entry *rle; 1545 int i; 1546 1547 /* Do we have any messages to release? */ 1548 if (msix->msix_alloc == 0) 1549 return (ENODEV); 1550 1551 /* Make sure none of the resources are allocated. */ 1552 for (i = 0; i < msix->msix_table_len; i++) { 1553 if (msix->msix_table[i].mte_vector == 0) 1554 continue; 1555 if (msix->msix_table[i].mte_handlers > 0) 1556 return (EBUSY); 1557 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1558 KASSERT(rle != NULL, ("missing resource")); 1559 if (rle->res != NULL) 1560 return (EBUSY); 1561 } 1562 1563 /* Update control register to disable MSI-X. */ 1564 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1565 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 1566 msix->msix_ctrl, 2); 1567 1568 /* Free the resource list entries. */ 1569 for (i = 0; i < msix->msix_table_len; i++) { 1570 if (msix->msix_table[i].mte_vector == 0) 1571 continue; 1572 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1573 } 1574 free(msix->msix_table, M_DEVBUF); 1575 msix->msix_table_len = 0; 1576 1577 /* Release the IRQs. */ 1578 for (i = 0; i < msix->msix_alloc; i++) 1579 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1580 msix->msix_vectors[i].mv_irq); 1581 free(msix->msix_vectors, M_DEVBUF); 1582 msix->msix_alloc = 0; 1583 return (0); 1584 } 1585 1586 /* 1587 * Return the max supported MSI-X messages this device supports. 1588 * Basically, assuming the MD code can alloc messages, this function 1589 * should return the maximum value that pci_alloc_msix() can return. 1590 * Thus, it is subject to the tunables, etc. 1591 */ 1592 int 1593 pci_msix_count_method(device_t dev, device_t child) 1594 { 1595 struct pci_devinfo *dinfo = device_get_ivars(child); 1596 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1597 1598 if (pci_do_msix && msix->msix_location != 0) 1599 return (msix->msix_msgnum); 1600 return (0); 1601 } 1602 1603 /* 1604 * HyperTransport MSI mapping control 1605 */ 1606 void 1607 pci_ht_map_msi(device_t dev, uint64_t addr) 1608 { 1609 struct pci_devinfo *dinfo = device_get_ivars(dev); 1610 struct pcicfg_ht *ht = &dinfo->cfg.ht; 1611 1612 if (!ht->ht_msimap) 1613 return; 1614 1615 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 1616 ht->ht_msiaddr >> 20 == addr >> 20) { 1617 /* Enable MSI -> HT mapping. */ 1618 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1619 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1620 ht->ht_msictrl, 2); 1621 } 1622 1623 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 1624 /* Disable MSI -> HT mapping. */ 1625 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 1626 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1627 ht->ht_msictrl, 2); 1628 } 1629 } 1630 1631 int 1632 pci_get_max_read_req(device_t dev) 1633 { 1634 int cap; 1635 uint16_t val; 1636 1637 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0) 1638 return (0); 1639 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2); 1640 val &= PCIM_EXP_CTL_MAX_READ_REQUEST; 1641 val >>= 12; 1642 return (1 << (val + 7)); 1643 } 1644 1645 int 1646 pci_set_max_read_req(device_t dev, int size) 1647 { 1648 int cap; 1649 uint16_t val; 1650 1651 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0) 1652 return (0); 1653 if (size < 128) 1654 size = 128; 1655 if (size > 4096) 1656 size = 4096; 1657 size = (1 << (fls(size) - 1)); 1658 val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2); 1659 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 1660 val |= (fls(size) - 8) << 12; 1661 pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2); 1662 return (size); 1663 } 1664 1665 /* 1666 * Support for MSI message signalled interrupts. 1667 */ 1668 void 1669 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1670 { 1671 struct pci_devinfo *dinfo = device_get_ivars(dev); 1672 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1673 1674 /* Write data and address values. */ 1675 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1676 address & 0xffffffff, 4); 1677 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1678 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH, 1679 address >> 32, 4); 1680 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT, 1681 data, 2); 1682 } else 1683 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data, 1684 2); 1685 1686 /* Enable MSI in the control register. */ 1687 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1688 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1689 2); 1690 1691 /* Enable MSI -> HT mapping. */ 1692 pci_ht_map_msi(dev, address); 1693 } 1694 1695 void 1696 pci_disable_msi(device_t dev) 1697 { 1698 struct pci_devinfo *dinfo = device_get_ivars(dev); 1699 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1700 1701 /* Disable MSI -> HT mapping. */ 1702 pci_ht_map_msi(dev, 0); 1703 1704 /* Disable MSI in the control register. */ 1705 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 1706 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1707 2); 1708 } 1709 1710 /* 1711 * Restore MSI registers during resume. If MSI is enabled then 1712 * restore the data and address registers in addition to the control 1713 * register. 1714 */ 1715 static void 1716 pci_resume_msi(device_t dev) 1717 { 1718 struct pci_devinfo *dinfo = device_get_ivars(dev); 1719 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1720 uint64_t address; 1721 uint16_t data; 1722 1723 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1724 address = msi->msi_addr; 1725 data = msi->msi_data; 1726 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1727 address & 0xffffffff, 4); 1728 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1729 pci_write_config(dev, msi->msi_location + 1730 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1731 pci_write_config(dev, msi->msi_location + 1732 PCIR_MSI_DATA_64BIT, data, 2); 1733 } else 1734 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 1735 data, 2); 1736 } 1737 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1738 2); 1739 } 1740 1741 static int 1742 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 1743 { 1744 struct pci_devinfo *dinfo = device_get_ivars(dev); 1745 pcicfgregs *cfg = &dinfo->cfg; 1746 struct resource_list_entry *rle; 1747 struct msix_table_entry *mte; 1748 struct msix_vector *mv; 1749 uint64_t addr; 1750 uint32_t data; 1751 int error, i, j; 1752 1753 /* 1754 * Handle MSI first. We try to find this IRQ among our list 1755 * of MSI IRQs. If we find it, we request updated address and 1756 * data registers and apply the results. 1757 */ 1758 if (cfg->msi.msi_alloc > 0) { 1759 1760 /* If we don't have any active handlers, nothing to do. */ 1761 if (cfg->msi.msi_handlers == 0) 1762 return (0); 1763 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1764 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1765 i + 1); 1766 if (rle->start == irq) { 1767 error = PCIB_MAP_MSI(device_get_parent(bus), 1768 dev, irq, &addr, &data); 1769 if (error) 1770 return (error); 1771 pci_disable_msi(dev); 1772 dinfo->cfg.msi.msi_addr = addr; 1773 dinfo->cfg.msi.msi_data = data; 1774 pci_enable_msi(dev, addr, data); 1775 return (0); 1776 } 1777 } 1778 return (ENOENT); 1779 } 1780 1781 /* 1782 * For MSI-X, we check to see if we have this IRQ. If we do, 1783 * we request the updated mapping info. If that works, we go 1784 * through all the slots that use this IRQ and update them. 1785 */ 1786 if (cfg->msix.msix_alloc > 0) { 1787 for (i = 0; i < cfg->msix.msix_alloc; i++) { 1788 mv = &cfg->msix.msix_vectors[i]; 1789 if (mv->mv_irq == irq) { 1790 error = PCIB_MAP_MSI(device_get_parent(bus), 1791 dev, irq, &addr, &data); 1792 if (error) 1793 return (error); 1794 mv->mv_address = addr; 1795 mv->mv_data = data; 1796 for (j = 0; j < cfg->msix.msix_table_len; j++) { 1797 mte = &cfg->msix.msix_table[j]; 1798 if (mte->mte_vector != i + 1) 1799 continue; 1800 if (mte->mte_handlers == 0) 1801 continue; 1802 pci_mask_msix(dev, j); 1803 pci_enable_msix(dev, j, addr, data); 1804 pci_unmask_msix(dev, j); 1805 } 1806 } 1807 } 1808 return (ENOENT); 1809 } 1810 1811 return (ENOENT); 1812 } 1813 1814 /* 1815 * Returns true if the specified device is blacklisted because MSI 1816 * doesn't work. 1817 */ 1818 int 1819 pci_msi_device_blacklisted(device_t dev) 1820 { 1821 const struct pci_quirk *q; 1822 1823 if (!pci_honor_msi_blacklist) 1824 return (0); 1825 1826 for (q = &pci_quirks[0]; q->devid; q++) { 1827 if (q->devid == pci_get_devid(dev) && 1828 q->type == PCI_QUIRK_DISABLE_MSI) 1829 return (1); 1830 } 1831 return (0); 1832 } 1833 1834 /* 1835 * Returns true if a specified chipset supports MSI when it is 1836 * emulated hardware in a virtual machine. 1837 */ 1838 static int 1839 pci_msi_vm_chipset(device_t dev) 1840 { 1841 const struct pci_quirk *q; 1842 1843 for (q = &pci_quirks[0]; q->devid; q++) { 1844 if (q->devid == pci_get_devid(dev) && 1845 q->type == PCI_QUIRK_ENABLE_MSI_VM) 1846 return (1); 1847 } 1848 return (0); 1849 } 1850 1851 /* 1852 * Determine if MSI is blacklisted globally on this sytem. Currently, 1853 * we just check for blacklisted chipsets as represented by the 1854 * host-PCI bridge at device 0:0:0. In the future, it may become 1855 * necessary to check other system attributes, such as the kenv values 1856 * that give the motherboard manufacturer and model number. 1857 */ 1858 static int 1859 pci_msi_blacklisted(void) 1860 { 1861 device_t dev; 1862 1863 if (!pci_honor_msi_blacklist) 1864 return (0); 1865 1866 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 1867 if (!(pcie_chipset || pcix_chipset)) { 1868 if (vm_guest != VM_GUEST_NO) { 1869 dev = pci_find_bsf(0, 0, 0); 1870 if (dev != NULL) 1871 return (pci_msi_vm_chipset(dev) == 0); 1872 } 1873 return (1); 1874 } 1875 1876 dev = pci_find_bsf(0, 0, 0); 1877 if (dev != NULL) 1878 return (pci_msi_device_blacklisted(dev)); 1879 return (0); 1880 } 1881 1882 /* 1883 * Attempt to allocate *count MSI messages. The actual number allocated is 1884 * returned in *count. After this function returns, each message will be 1885 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 1886 */ 1887 int 1888 pci_alloc_msi_method(device_t dev, device_t child, int *count) 1889 { 1890 struct pci_devinfo *dinfo = device_get_ivars(child); 1891 pcicfgregs *cfg = &dinfo->cfg; 1892 struct resource_list_entry *rle; 1893 int actual, error, i, irqs[32]; 1894 uint16_t ctrl; 1895 1896 /* Don't let count == 0 get us into trouble. */ 1897 if (*count == 0) 1898 return (EINVAL); 1899 1900 /* If rid 0 is allocated, then fail. */ 1901 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1902 if (rle != NULL && rle->res != NULL) 1903 return (ENXIO); 1904 1905 /* Already have allocated messages? */ 1906 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1907 return (ENXIO); 1908 1909 /* If MSI is blacklisted for this system, fail. */ 1910 if (pci_msi_blacklisted()) 1911 return (ENXIO); 1912 1913 /* MSI capability present? */ 1914 if (cfg->msi.msi_location == 0 || !pci_do_msi) 1915 return (ENODEV); 1916 1917 if (bootverbose) 1918 device_printf(child, 1919 "attempting to allocate %d MSI vectors (%d supported)\n", 1920 *count, cfg->msi.msi_msgnum); 1921 1922 /* Don't ask for more than the device supports. */ 1923 actual = min(*count, cfg->msi.msi_msgnum); 1924 1925 /* Don't ask for more than 32 messages. */ 1926 actual = min(actual, 32); 1927 1928 /* MSI requires power of 2 number of messages. */ 1929 if (!powerof2(actual)) 1930 return (EINVAL); 1931 1932 for (;;) { 1933 /* Try to allocate N messages. */ 1934 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 1935 actual, irqs); 1936 if (error == 0) 1937 break; 1938 if (actual == 1) 1939 return (error); 1940 1941 /* Try N / 2. */ 1942 actual >>= 1; 1943 } 1944 1945 /* 1946 * We now have N actual messages mapped onto SYS_RES_IRQ 1947 * resources in the irqs[] array, so add new resources 1948 * starting at rid 1. 1949 */ 1950 for (i = 0; i < actual; i++) 1951 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 1952 irqs[i], irqs[i], 1); 1953 1954 if (bootverbose) { 1955 if (actual == 1) 1956 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 1957 else { 1958 int run; 1959 1960 /* 1961 * Be fancy and try to print contiguous runs 1962 * of IRQ values as ranges. 'run' is true if 1963 * we are in a range. 1964 */ 1965 device_printf(child, "using IRQs %d", irqs[0]); 1966 run = 0; 1967 for (i = 1; i < actual; i++) { 1968 1969 /* Still in a run? */ 1970 if (irqs[i] == irqs[i - 1] + 1) { 1971 run = 1; 1972 continue; 1973 } 1974 1975 /* Finish previous range. */ 1976 if (run) { 1977 printf("-%d", irqs[i - 1]); 1978 run = 0; 1979 } 1980 1981 /* Start new range. */ 1982 printf(",%d", irqs[i]); 1983 } 1984 1985 /* Unfinished range? */ 1986 if (run) 1987 printf("-%d", irqs[actual - 1]); 1988 printf(" for MSI\n"); 1989 } 1990 } 1991 1992 /* Update control register with actual count. */ 1993 ctrl = cfg->msi.msi_ctrl; 1994 ctrl &= ~PCIM_MSICTRL_MME_MASK; 1995 ctrl |= (ffs(actual) - 1) << 4; 1996 cfg->msi.msi_ctrl = ctrl; 1997 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 1998 1999 /* Update counts of alloc'd messages. */ 2000 cfg->msi.msi_alloc = actual; 2001 cfg->msi.msi_handlers = 0; 2002 *count = actual; 2003 return (0); 2004 } 2005 2006 /* Release the MSI messages associated with this device. */ 2007 int 2008 pci_release_msi_method(device_t dev, device_t child) 2009 { 2010 struct pci_devinfo *dinfo = device_get_ivars(child); 2011 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2012 struct resource_list_entry *rle; 2013 int error, i, irqs[32]; 2014 2015 /* Try MSI-X first. */ 2016 error = pci_release_msix(dev, child); 2017 if (error != ENODEV) 2018 return (error); 2019 2020 /* Do we have any messages to release? */ 2021 if (msi->msi_alloc == 0) 2022 return (ENODEV); 2023 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2024 2025 /* Make sure none of the resources are allocated. */ 2026 if (msi->msi_handlers > 0) 2027 return (EBUSY); 2028 for (i = 0; i < msi->msi_alloc; i++) { 2029 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2030 KASSERT(rle != NULL, ("missing MSI resource")); 2031 if (rle->res != NULL) 2032 return (EBUSY); 2033 irqs[i] = rle->start; 2034 } 2035 2036 /* Update control register with 0 count. */ 2037 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2038 ("%s: MSI still enabled", __func__)); 2039 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2040 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2041 msi->msi_ctrl, 2); 2042 2043 /* Release the messages. */ 2044 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2045 for (i = 0; i < msi->msi_alloc; i++) 2046 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2047 2048 /* Update alloc count. */ 2049 msi->msi_alloc = 0; 2050 msi->msi_addr = 0; 2051 msi->msi_data = 0; 2052 return (0); 2053 } 2054 2055 /* 2056 * Return the max supported MSI messages this device supports. 2057 * Basically, assuming the MD code can alloc messages, this function 2058 * should return the maximum value that pci_alloc_msi() can return. 2059 * Thus, it is subject to the tunables, etc. 2060 */ 2061 int 2062 pci_msi_count_method(device_t dev, device_t child) 2063 { 2064 struct pci_devinfo *dinfo = device_get_ivars(child); 2065 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2066 2067 if (pci_do_msi && msi->msi_location != 0) 2068 return (msi->msi_msgnum); 2069 return (0); 2070 } 2071 2072 /* free pcicfgregs structure and all depending data structures */ 2073 2074 int 2075 pci_freecfg(struct pci_devinfo *dinfo) 2076 { 2077 struct devlist *devlist_head; 2078 int i; 2079 2080 devlist_head = &pci_devq; 2081 2082 if (dinfo->cfg.vpd.vpd_reg) { 2083 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2084 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2085 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2086 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2087 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2088 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2089 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2090 } 2091 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2092 free(dinfo, M_DEVBUF); 2093 2094 /* increment the generation count */ 2095 pci_generation++; 2096 2097 /* we're losing one device */ 2098 pci_numdevs--; 2099 return (0); 2100 } 2101 2102 /* 2103 * PCI power manangement 2104 */ 2105 int 2106 pci_set_powerstate_method(device_t dev, device_t child, int state) 2107 { 2108 struct pci_devinfo *dinfo = device_get_ivars(child); 2109 pcicfgregs *cfg = &dinfo->cfg; 2110 uint16_t status; 2111 int result, oldstate, highest, delay; 2112 2113 if (cfg->pp.pp_cap == 0) 2114 return (EOPNOTSUPP); 2115 2116 /* 2117 * Optimize a no state change request away. While it would be OK to 2118 * write to the hardware in theory, some devices have shown odd 2119 * behavior when going from D3 -> D3. 2120 */ 2121 oldstate = pci_get_powerstate(child); 2122 if (oldstate == state) 2123 return (0); 2124 2125 /* 2126 * The PCI power management specification states that after a state 2127 * transition between PCI power states, system software must 2128 * guarantee a minimal delay before the function accesses the device. 2129 * Compute the worst case delay that we need to guarantee before we 2130 * access the device. Many devices will be responsive much more 2131 * quickly than this delay, but there are some that don't respond 2132 * instantly to state changes. Transitions to/from D3 state require 2133 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2134 * is done below with DELAY rather than a sleeper function because 2135 * this function can be called from contexts where we cannot sleep. 2136 */ 2137 highest = (oldstate > state) ? oldstate : state; 2138 if (highest == PCI_POWERSTATE_D3) 2139 delay = 10000; 2140 else if (highest == PCI_POWERSTATE_D2) 2141 delay = 200; 2142 else 2143 delay = 0; 2144 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2145 & ~PCIM_PSTAT_DMASK; 2146 result = 0; 2147 switch (state) { 2148 case PCI_POWERSTATE_D0: 2149 status |= PCIM_PSTAT_D0; 2150 break; 2151 case PCI_POWERSTATE_D1: 2152 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2153 return (EOPNOTSUPP); 2154 status |= PCIM_PSTAT_D1; 2155 break; 2156 case PCI_POWERSTATE_D2: 2157 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2158 return (EOPNOTSUPP); 2159 status |= PCIM_PSTAT_D2; 2160 break; 2161 case PCI_POWERSTATE_D3: 2162 status |= PCIM_PSTAT_D3; 2163 break; 2164 default: 2165 return (EINVAL); 2166 } 2167 2168 if (bootverbose) 2169 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2170 state); 2171 2172 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2173 if (delay) 2174 DELAY(delay); 2175 return (0); 2176 } 2177 2178 int 2179 pci_get_powerstate_method(device_t dev, device_t child) 2180 { 2181 struct pci_devinfo *dinfo = device_get_ivars(child); 2182 pcicfgregs *cfg = &dinfo->cfg; 2183 uint16_t status; 2184 int result; 2185 2186 if (cfg->pp.pp_cap != 0) { 2187 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2188 switch (status & PCIM_PSTAT_DMASK) { 2189 case PCIM_PSTAT_D0: 2190 result = PCI_POWERSTATE_D0; 2191 break; 2192 case PCIM_PSTAT_D1: 2193 result = PCI_POWERSTATE_D1; 2194 break; 2195 case PCIM_PSTAT_D2: 2196 result = PCI_POWERSTATE_D2; 2197 break; 2198 case PCIM_PSTAT_D3: 2199 result = PCI_POWERSTATE_D3; 2200 break; 2201 default: 2202 result = PCI_POWERSTATE_UNKNOWN; 2203 break; 2204 } 2205 } else { 2206 /* No support, device is always at D0 */ 2207 result = PCI_POWERSTATE_D0; 2208 } 2209 return (result); 2210 } 2211 2212 /* 2213 * Some convenience functions for PCI device drivers. 2214 */ 2215 2216 static __inline void 2217 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2218 { 2219 uint16_t command; 2220 2221 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2222 command |= bit; 2223 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2224 } 2225 2226 static __inline void 2227 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2228 { 2229 uint16_t command; 2230 2231 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2232 command &= ~bit; 2233 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2234 } 2235 2236 int 2237 pci_enable_busmaster_method(device_t dev, device_t child) 2238 { 2239 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2240 return (0); 2241 } 2242 2243 int 2244 pci_disable_busmaster_method(device_t dev, device_t child) 2245 { 2246 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2247 return (0); 2248 } 2249 2250 int 2251 pci_enable_io_method(device_t dev, device_t child, int space) 2252 { 2253 uint16_t bit; 2254 2255 switch(space) { 2256 case SYS_RES_IOPORT: 2257 bit = PCIM_CMD_PORTEN; 2258 break; 2259 case SYS_RES_MEMORY: 2260 bit = PCIM_CMD_MEMEN; 2261 break; 2262 default: 2263 return (EINVAL); 2264 } 2265 pci_set_command_bit(dev, child, bit); 2266 return (0); 2267 } 2268 2269 int 2270 pci_disable_io_method(device_t dev, device_t child, int space) 2271 { 2272 uint16_t bit; 2273 2274 switch(space) { 2275 case SYS_RES_IOPORT: 2276 bit = PCIM_CMD_PORTEN; 2277 break; 2278 case SYS_RES_MEMORY: 2279 bit = PCIM_CMD_MEMEN; 2280 break; 2281 default: 2282 return (EINVAL); 2283 } 2284 pci_clear_command_bit(dev, child, bit); 2285 return (0); 2286 } 2287 2288 /* 2289 * New style pci driver. Parent device is either a pci-host-bridge or a 2290 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2291 */ 2292 2293 void 2294 pci_print_verbose(struct pci_devinfo *dinfo) 2295 { 2296 2297 if (bootverbose) { 2298 pcicfgregs *cfg = &dinfo->cfg; 2299 2300 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2301 cfg->vendor, cfg->device, cfg->revid); 2302 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2303 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2304 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2305 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2306 cfg->mfdev); 2307 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2308 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2309 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2310 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2311 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2312 if (cfg->intpin > 0) 2313 printf("\tintpin=%c, irq=%d\n", 2314 cfg->intpin +'a' -1, cfg->intline); 2315 if (cfg->pp.pp_cap) { 2316 uint16_t status; 2317 2318 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2319 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2320 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2321 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2322 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2323 status & PCIM_PSTAT_DMASK); 2324 } 2325 if (cfg->msi.msi_location) { 2326 int ctrl; 2327 2328 ctrl = cfg->msi.msi_ctrl; 2329 printf("\tMSI supports %d message%s%s%s\n", 2330 cfg->msi.msi_msgnum, 2331 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2332 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2333 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2334 } 2335 if (cfg->msix.msix_location) { 2336 printf("\tMSI-X supports %d message%s ", 2337 cfg->msix.msix_msgnum, 2338 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2339 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2340 printf("in map 0x%x\n", 2341 cfg->msix.msix_table_bar); 2342 else 2343 printf("in maps 0x%x and 0x%x\n", 2344 cfg->msix.msix_table_bar, 2345 cfg->msix.msix_pba_bar); 2346 } 2347 } 2348 } 2349 2350 static int 2351 pci_porten(device_t dev) 2352 { 2353 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2354 } 2355 2356 static int 2357 pci_memen(device_t dev) 2358 { 2359 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2360 } 2361 2362 static void 2363 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp) 2364 { 2365 pci_addr_t map, testval; 2366 int ln2range; 2367 uint16_t cmd; 2368 2369 map = pci_read_config(dev, reg, 4); 2370 ln2range = pci_maprange(map); 2371 if (ln2range == 64) 2372 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2373 2374 /* 2375 * Disable decoding via the command register before 2376 * determining the BAR's length since we will be placing it in 2377 * a weird state. 2378 */ 2379 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2380 pci_write_config(dev, PCIR_COMMAND, 2381 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 2382 2383 /* 2384 * Determine the BAR's length by writing all 1's. The bottom 2385 * log_2(size) bits of the BAR will stick as 0 when we read 2386 * the value back. 2387 */ 2388 pci_write_config(dev, reg, 0xffffffff, 4); 2389 testval = pci_read_config(dev, reg, 4); 2390 if (ln2range == 64) { 2391 pci_write_config(dev, reg + 4, 0xffffffff, 4); 2392 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2393 } 2394 2395 /* 2396 * Restore the original value of the BAR. We may have reprogrammed 2397 * the BAR of the low-level console device and when booting verbose, 2398 * we need the console device addressable. 2399 */ 2400 pci_write_config(dev, reg, map, 4); 2401 if (ln2range == 64) 2402 pci_write_config(dev, reg + 4, map >> 32, 4); 2403 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2404 2405 *mapp = map; 2406 *testvalp = testval; 2407 } 2408 2409 static void 2410 pci_write_bar(device_t dev, int reg, pci_addr_t base) 2411 { 2412 pci_addr_t map; 2413 int ln2range; 2414 2415 map = pci_read_config(dev, reg, 4); 2416 ln2range = pci_maprange(map); 2417 pci_write_config(dev, reg, base, 4); 2418 if (ln2range == 64) 2419 pci_write_config(dev, reg + 4, base >> 32, 4); 2420 } 2421 2422 /* 2423 * Add a resource based on a pci map register. Return 1 if the map 2424 * register is a 32bit map register or 2 if it is a 64bit register. 2425 */ 2426 static int 2427 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 2428 int force, int prefetch) 2429 { 2430 pci_addr_t base, map, testval; 2431 pci_addr_t start, end, count; 2432 int barlen, basezero, maprange, mapsize, type; 2433 uint16_t cmd; 2434 struct resource *res; 2435 2436 pci_read_bar(dev, reg, &map, &testval); 2437 if (PCI_BAR_MEM(map)) { 2438 type = SYS_RES_MEMORY; 2439 if (map & PCIM_BAR_MEM_PREFETCH) 2440 prefetch = 1; 2441 } else 2442 type = SYS_RES_IOPORT; 2443 mapsize = pci_mapsize(testval); 2444 base = pci_mapbase(map); 2445 #ifdef __PCI_BAR_ZERO_VALID 2446 basezero = 0; 2447 #else 2448 basezero = base == 0; 2449 #endif 2450 maprange = pci_maprange(map); 2451 barlen = maprange == 64 ? 2 : 1; 2452 2453 /* 2454 * For I/O registers, if bottom bit is set, and the next bit up 2455 * isn't clear, we know we have a BAR that doesn't conform to the 2456 * spec, so ignore it. Also, sanity check the size of the data 2457 * areas to the type of memory involved. Memory must be at least 2458 * 16 bytes in size, while I/O ranges must be at least 4. 2459 */ 2460 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 2461 return (barlen); 2462 if ((type == SYS_RES_MEMORY && mapsize < 4) || 2463 (type == SYS_RES_IOPORT && mapsize < 2)) 2464 return (barlen); 2465 2466 if (bootverbose) { 2467 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 2468 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 2469 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2470 printf(", port disabled\n"); 2471 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2472 printf(", memory disabled\n"); 2473 else 2474 printf(", enabled\n"); 2475 } 2476 2477 /* 2478 * If base is 0, then we have problems if this architecture does 2479 * not allow that. It is best to ignore such entries for the 2480 * moment. These will be allocated later if the driver specifically 2481 * requests them. However, some removable busses look better when 2482 * all resources are allocated, so allow '' to be overriden. 2483 * 2484 * Similarly treat maps whose values is the same as the test value 2485 * read back. These maps have had all f's written to them by the 2486 * BIOS in an attempt to disable the resources. 2487 */ 2488 if (!force && (basezero || map == testval)) 2489 return (barlen); 2490 if ((u_long)base != base) { 2491 device_printf(bus, 2492 "pci%d:%d:%d:%d bar %#x too many address bits", 2493 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 2494 pci_get_function(dev), reg); 2495 return (barlen); 2496 } 2497 2498 /* 2499 * This code theoretically does the right thing, but has 2500 * undesirable side effects in some cases where peripherals 2501 * respond oddly to having these bits enabled. Let the user 2502 * be able to turn them off (since pci_enable_io_modes is 1 by 2503 * default). 2504 */ 2505 if (pci_enable_io_modes) { 2506 /* Turn on resources that have been left off by a lazy BIOS */ 2507 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 2508 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2509 cmd |= PCIM_CMD_PORTEN; 2510 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2511 } 2512 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 2513 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2514 cmd |= PCIM_CMD_MEMEN; 2515 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2516 } 2517 } else { 2518 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2519 return (barlen); 2520 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2521 return (barlen); 2522 } 2523 2524 count = (pci_addr_t)1 << mapsize; 2525 if (basezero || base == pci_mapbase(testval)) { 2526 start = 0; /* Let the parent decide. */ 2527 end = ~0ULL; 2528 } else { 2529 start = base; 2530 end = base + count - 1; 2531 } 2532 resource_list_add(rl, type, reg, start, end, count); 2533 2534 /* 2535 * Try to allocate the resource for this BAR from our parent 2536 * so that this resource range is already reserved. The 2537 * driver for this device will later inherit this resource in 2538 * pci_alloc_resource(). 2539 */ 2540 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 2541 prefetch ? RF_PREFETCHABLE : 0); 2542 if (res == NULL) { 2543 /* 2544 * If the allocation fails, clear the BAR and delete 2545 * the resource list entry to force 2546 * pci_alloc_resource() to allocate resources from the 2547 * parent. 2548 */ 2549 resource_list_delete(rl, type, reg); 2550 start = 0; 2551 } else { 2552 start = rman_get_start(res); 2553 rman_set_device(res, bus); 2554 } 2555 pci_write_bar(dev, reg, start); 2556 return (barlen); 2557 } 2558 2559 /* 2560 * For ATA devices we need to decide early what addressing mode to use. 2561 * Legacy demands that the primary and secondary ATA ports sits on the 2562 * same addresses that old ISA hardware did. This dictates that we use 2563 * those addresses and ignore the BAR's if we cannot set PCI native 2564 * addressing mode. 2565 */ 2566 static void 2567 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 2568 uint32_t prefetchmask) 2569 { 2570 struct resource *r; 2571 int rid, type, progif; 2572 #if 0 2573 /* if this device supports PCI native addressing use it */ 2574 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2575 if ((progif & 0x8a) == 0x8a) { 2576 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 2577 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 2578 printf("Trying ATA native PCI addressing mode\n"); 2579 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 2580 } 2581 } 2582 #endif 2583 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2584 type = SYS_RES_IOPORT; 2585 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 2586 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 2587 prefetchmask & (1 << 0)); 2588 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 2589 prefetchmask & (1 << 1)); 2590 } else { 2591 rid = PCIR_BAR(0); 2592 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 2593 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 2594 8, 0); 2595 rman_set_device(r, bus); 2596 rid = PCIR_BAR(1); 2597 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 2598 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 2599 1, 0); 2600 rman_set_device(r, bus); 2601 } 2602 if (progif & PCIP_STORAGE_IDE_MODESEC) { 2603 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 2604 prefetchmask & (1 << 2)); 2605 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 2606 prefetchmask & (1 << 3)); 2607 } else { 2608 rid = PCIR_BAR(2); 2609 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 2610 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 2611 8, 0); 2612 rman_set_device(r, bus); 2613 rid = PCIR_BAR(3); 2614 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 2615 r = resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 2616 1, 0); 2617 rman_set_device(r, bus); 2618 } 2619 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 2620 prefetchmask & (1 << 4)); 2621 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 2622 prefetchmask & (1 << 5)); 2623 } 2624 2625 static void 2626 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 2627 { 2628 struct pci_devinfo *dinfo = device_get_ivars(dev); 2629 pcicfgregs *cfg = &dinfo->cfg; 2630 char tunable_name[64]; 2631 int irq; 2632 2633 /* Has to have an intpin to have an interrupt. */ 2634 if (cfg->intpin == 0) 2635 return; 2636 2637 /* Let the user override the IRQ with a tunable. */ 2638 irq = PCI_INVALID_IRQ; 2639 snprintf(tunable_name, sizeof(tunable_name), 2640 "hw.pci%d.%d.%d.INT%c.irq", 2641 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 2642 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 2643 irq = PCI_INVALID_IRQ; 2644 2645 /* 2646 * If we didn't get an IRQ via the tunable, then we either use the 2647 * IRQ value in the intline register or we ask the bus to route an 2648 * interrupt for us. If force_route is true, then we only use the 2649 * value in the intline register if the bus was unable to assign an 2650 * IRQ. 2651 */ 2652 if (!PCI_INTERRUPT_VALID(irq)) { 2653 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 2654 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 2655 if (!PCI_INTERRUPT_VALID(irq)) 2656 irq = cfg->intline; 2657 } 2658 2659 /* If after all that we don't have an IRQ, just bail. */ 2660 if (!PCI_INTERRUPT_VALID(irq)) 2661 return; 2662 2663 /* Update the config register if it changed. */ 2664 if (irq != cfg->intline) { 2665 cfg->intline = irq; 2666 pci_write_config(dev, PCIR_INTLINE, irq, 1); 2667 } 2668 2669 /* Add this IRQ as rid 0 interrupt resource. */ 2670 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 2671 } 2672 2673 /* Perform early OHCI takeover from SMM. */ 2674 static void 2675 ohci_early_takeover(device_t self) 2676 { 2677 struct resource *res; 2678 uint32_t ctl; 2679 int rid; 2680 int i; 2681 2682 rid = PCIR_BAR(0); 2683 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 2684 if (res == NULL) 2685 return; 2686 2687 ctl = bus_read_4(res, OHCI_CONTROL); 2688 if (ctl & OHCI_IR) { 2689 if (bootverbose) 2690 printf("ohci early: " 2691 "SMM active, request owner change\n"); 2692 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 2693 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 2694 DELAY(1000); 2695 ctl = bus_read_4(res, OHCI_CONTROL); 2696 } 2697 if (ctl & OHCI_IR) { 2698 if (bootverbose) 2699 printf("ohci early: " 2700 "SMM does not respond, resetting\n"); 2701 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 2702 } 2703 /* Disable interrupts */ 2704 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 2705 } 2706 2707 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 2708 } 2709 2710 /* Perform early UHCI takeover from SMM. */ 2711 static void 2712 uhci_early_takeover(device_t self) 2713 { 2714 struct resource *res; 2715 int rid; 2716 2717 /* 2718 * Set the PIRQD enable bit and switch off all the others. We don't 2719 * want legacy support to interfere with us XXX Does this also mean 2720 * that the BIOS won't touch the keyboard anymore if it is connected 2721 * to the ports of the root hub? 2722 */ 2723 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 2724 2725 /* Disable interrupts */ 2726 rid = PCI_UHCI_BASE_REG; 2727 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 2728 if (res != NULL) { 2729 bus_write_2(res, UHCI_INTR, 0); 2730 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 2731 } 2732 } 2733 2734 /* Perform early EHCI takeover from SMM. */ 2735 static void 2736 ehci_early_takeover(device_t self) 2737 { 2738 struct resource *res; 2739 uint32_t cparams; 2740 uint32_t eec; 2741 uint8_t eecp; 2742 uint8_t bios_sem; 2743 uint8_t offs; 2744 int rid; 2745 int i; 2746 2747 rid = PCIR_BAR(0); 2748 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 2749 if (res == NULL) 2750 return; 2751 2752 cparams = bus_read_4(res, EHCI_HCCPARAMS); 2753 2754 /* Synchronise with the BIOS if it owns the controller. */ 2755 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 2756 eecp = EHCI_EECP_NEXT(eec)) { 2757 eec = pci_read_config(self, eecp, 4); 2758 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 2759 continue; 2760 } 2761 bios_sem = pci_read_config(self, eecp + 2762 EHCI_LEGSUP_BIOS_SEM, 1); 2763 if (bios_sem == 0) { 2764 continue; 2765 } 2766 if (bootverbose) 2767 printf("ehci early: " 2768 "SMM active, request owner change\n"); 2769 2770 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 2771 2772 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 2773 DELAY(1000); 2774 bios_sem = pci_read_config(self, eecp + 2775 EHCI_LEGSUP_BIOS_SEM, 1); 2776 } 2777 2778 if (bios_sem != 0) { 2779 if (bootverbose) 2780 printf("ehci early: " 2781 "SMM does not respond\n"); 2782 } 2783 /* Disable interrupts */ 2784 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 2785 bus_write_4(res, offs + EHCI_USBINTR, 0); 2786 } 2787 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 2788 } 2789 2790 void 2791 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 2792 { 2793 struct pci_devinfo *dinfo = device_get_ivars(dev); 2794 pcicfgregs *cfg = &dinfo->cfg; 2795 struct resource_list *rl = &dinfo->resources; 2796 const struct pci_quirk *q; 2797 int i; 2798 2799 /* ATA devices needs special map treatment */ 2800 if ((pci_get_class(dev) == PCIC_STORAGE) && 2801 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 2802 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 2803 (!pci_read_config(dev, PCIR_BAR(0), 4) && 2804 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 2805 pci_ata_maps(bus, dev, rl, force, prefetchmask); 2806 else 2807 for (i = 0; i < cfg->nummaps;) 2808 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 2809 prefetchmask & (1 << i)); 2810 2811 /* 2812 * Add additional, quirked resources. 2813 */ 2814 for (q = &pci_quirks[0]; q->devid; q++) { 2815 if (q->devid == ((cfg->device << 16) | cfg->vendor) 2816 && q->type == PCI_QUIRK_MAP_REG) 2817 pci_add_map(bus, dev, q->arg1, rl, force, 0); 2818 } 2819 2820 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 2821 #ifdef __PCI_REROUTE_INTERRUPT 2822 /* 2823 * Try to re-route interrupts. Sometimes the BIOS or 2824 * firmware may leave bogus values in these registers. 2825 * If the re-route fails, then just stick with what we 2826 * have. 2827 */ 2828 pci_assign_interrupt(bus, dev, 1); 2829 #else 2830 pci_assign_interrupt(bus, dev, 0); 2831 #endif 2832 } 2833 2834 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 2835 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 2836 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 2837 ehci_early_takeover(dev); 2838 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 2839 ohci_early_takeover(dev); 2840 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 2841 uhci_early_takeover(dev); 2842 } 2843 } 2844 2845 void 2846 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size) 2847 { 2848 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 2849 device_t pcib = device_get_parent(dev); 2850 struct pci_devinfo *dinfo; 2851 int maxslots; 2852 int s, f, pcifunchigh; 2853 uint8_t hdrtype; 2854 2855 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 2856 ("dinfo_size too small")); 2857 maxslots = PCIB_MAXSLOTS(pcib); 2858 for (s = 0; s <= maxslots; s++) { 2859 pcifunchigh = 0; 2860 f = 0; 2861 DELAY(1); 2862 hdrtype = REG(PCIR_HDRTYPE, 1); 2863 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 2864 continue; 2865 if (hdrtype & PCIM_MFDEV) 2866 pcifunchigh = PCI_FUNCMAX; 2867 for (f = 0; f <= pcifunchigh; f++) { 2868 dinfo = pci_read_device(pcib, domain, busno, s, f, 2869 dinfo_size); 2870 if (dinfo != NULL) { 2871 pci_add_child(dev, dinfo); 2872 } 2873 } 2874 } 2875 #undef REG 2876 } 2877 2878 void 2879 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 2880 { 2881 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 2882 device_set_ivars(dinfo->cfg.dev, dinfo); 2883 resource_list_init(&dinfo->resources); 2884 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 2885 pci_cfg_restore(dinfo->cfg.dev, dinfo); 2886 pci_print_verbose(dinfo); 2887 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 2888 } 2889 2890 static int 2891 pci_probe(device_t dev) 2892 { 2893 2894 device_set_desc(dev, "PCI bus"); 2895 2896 /* Allow other subclasses to override this driver. */ 2897 return (BUS_PROBE_GENERIC); 2898 } 2899 2900 static int 2901 pci_attach(device_t dev) 2902 { 2903 int busno, domain; 2904 2905 /* 2906 * Since there can be multiple independantly numbered PCI 2907 * busses on systems with multiple PCI domains, we can't use 2908 * the unit number to decide which bus we are probing. We ask 2909 * the parent pcib what our domain and bus numbers are. 2910 */ 2911 domain = pcib_get_domain(dev); 2912 busno = pcib_get_bus(dev); 2913 if (bootverbose) 2914 device_printf(dev, "domain=%d, physical bus=%d\n", 2915 domain, busno); 2916 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo)); 2917 return (bus_generic_attach(dev)); 2918 } 2919 2920 int 2921 pci_suspend(device_t dev) 2922 { 2923 int dstate, error, i, numdevs; 2924 device_t acpi_dev, child, *devlist; 2925 struct pci_devinfo *dinfo; 2926 2927 /* 2928 * Save the PCI configuration space for each child and set the 2929 * device in the appropriate power state for this sleep state. 2930 */ 2931 acpi_dev = NULL; 2932 if (pci_do_power_resume) 2933 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2934 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 2935 return (error); 2936 for (i = 0; i < numdevs; i++) { 2937 child = devlist[i]; 2938 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2939 pci_cfg_save(child, dinfo, 0); 2940 } 2941 2942 /* Suspend devices before potentially powering them down. */ 2943 error = bus_generic_suspend(dev); 2944 if (error) { 2945 free(devlist, M_TEMP); 2946 return (error); 2947 } 2948 2949 /* 2950 * Always set the device to D3. If ACPI suggests a different 2951 * power state, use it instead. If ACPI is not present, the 2952 * firmware is responsible for managing device power. Skip 2953 * children who aren't attached since they are powered down 2954 * separately. Only manage type 0 devices for now. 2955 */ 2956 for (i = 0; acpi_dev && i < numdevs; i++) { 2957 child = devlist[i]; 2958 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2959 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 2960 dstate = PCI_POWERSTATE_D3; 2961 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 2962 pci_set_powerstate(child, dstate); 2963 } 2964 } 2965 free(devlist, M_TEMP); 2966 return (0); 2967 } 2968 2969 int 2970 pci_resume(device_t dev) 2971 { 2972 int i, numdevs, error; 2973 device_t acpi_dev, child, *devlist; 2974 struct pci_devinfo *dinfo; 2975 2976 /* 2977 * Set each child to D0 and restore its PCI configuration space. 2978 */ 2979 acpi_dev = NULL; 2980 if (pci_do_power_resume) 2981 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 2982 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 2983 return (error); 2984 for (i = 0; i < numdevs; i++) { 2985 /* 2986 * Notify ACPI we're going to D0 but ignore the result. If 2987 * ACPI is not present, the firmware is responsible for 2988 * managing device power. Only manage type 0 devices for now. 2989 */ 2990 child = devlist[i]; 2991 dinfo = (struct pci_devinfo *) device_get_ivars(child); 2992 if (acpi_dev && device_is_attached(child) && 2993 dinfo->cfg.hdrtype == 0) { 2994 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 2995 pci_set_powerstate(child, PCI_POWERSTATE_D0); 2996 } 2997 2998 /* Now the device is powered up, restore its config space. */ 2999 pci_cfg_restore(child, dinfo); 3000 } 3001 free(devlist, M_TEMP); 3002 return (bus_generic_resume(dev)); 3003 } 3004 3005 static void 3006 pci_load_vendor_data(void) 3007 { 3008 caddr_t vendordata, info; 3009 3010 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 3011 info = preload_search_info(vendordata, MODINFO_ADDR); 3012 pci_vendordata = *(char **)info; 3013 info = preload_search_info(vendordata, MODINFO_SIZE); 3014 pci_vendordata_size = *(size_t *)info; 3015 /* terminate the database */ 3016 pci_vendordata[pci_vendordata_size] = '\n'; 3017 } 3018 } 3019 3020 void 3021 pci_driver_added(device_t dev, driver_t *driver) 3022 { 3023 int numdevs; 3024 device_t *devlist; 3025 device_t child; 3026 struct pci_devinfo *dinfo; 3027 int i; 3028 3029 if (bootverbose) 3030 device_printf(dev, "driver added\n"); 3031 DEVICE_IDENTIFY(driver, dev); 3032 if (device_get_children(dev, &devlist, &numdevs) != 0) 3033 return; 3034 for (i = 0; i < numdevs; i++) { 3035 child = devlist[i]; 3036 if (device_get_state(child) != DS_NOTPRESENT) 3037 continue; 3038 dinfo = device_get_ivars(child); 3039 pci_print_verbose(dinfo); 3040 if (bootverbose) 3041 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 3042 pci_cfg_restore(child, dinfo); 3043 if (device_probe_and_attach(child) != 0) 3044 pci_cfg_save(child, dinfo, 1); 3045 } 3046 free(devlist, M_TEMP); 3047 } 3048 3049 int 3050 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 3051 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 3052 { 3053 struct pci_devinfo *dinfo; 3054 struct msix_table_entry *mte; 3055 struct msix_vector *mv; 3056 uint64_t addr; 3057 uint32_t data; 3058 void *cookie; 3059 int error, rid; 3060 3061 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 3062 arg, &cookie); 3063 if (error) 3064 return (error); 3065 3066 /* If this is not a direct child, just bail out. */ 3067 if (device_get_parent(child) != dev) { 3068 *cookiep = cookie; 3069 return(0); 3070 } 3071 3072 rid = rman_get_rid(irq); 3073 if (rid == 0) { 3074 /* Make sure that INTx is enabled */ 3075 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 3076 } else { 3077 /* 3078 * Check to see if the interrupt is MSI or MSI-X. 3079 * Ask our parent to map the MSI and give 3080 * us the address and data register values. 3081 * If we fail for some reason, teardown the 3082 * interrupt handler. 3083 */ 3084 dinfo = device_get_ivars(child); 3085 if (dinfo->cfg.msi.msi_alloc > 0) { 3086 if (dinfo->cfg.msi.msi_addr == 0) { 3087 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 3088 ("MSI has handlers, but vectors not mapped")); 3089 error = PCIB_MAP_MSI(device_get_parent(dev), 3090 child, rman_get_start(irq), &addr, &data); 3091 if (error) 3092 goto bad; 3093 dinfo->cfg.msi.msi_addr = addr; 3094 dinfo->cfg.msi.msi_data = data; 3095 } 3096 if (dinfo->cfg.msi.msi_handlers == 0) 3097 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 3098 dinfo->cfg.msi.msi_data); 3099 dinfo->cfg.msi.msi_handlers++; 3100 } else { 3101 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3102 ("No MSI or MSI-X interrupts allocated")); 3103 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3104 ("MSI-X index too high")); 3105 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3106 KASSERT(mte->mte_vector != 0, ("no message vector")); 3107 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 3108 KASSERT(mv->mv_irq == rman_get_start(irq), 3109 ("IRQ mismatch")); 3110 if (mv->mv_address == 0) { 3111 KASSERT(mte->mte_handlers == 0, 3112 ("MSI-X table entry has handlers, but vector not mapped")); 3113 error = PCIB_MAP_MSI(device_get_parent(dev), 3114 child, rman_get_start(irq), &addr, &data); 3115 if (error) 3116 goto bad; 3117 mv->mv_address = addr; 3118 mv->mv_data = data; 3119 } 3120 if (mte->mte_handlers == 0) { 3121 pci_enable_msix(child, rid - 1, mv->mv_address, 3122 mv->mv_data); 3123 pci_unmask_msix(child, rid - 1); 3124 } 3125 mte->mte_handlers++; 3126 } 3127 3128 /* Make sure that INTx is disabled if we are using MSI/MSIX */ 3129 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3130 bad: 3131 if (error) { 3132 (void)bus_generic_teardown_intr(dev, child, irq, 3133 cookie); 3134 return (error); 3135 } 3136 } 3137 *cookiep = cookie; 3138 return (0); 3139 } 3140 3141 int 3142 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 3143 void *cookie) 3144 { 3145 struct msix_table_entry *mte; 3146 struct resource_list_entry *rle; 3147 struct pci_devinfo *dinfo; 3148 int error, rid; 3149 3150 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 3151 return (EINVAL); 3152 3153 /* If this isn't a direct child, just bail out */ 3154 if (device_get_parent(child) != dev) 3155 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 3156 3157 rid = rman_get_rid(irq); 3158 if (rid == 0) { 3159 /* Mask INTx */ 3160 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3161 } else { 3162 /* 3163 * Check to see if the interrupt is MSI or MSI-X. If so, 3164 * decrement the appropriate handlers count and mask the 3165 * MSI-X message, or disable MSI messages if the count 3166 * drops to 0. 3167 */ 3168 dinfo = device_get_ivars(child); 3169 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 3170 if (rle->res != irq) 3171 return (EINVAL); 3172 if (dinfo->cfg.msi.msi_alloc > 0) { 3173 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 3174 ("MSI-X index too high")); 3175 if (dinfo->cfg.msi.msi_handlers == 0) 3176 return (EINVAL); 3177 dinfo->cfg.msi.msi_handlers--; 3178 if (dinfo->cfg.msi.msi_handlers == 0) 3179 pci_disable_msi(child); 3180 } else { 3181 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3182 ("No MSI or MSI-X interrupts allocated")); 3183 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3184 ("MSI-X index too high")); 3185 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3186 if (mte->mte_handlers == 0) 3187 return (EINVAL); 3188 mte->mte_handlers--; 3189 if (mte->mte_handlers == 0) 3190 pci_mask_msix(child, rid - 1); 3191 } 3192 } 3193 error = bus_generic_teardown_intr(dev, child, irq, cookie); 3194 if (rid > 0) 3195 KASSERT(error == 0, 3196 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 3197 return (error); 3198 } 3199 3200 int 3201 pci_print_child(device_t dev, device_t child) 3202 { 3203 struct pci_devinfo *dinfo; 3204 struct resource_list *rl; 3205 int retval = 0; 3206 3207 dinfo = device_get_ivars(child); 3208 rl = &dinfo->resources; 3209 3210 retval += bus_print_child_header(dev, child); 3211 3212 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 3213 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 3214 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 3215 if (device_get_flags(dev)) 3216 retval += printf(" flags %#x", device_get_flags(dev)); 3217 3218 retval += printf(" at device %d.%d", pci_get_slot(child), 3219 pci_get_function(child)); 3220 3221 retval += bus_print_child_footer(dev, child); 3222 3223 return (retval); 3224 } 3225 3226 static struct 3227 { 3228 int class; 3229 int subclass; 3230 char *desc; 3231 } pci_nomatch_tab[] = { 3232 {PCIC_OLD, -1, "old"}, 3233 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 3234 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 3235 {PCIC_STORAGE, -1, "mass storage"}, 3236 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 3237 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 3238 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 3239 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 3240 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 3241 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"}, 3242 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"}, 3243 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"}, 3244 {PCIC_NETWORK, -1, "network"}, 3245 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 3246 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 3247 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 3248 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 3249 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 3250 {PCIC_DISPLAY, -1, "display"}, 3251 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 3252 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 3253 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 3254 {PCIC_MULTIMEDIA, -1, "multimedia"}, 3255 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 3256 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 3257 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 3258 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"}, 3259 {PCIC_MEMORY, -1, "memory"}, 3260 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 3261 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 3262 {PCIC_BRIDGE, -1, "bridge"}, 3263 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 3264 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 3265 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 3266 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 3267 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 3268 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 3269 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 3270 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 3271 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 3272 {PCIC_SIMPLECOMM, -1, "simple comms"}, 3273 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 3274 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 3275 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 3276 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 3277 {PCIC_BASEPERIPH, -1, "base peripheral"}, 3278 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 3279 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 3280 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 3281 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 3282 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 3283 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"}, 3284 {PCIC_INPUTDEV, -1, "input device"}, 3285 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 3286 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 3287 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 3288 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 3289 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 3290 {PCIC_DOCKING, -1, "docking station"}, 3291 {PCIC_PROCESSOR, -1, "processor"}, 3292 {PCIC_SERIALBUS, -1, "serial bus"}, 3293 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 3294 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 3295 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 3296 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 3297 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 3298 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 3299 {PCIC_WIRELESS, -1, "wireless controller"}, 3300 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 3301 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 3302 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 3303 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 3304 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 3305 {PCIC_SATCOM, -1, "satellite communication"}, 3306 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 3307 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 3308 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 3309 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 3310 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 3311 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 3312 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 3313 {PCIC_DASP, -1, "dasp"}, 3314 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 3315 {0, 0, NULL} 3316 }; 3317 3318 void 3319 pci_probe_nomatch(device_t dev, device_t child) 3320 { 3321 int i; 3322 char *cp, *scp, *device; 3323 3324 /* 3325 * Look for a listing for this device in a loaded device database. 3326 */ 3327 if ((device = pci_describe_device(child)) != NULL) { 3328 device_printf(dev, "<%s>", device); 3329 free(device, M_DEVBUF); 3330 } else { 3331 /* 3332 * Scan the class/subclass descriptions for a general 3333 * description. 3334 */ 3335 cp = "unknown"; 3336 scp = NULL; 3337 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 3338 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 3339 if (pci_nomatch_tab[i].subclass == -1) { 3340 cp = pci_nomatch_tab[i].desc; 3341 } else if (pci_nomatch_tab[i].subclass == 3342 pci_get_subclass(child)) { 3343 scp = pci_nomatch_tab[i].desc; 3344 } 3345 } 3346 } 3347 device_printf(dev, "<%s%s%s>", 3348 cp ? cp : "", 3349 ((cp != NULL) && (scp != NULL)) ? ", " : "", 3350 scp ? scp : ""); 3351 } 3352 printf(" at device %d.%d (no driver attached)\n", 3353 pci_get_slot(child), pci_get_function(child)); 3354 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1); 3355 return; 3356 } 3357 3358 /* 3359 * Parse the PCI device database, if loaded, and return a pointer to a 3360 * description of the device. 3361 * 3362 * The database is flat text formatted as follows: 3363 * 3364 * Any line not in a valid format is ignored. 3365 * Lines are terminated with newline '\n' characters. 3366 * 3367 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 3368 * the vendor name. 3369 * 3370 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 3371 * - devices cannot be listed without a corresponding VENDOR line. 3372 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 3373 * another TAB, then the device name. 3374 */ 3375 3376 /* 3377 * Assuming (ptr) points to the beginning of a line in the database, 3378 * return the vendor or device and description of the next entry. 3379 * The value of (vendor) or (device) inappropriate for the entry type 3380 * is set to -1. Returns nonzero at the end of the database. 3381 * 3382 * Note that this is slightly unrobust in the face of corrupt data; 3383 * we attempt to safeguard against this by spamming the end of the 3384 * database with a newline when we initialise. 3385 */ 3386 static int 3387 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 3388 { 3389 char *cp = *ptr; 3390 int left; 3391 3392 *device = -1; 3393 *vendor = -1; 3394 **desc = '\0'; 3395 for (;;) { 3396 left = pci_vendordata_size - (cp - pci_vendordata); 3397 if (left <= 0) { 3398 *ptr = cp; 3399 return(1); 3400 } 3401 3402 /* vendor entry? */ 3403 if (*cp != '\t' && 3404 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 3405 break; 3406 /* device entry? */ 3407 if (*cp == '\t' && 3408 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 3409 break; 3410 3411 /* skip to next line */ 3412 while (*cp != '\n' && left > 0) { 3413 cp++; 3414 left--; 3415 } 3416 if (*cp == '\n') { 3417 cp++; 3418 left--; 3419 } 3420 } 3421 /* skip to next line */ 3422 while (*cp != '\n' && left > 0) { 3423 cp++; 3424 left--; 3425 } 3426 if (*cp == '\n' && left > 0) 3427 cp++; 3428 *ptr = cp; 3429 return(0); 3430 } 3431 3432 static char * 3433 pci_describe_device(device_t dev) 3434 { 3435 int vendor, device; 3436 char *desc, *vp, *dp, *line; 3437 3438 desc = vp = dp = NULL; 3439 3440 /* 3441 * If we have no vendor data, we can't do anything. 3442 */ 3443 if (pci_vendordata == NULL) 3444 goto out; 3445 3446 /* 3447 * Scan the vendor data looking for this device 3448 */ 3449 line = pci_vendordata; 3450 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 3451 goto out; 3452 for (;;) { 3453 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 3454 goto out; 3455 if (vendor == pci_get_vendor(dev)) 3456 break; 3457 } 3458 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 3459 goto out; 3460 for (;;) { 3461 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 3462 *dp = 0; 3463 break; 3464 } 3465 if (vendor != -1) { 3466 *dp = 0; 3467 break; 3468 } 3469 if (device == pci_get_device(dev)) 3470 break; 3471 } 3472 if (dp[0] == '\0') 3473 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 3474 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 3475 NULL) 3476 sprintf(desc, "%s, %s", vp, dp); 3477 out: 3478 if (vp != NULL) 3479 free(vp, M_DEVBUF); 3480 if (dp != NULL) 3481 free(dp, M_DEVBUF); 3482 return(desc); 3483 } 3484 3485 int 3486 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 3487 { 3488 struct pci_devinfo *dinfo; 3489 pcicfgregs *cfg; 3490 3491 dinfo = device_get_ivars(child); 3492 cfg = &dinfo->cfg; 3493 3494 switch (which) { 3495 case PCI_IVAR_ETHADDR: 3496 /* 3497 * The generic accessor doesn't deal with failure, so 3498 * we set the return value, then return an error. 3499 */ 3500 *((uint8_t **) result) = NULL; 3501 return (EINVAL); 3502 case PCI_IVAR_SUBVENDOR: 3503 *result = cfg->subvendor; 3504 break; 3505 case PCI_IVAR_SUBDEVICE: 3506 *result = cfg->subdevice; 3507 break; 3508 case PCI_IVAR_VENDOR: 3509 *result = cfg->vendor; 3510 break; 3511 case PCI_IVAR_DEVICE: 3512 *result = cfg->device; 3513 break; 3514 case PCI_IVAR_DEVID: 3515 *result = (cfg->device << 16) | cfg->vendor; 3516 break; 3517 case PCI_IVAR_CLASS: 3518 *result = cfg->baseclass; 3519 break; 3520 case PCI_IVAR_SUBCLASS: 3521 *result = cfg->subclass; 3522 break; 3523 case PCI_IVAR_PROGIF: 3524 *result = cfg->progif; 3525 break; 3526 case PCI_IVAR_REVID: 3527 *result = cfg->revid; 3528 break; 3529 case PCI_IVAR_INTPIN: 3530 *result = cfg->intpin; 3531 break; 3532 case PCI_IVAR_IRQ: 3533 *result = cfg->intline; 3534 break; 3535 case PCI_IVAR_DOMAIN: 3536 *result = cfg->domain; 3537 break; 3538 case PCI_IVAR_BUS: 3539 *result = cfg->bus; 3540 break; 3541 case PCI_IVAR_SLOT: 3542 *result = cfg->slot; 3543 break; 3544 case PCI_IVAR_FUNCTION: 3545 *result = cfg->func; 3546 break; 3547 case PCI_IVAR_CMDREG: 3548 *result = cfg->cmdreg; 3549 break; 3550 case PCI_IVAR_CACHELNSZ: 3551 *result = cfg->cachelnsz; 3552 break; 3553 case PCI_IVAR_MINGNT: 3554 *result = cfg->mingnt; 3555 break; 3556 case PCI_IVAR_MAXLAT: 3557 *result = cfg->maxlat; 3558 break; 3559 case PCI_IVAR_LATTIMER: 3560 *result = cfg->lattimer; 3561 break; 3562 default: 3563 return (ENOENT); 3564 } 3565 return (0); 3566 } 3567 3568 int 3569 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 3570 { 3571 struct pci_devinfo *dinfo; 3572 3573 dinfo = device_get_ivars(child); 3574 3575 switch (which) { 3576 case PCI_IVAR_INTPIN: 3577 dinfo->cfg.intpin = value; 3578 return (0); 3579 case PCI_IVAR_ETHADDR: 3580 case PCI_IVAR_SUBVENDOR: 3581 case PCI_IVAR_SUBDEVICE: 3582 case PCI_IVAR_VENDOR: 3583 case PCI_IVAR_DEVICE: 3584 case PCI_IVAR_DEVID: 3585 case PCI_IVAR_CLASS: 3586 case PCI_IVAR_SUBCLASS: 3587 case PCI_IVAR_PROGIF: 3588 case PCI_IVAR_REVID: 3589 case PCI_IVAR_IRQ: 3590 case PCI_IVAR_DOMAIN: 3591 case PCI_IVAR_BUS: 3592 case PCI_IVAR_SLOT: 3593 case PCI_IVAR_FUNCTION: 3594 return (EINVAL); /* disallow for now */ 3595 3596 default: 3597 return (ENOENT); 3598 } 3599 } 3600 3601 #include "opt_ddb.h" 3602 #ifdef DDB 3603 #include <ddb/ddb.h> 3604 #include <sys/cons.h> 3605 3606 /* 3607 * List resources based on pci map registers, used for within ddb 3608 */ 3609 3610 DB_SHOW_COMMAND(pciregs, db_pci_dump) 3611 { 3612 struct pci_devinfo *dinfo; 3613 struct devlist *devlist_head; 3614 struct pci_conf *p; 3615 const char *name; 3616 int i, error, none_count; 3617 3618 none_count = 0; 3619 /* get the head of the device queue */ 3620 devlist_head = &pci_devq; 3621 3622 /* 3623 * Go through the list of devices and print out devices 3624 */ 3625 for (error = 0, i = 0, 3626 dinfo = STAILQ_FIRST(devlist_head); 3627 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 3628 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 3629 3630 /* Populate pd_name and pd_unit */ 3631 name = NULL; 3632 if (dinfo->cfg.dev) 3633 name = device_get_name(dinfo->cfg.dev); 3634 3635 p = &dinfo->conf; 3636 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 3637 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 3638 (name && *name) ? name : "none", 3639 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 3640 none_count++, 3641 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 3642 p->pc_sel.pc_func, (p->pc_class << 16) | 3643 (p->pc_subclass << 8) | p->pc_progif, 3644 (p->pc_subdevice << 16) | p->pc_subvendor, 3645 (p->pc_device << 16) | p->pc_vendor, 3646 p->pc_revid, p->pc_hdr); 3647 } 3648 } 3649 #endif /* DDB */ 3650 3651 static struct resource * 3652 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 3653 u_long start, u_long end, u_long count, u_int flags) 3654 { 3655 struct pci_devinfo *dinfo = device_get_ivars(child); 3656 struct resource_list *rl = &dinfo->resources; 3657 struct resource_list_entry *rle; 3658 struct resource *res; 3659 pci_addr_t map, testval; 3660 int mapsize; 3661 3662 /* 3663 * Weed out the bogons, and figure out how large the BAR/map 3664 * is. Bars that read back 0 here are bogus and unimplemented. 3665 * Note: atapci in legacy mode are special and handled elsewhere 3666 * in the code. If you have a atapci device in legacy mode and 3667 * it fails here, that other code is broken. 3668 */ 3669 res = NULL; 3670 pci_read_bar(child, *rid, &map, &testval); 3671 3672 /* Ignore a BAR with a base of 0. */ 3673 if (pci_mapbase(testval) == 0) 3674 goto out; 3675 3676 if (PCI_BAR_MEM(testval)) { 3677 if (type != SYS_RES_MEMORY) { 3678 if (bootverbose) 3679 device_printf(dev, 3680 "child %s requested type %d for rid %#x," 3681 " but the BAR says it is an memio\n", 3682 device_get_nameunit(child), type, *rid); 3683 goto out; 3684 } 3685 } else { 3686 if (type != SYS_RES_IOPORT) { 3687 if (bootverbose) 3688 device_printf(dev, 3689 "child %s requested type %d for rid %#x," 3690 " but the BAR says it is an ioport\n", 3691 device_get_nameunit(child), type, *rid); 3692 goto out; 3693 } 3694 } 3695 3696 /* 3697 * For real BARs, we need to override the size that 3698 * the driver requests, because that's what the BAR 3699 * actually uses and we would otherwise have a 3700 * situation where we might allocate the excess to 3701 * another driver, which won't work. 3702 */ 3703 mapsize = pci_mapsize(testval); 3704 count = (pci_addr_t)1 << mapsize; 3705 if (RF_ALIGNMENT(flags) < mapsize) 3706 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 3707 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH)) 3708 flags |= RF_PREFETCHABLE; 3709 3710 /* 3711 * Allocate enough resource, and then write back the 3712 * appropriate bar for that resource. 3713 */ 3714 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 3715 start, end, count, flags & ~RF_ACTIVE); 3716 if (res == NULL) { 3717 device_printf(child, 3718 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 3719 count, *rid, type, start, end); 3720 goto out; 3721 } 3722 rman_set_device(res, dev); 3723 resource_list_add(rl, type, *rid, start, end, count); 3724 rle = resource_list_find(rl, type, *rid); 3725 if (rle == NULL) 3726 panic("pci_alloc_map: unexpectedly can't find resource."); 3727 rle->res = res; 3728 rle->start = rman_get_start(res); 3729 rle->end = rman_get_end(res); 3730 rle->count = count; 3731 if (bootverbose) 3732 device_printf(child, 3733 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 3734 count, *rid, type, rman_get_start(res)); 3735 map = rman_get_start(res); 3736 pci_write_bar(child, *rid, map); 3737 out:; 3738 return (res); 3739 } 3740 3741 struct resource * 3742 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 3743 u_long start, u_long end, u_long count, u_int flags) 3744 { 3745 struct pci_devinfo *dinfo = device_get_ivars(child); 3746 struct resource_list *rl = &dinfo->resources; 3747 struct resource_list_entry *rle; 3748 struct resource *res; 3749 pcicfgregs *cfg = &dinfo->cfg; 3750 3751 if (device_get_parent(child) != dev) 3752 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 3753 type, rid, start, end, count, flags)); 3754 3755 /* 3756 * Perform lazy resource allocation 3757 */ 3758 switch (type) { 3759 case SYS_RES_IRQ: 3760 /* 3761 * Can't alloc legacy interrupt once MSI messages have 3762 * been allocated. 3763 */ 3764 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 3765 cfg->msix.msix_alloc > 0)) 3766 return (NULL); 3767 3768 /* 3769 * If the child device doesn't have an interrupt 3770 * routed and is deserving of an interrupt, try to 3771 * assign it one. 3772 */ 3773 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 3774 (cfg->intpin != 0)) 3775 pci_assign_interrupt(dev, child, 0); 3776 break; 3777 case SYS_RES_IOPORT: 3778 case SYS_RES_MEMORY: 3779 #ifdef NEW_PCIB 3780 /* 3781 * PCI-PCI bridge I/O window resources are not BARs. 3782 * For those allocations just pass the request up the 3783 * tree. 3784 */ 3785 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 3786 switch (*rid) { 3787 case PCIR_IOBASEL_1: 3788 case PCIR_MEMBASE_1: 3789 case PCIR_PMBASEL_1: 3790 /* 3791 * XXX: Should we bother creating a resource 3792 * list entry? 3793 */ 3794 return (bus_generic_alloc_resource(dev, child, 3795 type, rid, start, end, count, flags)); 3796 } 3797 } 3798 #endif 3799 /* Allocate resources for this BAR if needed. */ 3800 rle = resource_list_find(rl, type, *rid); 3801 if (rle == NULL) { 3802 res = pci_alloc_map(dev, child, type, rid, start, end, 3803 count, flags); 3804 if (res == NULL) 3805 return (NULL); 3806 rle = resource_list_find(rl, type, *rid); 3807 } 3808 3809 /* 3810 * If the resource belongs to the bus, then give it to 3811 * the child. We need to activate it if requested 3812 * since the bus always allocates inactive resources. 3813 */ 3814 if (rle != NULL && rle->res != NULL && 3815 rman_get_device(rle->res) == dev) { 3816 if (bootverbose) 3817 device_printf(child, 3818 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 3819 rman_get_size(rle->res), *rid, type, 3820 rman_get_start(rle->res)); 3821 rman_set_device(rle->res, child); 3822 if ((flags & RF_ACTIVE) && 3823 bus_activate_resource(child, type, *rid, 3824 rle->res) != 0) 3825 return (NULL); 3826 return (rle->res); 3827 } 3828 } 3829 return (resource_list_alloc(rl, dev, child, type, rid, 3830 start, end, count, flags)); 3831 } 3832 3833 int 3834 pci_release_resource(device_t dev, device_t child, int type, int rid, 3835 struct resource *r) 3836 { 3837 int error; 3838 3839 if (device_get_parent(child) != dev) 3840 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 3841 type, rid, r)); 3842 3843 /* 3844 * For BARs we don't actually want to release the resource. 3845 * Instead, we deactivate the resource if needed and then give 3846 * ownership of the BAR back to the bus. 3847 */ 3848 switch (type) { 3849 case SYS_RES_IOPORT: 3850 case SYS_RES_MEMORY: 3851 if (rman_get_device(r) != child) 3852 return (EINVAL); 3853 if (rman_get_flags(r) & RF_ACTIVE) { 3854 error = bus_deactivate_resource(child, type, rid, r); 3855 if (error) 3856 return (error); 3857 } 3858 rman_set_device(r, dev); 3859 return (0); 3860 } 3861 return (bus_generic_rl_release_resource(dev, child, type, rid, r)); 3862 } 3863 3864 int 3865 pci_activate_resource(device_t dev, device_t child, int type, int rid, 3866 struct resource *r) 3867 { 3868 int error; 3869 3870 error = bus_generic_activate_resource(dev, child, type, rid, r); 3871 if (error) 3872 return (error); 3873 3874 /* Enable decoding in the command register when activating BARs. */ 3875 if (device_get_parent(child) == dev) { 3876 switch (type) { 3877 case SYS_RES_IOPORT: 3878 case SYS_RES_MEMORY: 3879 error = PCI_ENABLE_IO(dev, child, type); 3880 break; 3881 } 3882 } 3883 return (error); 3884 } 3885 3886 void 3887 pci_delete_resource(device_t dev, device_t child, int type, int rid) 3888 { 3889 struct pci_devinfo *dinfo; 3890 struct resource_list *rl; 3891 struct resource_list_entry *rle; 3892 3893 if (device_get_parent(child) != dev) 3894 return; 3895 3896 dinfo = device_get_ivars(child); 3897 rl = &dinfo->resources; 3898 rle = resource_list_find(rl, type, rid); 3899 if (rle == NULL) 3900 return; 3901 3902 if (rle->res) { 3903 if (rman_get_device(rle->res) != dev || 3904 rman_get_flags(rle->res) & RF_ACTIVE) { 3905 device_printf(dev, "delete_resource: " 3906 "Resource still owned by child, oops. " 3907 "(type=%d, rid=%d, addr=%lx)\n", 3908 rle->type, rle->rid, 3909 rman_get_start(rle->res)); 3910 return; 3911 } 3912 3913 #ifndef __PCI_BAR_ZERO_VALID 3914 /* 3915 * If this is a BAR, clear the BAR so it stops 3916 * decoding before releasing the resource. 3917 */ 3918 switch (type) { 3919 case SYS_RES_IOPORT: 3920 case SYS_RES_MEMORY: 3921 pci_write_bar(child, rid, 0); 3922 break; 3923 } 3924 #endif 3925 bus_release_resource(dev, type, rid, rle->res); 3926 } 3927 resource_list_delete(rl, type, rid); 3928 } 3929 3930 struct resource_list * 3931 pci_get_resource_list (device_t dev, device_t child) 3932 { 3933 struct pci_devinfo *dinfo = device_get_ivars(child); 3934 3935 return (&dinfo->resources); 3936 } 3937 3938 uint32_t 3939 pci_read_config_method(device_t dev, device_t child, int reg, int width) 3940 { 3941 struct pci_devinfo *dinfo = device_get_ivars(child); 3942 pcicfgregs *cfg = &dinfo->cfg; 3943 3944 return (PCIB_READ_CONFIG(device_get_parent(dev), 3945 cfg->bus, cfg->slot, cfg->func, reg, width)); 3946 } 3947 3948 void 3949 pci_write_config_method(device_t dev, device_t child, int reg, 3950 uint32_t val, int width) 3951 { 3952 struct pci_devinfo *dinfo = device_get_ivars(child); 3953 pcicfgregs *cfg = &dinfo->cfg; 3954 3955 PCIB_WRITE_CONFIG(device_get_parent(dev), 3956 cfg->bus, cfg->slot, cfg->func, reg, val, width); 3957 } 3958 3959 int 3960 pci_child_location_str_method(device_t dev, device_t child, char *buf, 3961 size_t buflen) 3962 { 3963 3964 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 3965 pci_get_function(child)); 3966 return (0); 3967 } 3968 3969 int 3970 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 3971 size_t buflen) 3972 { 3973 struct pci_devinfo *dinfo; 3974 pcicfgregs *cfg; 3975 3976 dinfo = device_get_ivars(child); 3977 cfg = &dinfo->cfg; 3978 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 3979 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 3980 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 3981 cfg->progif); 3982 return (0); 3983 } 3984 3985 int 3986 pci_assign_interrupt_method(device_t dev, device_t child) 3987 { 3988 struct pci_devinfo *dinfo = device_get_ivars(child); 3989 pcicfgregs *cfg = &dinfo->cfg; 3990 3991 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 3992 cfg->intpin)); 3993 } 3994 3995 static int 3996 pci_modevent(module_t mod, int what, void *arg) 3997 { 3998 static struct cdev *pci_cdev; 3999 4000 switch (what) { 4001 case MOD_LOAD: 4002 STAILQ_INIT(&pci_devq); 4003 pci_generation = 0; 4004 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 4005 "pci"); 4006 pci_load_vendor_data(); 4007 break; 4008 4009 case MOD_UNLOAD: 4010 destroy_dev(pci_cdev); 4011 break; 4012 } 4013 4014 return (0); 4015 } 4016 4017 void 4018 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 4019 { 4020 int i; 4021 4022 /* 4023 * Only do header type 0 devices. Type 1 devices are bridges, 4024 * which we know need special treatment. Type 2 devices are 4025 * cardbus bridges which also require special treatment. 4026 * Other types are unknown, and we err on the side of safety 4027 * by ignoring them. 4028 */ 4029 if (dinfo->cfg.hdrtype != 0) 4030 return; 4031 4032 /* 4033 * Restore the device to full power mode. We must do this 4034 * before we restore the registers because moving from D3 to 4035 * D0 will cause the chip's BARs and some other registers to 4036 * be reset to some unknown power on reset values. Cut down 4037 * the noise on boot by doing nothing if we are already in 4038 * state D0. 4039 */ 4040 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 4041 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 4042 } 4043 for (i = 0; i < dinfo->cfg.nummaps; i++) 4044 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 4045 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 4046 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 4047 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 4048 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 4049 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 4050 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 4051 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 4052 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 4053 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 4054 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 4055 4056 /* Restore MSI and MSI-X configurations if they are present. */ 4057 if (dinfo->cfg.msi.msi_location != 0) 4058 pci_resume_msi(dev); 4059 if (dinfo->cfg.msix.msix_location != 0) 4060 pci_resume_msix(dev); 4061 } 4062 4063 void 4064 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 4065 { 4066 int i; 4067 uint32_t cls; 4068 int ps; 4069 4070 /* 4071 * Only do header type 0 devices. Type 1 devices are bridges, which 4072 * we know need special treatment. Type 2 devices are cardbus bridges 4073 * which also require special treatment. Other types are unknown, and 4074 * we err on the side of safety by ignoring them. Powering down 4075 * bridges should not be undertaken lightly. 4076 */ 4077 if (dinfo->cfg.hdrtype != 0) 4078 return; 4079 for (i = 0; i < dinfo->cfg.nummaps; i++) 4080 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 4081 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 4082 4083 /* 4084 * Some drivers apparently write to these registers w/o updating our 4085 * cached copy. No harm happens if we update the copy, so do so here 4086 * so we can restore them. The COMMAND register is modified by the 4087 * bus w/o updating the cache. This should represent the normally 4088 * writable portion of the 'defined' part of type 0 headers. In 4089 * theory we also need to save/restore the PCI capability structures 4090 * we know about, but apart from power we don't know any that are 4091 * writable. 4092 */ 4093 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 4094 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4095 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 4096 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 4097 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 4098 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 4099 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 4100 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 4101 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 4102 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 4103 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 4104 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 4105 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 4106 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 4107 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 4108 4109 /* 4110 * don't set the state for display devices, base peripherals and 4111 * memory devices since bad things happen when they are powered down. 4112 * We should (a) have drivers that can easily detach and (b) use 4113 * generic drivers for these devices so that some device actually 4114 * attaches. We need to make sure that when we implement (a) we don't 4115 * power the device down on a reattach. 4116 */ 4117 cls = pci_get_class(dev); 4118 if (!setstate) 4119 return; 4120 switch (pci_do_power_nodriver) 4121 { 4122 case 0: /* NO powerdown at all */ 4123 return; 4124 case 1: /* Conservative about what to power down */ 4125 if (cls == PCIC_STORAGE) 4126 return; 4127 /*FALLTHROUGH*/ 4128 case 2: /* Agressive about what to power down */ 4129 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 4130 cls == PCIC_BASEPERIPH) 4131 return; 4132 /*FALLTHROUGH*/ 4133 case 3: /* Power down everything */ 4134 break; 4135 } 4136 /* 4137 * PCI spec says we can only go into D3 state from D0 state. 4138 * Transition from D[12] into D0 before going to D3 state. 4139 */ 4140 ps = pci_get_powerstate(dev); 4141 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 4142 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 4143 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 4144 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 4145 }
Cache object: 53edbded63a7587250749aedca86c74c
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